HPMICRO HPM6830 HPM6800 1.0 HPM6800 device /* * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ other r0p0 little false true true 7 false 8 32 32 read-write 0x0 0xFFFFFFFF FGPIO FGPIO GPIO 0xc0000 0x0 0x824 registers 16 0x10 gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz DI[%s] no description available 0x0 VALUE GPIO input value 0x0 32 0x00000000 0xFFFFFFFF INPUT GPIO input bus value, each bit represents a bus bit 0: low level presents on chip pin 1: high level presents on chip pin 0 32 read-only 16 0x10 gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz DO[%s] no description available 0x100 VALUE GPIO output value 0x0 32 0x00000000 0xFFFFFFFF OUTPUT GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output 0 32 read-write SET GPIO output set 0x4 32 0x00000000 0xFFFFFFFF OUTPUT GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output 0 32 read-write CLEAR GPIO output clear 0x8 32 0x00000000 0xFFFFFFFF OUTPUT GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output 0 32 read-write TOGGLE GPIO output toggle 0xc 32 0x00000000 0xFFFFFFFF OUTPUT GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output 0 32 read-write 16 0x10 gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz OE[%s] no description available 0x200 VALUE GPIO direction value 0x0 32 0x00000000 0xFFFFFFFF DIRECTION GPIO direction, each bit represents a bus bit 0: input 1: output 0 32 read-write SET GPIO direction set 0x4 32 0x00000000 0xFFFFFFFF DIRECTION GPIO direction, each bit represents a bus bit 0: input 1: output 0 32 read-write CLEAR GPIO direction clear 0x8 32 0x00000000 0xFFFFFFFF DIRECTION GPIO direction, each bit represents a bus bit 0: input 1: output 0 32 read-write TOGGLE GPIO direction toggle 0xc 32 0x00000000 0xFFFFFFFF DIRECTION GPIO direction, each bit represents a bus bit 0: input 1: output 0 32 read-write 16 0x10 gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz IF[%s] no description available 0x300 VALUE GPIO interrupt flag value 0x0 32 0x00000000 0xFFFFFFFF IRQ_FLAG GPIO interrupt flag, write 1 to clear this flag 0: no irq 1: irq pending 0 32 write-only 16 0x10 gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz IE[%s] no description available 0x400 VALUE GPIO interrupt enable value 0x0 32 0x00000000 0xFFFFFFFF IRQ_EN GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable 0 32 read-write SET GPIO interrupt enable set 0x4 32 0x00000000 0xFFFFFFFF IRQ_EN GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable 0 32 read-write CLEAR GPIO interrupt enable clear 0x8 32 0x00000000 0xFFFFFFFF IRQ_EN GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable 0 32 read-write TOGGLE GPIO interrupt enable toggle 0xc 32 0x00000000 0xFFFFFFFF IRQ_EN GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable 0 32 read-write 16 0x10 gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz PL[%s] no description available 0x500 VALUE GPIO interrupt polarity value 0x0 32 0x00000000 0xFFFFFFFF IRQ_POL GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge 0 32 read-write SET GPIO interrupt polarity set 0x4 32 0x00000000 0xFFFFFFFF IRQ_POL GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge 0 32 read-write CLEAR GPIO interrupt polarity clear 0x8 32 0x00000000 0xFFFFFFFF IRQ_POL GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge 0 32 read-write TOGGLE GPIO interrupt polarity toggle 0xc 32 0x00000000 0xFFFFFFFF IRQ_POL GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge 0 32 read-write 16 0x10 gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz TP[%s] no description available 0x600 VALUE GPIO interrupt type value 0x0 32 0x00000000 0xFFFFFFFF IRQ_TYPE GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge 0 32 read-write SET GPIO interrupt type set 0x4 32 0x00000000 0xFFFFFFFF IRQ_TYPE GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge 0 32 read-write CLEAR GPIO interrupt type clear 0x8 32 0x00000000 0xFFFFFFFF IRQ_TYPE GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge 0 32 read-write TOGGLE GPIO interrupt type toggle 0xc 32 0x00000000 0xFFFFFFFF IRQ_TYPE GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge 0 32 read-write 16 0x10 gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz AS[%s] no description available 0x700 VALUE GPIO interrupt asynchronous value 0x0 32 0x00000000 0xFFFFFFFF IRQ_ASYNC GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise 0 32 read-write SET GPIO interrupt asynchronous set 0x4 32 0x00000000 0xFFFFFFFF IRQ_ASYNC GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise 0 32 read-write CLEAR GPIO interrupt asynchronous clear 0x8 32 0x00000000 0xFFFFFFFF IRQ_ASYNC GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise 0 32 read-write TOGGLE GPIO interrupt asynchronous toggle 0xc 32 0x00000000 0xFFFFFFFF IRQ_ASYNC GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise 0 32 read-write GPIO0 GPIO0 GPIO 0xf00d0000 PGPIO PGPIO GPIO 0xf411c000 BGPIO BGPIO GPIO 0xf4214000 PLIC PLIC PLIC 0xe4000000 0x0 0x202000 registers feature Feature enable register 0x0 32 0x00000000 0x00000003 VECTORED Vector mode enable 0: Disabled 1: Enabled 1 1 read-write PREEMPT Preemptive priority interrupt enable 0: Disabled 1: Enabled 0 1 read-write 127 0x4 PRIORITY1,PRIORITY2,PRIORITY3,PRIORITY4,PRIORITY5,PRIORITY6,PRIORITY7,PRIORITY8,PRIORITY9,PRIORITY10,PRIORITY11,PRIORITY12,PRIORITY13,PRIORITY14,PRIORITY15,PRIORITY16,PRIORITY17,PRIORITY18,PRIORITY19,PRIORITY20,PRIORITY21,PRIORITY22,PRIORITY23,PRIORITY24,PRIORITY25,PRIORITY26,PRIORITY27,PRIORITY28,PRIORITY29,PRIORITY30,PRIORITY31,PRIORITY32,PRIORITY33,PRIORITY34,PRIORITY35,PRIORITY36,PRIORITY37,PRIORITY38,PRIORITY39,PRIORITY40,PRIORITY41,PRIORITY42,PRIORITY43,PRIORITY44,PRIORITY45,PRIORITY46,PRIORITY47,PRIORITY48,PRIORITY49,PRIORITY50,PRIORITY51,PRIORITY52,PRIORITY53,PRIORITY54,PRIORITY55,PRIORITY56,PRIORITY57,PRIORITY58,PRIORITY59,PRIORITY60,PRIORITY61,PRIORITY62,PRIORITY63,PRIORITY64,PRIORITY65,PRIORITY66,PRIORITY67,PRIORITY68,PRIORITY69,PRIORITY70,PRIORITY71,PRIORITY72,PRIORITY73,PRIORITY74,PRIORITY75,PRIORITY76,PRIORITY77,PRIORITY78,PRIORITY79,PRIORITY80,PRIORITY81,PRIORITY82,PRIORITY83,PRIORITY84,PRIORITY85,PRIORITY86,PRIORITY87,PRIORITY88,PRIORITY89,PRIORITY90,PRIORITY91,PRIORITY92,PRIORITY93,PRIORITY94,PRIORITY95,PRIORITY96,PRIORITY97,PRIORITY98,PRIORITY99,PRIORITY100,PRIORITY101,PRIORITY102,PRIORITY103,PRIORITY104,PRIORITY105,PRIORITY106,PRIORITY107,PRIORITY108,PRIORITY109,PRIORITY110,PRIORITY111,PRIORITY112,PRIORITY113,PRIORITY114,PRIORITY115,PRIORITY116,PRIORITY117,PRIORITY118,PRIORITY119,PRIORITY120,PRIORITY121,PRIORITY122,PRIORITY123,PRIORITY124,PRIORITY125,PRIORITY126,PRIORITY127 PRIORITY[%s] no description available 0x4 32 0x00000001 0xFFFFFFFF PRIORITY Interrupt source priority. The valid range of this field is 0-7. 0: Never interrupt 1-7: Interrupt source priority. The larger the value, the higher the priority. 0 32 read-write 4 0x4 PENDING0,PENDING1,PENDING2,PENDING3 PENDING[%s] no description available 0x1000 32 0x00000000 0xFFFFFFFF INTERRUPT The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. 0 32 read-write 4 0x4 TRIGGER0,TRIGGER1,TRIGGER2,TRIGGER3 TRIGGER[%s] no description available 0x1080 32 0x00000000 0xFFFFFFFF INTERRUPT The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. 0: Level-triggered interrupt 1: Edge-triggered interrupt 0 32 read-only NUMBER Number of supported interrupt sources and targets 0x1100 32 0xFFFFFFFF NUM_TARGET The number of supported targets 16 16 read-only NUM_INTERRUPT The number of supported interrupt sources 0 16 read-only INFO Version and the maximum priority 0x1104 32 0xFFFFFFFF MAX_PRIORITY The maximum priority supported 16 16 read-only VERSION The version of the PLIC design 0 16 read-only 2 0x80 target0,target1 TARGETINT[%s] no description available 0x2000 4 0x4 INTEN0,INTEN1,INTEN2,INTEN3 INTEN[%s] no description available 0x0 32 0x00000000 0xFFFFFFFF INTERRUPT The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. 0 32 read-write 2 0x1000 target0,target1 TARGETCONFIG[%s] no description available 0x200000 THRESHOLD Target0 priority threshold 0x0 32 0x00000000 0xFFFFFFFF THRESHOLD Interrupt priority threshold. 0 32 read-write CLAIM Target claim and complete 0x4 32 0x00000000 0x000003FF INTERRUPT_ID On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). 0 10 read-write PPS Preempted priority stack 0x400 32 0x00000000 0xFFFFFFFF PRIORITY_PREEMPTED Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. 0 32 read-write MCHTMR MCHTMR MCHTMR 0xe6000000 0x0 0x10 registers MTIME Machine Time 0x0 64 0x0000000000020210 0xFFFFFFFFFFFFFFFF MTIME Machine time 0 64 read-write MTIMECMP Machine Time Compare 0x8 64 0x0000000000020210 0xFFFFFFFFFFFFFFFF MTIMECMP Machine time compare 0 64 read-write PLICSW PLICSW PLIC_SW 0xe6400000 0x1000 0x1ff008 registers PENDING Pending status 0x1000 32 0x00000000 0x00000002 INTERRUPT writing 1 to trigger software interrupt 1 1 read-write INTEN Interrupt enable 0x2000 32 0x00000000 0x00000001 INTERRUPT enable software interrupt 0 1 read-write CLAIM Claim and complete. 0x200004 32 0x00000000 0x00000001 INTERRUPT_ID On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). 0 1 read-write CRC CRC CRC 0xf000c000 0x0 0x200 registers 8 0x40 0,1,2,3,4,5,6,7 CHN[%s] no description available 0x0 pre_set &index0 pre set for crc setting 0x0 32 0x00000000 0x000000FF PRE_SET 0: no pre set 1: CRC32 2: CRC32-AUTOSAR 3: CRC16-CCITT 4: CRC16-XMODEM 5: CRC16-MODBUS 1: CRC32 2: CRC32-autosar 3: CRC16-ccitt 4: CRC16-xmodem 5: CRC16-modbus 6: crc16_dnp 7: crc16_x25 8: crc16_usb 9: crc16_maxim 10: crc16_ibm 11: crc8_maxim 12: crc8_rohc 13: crc8_itu 14: crc8 15: crc5_usb 0 8 read-write clr chn&index0 clear crc result and setting 0x4 32 0x00000000 0x00000001 CLR write 1 to clr crc setting and result for its channel. always read 0. 0 1 read-write poly chn&index0 poly 0x8 32 0x00000000 0xFFFFFFFF POLY poly setting 0 32 read-write init_data chn&index0 init_data 0xc 32 0x00000000 0xFFFFFFFF INIT_DATA initial data of CRC 0 32 read-write xorout chn&index0 xorout 0x10 32 0x00000000 0xFFFFFFFF XOROUT XOR for CRC result 0 32 read-write misc_setting chn&index0 misc_setting 0x14 32 0x00000000 0x0101013F BYTE_REV 0: no wrap input byte order 1: wrap input byte order 24 1 read-write REV_OUT 0: no wrap output bit order 1: wrap output bit order 16 1 read-write REV_IN 0: no wrap input bit order 1: wrap input bit order 8 1 read-write POLY_WIDTH crc data length 0 6 read-write data chn&index0 data 0x18 32 0x00000000 0xFFFFFFFF DATA data for crc 0 32 read-write result chn&index0 result 0x1c 32 0x00000000 0xFFFFFFFF RESULT crc result 0 32 read-write UART0 UART0 UART 0xf0040000 0x4 0x3c registers IDLE_CFG Idle Configuration Register 0x4 32 0x00000000 0x00000BFF RXEN UART receive enable. 0 - hold RX input to high, avoide wrong data input when config pinmux 1 - bypass RX input from PIN software should set it after config pinmux 11 1 read-write RX_IDLE_COND IDLE Detection Condition 0 - Treat as idle if RX pin is logic one 1 - Treat as idle if UART state machine state is idle 9 1 read-write RX_IDLE_EN UART Idle Detect Enable 0 - Disable 1 - Enable it should be enabled if enable address match feature 8 1 read-write RX_IDLE_THR Threshold for UART Receive Idle detection (in terms of bits) 0 8 read-write Cfg Configuration Register 0x10 32 0x00000000 0xFFFFFFFF FIFOSIZE The depth of RXFIFO and TXFIFO 0: 16-byte FIFO 1: 32-byte FIFO 2: 64-byte FIFO 3: 128-byte FIFO 0 2 read-only OSCR Over Sample Control Register 0x14 32 0x00000010 0x0000001F OSC Over-sample control The value must be an even number; any odd value writes to this field will be converted to an even value. OSC=0: reserved OSC<=8: The over-sample ratio is 8 8 < OSC< 32: The over sample ratio is OSC 0 5 read-write FCRR FIFO Control Register config 0x18 32 0x00000000 0x000000FF RFIFOT Receiver FIFO trigger level 6 2 read-write TFIFOT Transmitter FIFO trigger level 4 2 read-write DMAE DMA enable 0: Disable 1: Enable 3 1 read-write TFIFORST Transmitter FIFO reset Write 1 to clear all bytes in the TXFIFO and resets its counter. The Transmitter Shift Register is not cleared. This bit will automatically be cleared. 2 1 write-only RFIFORST Receiver FIFO reset Write 1 to clear all bytes in the RXFIFO and resets its counter. The Receiver Shift Register is not cleared. This bit will automatically be cleared. 1 1 write-only FIFOE FIFO enable Write 1 to enable both the transmitter and receiver FIFOs. The FIFOs are reset when the value of this bit toggles. 0 1 read-write RBR Receiver Buffer Register (when DLAB = 0) UNION_20 0x20 32 0x00000000 0x000000FF RBR Receive data read port 0 8 read-only THR Transmitter Holding Register (when DLAB = 0) UNION_20 0x20 32 0x00000000 0x000000FF THR Transmit data write port 0 8 write-only DLL Divisor Latch LSB (when DLAB = 1) UNION_20 0x20 32 0x00000001 0x000000FF DLL Least significant byte of the Divisor Latch 0 8 read-write IER Interrupt Enable Register (when DLAB = 0) UNION_24 0x24 32 0x00000000 0x8000000F ERXIDLE Enable Receive Idle interrupt 0 - Disable Idle interrupt 1 - Enable Idle interrupt 31 1 read-write EMSI Enable modem status interrupt The interrupt asserts when the status of one of the following occurs: The status of modem_rin, modem_dcdn, modem_dsrn or modem_ctsn (If the auto-cts mode is disabled) has been changed. If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), modem_ctsn would be used to control the transmitter. 3 1 read-write ELSI Enable receiver line status interrupt 2 1 read-write ETHEI Enable transmitter holding register interrupt 1 1 read-write ERBI Enable received data available interrupt and the character timeout interrupt 0: Disable 1: Enable 0 1 read-write DLM Divisor Latch MSB (when DLAB = 1) UNION_24 0x24 32 0x00000000 0x000000FF DLM Most significant byte of the Divisor Latch 0 8 read-write IIR Interrupt Identification Register UNION_28 0x28 32 0x00000001 0x800000CF RXIDLE_FLAG UART IDLE Flag 0 - UART is busy 1 - UART is idle NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR 31 1 write-only FIFOED FIFOs enabled These two bits are 1 when bit 0 of the FIFO Control Register (FIFOE) is set to 1. 6 2 read-only INTRID Interrupt ID, see IIR2 for detail decoding 0 4 read-only FCR FIFO Control Register UNION_28 0x28 32 0x00000000 0x000000FF RFIFOT Receiver FIFO trigger level 6 2 write-only TFIFOT Transmitter FIFO trigger level 4 2 write-only DMAE DMA enable 0: Disable 1: Enable 3 1 write-only TFIFORST Transmitter FIFO reset Write 1 to clear all bytes in the TXFIFO and resets its counter. The Transmitter Shift Register is not cleared. This bit will automatically be cleared. 2 1 write-only RFIFORST Receiver FIFO reset Write 1 to clear all bytes in the RXFIFO and resets its counter. The Receiver Shift Register is not cleared. This bit will automatically be cleared. 1 1 write-only FIFOE FIFO enable Write 1 to enable both the transmitter and receiver FIFOs. The FIFOs are reset when the value of this bit toggles. 0 1 write-only LCR Line Control Register 0x2c 32 0x00000000 0x000000FF DLAB Divisor latch access bit 7 1 read-write BC Break control 6 1 read-write SPS Stick parity 1: Parity bit is constant 0 or 1, depending on bit4 (EPS). 0: Disable the sticky bit parity. 5 1 read-write EPS Even parity select 1: Even parity (an even number of logic-1 is in the data and parity bits) 0: Old parity. 4 1 read-write PEN Parity enable When this bit is set, a parity bit is generated in transmitted data before the first STOP bit and the parity bit would be checked for the received data. 3 1 read-write STB Number of STOP bits 0: 1 bits 1: The number of STOP bit is based on the WLS setting When WLS = 0, STOP bit is 1.5 bits When WLS = 1, 2, 3, STOP bit is 2 bits 2 1 read-write WLS Word length setting 0: 5 bits 1: 6 bits 2: 7 bits 3: 8 bits 0 2 read-write MCR Modem Control Register ( 0x30 32 0x00000000 0x00000032 AFE Auto flow control enable 0: Disable 1: The auto-CTS and auto-RTS setting is based on the RTS bit setting: When RTS = 0, auto-CTS only When RTS = 1, auto-CTS and auto-RTS 5 1 read-write LOOP Enable loopback mode 0: Disable 1: Enable 4 1 read-write RTS Request to send This bit controls the modem_rtsn output. 0: The modem_rtsn output signal will be driven HIGH 1: The modem_rtsn output signal will be driven LOW 1 1 read-write LSR Line Status Register 0x34 32 0x00000000 0x000000FF ERRF Error in RXFIFO In the FIFO mode, this bit is set when there is at least one parity error, framing error, or line break associated with data in the RXFIFO. It is cleared when this register is read and there is no more error for the rest of data in the RXFIFO. 7 1 read-only TEMT Transmitter empty This bit is 1 when the THR (TXFIFO in the FIFO mode) and the Transmitter Shift Register (TSR) are both empty. Otherwise, it is zero. 6 1 read-only THRE Transmitter Holding Register empty This bit is 1 when the THR (TXFIFO in the FIFO mode) is empty. Otherwise, it is zero. If the THRE interrupt is enabled, an interrupt is triggered when THRE becomes 1. 5 1 read-only LBREAK Line break This bit is set when the uart_sin input signal was held LOWfor longer than the time for a full-word transmission. A full-word transmission is the transmission of the START, data, parity, and STOP bits. It is cleared when this register is read. In the FIFO mode, this bit indicates the line break for the received data at the top of the RXFIFO. 4 1 read-only FE Framing error This bit is set when the received STOP bit is not HIGH. It is cleared when this register is read. In the FIFO mode, this bit indicates the framing error for the received data at the top of the RXFIFO. 3 1 read-only PE Parity error This bit is set when the received parity does not match with the parity selected in the LCR[5:4]. It is cleared when this register is read. In the FIFO mode, this bit indicates the parity error for the received data at the top of the RXFIFO. 2 1 read-only OE Overrun error This bit indicates that data in the Receiver Buffer Register (RBR) is overrun. 1 1 read-only DR Data ready. This bit is set when there are incoming received data in the Receiver Buffer Register (RBR). It is cleared when all of the received data are read. 0 1 read-only MSR Modem Status Register 0x38 32 0x00000000 0x00000011 CTS Clear to send 0: The modem_ctsn input signal is HIGH. 1: The modem_ctsn input signal is LOW. 4 1 read-only DCTS Delta clear to send This bit is set when the state of the modem_ctsn input signal has been changed since the last time this register is read. 0 1 read-only GPR GPR Register 0x3c 32 0x00000000 0x000000FF DATA A one-byte storage register 0 8 read-write UART1 UART1 UART 0xf0044000 UART2 UART2 UART 0xf0048000 UART3 UART3 UART 0xf004c000 UART4 UART4 UART 0xf0050000 UART5 UART5 UART 0xf0054000 UART6 UART6 UART 0xf0058000 UART7 UART7 UART 0xf005c000 PUART PUART UART 0xf4124000 I2C0 I2C0 I2C 0xf0060000 0x4 0x30 registers Cfg Configuration Register 0x10 32 0x00000001 0xFFFFFFFF FIFOSIZE FIFO Size: 0: 2 bytes 1: 4 bytes 2: 8 bytes 3: 16 bytes 0 2 read-only IntEn Interrupt Enable Register 0x14 32 0x00000000 0xFFFFFFFF CMPL Set to enable the Completion Interrupt. Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. Slave: interrupts when a transaction addressing the controller is completed. 9 1 read-write BYTERECV Set to enable the Byte Receive Interrupt. Interrupts when a byte of data is received Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. 8 1 read-write BYTETRANS Set to enable the Byte Transmit Interrupt. Interrupts when a byte of data is transmitted. 7 1 read-write START Set to enable the START Condition Interrupt. Interrupts when a START condition/repeated START condition is detected. 6 1 read-write STOP Set to enable the STOP Condition Interrupt Interrupts when a STOP condition is detected. 5 1 read-write ARBLOSE Set to enable the Arbitration Lose Interrupt. Master: interrupts when the controller loses the bus arbitration Slave: not available in this mode. 4 1 read-write ADDRHIT Set to enable the Address Hit Interrupt. Master: interrupts when the addressed slave returned an ACK. Slave: interrupts when the controller is addressed. 3 1 read-write FIFOHALF Set to enable the FIFO Half Interrupt. Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. 2 1 read-write FIFOFULL Set to enable the FIFO Full Interrupt. Interrupts when the FIFO is full. 1 1 read-write FIFOEMPTY Set to enabled the FIFO Empty Interrupt Interrupts when the FIFO is empty. 0 1 read-write Status Status Register 0x18 32 0x00000001 0xFFFFFFFF LINESDA Indicates the current status of the SDA line on the bus 1: high 0: low 14 1 read-only LINESCL Indicates the current status of the SCL line on the bus 1: high 0: low 13 1 read-only GENCALL Indicates that the address of the current transaction is a general call address: 1: General call 0: Not general call 12 1 read-only BUSBUSY Indicates that the bus is busy The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus 1: Busy 0: Not busy 11 1 read-only ACK Indicates the type of the last received/transmitted acknowledgement bit: 1: ACK 0: NACK 10 1 read-only CMPL Transaction Completion Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. 9 1 write-only BYTERECV Indicates that a byte of data has been received. 8 1 write-only BYTETRANS Indicates that a byte of data has been transmitted. 7 1 write-only START Indicates that a START Condition or a repeated START condition has been transmitted/received. 6 1 write-only STOP Indicates that a STOP Condition has been transmitted/received. 5 1 write-only ARBLOSE Indicates that the controller has lost the bus arbitration. 4 1 write-only ADDRHIT Master: indicates that a slave has responded to the transaction. Slave: indicates that a transaction is targeting the controller (including the General Call). 3 1 write-only FIFOHALF Transmitter: Indicates that the FIFO is half-empty. 2 1 read-only FIFOFULL Indicates that the FIFO is full. 1 1 read-only FIFOEMPTY Indicates that the FIFO is empty. 0 1 read-only Addr Address Register 0x1c 32 0x00000000 0xFFFFFFFF ADDR The slave address. For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid 0 10 read-write Data Data Register 0x20 32 0x00000000 0xFFFFFFFF DATA Write this register to put one byte of data to the FIFO. Read this register to get one byte of data from the FIFO. 0 8 read-write Ctrl Control Register 0x24 32 0x00905E00 0xFFFFFFFF DATACNT_HIGH Data counts in bytes. Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. Slave: the meaning of DataCnt depends on the DMA mode: If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. 24 8 read-write RESET_LEN reset clock cycles. the clock high/low time is defined by Setup.T_SCLHi, 50% duty cycle. 20 4 read-write RESET_HOLD_SCKIN set to hold input clock to high when reset is active 14 1 read-write RESET_ON set to send reset signals(just toggle clock bus defined by reset_len). this register is clered when reset is end, can't be cleared by software 13 1 read-write PHASE_START Enable this bit to send a START condition at the beginning of transaction. Master mode only. 12 1 read-write PHASE_ADDR Enable this bit to send the address after START condition. Master mode only. 11 1 read-write PHASE_DATA Enable this bit to send the data after Address phase. Master mode only. 10 1 read-write PHASE_STOP Enable this bit to send a STOP condition at the end of a transaction. Master mode only. 9 1 read-write DIR Transaction direction Master: Set this bit to determine the direction for the next transaction. 0: Transmitter 1: Receiver Slave: The direction of the last received transaction. 0: Receiver 1: Transmitter 8 1 read-write DATACNT Data counts in bytes. Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. Slave: the meaning of DataCnt depends on the DMA mode: If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. 0 8 read-write Cmd Command Register 0x28 32 0x00000000 0xFFFFFFFF CMD Write this register with the following values to perform the corresponding actions: 0x0: no action 0x1: issue a data transaction (Master only) 0x2: respond with an ACK to the received byte 0x3: respond with a NACK to the received byte 0x4: clear the FIFO 0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. 0 3 read-write Setup Setup Register 0x2c 32 0x05252100 0xFFFFFFFF T_SUDAT T_SUDAT defines the data setup time before releasing the SCL. Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) tpclk = PCLK period TPM = The multiplier value in Timing Parameter Multiplier Register 24 5 read-write T_SP T_SP defines the pulse width of spikes that must be suppressed by the input filter. Pulse width = T_SP * tpclk* (TPM+1) 21 3 read-write T_HDDAT T_HDDAT defines the data hold time after SCL goes LOW Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) 16 5 read-write T_SCLRADIO The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) 1: ratio = 2 0: ratio = 1 This field is only valid when the controller is in the master mode. 13 1 read-write T_SCLHI The HIGH period of generated SCL clock is defined by T_SCLHi. SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) The T_SCLHi value must be greater than T_SP and T_HDDAT values. This field is only valid when the controller is in the master mode. 4 9 read-write DMAEN Enable the direct memory access mode data transfer. 1: Enable 0: Disable 3 1 read-write MASTER Configure this device as a master or a slave. 1: Master mode 0: Slave mode 2 1 read-write ADDRESSING I2C addressing mode: 1: 10-bit addressing mode 0: 7-bit addressing mode 1 1 read-write IICEN Enable the I2C controller. 1: Enable 0: Disable 0 1 read-write TPM I2C Timing Paramater Multiplier 0x30 32 0x00000000 0xFFFFFFFF TPM A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). 0 5 read-write I2C1 I2C1 I2C 0xf0064000 I2C2 I2C2 I2C 0xf0068000 I2C3 I2C3 I2C 0xf006c000 SPI0 SPI0 SPI 0xf0070000 0x4 0x7c registers wr_trans_cnt Transfer count for write data 0x4 32 0x00000000 0xFFFFFFFF WRTRANCNT Transfer count for write data WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must be equal to RdTranCnt. 0 32 read-write rd_trans_cnt Transfer count for read data 0x8 32 0x00000000 0xFFFFFFFF RDTRANCNT Transfer count for read data RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must equal RdTranCnt. 0 32 read-write TransFmt Transfer Format Register 0x10 32 0x00020780 0xFFFF1F9F ADDRLEN Address length in bytes 0x0: 1 byte 0x1: 2 bytes 0x2: 3 bytes 0x3: 4 bytes 16 2 read-write DATALEN The length of each data unit in bits The actual bit number of a data unit is (DataLen + 1) 8 5 read-write DATAMERGE Enable Data Merge mode, which does automatic data split on write and data coalescing on read. This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. 7 1 read-write MOSIBIDIR Bi-directional MOSI in regular (single) mode 0x0: MOSI is uni-directional signal in regular mode. 0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two 4 1 read-write LSB Transfer data with the least significant bit first 0x0: Most significant bit first 0x1: Least significant bit first 3 1 read-write SLVMODE SPI Master/Slave mode selection 0x0: Master mode 0x1: Slave mode 2 1 read-write CPOL SPI Clock Polarity 0x0: SCLK is LOW in the idle states 0x1: SCLK is HIGH in the idle states 1 1 read-write CPHA SPI Clock Phase 0x0: Sampling data at odd SCLK edges 0x1: Sampling data at even SCLK edges 0 1 read-write DirectIO Direct IO Control Register 0x14 32 0x00003100 0x013F3F3F DIRECTIOEN Enable Direct IO 0x0: Disable 0x1: Enable 24 1 read-write HOLD_OE Output enable for the SPI Flash hold signal 21 1 read-write WP_OE Output enable for the SPI Flash write protect signal 20 1 read-write MISO_OE Output enable fo the SPI MISO signal 19 1 read-write MOSI_OE Output enable for the SPI MOSI signal 18 1 read-write SCLK_OE Output enable for the SPI SCLK signal 17 1 read-write CS_OE Output enable for SPI CS (chip select) signal 16 1 read-write HOLD_O Output value for the SPI Flash hold signal 13 1 read-write WP_O Output value for the SPI Flash write protect signal 12 1 read-write MISO_O Output value for the SPI MISO signal 11 1 read-write MOSI_O Output value for the SPI MOSI signal 10 1 read-write SCLK_O Output value for the SPI SCLK signal 9 1 read-write CS_O Output value for the SPI CS (chip select) signal 8 1 read-write HOLD_I Status of the SPI Flash hold signal 5 1 read-only WP_I Status of the SPI Flash write protect signal 4 1 read-only MISO_I Status of the SPI MISO signal 3 1 read-only MOSI_I Status of the SPI MOSI signal 2 1 read-only SCLK_I Status of the SPI SCLK signal 1 1 read-only CS_I Status of the SPI CS (chip select) signal 0 1 read-only TransCtrl Transfer Control Register 0x20 32 0x00000000 0xFFFFFFFF SLVDATAONLY Data-only mode (slave mode only) 0x0: Disable the data-only mode 0x1: Enable the data-only mode Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. 31 1 read-write CMDEN SPI command phase enable (Master mode only) 0x0: Disable the command phase 0x1: Enable the command phase 30 1 read-write ADDREN SPI address phase enable (Master mode only) 0x0: Disable the address phase 0x1: Enable the address phase 29 1 read-write ADDRFMT SPI address phase format (Master mode only) 0x0: Address phase is the regular (single) mode 0x1: The format of the address phase is the same as the data phase (DualQuad). 28 1 read-write TRANSMODE Transfer mode The transfer sequence could be 0x0: Write and read at the same time 0x1: Write only 0x2: Read only 0x3: Write, Read 0x4: Read, Write 0x5: Write, Dummy, Read 0x6: Read, Dummy, Write 0x7: None Data (must enable CmdEn or AddrEn in master mode) 0x8: Dummy, Write 0x9: Dummy, Read 0xa~0xf: Reserved 24 4 read-write DUALQUAD SPI data phase format 0x0: Regular (Single) mode 0x1: Dual I/O mode 0x2: Quad I/O mode 0x3: Reserved 22 2 read-write TOKENEN Token transfer enable (Master mode only) Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. 0x0: Disable the one-byte special token 0x1: Enable the one-byte special token 21 1 read-write WRTRANCNT Transfer count for write data WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must be equal to RdTranCnt. 12 9 read-write TOKENVALUE Token value (Master mode only) The value of the one-byte special token following the address phase for SPI read transfers. 0x0: token value = 0x00 0x1: token value = 0x69 11 1 read-write DUMMYCNT Dummy data count. The actual dummy count is (DummyCnt +1). The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) The Data pins are put into the high impedance during the dummy data phase. DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. 9 2 read-write RDTRANCNT Transfer count for read data RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must equal RdTranCnt. 0 9 read-write Cmd Command Register 0x24 32 0x00000000 0x000000FF CMD SPI Command 0 8 read-write Addr Address Register 0x28 32 0x00000000 0xFFFFFFFF ADDR SPI Address (Master mode only) 0 32 read-write Data Data Register 0x2c 32 0x00000000 0xFFFFFFFF DATA Data to transmit or the received data For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. 0 32 read-write Ctrl Control Register 0x30 32 0x00000000 0x0FFFFF1F CS_EN No description available 24 4 read-write TXTHRES Transmit (TX) FIFO Threshold The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. 16 8 read-write RXTHRES Receive (RX) FIFO Threshold The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. 8 8 read-write TXDMAEN TX DMA enable 4 1 read-write RXDMAEN RX DMA enable 3 1 read-write TXFIFORST Transmit FIFO reset Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. 2 1 read-write RXFIFORST Receive FIFO reset Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. 1 1 read-write SPIRST SPI reset Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. 0 1 read-write Status Status Register 0x34 32 0x00000000 0x33FFFF01 TXNUM_7_6 Number of valid entries in the Transmit FIFO 28 2 read-only RXNUM_7_6 Number of valid entries in the Receive FIFO 24 2 read-only TXFULL Transmit FIFO Full flag 23 1 read-only TXEMPTY Transmit FIFO Empty flag 22 1 read-only TXNUM_5_0 Number of valid entries in the Transmit FIFO 16 6 read-only RXFULL Receive FIFO Full flag 15 1 read-only RXEMPTY Receive FIFO Empty flag 14 1 read-only RXNUM_5_0 Number of valid entries in the Receive FIFO 8 6 read-only SPIACTIVE SPI register programming is in progress. In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. 0 1 read-only IntrEn Interrupt Enable Register 0x38 32 0x00000000 0x0000003F SLVCMDEN Enable the Slave Command Interrupt. Control whether interrupts are triggered whenever slave commands are received. (Slave mode only) 5 1 read-write ENDINTEN Enable the End of SPI Transfer interrupt. Control whether interrupts are triggered when SPI transfers end. (In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) 4 1 read-write TXFIFOINTEN Enable the SPI Transmit FIFO Threshold interrupt. Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. 3 1 read-write RXFIFOINTEN Enable the SPI Receive FIFO Threshold interrupt. Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. 2 1 read-write TXFIFOURINTEN Enable the SPI Transmit FIFO Underrun interrupt. Control whether interrupts are triggered when the Transmit FIFO run out of data. (Slave mode only) 1 1 read-write RXFIFOORINTEN Enable the SPI Receive FIFO Overrun interrupt. Control whether interrupts are triggered when the Receive FIFO overflows. (Slave mode only) 0 1 read-write IntrSt Interrupt Status Register 0x3c 32 0x00000000 0x0000003F SLVCMDINT Slave Command Interrupt. This bit is set when Slave Command interrupts occur. (Slave mode only) 5 1 write-only ENDINT End of SPI Transfer interrupt. This bit is set when End of SPI Transfer interrupts occur. 4 1 write-only TXFIFOINT TX FIFO Threshold interrupt. This bit is set when TX FIFO Threshold interrupts occur. 3 1 write-only RXFIFOINT RX FIFO Threshold interrupt. This bit is set when RX FIFO Threshold interrupts occur. 2 1 write-only TXFIFOURINT TX FIFO Underrun interrupt. This bit is set when TX FIFO Underrun interrupts occur. (Slave mode only) 1 1 write-only RXFIFOORINT RX FIFO Overrun interrupt. This bit is set when RX FIFO Overrun interrupts occur. (Slave mode only) 0 1 write-only Timing Interface Timing Register 0x40 32 0x00000000 0x00003FFF CS2SCLK The minimum time between the edges of SPI CS and the edges of SCLK. SCLK_period * (CS2SCLK + 1) / 2 12 2 read-write CSHT The minimum time that SPI CS should stay HIGH. SCLK_period * (CSHT + 1) / 2 8 4 read-write SCLK_DIV The clock frequency ratio between the clock source and SPI interface SCLK. SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. 0 8 read-write SlvSt Slave Status Register 0x60 32 0x00000000 0x0007FFFF UNDERRUN Data underrun occurs in the last transaction 18 1 write-only OVERRUN Data overrun occurs in the last transaction 17 1 read-write READY Set this bit to indicate that the ATCSPI200 is ready for data transaction. When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. 16 1 read-write USR_STATUS User defined status flags 0 16 read-write SlvDataCnt Slave Data Count Register 0x64 32 0x00000000 0x03FF03FF WCNT Slave transmitted data count 16 10 read-only RCNT Slave received data count 0 10 read-only SlvDataWCnt WCnt 0x68 32 0x00000000 0xFFFFFFFF VAL No description available 0 32 read-only SlvDataRCnt RCnt 0x6c 32 0x00000000 0xFFFFFFFF VAL No description available 0 32 read-only Config Configuration Register 0x7c 32 0x00004311 0x000043FF SLAVE Support for SPI Slave mode 14 1 read-only QUADSPI Support for Quad I/O SPI 9 1 read-only DUALSPI Support for Dual I/O SPI 8 1 read-only TXFIFOSIZE Depth of TX FIFO 0x0: 2 words 0x1: 4 words 0x2: 8 words 0x3: 16 words 0x4: 32 words 0x5: 64 words 0x6: 128 words 4 4 read-only RXFIFOSIZE Depth of RX FIFO 0x0: 2 words 0x1: 4 words 0x2: 8 words 0x3: 16 words 0x4: 32 words 0x5: 64 words 0x6: 128 words 0 4 read-only SPI1 SPI1 SPI 0xf0074000 SPI2 SPI2 SPI 0xf0078000 SPI3 SPI3 SPI 0xf007c000 GPTMR0 GPTMR0 TMR 0xf0080000 0x0 0x20c registers 4 0x40 ch0,ch1,ch2,ch3 CHANNEL[%s] no description available 0x0 CR Control Register 0x0 32 0x00000000 0x8003FFFF CNTUPT 1- update counter to new value as CNTUPTVAL This bit will be auto cleared after 1 cycle 31 1 write-only OPMODE 0: round mode 1: one-shot mode, timer will stopped at reload point. NOTE: reload irq will be always set at one-shot mode at end 17 1 read-write MONITOR_SEL set to monitor input signal high level time(chan_meas_high) clr to monitor input signal period(chan_meas_prd) 16 1 read-write MONITOR_EN set to monitor input signal period or high level time. When this bit is set, if detected period less than val_0 or more than val_1, will set related irq_sts * only can be used when trig_mode is selected as measure mode(100) * the time may not correct after reload, so monitor is disabled after reload point, and enabled again after two continul posedge. if no posedge after reload for more than val_1, will also assert irq_capt 15 1 read-write CNTRST 1- reset counter 14 1 read-write SYNCFLW 1- enable this channel to reset counter to reload(RLD) together with its previous channel. This bit is not valid for channel 0. 13 1 read-write SYNCIFEN 1- SYNCI is valid on its falling edge 12 1 read-write SYNCIREN 1- SYNCI is valid on its rising edge 11 1 read-write CEN 1- counter enable 10 1 read-write CMPINIT Output compare initial poliarity 1- The channel output initial level is high 0- The channel output initial level is low User should set this bit before set CMPEN to 1. 9 1 read-write CMPEN 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. 8 1 read-write DMASEL select one of DMA request: 00- CMP0 flag 01- CMP1 flag 10- Input signal toggle captured 11- RLD flag, counter reload; 6 2 read-write DMAEN 1- enable dma 5 1 read-write SWSYNCIEN 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set 4 1 read-write DBGPAUSE 1- counter will pause if chip is in debug mode 3 1 read-write CAPMODE This bitfield define the input capture mode 100: width measure mode, timer will calculate the input signal period and duty cycle 011: capture at both rising edge and falling edge 010: capture at falling edge 001: capture at rising edge 000: No capture 0 3 read-write 2 0x4 CMP0,CMP1 CMP[%s] no description available 0x4 32 0xFFFFFFF0 0xFFFFFFFF CMP compare value 0 0 32 read-write RLD Reload register 0xc 32 0xFFFFFFFF 0xFFFFFFFF RLD reload value 0 32 read-write CNTUPTVAL Counter update value register 0x10 32 0x00000000 0xFFFFFFFF CNTUPTVAL counter will be set to this value when software write cntupt bit in CR 0 32 read-write CAPPOS Capture rising edge register 0x20 32 0x00000000 0xFFFFFFFF CAPPOS This register contains the counter value captured at input signal rising edge 0 32 read-only CAPNEG Capture falling edge register 0x24 32 0x00000000 0xFFFFFFFF CAPNEG This register contains the counter value captured at input signal falling edge 0 32 read-only CAPPRD PWM period measure register 0x28 32 0x00000000 0xFFFFFFFF CAPPRD This register contains the input signal period when channel is configured to input capture measure mode. 0 32 read-only CAPDTY PWM duty cycle measure register 0x2c 32 0x00000000 0xFFFFFFFF MEAS_HIGH This register contains the input signal duty cycle when channel is configured to input capture measure mode. 0 32 read-only CNT Counter 0x30 32 0x00000000 0xFFFFFFFF COUNTER 32 bit counter value 0 32 read-only SR Status register 0x200 32 0x00000000 0xFFFFFFFF CH3CMP1F channel 3 compare value 1 match flag 15 1 write-only CH3CMP0F channel 3 compare value 1 match flag 14 1 write-only CH3CAPF channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. 13 1 write-only CH3RLDF channel 3 counter reload flag 12 1 write-only CH2CMP1F channel 2 compare value 1 match flag 11 1 write-only CH2CMP0F channel 2 compare value 1 match flag 10 1 write-only CH2CAPF channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. 9 1 write-only CH2RLDF channel 2 counter reload flag 8 1 write-only CH1CMP1F channel 1 compare value 1 match flag 7 1 write-only CH1CMP0F channel 1 compare value 1 match flag 6 1 write-only CH1CAPF channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. 5 1 write-only CH1RLDF channel 1 counter reload flag 4 1 write-only CH0CMP1F channel 1 compare value 1 match flag 3 1 write-only CH0CMP0F channel 1 compare value 1 match flag 2 1 write-only CH0CAPF channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. 1 1 write-only CH0RLDF channel 1 counter reload flag 0 1 write-only IRQEN Interrupt request enable register 0x204 32 0x00000000 0xFFFFFFFF CH3CMP1EN 1- generate interrupt request when ch3cmp1f flag is set 15 1 read-write CH3CMP0EN 1- generate interrupt request when ch3cmp0f flag is set 14 1 read-write CH3CAPEN 1- generate interrupt request when ch3capf flag is set 13 1 read-write CH3RLDEN 1- generate interrupt request when ch3rldf flag is set 12 1 read-write CH2CMP1EN 1- generate interrupt request when ch2cmp1f flag is set 11 1 read-write CH2CMP0EN 1- generate interrupt request when ch2cmp0f flag is set 10 1 read-write CH2CAPEN 1- generate interrupt request when ch2capf flag is set 9 1 read-write CH2RLDEN 1- generate interrupt request when ch2rldf flag is set 8 1 read-write CH1CMP1EN 1- generate interrupt request when ch1cmp1f flag is set 7 1 read-write CH1CMP0EN 1- generate interrupt request when ch1cmp0f flag is set 6 1 read-write CH1CAPEN 1- generate interrupt request when ch1capf flag is set 5 1 read-write CH1RLDEN 1- generate interrupt request when ch1rldf flag is set 4 1 read-write CH0CMP1EN 1- generate interrupt request when ch0cmp1f flag is set 3 1 read-write CH0CMP0EN 1- generate interrupt request when ch0cmp0f flag is set 2 1 read-write CH0CAPEN 1- generate interrupt request when ch0capf flag is set 1 1 read-write CH0RLDEN 1- generate interrupt request when ch0rldf flag is set 0 1 read-write GCR Global control register 0x208 32 0x00000000 0x0000000F SWSYNCT set this bitfield to trigger software counter sync event 0 4 read-write GPTMR1 GPTMR1 TMR 0xf0084000 GPTMR2 GPTMR2 TMR 0xf0088000 GPTMR3 GPTMR3 TMR 0xf008c000 GPTMR4 GPTMR4 TMR 0xf0090000 GPTMR5 GPTMR5 TMR 0xf0094000 GPTMR6 GPTMR6 TMR 0xf0098000 GPTMR7 GPTMR7 TMR 0xf009c000 NTMR0 NTMR0 TMR 0xf1110000 PTMR PTMR TMR 0xf4120000 MBX0A MBX0A MBX 0xf00a0000 0x0 0x24 registers CR Command Registers 0x0 32 0x00000000 0xFFFFFFFF TXRESET Reset TX Fifo and word. 31 1 read-write BARCTL Bus Access Response Control, when bit 15:14= 00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. 10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. 11: reserved. 14 2 read-write BEIE Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. 1, enable the bus access error interrupt. 0, disable the bus access error interrupt. 8 1 read-write TFMAIE TX FIFO message available interrupt enable. 1, enable the TX FIFO massage available interrupt. 0, disable the TX FIFO message available interrupt. 7 1 read-write TFMEIE TX FIFO message empty interrupt enable. 1, enable the TX FIFO massage empty interrupt. 0, disable the TX FIFO message empty interrupt. 6 1 read-write RFMAIE RX FIFO message available interrupt enable. 1, enable the RX FIFO massage available interrupt. 0, disable the RX FIFO message available interrupt. 5 1 read-write RFMFIE RX fifo message full interrupt enable. 1, enable the RX fifo message full interrupt. 0, disable the RX fifo message full interrupt. 4 1 read-write TWMEIE TX word message empty interrupt enable. 1, enable the TX word massage empty interrupt. 0, disable the TX word message empty interrupt. 1 1 read-write RWMVIE RX word message valid interrupt enable. 1, enable the RX word massage valid interrupt. 0, disable the RX word message valid interrupt. 0 1 read-write SR Status Registers 0x4 32 0x000000E2 0xFFFF3FFF RFVC RX FIFO valid message count 20 4 read-only TFEC TX FIFO empty message word count 16 4 read-only ERRRE bus Error for read when rx word message are still invalid, this bit is W1C bit. 1, read from word message when the word message are still invalid will cause this error bit set. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. 13 1 write-only EWTRF bus Error for write when tx word message are still valid, this bit is W1C bit. 1, write to word message when the word message are still valid will cause this error bit set. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. 12 1 write-only ERRFE bus Error for read when rx fifo empty, this bit is W1C bit. 1, read from a empty rx fifo will cause this error bit set. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. 11 1 write-only EWTFF bus Error for write when tx fifo full, this bit is W1C bit. 1, write to a fulled tx fifo will cause this error bit set. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. 10 1 write-only EAIVA bus Error for Accessing Invalid Address; this bit is W1C bit. 1, read and write to invalid address in the bus of this block, will set this bit. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. 9 1 write-only EW2RO bus Error for Write to Read Only address; this bit is W1C bit. 1, write to read only address happened in the bus of this block. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. 8 1 write-only TFMA TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. 1, TXFIFO message buffer has slot available 0, no slot available (fifo full) 7 1 read-write TFME TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. 1, no any message data in TXFIFO from other core. 0, there are some data in the 4x32 TX FIFO from other core yet. 6 1 read-write RFMA RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. 1, no any data in the 4x32 TXFIFO message buffer. 0, there are some data in the the 4x32 TXFIFO message buffer already. 5 1 read-only RFMF RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. 1, the other core had written 4x32 message in the RXFIFO. 0, no 4x32 RX FIFO message from other core yet. 4 1 read-only TWME TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. 1, means this core had write word message to TXREG. 0, means no valid word message in the TXREG yet. 1 1 read-only RWMV RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. 1, the other core had written word message in the RXREG. 0, no valid word message yet in the RXREG. 0 1 read-only TXREG Transmit word message to other core. 0x8 32 0x00000000 0xFFFFFFFF TXREG Transmit word message to other core. 0 32 write-only RXREG Receive word message from other core. 0xc 32 0x00000000 0xFFFFFFFF RXREG Receive word message from other core. 0 32 read-only 1 0x4 TXFIFO0 TXWRD[%s] no description available 0x10 32 0x00000000 0xFFFFFFFF TXFIFO TXFIFO for sending message to other core, FIFO size, 4x32 can write one of the word address to push data to the FIFO; can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. 0 32 write-only 1 0x4 RXFIFO0 RXWRD[%s] no description available 0x20 32 0x00000000 0xFFFFFFFF RXFIFO RXFIFO for receiving message from other core, FIFO size, 4x32 can read one of the word address to pop data to the FIFO; can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. 0 32 read-only MBX0B MBX0B MBX 0xf00a4000 MBX1A MBX1A MBX 0xf00a8000 MBX1B MBX1B MBX 0xf00ac000 EWDG0 EWDG0 EWDG 0xf00b0000 0x0 0x28 registers CTRL0 wdog ctrl register 0 Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits 0x0 32 0x00000000 0x2FE2F03F CLK_SEL clock select 0：bus clock 1：ext clock 29 1 read-write DIV_VALUE clock divider, the clock divider works as 2 ^ div_value for wdt counter 25 3 read-write WIN_EN window mode enable 24 1 read-write WIN_LOWER Once window mode is opened, the lower counter value to refresh wdt 00: 4/8 overtime value 01: 5/8 of overtime value 10: 6/8 of overtime value 11: 7/8 of overtime value 22 2 read-write CFG_LOCK The register is locked and unlock is needed before re-config registers Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. The register update needs to be finished in the required period defined by UPD_OT_TIME register 21 1 read-write OT_SELF_CLEAR overtime reset can be self released after 32 function cycles 17 1 read-write REF_OT_REQ If refresh event has to be limited into a period after refresh unlocked. Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter 15 1 read-write WIN_UPPER The upper threshold of window value The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value If this register value is zero, then no upper level limitation 12 3 read-write REF_LOCK WDT refresh has to be unlocked firstly once refresh lock is enable. 5 1 read-write REF_UNLOCK_MEC Unlock refresh mechanism 00: the required unlock password is the same with refresh_psd_register 01: the required unlock password is a ring shift left value of refresh_psd_register 10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is 11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1 3 2 read-write EN_DBG WTD enable or not in debug mode 2 1 read-write EN_LP WDT enable or not in low power mode 2'b00: wdt is halted once in low power mode 2'b01: wdt will work with 1/4 normal clock freq in low power mode 2'b10: wdt will work with 1/2 normal clock freq in low power mode 2'b11: wdt will work with normal clock freq in low power mode 0 2 read-write CTRL1 wdog ctrl register 1 Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits 0x4 32 0x00000000 0x00F200FC REF_FAIL_RST_EN Refresh violation will trigger an reset. These event will be taken as a refresh violation: 1) Not refresh in the window once window mode is enabled 2) Not unlock refresh firstly if unlock is required 3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. 4) Not write the required word to refresh wdt. 23 1 read-write REF_FAIL_INT_EN Refresh violation will trigger an interrupt 22 1 read-write UNL_REF_FAIL_RST_EN Refresh unlock fail will trigger a reset 21 1 read-write UNL_REF_FAIL_INT_EN Refresh unlock fail will trigger a interrupt 20 1 read-write OT_RST_EN WDT overtime will generate a reset 17 1 read-write CTL_VIO_RST_EN Ctrl update violation will trigger a reset The violation event is to try updating the locked register before unlock them 7 1 read-write CTL_VIO_INT_EN Ctrl update violation will trigger a interrupt 6 1 read-write UNL_CTL_FAIL_RST_EN Unlock register update failure will trigger a reset 5 1 read-write UNL_CTL_FAIL_INT_EN Unlock register update failure will trigger a interrupt 4 1 read-write PARITY_FAIL_RST_EN Parity error will trigger a reset A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits 3 1 read-write PARITY_FAIL_INT_EN Parity error will trigger a interrupt 2 1 read-write OT_RST_VAL wdog timeout reset counter value 0xc 32 0x00000000 0x0000FFFF OT_RST_VAL WDT timeout reset value 0 16 read-write WDT_REFRESH_REG wdog refresh register 0x10 32 0x00000000 0xFFFFFFFF WDT_REFRESH_REG Write this register by 32'h5A45_524F to refresh wdog Note: Reading this register can read back wdt real time counter value, while it is only used by debug purpose 0 32 write-only WDT_STATUS wdog status register 0x14 32 0x00000000 0x0000006F PARITY_ERROR parity error Write one to clear the bit 6 1 read-write OT_RST Timeout happens, a reset will happen once enable bit set This bit can be cleared only by refreshing wdt or reset 5 1 read-only CTL_UNL_FAIL Unlock ctrl reg update protection fail Write one to clear the bit 3 1 read-write CTL_VIO Violate register update protection mechanism Write one to clear the bit 2 1 read-write REF_UNL_FAIL Refresh unlock fail Write one to clear the bit 1 1 read-write REF_VIO Refresh fail Write one to clear the bit 0 1 read-write CFG_PROT ctrl register protection register 0x18 32 0x00000000 0x000FFFFF UPD_OT_TIME The period in which register update has to be in after unlock The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle 16 4 read-write UPD_PSD The password of unlocking register update 0 16 read-write REF_PROT refresh protection register 0x1c 32 0x00000000 0x0000FFFF REF_UNL_PSD The password to unlock refreshing 0 16 read-write WDT_EN Wdog enable 0x20 32 0x00000000 0x00000001 WDOG_EN Wdog is enabled, the re-written of this register is impacted by enable lock function 0 1 read-write REF_TIME Refresh period value 0x24 32 0x00000000 0x0000FFFF REFRESH_PERIOD The refresh period after refresh unlocked Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter 0 16 read-write EWDG1 EWDG1 EWDG 0xf00b4000 PEWDG PEWDG EWDG 0xf4128000 DMAMUX DMAMUX DMAMUX 0xf00c4000 0x0 0x100 registers 64 0x4 HDMA_MUX0,HDMA_MUX1,HDMA_MUX2,HDMA_MUX3,HDMA_MUX4,HDMA_MUX5,HDMA_MUX6,HDMA_MUX7,HDMA_MUX8,HDMA_MUX9,HDMA_MUX10,HDMA_MUX11,HDMA_MUX12,HDMA_MUX13,HDMA_MUX14,HDMA_MUX15,HDMA_MUX16,HDMA_MUX17,HDMA_MUX18,HDMA_MUX19,HDMA_MUX20,HDMA_MUX21,HDMA_MUX22,HDMA_MUX23,HDMA_MUX24,HDMA_MUX25,HDMA_MUX26,HDMA_MUX27,HDMA_MUX28,HDMA_MUX29,HDMA_MUX30,HDMA_MUX31,XDMA_MUX0,XDMA_MUX1,XDMA_MUX2,XDMA_MUX3,XDMA_MUX4,XDMA_MUX5,XDMA_MUX6,XDMA_MUX7,XDMA_MUX8,XDMA_MUX9,XDMA_MUX10,XDMA_MUX11,XDMA_MUX12,XDMA_MUX13,XDMA_MUX14,XDMA_MUX15,XDMA_MUX16,XDMA_MUX17,XDMA_MUX18,XDMA_MUX19,XDMA_MUX20,XDMA_MUX21,XDMA_MUX22,XDMA_MUX23,XDMA_MUX24,XDMA_MUX25,XDMA_MUX26,XDMA_MUX27,XDMA_MUX28,XDMA_MUX29,XDMA_MUX30,XDMA_MUX31 MUXCFG[%s] no description available 0x0 32 0x00000000 0x8000007F ENABLE DMA Mux Channel Enable Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. 0b - DMA Mux channel is disabled 1b - DMA Mux channel is enabled 31 1 read-write SOURCE DMA Channel Source Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" 0 7 read-write HDMA HDMA DMAV2 0xf00c8000 0x4 0x43c registers IDMisc ID Misc 0x4 32 0x00000000 0x0000FF00 DMASTATE DMA state machine localparam ST_IDLE = 3'b000; localparam ST_READ = 3'b001; localparam ST_READ_ACK = 3'b010; localparam ST_WRITE = 3'b011; localparam ST_WRITE_ACK = 3'b100; localparam ST_LL = 3'b101; localparam ST_END = 3'b110; localparam ST_END_WAIT = 3'b111; 13 3 read-only CURCHAN current channel in used 8 5 read-only DMACfg DMAC Configuration Register 0x10 32 0x00000000 0xC3FFFFFF CHAINXFR Chain transfer 0x0: Chain transfer is not configured 0x1: Chain transfer is configured 31 1 read-only REQSYNC DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. 0x0: Request synchronization is not configured 0x1: Request synchronization is configured 30 1 read-only DATAWIDTH AXI bus data width 0x0: 32 bits 0x1: 64 bits 0x2: 128 bits 0x3: 256 bits 24 2 read-only ADDRWIDTH AXI bus address width 0x18: 24 bits 0x19: 25 bits ... 0x40: 64 bits Others: Invalid 17 7 read-only CORENUM DMA core number 0x0: 1 core 0x1: 2 cores 16 1 read-only BUSNUM AXI bus interface number 0x0: 1 AXI bus 0x1: 2 AXI busses 15 1 read-only REQNUM Request/acknowledge pair number 0x0: 0 pair 0x1: 1 pair 0x2: 2 pairs ... 0x10: 16 pairs 10 5 read-only FIFODEPTH FIFO depth 0x4: 4 entries 0x8: 8 entries 0x10: 16 entries 0x20: 32 entries Others: Invalid 4 6 read-only CHANNELNUM Channel number 0x1: 1 channel 0x2: 2 channels ... 0x8: 8 channels Others: Invalid 0 4 read-only DMACtrl DMAC Control Register 0x14 32 0x00000000 0x00000001 RESET Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. Note: The software reset may cause the in-completion of AXI transaction. 0 1 write-only ChAbort Channel Abort Register 0x18 32 0x00000000 0xFFFFFFFF CHABORT Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) 0 32 write-only INTHALFSTS Harlf Complete Interrupt Status 0x24 32 0x00000000 0xFFFFFFFF STS half transfer done irq status 0 32 read-write INTTCSTS Trans Complete Interrupt Status Register 0x28 32 0x00000000 0xFFFFFFFF STS The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. 0x0: Channel n has no terminal count status 0x1: Channel n has terminal count status 0 32 write-only INTABORTSTS Abort Interrupt Status Register 0x2c 32 0x00000000 0xFFFFFFFF STS The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. 0x0: Channel n has no abort status 0x1: Channel n has abort status 0 32 write-only INTERRSTS Error Interrupt Status Register 0x30 32 0x00000000 0xFFFFFFFF STS The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: - Bus error - Unaligned address - Unaligned transfer width - Reserved configuration 0x0: Channel n has no error status 0x1: Channel n has error status 0 32 write-only ChEN Channel Enable Register 0x34 32 0x00000000 0xFFFFFFFF CHEN Alias of the Enable field of all ChnCtrl registers 0 32 read-only 32 0x20 ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7,ch8,ch9,ch10,ch11,ch12,ch13,ch14,ch15,ch16,ch17,ch18,ch19,ch20,ch21,ch22,ch23,ch24,ch25,ch26,ch27,ch28,ch29,ch30,ch31 CHCTRL[%s] no description available 0x40 Ctrl Channel &index0 Control Register 0x0 32 0x00000000 0xFFFFF01F INFINITELOOP set to loop current config infinitely 31 1 read-write HANDSHAKEOPT 0: one request to transfer one burst 1: one request to transfer all the data defined in ch_tts 30 1 read-write PRIORITY Channel priority level 0x0: Lower priority 0x1: Higher priority 29 1 read-write BURSTOPT set to change burst_size definition 28 1 read-write SRCBURSTSIZE Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x0: 1 transfer 0x1: 2 transfers 0x2: 4 transfers 0x3: 8 transfers 0x4: 16 transfers 0x5: 32 transfers 0x6: 64 transfers 0x7: 128 transfers 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers 0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception 24 4 read-write SRCWIDTH Source transfer width 0x0: Byte transfer 0x1: Half-word transfer 0x2: Word transfer 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception 21 3 read-write DSTWIDTH Destination transfer width. Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. 0x0: Byte transfer 0x1: Half-word transfer 0x2: Word transfer 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception 18 3 read-write SRCMODE Source DMA handshake mode 0x0: Normal mode 0x1: Handshake mode Normal mode is enabled and started by software set Enable bit; Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block 17 1 read-write DSTMODE Destination DMA handshake mode 0x0: Normal mode 0x1: Handshake mode the difference bewteen Source/Destination handshake mode is: the dma block will response hardware request after read in Source handshake mode; the dma block will response hardware request after write in Destination handshake mode; NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown. 16 1 read-write SRCADDRCTRL Source address control 0x0: Increment address 0x1: Decrement address 0x2: Fixed address 0x3: Reserved, setting the field with this value triggers the error exception 14 2 read-write DSTADDRCTRL Destination address control 0x0: Increment address 0x1: Decrement address 0x2: Fixed address 0x3: Reserved, setting the field with this value triggers the error exception 12 2 read-write INTHALFCNTMASK Channel half interrupt mask 0x0: Allow the half interrupt to be triggered 0x1: Disable the half interrupt 4 1 read-write INTABTMASK Channel abort interrupt mask 0x0: Allow the abort interrupt to be triggered 0x1: Disable the abort interrupt 3 1 read-write INTERRMASK Channel error interrupt mask 0x0: Allow the error interrupt to be triggered 0x1: Disable the error interrupt 2 1 read-write INTTCMASK Channel terminal count interrupt mask 0x0: Allow the terminal count interrupt to be triggered 0x1: Disable the terminal count interrupt 1 1 read-write ENABLE Channel enable bit 0x0: Disable 0x1: Enable 0 1 read-write TranSize Channel &index0Transfer Size Register 0x4 32 0x00000000 0x0FFFFFFF TRANSIZE Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. 0 28 read-write SrcAddr Channel &index0 Source Address Low Part Register 0x8 32 0x00000000 0xFFFFFFFF SRCADDRL Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. This address must be aligned to the source transfer size; otherwise, an error event will be triggered. 0 32 read-write ChanReqCtrl Channel &index0 DMA Request Control Register 0xc 32 0x00000000 0x1F1F0000 SRCREQSEL Source DMA request select. Select the request/ack handshake pair that the source device is connected to. 24 5 read-write DSTREQSEL Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. 16 5 read-write DstAddr Channel &index0 Destination Address Low Part Register 0x10 32 0x00000000 0xFFFFFFFF DSTADDRL Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. This address must be aligned to the destination transfer size; otherwise the error event will be triggered. 0 32 read-write LLPointer Channel &index0 Linked List Pointer Low Part Register 0x18 32 0x00000000 0xFFFFFFF8 LLPOINTERL Low part of the pointer to the next descriptor. The pointer must be double word aligned. 3 29 read-write XDMA XDMA DMAV2 0xf3008000 GPIOM GPIOM GPIOM 0xf00d8000 0x0 0x800 registers 16 0x80 gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz ASSIGN[%s] no description available 0x0 32 0x4 PIN00,PIN01,PIN02,PIN03,PIN04,PIN05,PIN06,PIN07,PIN08,PIN09,PIN10,PIN11,PIN12,PIN13,PIN14,PIN15,PIN16,PIN17,PIN18,PIN19,PIN20,PIN21,PIN22,PIN23,PIN24,PIN25,PIN26,PIN27,PIN28,PIN29,PIN30,PIN31 PIN[%s] no description available 0x0 32 0x00000000 0x80000303 LOCK lock fields in this register, lock can only be cleared by soc reset 0: fields can be changed 1: fields locked to current value, not changeable 31 1 read-write HIDE pin value visibility to gpios, bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio 8 2 read-write SELECT select which gpio controls chip pin, 0: soc gpio0; 2: cpu0 fastgpio 0 2 read-write ADC0 ADC0 ADC16 0xf00e0000 0x0 0x1464 registers 12 0x4 trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c CONFIG[%s] no description available 0x0 32 0x00000000 0xFF3F3F7F TRIG_LEN length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 30 2 write-only INTEN3 interrupt enable for 4th conversion 29 1 read-write CHAN3 channel number for 4th conversion 24 5 read-write INTEN2 interrupt enable for 3rd conversion 21 1 read-write CHAN2 channel number for 3rd conversion 16 5 read-write INTEN1 interrupt enable for 2nd conversion 13 1 read-write CHAN1 channel number for 2nd conversion 8 5 read-write QUEUE_EN preemption queue enable control 6 1 read-write INTEN0 interrupt enable for 1st conversion 5 1 read-write CHAN0 channel number for 1st conversion 0 5 read-write trg_dma_addr No description available 0x30 32 0x00000000 0xFFFFFFFC TRG_DMA_ADDR buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) 2 30 read-write trg_sw_sta No description available 0x34 32 0x00000000 0x0000001F TRG_SW_STA SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. 4 1 read-write TRIG_SW_INDEX which trigger for the SW trigger 0 for trig0a, 1 for trig0b… 3 for trig1a, …11 for trig3c 0 4 read-write 16 0x4 chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 BUS_RESULT[%s] no description available 0x400 32 0x00000000 0x0001FFFF VALID set after conversion finished if wait_dis is set, cleared after software read. The first time read with 0 will trigger one new conversion. If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. the result may not realtime if software read once and wait long time to read again 16 1 read-only CHAN_RESULT read this register will trigger one adc conversion. If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long 0 16 read-only buf_cfg0 No description available 0x500 32 0x00000000 0x00000001 WAIT_DIS set to disable read waiting, get result immediately but maybe not current conversion result. 0 1 read-write seq_cfg0 No description available 0x800 32 0x00000000 0x80000F1F CYCLE current dma write cycle bit 31 1 read-only SEQ_LEN sequence queue length, 0 for one, 0xF for 16 8 4 read-write RESTART_EN if set together with cont_en, HW will continue process the whole queue after trigger once. If cont_en is 0, this bit is not used 4 1 read-write CONT_EN if set, HW will continue process the queue till end(seq_len) after trigger once 3 1 read-write SW_TRIG SW trigger, pulse signal, cleared by HW one cycle later 2 1 write-only SW_TRIG_EN set to enable SW trigger 1 1 read-write HW_TRIG_EN set to enable external HW trigger, only trigger on posedge 0 1 read-write seq_dma_addr No description available 0x804 32 0x00000000 0xFFFFFFFC TAR_ADDR dma target address, should be 4-byte aligned 2 30 read-write seq_wr_addr No description available 0x808 32 0x00000000 0x00FFFFFF SEQ_WR_POINTER HW update this field after each dma write, it indicate the next dma write pointer. dma write address is (tar_addr+seq_wr_pointer)*4 0 24 read-only seq_dma_cfg No description available 0x80c 32 0x00000000 0x0FFF3FFF STOP_POS if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet 16 12 read-write DMA_RST set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. SW should clear all cycle bit in buffer to 0 before clear dma_rst 13 1 read-write STOP_EN set to stop dma if reach the stop_pos 12 1 read-write BUF_LEN dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 0 for 4byte; 0xFFF for 16kbyte. 0 12 read-write 16 0x4 cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 SEQ_QUE[%s] no description available 0x810 32 0x00000000 0x0000003F SEQ_INT_EN interrupt enable for current conversion 5 1 read-write CHAN_NUM_4_0 channel number for current conversion 0 5 read-write seq_high_cfg No description available 0x850 32 0x00000000 0x00FFFFFF STOP_POS_HIGH No description available 12 12 read-write BUF_LEN_HIGH No description available 0 12 read-write 16 0x10 chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 PRD_CFG[%s] no description available 0xc00 prd_cfg No description available 0x0 32 0x00000000 0x00001FFF PRESCALE 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx 8 5 read-write PRD conver period, with prescale. Set to 0 means disable current channel 0 8 read-write prd_thshd_cfg No description available 0x4 32 0x00000000 0xFFFFFFFF THSHDH threshold high, assert interrupt(if enabled) if result exceed high or low. 16 16 read-write THSHDL threshold low 0 16 read-write prd_result No description available 0x8 32 0x00000000 0x0000FFFF CHAN_RESULT adc convert result, update after each valid conversion. it may be updated period according to config, also may be updated due to other queue convert the same channel 0 16 read-only 16 0x4 chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 SAMPLE_CFG[%s] no description available 0x1000 32 0x00000000 0x00000FFF SAMPLE_CLOCK_NUMBER_SHIFT shift for sample clock number 9 3 read-write SAMPLE_CLOCK_NUMBER sample clock number, base on clock_period, default one period 0 9 read-write conv_cfg1 No description available 0x1104 32 0x00000000 0x000001FF CONVERT_CLOCK_NUMBER convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). 4 5 read-write CLOCK_DIVIDER clock_period, N half clock cycle per half adc cycle 0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3, ... 15 for 1:16 Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk 0 4 read-write adc_cfg0 No description available 0x1108 32 0x00000000 0xA0000001 SEL_SYNC_AHB set to 1 will enable sync AHB bus, to get better bus performance. Adc_clk must to be set to same as bus clock at this mode 31 1 read-write ADC_AHB_EN set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; 29 1 read-write PORT3_REALTIME set to enable trg queue stop other queues 0 1 read-write int_sts No description available 0x1110 32 0x00000000 0xFFE0FFFF TRIG_CMPT interrupt for one trigger conversion complete if enabled 31 1 read-write TRIG_SW_CFLCT No description available 30 1 read-write TRIG_HW_CFLCT No description available 29 1 read-write READ_CFLCT read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel 28 1 read-write SEQ_SW_CFLCT sequence queue conflict interrupt, set if HW or SW trigger received during conversion 27 1 read-write SEQ_HW_CFLCT No description available 26 1 read-write SEQ_DMAABT dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set 25 1 read-write SEQ_CMPT the whole sequence complete interrupt 24 1 read-write SEQ_CVC one conversion complete in seq_queue if related seq_int_en is set 23 1 read-write DMA_FIFO_FULL DMA fifo full interrupt, user need to check clock frequency if it's set. 22 1 read-write AHB_ERR set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr 21 1 read-write WDOG set if one chanel watch dog event triggered 0 16 read-write int_en No description available 0x1114 32 0x00000000 0xFFE0FFFF TRIG_CMPT interrupt for one trigger conversion complete if enabled 31 1 read-write TRIG_SW_CFLCT No description available 30 1 read-write TRIG_HW_CFLCT No description available 29 1 read-write READ_CFLCT read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel 28 1 read-write SEQ_SW_CFLCT sequence queue conflict interrupt, set if HW or SW trigger received during conversion 27 1 read-write SEQ_HW_CFLCT No description available 26 1 read-write SEQ_DMAABT dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set 25 1 read-write SEQ_CMPT the whole sequence complete interrupt 24 1 read-write SEQ_CVC one conversion complete in seq_queue if related seq_int_en is set 23 1 read-write DMA_FIFO_FULL DMA fifo full interrupt, user need to check clock frequency if it's set. 22 1 read-write AHB_ERR set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr 21 1 read-write WDOG set if one chanel watch dog event triggered 0 16 read-write ana_ctrl0 No description available 0x1200 32 0x00000000 0x00001004 ADC_CLK_ON set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. MUST set clock_period to 0 or 1 for adc16 reg access 12 1 read-write STARTCAL set to start the offset calibration cycle (Active H). user need to clear it after setting it. 2 1 read-write ana_status No description available 0x1210 32 0x00000000 0x00000080 CALON Indicates if the ADC is in calibration mode (Active H). 7 1 read-write 34 0x2 adc16_para00,adc16_para01,adc16_para02,adc16_para03,adc16_para04,adc16_para05,adc16_para06,adc16_para07,adc16_para08,adc16_para09,adc16_para10,adc16_para11,adc16_para12,adc16_para13,adc16_para14,adc16_para15,adc16_para16,adc16_para17,adc16_para18,adc16_para19,adc16_para20,adc16_para21,adc16_para22,adc16_para23,adc16_para24,adc16_para25,adc16_para26,adc16_para27,adc16_para28,adc16_para29,adc16_para30,adc16_para31,adc16_para32,adc16_para33 ADC16_PARAMS[%s] no description available 0x1400 16 0x0000 0xFFFF PARAM_VAL No description available 0 16 read-write adc16_config0 No description available 0x1444 32 0x00000000 0x01F07FFF REG_EN set to enable regulator 24 1 read-write BANDGAP_EN set to enable bandgap. user should set reg_en and bandgap_en before use adc16. 23 1 read-write CAL_AVG_CFG for average the calibration result. 0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; 4- 16 loops; 5-32 loops; others reserved 20 3 read-write PREEMPT_EN set to enable preemption feature 14 1 read-write CONV_PARAM conversion parameter 0 14 read-write adc16_config1 No description available 0x1460 32 0x00000000 0x00001F00 COV_END_CNT used for faster conversion, user can change it to get higher convert speed(but less accuracy). should set to (21-convert_clock_number+1). 8 5 read-write I2S0 I2S0 I2S 0xf0200000 0x0 0x80 registers CTRL Control Register 0x0 32 0x00000000 0xFFFFFFFF SFTRST_RX software reset the RX module if asserted to be 1'b1. Self-clear. 18 1 read-write SFTRST_TX software reset the TX module if asserted to be 1'b1. Self-clear. 17 1 read-write SFTRST_CLKGEN software reset the CLK GEN module if asserted to be 1'b1. Self-clear. 16 1 read-write TXDNIE TX buffer data needed interrupt enable 0: TXE interrupt masked 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. 15 1 read-write RXDAIE RX buffer data available interrupt enable 0: RXNE interrupt masked 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. 14 1 read-write ERRIE Error interrupt enable This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. 0: Error interrupt is masked 1: Error interrupt is enabled 13 1 read-write TX_DMA_EN Asserted to use DMA, else to use interrupt 12 1 read-write RX_DMA_EN Asserted to use DMA, else to use interrupt 11 1 read-write TXFIFOCLR Self-clear 10 1 read-write RXFIFOCLR Self-clear 9 1 read-write TX_EN enable for each TX data pad 5 4 read-write RX_EN enable for each RX data pad 1 4 read-write I2S_EN enable for the module 0 1 read-write RFIFO_FILLINGS Rx FIFO Filling Level 0x4 32 0x00000000 0xFFFFFFFF RX3 RX3 fifo fillings 24 8 read-only RX2 RX2 fifo fillings 16 8 read-only RX1 RX1 fifo fillings 8 8 read-only RX0 RX0 fifo fillings 0 8 read-only TFIFO_FILLINGS Tx FIFO Filling Level 0x8 32 0x00000000 0xFFFFFFFF TX3 TX3 fifo fillings 24 8 read-only TX2 TX2 fifo fillings 16 8 read-only TX1 TX1 fifo fillings 8 8 read-only TX0 TX0 fifo fillings 0 8 read-only FIFO_THRESH TX/RX FIFO Threshold setting. 0xc 32 0x00000000 0xFFFFFFFF TX TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. 8 8 read-write RX RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. 0 8 read-write STA Status Registers 0x10 32 0x00000000 0xFFFFFFFF TX_UD Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. 13 4 write-only RX_OV Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. 9 4 write-only TX_DN Asserted when tx fifo data are needed. 5 4 read-only RX_DA Asserted when rx fifo data are available. 1 4 read-only 4 0x4 DATA0,DATA1,DATA2,DATA3 RXD[%s] no description available 0x20 32 0x00000000 0xFFFFFFFF D No description available 0 32 read-only 4 0x4 DATA0,DATA1,DATA2,DATA3 TXD[%s] no description available 0x30 32 0x00000000 0xFFFFFFFF D No description available 0 32 write-only CFGR Configruation Regsiters 0x50 32 0x40000000 0xFFFFFFFF BCLK_GATEOFF Gate off the bclk. Asserted to gate-off the BCLK. 30 1 read-write BCLK_DIV Linear prescaler to generate BCLK from MCLK. BCLK_DIV [8:0] = 0: BCLK=No CLK. BCLK_DIV [8:0] = 1: BCLK=MCLK/1 BCLK_DIV [8:0] = n: BCLK=MCLK/(n). Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. 21 9 read-write INV_BCLK_OUT Invert the BCLK before sending it out to pad. Only valid in BCLK master mode 20 1 read-write INV_BCLK_IN Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode 19 1 read-write INV_FCLK_OUT Invert the FCLK before sending it out to pad. Only valid in FCLK master mode 18 1 read-write INV_FCLK_IN Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode 17 1 read-write INV_MCLK_OUT Invert the MCLK before sending it out to pad. Only valid in MCLK master mode 16 1 read-write INV_MCLK_IN Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode 15 1 read-write BCLK_SEL_OP asserted to use external clk source 14 1 read-write FCLK_SEL_OP asserted to use external clk source 13 1 read-write MCK_SEL_OP asserted to use external clk source 12 1 read-write FRAME_EDGE The start edge of a frame 0: Falling edge indicates a new frame (Just like standard I2S Philips standard) 1: Rising edge indicates a new frame 11 1 read-write CH_MAX CH_MAX[4:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. It must be an even number, so CH_MAX[0] is always 0. 5'h2: 2 channels 5'h4: 4 channels ... 5‘h10: 16 channels (max) 6 5 read-write TDM_EN TDM mode 0: not TDM mode 1: TDM mode 5 1 read-write STD I2S standard selection 00: I2S Philips standard. 01: MSB justified standard (left justified) 10: LSB justified standard (right justified) 11: PCM standard Note: For correct operation, these bits should be configured when the I2S is disabled. 3 2 read-write DATSIZ Data length to be transferred 00: 16-bit data length 01: 24-bit data length 10: 32-bit data length 11: Not allowed Note: For correct operation, these bits should be configured when the I2S is disabled. 1 2 read-write CHSIZ Channel length (number of bits per audio channel) 0: 16-bit wide 1: 32-bit wide The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Note: For correct operation, this bit should be configured when the I2S is disabled. 0 1 read-write MISC_CFGR Misc configuration Registers 0x58 32 0x00042000 0xFFFFEC01 MCLK_GATEOFF Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. 13 1 read-write MCLKOE Master clock output to pad enable 0: Master clock output is disabled 1: Master clock output is enabled Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. 0 1 read-write 4 0x4 DATA0,DATA1,DATA2,DATA3 RXDSLOT[%s] no description available 0x60 32 0x0000FFFF 0x0000FFFF EN No description available 0 16 read-write 4 0x4 DATA0,DATA1,DATA2,DATA3 TXDSLOT[%s] no description available 0x70 32 0x0000FFFF 0x0000FFFF EN No description available 0 16 read-write I2S1 I2S1 I2S 0xf0204000 I2S2 I2S2 I2S 0xf0208000 I2S3 I2S3 I2S 0xf020c000 DAO DAO DAO 0xf0210000 0x0 0x1c registers CTRL Control Register 0x0 32 0x00000000 0x000200FF HPF_EN Whether HPF is enabled. This HPF is used to filter out the DC part. 17 1 read-write MONO Asserted to let the left and right channel output the same value. 7 1 read-write RIGHT_EN Asserted to enable the right channel 6 1 read-write LEFT_EN Asserted to enable the left channel 5 1 read-write REMAP 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative 0: Don't use remap pwm version 4 1 read-write INVERT all the outputs are inverted before sending to pad 3 1 read-write FALSE_LEVEL the pad output in False run mode, or when the module is disabled 0: all low 1: all high 2: P-high, N-low 3. output is not enabled 1 2 read-write FALSE_RUN the module continues to consume data, but all the pads are constant, thus no audio out 0 1 read-write CMD Command Register 0x8 32 0x00000000 0x00000003 SFTRST Self-clear 1 1 read-write RUN Enable this module to run. 0 1 read-write RX_CFGR Configuration Register 0xc 32 0x00000000 0x00000FFF FRAME_EDGE The start edge of a frame 0: Falling edge indicates a new frame (Just like standard I2S Philips standard) 1: Rising edge indicates a new frame 11 1 read-write CH_MAX CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. It must be an even number, so CH_MAX[0] is always 0. 4'h2: 2 channels 4'h4: 4 channels etc 6 5 read-write TDM_EN TDM mode 0: not TDM mode 1: TDM mode 5 1 read-write STD I2S standard selection 00: I2S Philips standard. 01: MSB justified standard (left justified) 10: LSB justified standard (right justified) 11: PCM standard For more details on I2S standards. Note: For correct operation, these bits should be configured when the I2S is disabled. 3 2 read-write DATSIZ Data length to be transferred 00: 16-bit data length 01: 24-bit data length 10: 32-bit data length 11: Not allowed Note: For correct operation, these bits should be configured when the I2S is disabled. 1 2 read-write CHSIZ Channel length (number of bits per audio channel) 0: 16-bit wide 1: 32-bit wide The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Note: For correct operation, this bit should be configured when the I2S is disabled. 0 1 read-write RXSLT RX Slot Control Register 0x10 32 0x00000000 0xFFFFFFFF EN Slot enable for the channels. 0 32 read-write HPF_MA HPF A Coef Register 0x14 32 0x00000000 0xFFFFFFFF COEF Composite value of coef A of the Order-1 HPF 0 32 read-write HPF_B HPF B Coef Register 0x18 32 0x00000000 0xFFFFFFFF COEF coef B of the Order-1 HPF 0 32 read-write PDM PDM PDM 0xf0214000 0x0 0x34 registers CTRL Control Register 0x0 32 0x00000000 0x809FF7FF SFTRST software reset the module. Self-clear. 31 1 read-write SOF_FEDGE asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. 23 1 read-write USE_COEF_RAM Asserted to use Coef RAM instead of Coef ROM 20 1 read-write FILT_CRX_ERR_IE data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. 19 1 read-write OFIFO_OVFL_ERR_IE output fifo overflow error interrupt enable 18 1 read-write CIC_OVLD_ERR_IE CIC overload error interrupt enable 17 1 read-write CIC_SAT_ERR_IE Error interrupt enable This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. 0: Error interrupt is masked 1: Error interrupt is enabled 16 1 read-write DEC_AFT_CIC decimation rate after CIC. Now it is forced to be 3. 12 4 read-write CAPT_DLY Capture cycle delay>=0, should be less than PDM_CLK_HFDIV 7 4 read-write PDM_CLK_HFDIV The clock divider will work at least 4. 0: div-by-2, 1: div-by-4 . . . n: div-by-2*(n+1) 3 4 read-write PDM_CLK_DIV_BYPASS asserted to bypass the pdm clock divider 2 1 read-write PDM_CLK_OE pdm_clk_output_en 1 1 read-write HPF_EN pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. 0 1 read-write CH_CTRL Channel Control Register 0x4 32 0x00000000 0x00FF03FF CH_POL Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. 16 8 read-write CH_EN Asserted to enable the channel. Ch8 & 9 are refs. Ch0-7 are pdm mics. 0 10 read-write ST Status Register 0x8 32 0x00000000 0x0000000F FILT_CRX_ERR data accessed out of boundary error 3 1 write-only OFIFO_OVFL_ERR output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. 2 1 write-only CIC_OVLD_ERR CIC overload error. write 1 clear 1 1 write-only CIC_SAT_ERR CIC saturation. Write 1 clear 0 1 write-only CH_CFG Channel Configuration Register 0xc 32 0x00000000 0x000FFFFF CH9_TYPE No description available 18 2 read-write CH8_TYPE No description available 16 2 read-write CH7_TYPE No description available 14 2 read-write CH6_TYPE No description available 12 2 read-write CH5_TYPE No description available 10 2 read-write CH4_TYPE No description available 8 2 read-write CH3_TYPE No description available 6 2 read-write CH2_TYPE No description available 4 2 read-write CH1_TYPE No description available 2 2 read-write CH0_TYPE Type of Channel 0 2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) 2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) 0 2 read-write CIC_CFG CIC configuration register 0x10 32 0x00000000 0x0000FFFF POST_SCALE the shift value after CIC results. 10 6 read-write SGD Sigma_delta_order[1:0] 2'b00: 7 2'b01: 6 2'b10: 5 Others: unused 8 2 read-write CIC_DEC_RATIO CIC decimation factor 0 8 read-write CTRL_INBUF In Buf Control Register 0x14 32 0x00000000 0x3FFFFFFF MAX_PTR The buf size-1 for each channel 22 8 read-write PITCH The spacing between starting address of adjacent channels 11 11 read-write START_ADDR The starting address of channel 0 in filter data buffer 0 11 read-write CTRL_FILT0 Filter 0 Control Register 0x18 32 0x00000000 0x0000FFFF COEF_LEN_M0 Coef length of filter type 2'b00 in coef memory 8 8 read-write COEF_START_ADDR Starting address of Coef of filter type 2'b00 in coef memory 0 8 read-write CTRL_FILT1 Filter 1 Control Register 0x1c 32 0x00000000 0x0000FFFF COEF_LEN_M1 Coef length of filter type 2'b01 in coef memory 8 8 read-write COEF_START_ADDR Starting address of Coef of filter type 2'b01 in coef memory 0 8 read-write RUN Run Register 0x20 32 0x00000000 0x00000001 PDM_EN Asserted to enable the module 0 1 read-write MEMAddr Memory Access Address 0x24 32 0x00000000 0xFFFFFFFF ADDR 0--0x0FFFFFFF: COEF_RAM 0x10000000--0x1FFFFFFF: DATA_RAM 0 32 read-write MEMData Memory Access Data 0x28 32 0x00000000 0xFFFFFFFF DATA The data write-to/read-from buffer 0 32 read-write HPF_MA HPF A Coef Register 0x2c 32 0x00000000 0xFFFFFFFF COEF Composite value of coef A of the Order-1 HPF 0 32 read-write HPF_B HPF B Coef Register 0x30 32 0x00000000 0xFFFFFFFF COEF coef B of the Order-1 HPF 0 32 read-write SMIX SMIX SMIX 0xf0218000 0x0 0xac0 registers DMAC_ID DMAC_ID Register 0x0 32 0x00000001 0x0007FFFF REV Revision 0 19 read-only DMAC_TC_ST Transfer Complete Status 0x4 32 0x00000000 0xFFFFFFFF CH The terminal count status is set when a channel transfer finishes without abort or error events 0 26 write-only DMAC_ABRT_ST Transfer Abort Status 0x8 32 0x00000000 0xFFFFFFFF CH The abort status is set when a channel transfer is aborted 0 26 write-only DMAC_ERR_ST Transfer Error Status 0xc 32 0x00000000 0xFFFFFFFF CH The error status is set when a channel transfer encounters the following error events: . Bus error . Unaligned address . Unaligned transfer width . Reserved configuration 0 26 write-only DMAC_CTRL Control Register 0x20 32 0x00000000 0xFFFFFFFF SRST Software Reset 0 1 read-write DMAC_ABRT_CMD Abort Command Register 0x24 32 0x00000000 0xFFFFFFFF CH Write 1 to force the corresponding channel into abort status 0 26 write-only DMAC_CHEN Channel Enable Register 0x34 32 0x00000000 0xFFFFFFFF CH Write 1 to enable the corresponding channel 0 26 read-only 26 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25 DMA_CH[%s] no description available 0x40 CTL Channel N Control Register 0x0 32 0x00000000 0xFFEFFFEF SRCREQSEL Source DMA request select. Select the request/ack handshake pair that the source device is connected to. 26 5 read-write DSTREQSEL Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. 21 5 read-write PRIORITY 0x0: Lower priority 0x1: Higher priority 19 1 read-write SRCBURSTSIZE 0x0: 1 beat per transfer 0x1: 2 beats per transfer 0x2: 4 beats per transfer 0x3: 8 beats per transfer 0x4: 16 beats per transfer 0x5: 32 beats per transfer 0x6: 64 beats per transfer 0x7: 128 beats per transfer 15 4 read-write SRCWIDTH Source Transfer Beat Size: 0x0: Byte transfer 0x1: Half-word transfer 0x2: Word transfer 13 2 read-write DSTWIDTH Destination Transfer Beat Size: 0x0: Byte transfer 0x1: Half-word transfer 0x2: Word transfer 11 2 read-write SRCMODE DMA Source handshake mode 0x0: Normal mode 0x1: Handshake mode 10 1 read-write DSTMODE DMA Destination handshake mode 0x0: Normal mode 0x1: Handshake mode 9 1 read-write SRCADDRCTRL 0x0: Increment address 0x1: Decrement address 0x2: Fixed address 0x3: Reserved, setting the field with this value triggers an error exception 7 2 read-write DSTADDRCTRL 0x0: Increment address 0x1: Decrement address 0x2: Fixed address 0x3: Reserved, setting the field with this value triggers an error exception 5 2 read-write ABRT_INT_EN Abort interrupt enable 3 1 read-write ERR_INT_EN Err interrupt enable 2 1 read-write TC_INT_EN TC interrupt enable 1 1 read-write EN channel enable bit 0 1 read-write BURST_COUNT Channel N Source Total Beats Register 0x4 32 0x00000000 0xFFFFFFFF NUM the total number of source beats 0 32 read-write SrcAddr Channel N Source Register 0x8 32 0x00000000 0xFFFFFFFF PTR source address 0 32 read-write DstAddr Channel N Destination Register 0x10 32 0x00000000 0xFFFFFFFF PTR destination address 0 32 read-write LLP Channel N Linked List Pointer Register 0x18 32 0x00000000 0xFFFFFFFF PTR the address pointer for the linked list descriptor 0 32 read-write CALSAT_ST SMIX Cal Saturation Status Register 0x800 32 0x00000000 0xFFFFFFFF DST DST CAL_SAT_ERR. W1C 30 2 write-only SRC SRC CAL_SAT_ERR. W1C 0 14 write-only FDOT_DONE_ST SMIX Fade-Out Done Status Register 0x804 32 0x00000000 0xFFFFFFFF DST DST fadeout done. W1C 30 2 write-only SRC SRC fadeout done. W1C 0 14 write-only DATA_ST SMIX Data Status Register 0x808 32 0x00000000 0xFFFFFFFF DST_DA DST data available 30 2 read-only DST_UNDL DST data underflow 28 2 read-only SRC_DN SRC data needed 0 14 read-only 2 0x40 0,1 DST_CH[%s] no description available 0x840 CTRL SMIX Dstination N Control Register 0x0 32 0x00000000 0xFFFFFFFF DATA_UNFL_IE Data Underflow Error IntEn 20 1 read-write THRSH FIFO threshold for DMA or Int. >= will generate req. Must be greater or equal than 8. The read burst of DMA should make the fillings in the buffer be greater than 4. 12 8 read-write CALSAT_INT_EN Cal Saturation IntEn 11 1 read-write DA_INT_EN Data Available IntEn 10 1 read-write ADEACTFADEOUT_EN AutoDeactAfterFadeOut_En: Asserted to enter de-activated mode after fade-out done 9 1 read-write FADEOUT_DONE_IE Fade-Out interrupt enable 8 1 read-write DST_DEACT de-activate the destination channel 7 1 read-write DST_ACT activate the destination channel 6 1 read-write DSTFADOUT_MEN Manual FadeOut_Ctrl for destionation. Auto clear. 5 1 read-write DSTFADOUT_AEN Automatically FadeOut_Ctrl for destionation. Only effective after DST_AFADEOUT is assigned a non-zero value 4 1 read-write DSTFADIN_EN FadeIn_Ctrl for destionation. Auto clear. 3 1 read-write DST_EN Dst enabled. When disabled, clear the FIFO pointers. 2 1 read-write SOFTRST Soft reset 1 1 read-write MIXER_EN mixer function enable. 0 1 read-write GAIN SMIX Dstination N Gain Register 0x4 32 0x00000000 0xFFFFFFFF VAL Unsigned Int, with 12 fractional bits. . The top 3 bits are for shift. Same as SHFT_CTR[2:0] 0 15 read-write BUFSIZE SMIX Dstination N Max Index Register 0x8 32 0x00000000 0xFFFFFFFF MAX_IDX The total length of the dst stream -1. If zero, means there is no end of the stream. 0 32 read-write FADEIN SMIX Dstination N Fade-In Configuration Register 0xc 32 0x00000000 0xFFFFFFFF DELTA Fade-in delta for linear fading in from 0 to 1 (about at most 20s for 48kHz sampled sound) (Using only top 14 bits for mul) 0 20 read-write FADEOUT SMIX Dstination N Fade-Out Configuration Register 0x10 32 0x00000000 0xFFFFFFFF DELTA Fade out in 2^DELTA samples. Now DELTA can be at most 14。 0 20 read-write ST SMIX Dstination N Status Register 0x14 32 0x00000000 0xFFFFFFFF FIFO_FILLINGS destination channel output FIFO fillings 6 9 read-only FDOUT_DONE Fade-Out Done. W1C 5 1 read-only CALSAT Saturate Error Found. W1C 4 1 read-only DA Data Available 3 1 read-only MODE The modes are: Mode 0: Disabled: after reset. Program the registers, and DSTn_CTRL [DST_EN] to enter Mode 1. Mode 1: Enabled and not-activated. wait for DSTn_CTRL [DSTFADIN_EN] or DSTn_CTRL [DST_ACT], jump to Mode 3 or Mode 4 based on whether Fade-in enabled. Mode 3: Enabled and activated and fade-in in progress: Can not be fade out. Will send data to DMA. Jump to Mode 4 after fadin op done. Mode 4: Enabled and activated and done fade-in, no fade-out yet: Can be fade out. Will send data to DMA. Mode 5: Enabled and activated and fade-out in progress: After faded out OP. Will send data to DMA. Will transfer to mode 6 or mode 7 depending on the DSTn_CTRL [ADeactFadeOut_En] cfg Mode 6: Enabled and activated and faded-out: faded out is done. Will send data to DMA. Will transfer to mode 7 if manual deactivated. Mode 7: Enabled and De-activated: If configured to enter this mode, after auto or manuallly fade-out, or after manual de-activated. Won't send data to DMA. Won't gen data avail signals. Intf register can be programmed. Will change to Mode 3 or Mode 4 after manual ACT or Fade-in CMD. Will transfer to Mode 0 if DSTn_CTRL [DST_EN] is assigned 0. To support a new stream or, to continue the old stream after a pause. 0 3 read-only Data SMIX Dstination N Data Out Register 0x18 32 0x00000000 0xFFFFFFFF VAL Output data buffer 0 32 read-only SOURCE_EN SMIX Dstination N Source Enable Register 0x20 32 0x00000000 0xFFFFFFFF VAL After enabled, Data needed req will be asserted. DMA can feed in data. The channel will join in the sum operation of mixer operation. 0 8 read-write SOURCE_ACT SMIX Dstination N Source Activation Register 0x24 32 0x00000000 0xFFFFFFFF VAL Manually Activate the channel 0 8 write-only SOURCE_DEACT SMIX Dstination N Source De-Activation Register 0x28 32 0x00000000 0xFFFFFFFF VAL Manually DeActivate the channel 0 8 write-only SOURCE_FADEIN_CTRL SMIX Dstination N Source Fade-in Control Register 0x2c 32 0x00000000 0xFFFFFFFF AOP Asserted to start fade-in operation. When the amplification factors are stable, auto clear. 0 8 read-write DEACT_ST SMIX Dstination N Source Deactivation Status Register 0x30 32 0x00000000 0xFFFFFFFF DST_DEACT Asserted when in de-active mode 31 1 read-only SRC_DEACT_ST Asserted when in de-active mode 0 8 read-only SOURCE_MFADEOUT_CTRL SMIX Dstination N Source Manual Fade-out Control Register 0x34 32 0x00000000 0xFFFFFFFF OP Asserted to start fade-out operation. When the amplification factors are stable, auto clear. 0 8 read-write 14 0x20 0,1,2,3,4,5,6,7,8,9,10,11,12,13 SOURCE_CH[%s] no description available 0x900 CTRL SMIX Source N Control Register 0x0 32 0x00000000 0xFFFFFFC7 FIFO_RESET Asserted to reset FIFO pointer. Cleared to exit reset state. 21 1 read-write THRSH FIFO threshold for DMA or Int. <= will generate req. Must be greater or equal than 8. This threshold is also used to trgger the internal FIR operation. To avoid the reading and writing to the same address in the memory block, the threshold should greater than 4. 13 8 read-write CALSAT_INT_EN Cal Saturation IntEn 12 1 read-write DN_INT_EN Data Needed IntEn 11 1 read-write SHFT_CTRL Shift operation after FIR 0: no shift (when no upsampling or up-sampling-by-2 or up-sampling-by-3) 1: left-shift-by-1 (when up-sampling-by-4 or up-sampling-by-6) 2: left-shift-by-1 (when up-sampling-by-8 or up-sampling-by-12) 7: /2 (when rate /2) Other n: shift-left-by-n, but not suggested to be used. 8 3 read-write AUTODEACTAFTERFADEOUT_EN Asserted to enter de-activated mode after fade-out done 7 1 read-write FADEOUT_DONE_IE Fade-Out interrupt enable 6 1 read-write RATECONV 0: no rate conversion 1: up-conversion x2 2: up-conversion x3 3: up-conversion x4 4: up-conversion x6 5: up-conversion x8 6: up-conversion x12 7: down-conversion /2 0 3 read-write GAIN SMIX Source N Gain Register 0x4 32 0x00000000 0xFFFFFFFF VAL Unsigned Int, with 12 fractional bits. The top 3 bits are for shift. Same as SHFT_CTR[2:0]. 0 15 read-write FADEIN SMIX Source N Fade-in Control Register 0x8 32 0x00000000 0xFFFFFFFF DELTA Fade -in confg. 0 20 read-write FADEOUT SMIX Source N Fade-out Control Register 0xc 32 0x00000000 0xFFFFFFFF DELTA Fade out in 2^DELTA samples. Now DELTA can be at most 14。 0 20 read-write BufSize SMIX Source N Buffer Size Register 0x10 32 0x00000000 0xFFFFFFFF MAXIDX unit as 16-bits per sample. Zero means no length limit. = Act Len-1. The actual length is the up_rate*(input_data_length-4). If the filter processing is down-sampling, the value of up_rate above is 1. If the filter processing is up-sampling, the value of up_rate above is the up-sampling rate. 0 32 read-write ST SMIX Source N Status Register 0x14 32 0x00000000 0x0007FFFF FIFO_FILLINGS The fillings of input FIFO. 10 9 read-only FDOUT_DONE Fade-Out Done. W1C 9 1 write-only CALSAT Calculation saturation status. W1C 8 1 write-only DN Data needed flag 7 1 read-only FIRPHASE the poly phase counter 3 4 read-only MODE The modes are: Mode 0: Disabled: after reset. Program the registers, and DSTx_SRC_EN[n] to enter Mode 1. Mode 1: Enabled but not activated: After Enabled. Data needed signal can send out, can receive DMA data. Will enter Mode 2 after manual ACT or Fade-in CMD Mode 2: Enabled and activated and buffer feed-in in progress: Can not be fade out. Will consume data from DMA. If not enter due to Fade-in CMD, will enter Mode 4, else enter Mode 3. This mode is used to make the channel in MIX only after initial data are ready, thus will not stall mix operation due to the lackness of data of this channel omly. Mode 3: Enabled and activated and fade-in in progress: Can not be fade out. Will consume data from DMA. Mode 4: Enabled and activated and done fade-in, no fade-out yet: Can be fade out. Will consume data from DMA. Mode 5: Enabled and activated and fade-out in progress: After faded out done. Will consume data from DMA. Will transfer to mode 6 or mode 7 depending on the SRCn_CTRL[AutoDeactAfterFadeOut_En] cfg Mode 6: Enabled and activated and faded-out: faded out is done. Will consume data from DMA. Will transfer to mode 7 if manual deactivated. Mode 7: Enabled and De-activated: If configured to enter this mode, after auto or manuallly fade-out, or after manual de-activated. Won't consume data from DMA. Won't gen data needed signals. Intf register can be programmed. Will change to Mode 2 after manual ACT or Fade-in CMD. Will transfer to Mode 0 if DSTx_SRC_EN[n] is assigned 0. To support a new stream or, to continue the old stream after a pause. 0 3 read-only Data SMIX Source N Data Input Register 0x18 32 0x00000000 0xFFFFFFFF VAL Data input register 0 32 write-only MCAN0 MCAN0 MCAN 0xf0280000 0x4 0x29fc registers ENDN endian register 0x4 32 0x87654321 0xFFFFFFFF EVT Endianness Test Value The endianness test value is 0x87654321. 0 32 read-only DBTP data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set 0xc 32 0x00000A33 0x009F1FFF TDC transmitter delay compensation enable 0= Transmitter Delay Compensation disabled 1= Transmitter Delay Compensation enabled 23 1 read-write DBRP Data Bit Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 16 5 read-write DTSEG1 Data time segment before sample point Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. 8 5 read-write DTSEG2 Data time segment after sample point Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. 4 4 read-write DSJW Data (Re)Synchronization Jump Width Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 0 4 read-write TEST test register 0x10 32 0x00000000 0x003F3FF0 SVAL Started Valid 0= Value of TXBNS not valid 1= Value of TXBNS valid 21 1 read-only TXBNS Tx Buffer Number Started Tx Buffer number of message whose transmission was started last. Valid when SVAL is set. Valid values are 0 to 31. 16 5 read-only PVAL Prepared Valid 0= Value of TXBNP not valid 1= Value of TXBNP valid 13 1 read-only TXBNP Tx Buffer Number Prepared Tx Buffer number of message that is ready for transmission. Valid when PVAL is set.Valid values are 0 to 31. 8 5 read-only RX Receive Pin Monitors the actual value of pin m_can_rx 0= The CAN bus is dominant (m_can_rx = ‘0’) 1= The CAN bus is recessive (m_can_rx = ‘1’) 7 1 read-only TX Control of Transmit Pin 00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time 01 Sample Point can be monitored at pin m_can_tx 10 Dominant (‘0’) level at pin m_can_tx 11 Recessive (‘1’) at pin m_can_tx 5 2 read-write LBCK Loop Back Mode 0= Reset value, Loop Back Mode is disabled 1= Loop Back Mode is enabled 4 1 read-write RWD ram watchdog 0x14 32 0x00000000 0x0000FFFF WDV Watchdog Value Actual Message RAM Watchdog Counter Value. 8 8 read-only WDC Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled. 0 8 read-write CCCR CC control register 0x18 32 0x00000001 0x0000FFFF NISO Non ISO Operation If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 0= CAN FD frame format according to ISO 11898-1:2015 1= CAN FD frame format according to Bosch CAN FD Specification V1.0 Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015. 15 1 read-write TXP Transmit Pause If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Section 3.5). 0= Transmit pause disabled 1= Transmit pause enabled 14 1 read-write EFBI Edge Filtering during Bus Integration 0= Edge filtering disabled 1= Two consecutive dominant tq required to detect an edge for hard synchronization 13 1 read-write PXHD Protocol Exception Handling Disable 0= Protocol exception handling enabled 1= Protocol exception handling disabled Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition. 12 1 read-write WMM Wide Message Marker Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. 0= 8-bit Message Marker used 1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO 11 1 read-write UTSU Use Timestamping Unit When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. 0= Internal time stamping 1= External time stamping by TSU Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. In this case bit UTSU is fixed to zero by synthesis. 10 1 read-write BRSE Bit Rate Switch Enable 0= Bit rate switching for transmissions disabled 1= Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated. 9 1 read-write FDOE FD Operation Enable 0= FD operation disabled 1= FD operation enabled 8 1 read-write TEST Test Mode Enable 0= Normal operation, register TEST holds reset values 1= Test Mode, write access to register TEST enabled 7 1 read-write DAR Disable Automatic Retransmission 0= Automatic retransmission of messages not transmitted successfully enabled 1= Automatic retransmission disabled 6 1 read-write MON Bus Monitoring Mode Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. 0= Bus Monitoring Mode is disabled 1= Bus Monitoring Mode is enabled 5 1 read-write CSR Clock Stop Request 0= No clock stop is requested 1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. 4 1 read-write CSA Clock Stop Acknowledge 0= No clock stop acknowledged 1= M_CAN may be set in power down by stopping m_can_hclk and m_can_cclk 3 1 read-only ASM Restricted Operation Mode Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. 0= Normal CAN operation 1= Restricted Operation Mode active 2 1 read-write CCE Configuration Change Enable 0= The CPU has no write access to the protected configuration registers 1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’) 1 1 read-write INIT Initialization 0= Normal Operation 1= Initialization is started 0 1 read-write NBTP nominal bit timing and prescaler register 0x1c 32 0x06000A03 0xFFFFFF7F NSJW Nominal (Re)Synchronization Jump Width Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 25 7 read-write NBRP Nominal Bit Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 16 9 read-write NTSEG1 Nominal Time segment before sample point Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. 8 8 read-write NTSEG2 Nominal Time segment after sample point Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. 0 7 read-write TSCC timestamp counter configuration 0x20 32 0x00000000 0x000F0003 TCP Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1…16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 16 4 read-write TSS timestamp Select 00= Timestamp counter value always 0x0000 01= Timestamp counter value incremented according to TCP 10= External timestamp counter value used 11= Same as “00” 0 2 read-write TSCV timestamp counter value 0x24 32 0x00000000 0x0000FFFF TSC Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. 0 16 read-only TOCC timeout counter configuration 0x28 32 0xFFFF0000 0xFFFF0007 TOP Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period. 16 16 read-write TOS Timeout Select When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. 00= Continuous operation 01= Timeout controlled by Tx Event FIFO 10= Timeout controlled by Rx FIFO 0 11= Timeout controlled by Rx FIFO 1 1 2 read-write RP Enable Timeout Counter 0= Timeout Counter disabled 1= Timeout Counter enabled 0 1 read-write TOCV timeout counter value 0x2c 32 0x0000FFFF 0x0000FFFF TOC Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. 0 16 read-only ECR error counter register 0x40 32 0x00000000 0x00FFFFFF CEL CAN Error Logging The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. 16 8 read-only RP Receive Error Passive 0= The Receive Error Counter is below the error passive level of 128 1= The Receive Error Counter has reached the error passive level of 128 15 1 read-only REC Receive Error Counter Actual state of the Receive Error Counter, values between 0 and 127 8 7 read-only TEC Transmit Error Counter Actual state of the Transmit Error Counter, values between 0 and 255 Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. 0 8 read-only PSR protocol status register 0x44 32 0x00000707 0x007F7FFF TDCV Transmitter Delay Compensation Value Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. 16 7 read-only PXE Protocol Exception Event 0= No protocol exception event occurred since last read access 1= Protocol exception event occurred Note: Byte access: Reading byte 0 will reset PXE, reading bytes 3/2/1 has no impact. 14 1 read-only RFDF Received a CAN FD Message This bit is set independent of acceptance filtering. 0= Since this bit was reset by the CPU, no CAN FD message has been received 1= Message in CAN FD format with FDF flag set has been received Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. 13 1 read-only RBRS BRS flag of last received CAN FD Message This bit is set together with RFDF, independent of acceptance filtering. 0= Last received CAN FD message did not have its BRS flag set 1= Last received CAN FD message had its BRS flag set Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. 12 1 read-only RESI ESI flag of last received CAN FD Message This bit is set together with RFDF, independent of acceptance filtering. 0= Last received CAN FD message did not have its ESI flag set 1= Last received CAN FD message had its ESI flag set Note: Byte access: Reading byte 0 will reset RESI, reading bytes 3/2/1 has no impact. 11 1 read-only DLEC Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. Note: Byte access: Reading byte 0 will set DLEC to “111”, reading bytes 3/2/1 has no impact. 8 3 read-only BO Bus_Off Status 0= The M_CAN is not Bus_Off 1= The M_CAN is in Bus_Off state 7 1 read-only EW Warning Status 0= Both error counters are below the Error_Warning limit of 96 1= At least one of error counter has reached the Error_Warning limit of 96 6 1 read-only EP Error Passive 0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1= The M_CAN is in the Error_Passive state 5 1 read-only ACT Activity Monitors the module’s CAN communication state. 00= Synchronizing - node is synchronizing on CAN communication 01= Idle - node is neither receiver nor transmitter 10= Receiver - node is operating as receiver 11= Transmitter - node is operating as transmitter Note: ACT is set to “00” by a Protocol Exception Event. 3 2 read-only LEC Last Error Code The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’when a message has been transferred (reception or transmission) without error. 0= No Error: No error occurred since LEC has been reset by successful reception or transmission. 1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2= Form Error: A fixed format part of a received frame has the wrong format. 3= AckError: The message transmitted by the M_CAN was not acknowledged by another node. 4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus value was dominant. 5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. 0 3 read-only TDCR transmitter delay compensation 0x48 32 0x00000000 0x00007F7F TDCO Transmitter Delay Compensation SSP Offset Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq. 8 7 read-write TDCF Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. 0 7 read-write IR interrupt register 0x50 32 0x00000000 0x3FFFFFFF ARA Access to Reserved Address 0= No access to reserved address occurred 1= Access to reserved address occurred 29 1 read-write PED Protocol Error in Data Phase (Data Bit Time is used) 0= No protocol error in data phase 1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7) 28 1 read-write PEA Protocol Error in Arbitration Phase (Nominal Bit Time is used) 0= No protocol error in arbitration phase 1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) 27 1 read-write WDI Watchdog Interrupt 0= No Message RAM Watchdog event occurred 1= Message RAM Watchdog event due to missing READY 26 1 read-write BO Bus_Off Status 0= Bus_Off status unchanged 1= Bus_Off status changed 25 1 read-write EW Warning Status 0= Error_Warning status unchanged 1= Error_Warning status changed 24 1 read-write EP Error Passive 0= Error_Passive status unchanged 1= Error_Passive status changed 23 1 read-write ELO Error Logging Overflow 0= CAN Error Logging Counter did not overflow 1= Overflow of CAN Error Logging Counter occurred 22 1 read-write BEU Bit Error Uncorrected Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. 0= No bit error detected when reading from Message RAM 1= Bit error detected, uncorrected (e.g. parity logic) 21 1 read-write BEC Bit Error Corrected Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. 0= No bit error detected when reading from Message RAM 1= Bit error detected and corrected (e.g. ECC) 20 1 read-write DRX Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0= No Rx Buffer updated 1= At least one received message stored into an Rx Buffer 19 1 read-write TOO Timeout Occurred 0= No timeout 1= Timeout reached 18 1 read-write MRAF Message RAM Access Failure The flag is set, when the Rx Handler .has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. .was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. 0= No Message RAM access failure occurred 1= Message RAM access failure occurred 17 1 read-write TSW Timestamp Wraparound 0= No timestamp counter wrap-around 1= Timestamp counter wrapped around 16 1 read-write TEFL Tx Event FIFO Element Lost 0= No Tx Event FIFO element lost 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero 15 1 read-write TEFF Tx Event FIFO Full 0= Tx Event FIFO not full 1= Tx Event FIFO full 14 1 read-write TEFW Tx Event FIFO Watermark Reached 0= Tx Event FIFO fill level below watermark 1= Tx Event FIFO fill level reached watermark 13 1 read-write TEFN Tx Event FIFO New Entry 0= Tx Event FIFO unchanged 1= Tx Handler wrote Tx Event FIFO element 12 1 read-write TFE Tx FIFO Empty 0= Tx FIFO non-empty 1= Tx FIFO empty 11 1 read-write TCF Transmission Cancellation Finished 0= No transmission cancellation finished 1= Transmission cancellation finished 10 1 read-write TC Transmission Completed 0= No transmission completed 1= Transmission completed 9 1 read-write HPM High Priority Message 0= No high priority message received 1= High priority message received 8 1 read-write RF1L Rx FIFO 1 Message Lost 0= No Rx FIFO 1 message lost 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero 7 1 read-write RF1F Rx FIFO 1 Full 0= Rx FIFO 1 not full 1= Rx FIFO 1 full 6 1 read-write RF1W Rx FIFO 1 Watermark Reached 0= Rx FIFO 1 fill level below watermark 1= Rx FIFO 1 fill level reached watermark 5 1 read-write RF1N Rx FIFO 1 New Message 0= No new message written to Rx FIFO 1 1= New message written to Rx FIFO 1 4 1 read-write RF0L Rx FIFO 0 Message Lost 0= No Rx FIFO 0 message lost 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero 3 1 read-write RF0F Rx FIFO 0 Full 0= Rx FIFO 0 not full 1= Rx FIFO 0 full 2 1 read-write RF0W Rx FIFO 0 Watermark Reached 0= Rx FIFO 0 fill level below watermark 1= Rx FIFO 0 fill level reached watermark 1 1 read-write RF0N Rx FIFO 0 New Message 0= No new message written to Rx FIFO 0 1= New message written to Rx FIFO 0 0 1 read-write IE interrupt enable 0x54 32 0x00000000 0x3FFFFFFF ARAE Access to Reserved Address Enable 29 1 read-write PEDE Protocol Error in Data Phase Enable 28 1 read-write PEAE Protocol Error in Arbitration Phase Enable 27 1 read-write WDIE Watchdog Interrupt Enable 26 1 read-write BOE Bus_Off Status Interrupt Enable 25 1 read-write EWE Warning Status Interrupt Enable 24 1 read-write EPE Error Passive Interrupt Enable 23 1 read-write ELOE Error Logging Overflow Interrupt Enable 22 1 read-write BEUE Bit Error Uncorrected Interrupt Enable 21 1 read-write BECE Bit Error Corrected Interrupt Enable 20 1 read-write DRXE Message stored to Dedicated Rx Buffer Interrupt Enable 19 1 read-write TOOE Timeout Occurred Interrupt Enable 18 1 read-write MRAFE Message RAM Access Failure Interrupt Enable 17 1 read-write TSWE Timestamp Wraparound Interrupt Enable 16 1 read-write TEFLE Tx Event FIFO Event Lost Interrupt Enable 15 1 read-write TEFFE Tx Event FIFO Full Interrupt Enable 14 1 read-write TEFWE Tx Event FIFO Watermark Reached Interrupt Enable 13 1 read-write TEFNE Tx Event FIFO New Entry Interrupt Enable 12 1 read-write TFEE Tx FIFO Empty Interrupt Enable 11 1 read-write TCFE Transmission Cancellation Finished Interrupt Enable 10 1 read-write TCE Transmission Completed Interrupt Enable 9 1 read-write HPME High Priority Message Interrupt Enable 8 1 read-write RF1LE Rx FIFO 1 Message Lost Interrupt Enable 7 1 read-write RF1FE Rx FIFO 1 Full Interrupt Enable 6 1 read-write RF1WE Rx FIFO 1 Watermark Reached Interrupt Enable 5 1 read-write RF1NE Rx FIFO 1 New Message Interrupt Enable 4 1 read-write RF0LE Rx FIFO 0 Message Lost Interrupt Enable 3 1 read-write RF0FE Rx FIFO 0 Full Interrupt Enable 2 1 read-write RF0WE Rx FIFO 0 Watermark Reached Interrupt Enable 1 1 read-write RF0NE Rx FIFO 0 New Message Interrupt Enable 0 1 read-write ILS interrupt line select 0x58 32 0x00000000 0x3FFFFFFF ARAL Access to Reserved Address Line 29 1 read-write PEDL Protocol Error in Data Phase Line 28 1 read-write PEAL Protocol Error in Arbitration Phase Line 27 1 read-write WDIL Watchdog Interrupt Line 26 1 read-write BOL Bus_Off Status Interrupt Line 25 1 read-write EWL Warning Status Interrupt Line 24 1 read-write EPL Error Passive Interrupt Line 23 1 read-write ELOL Error Logging Overflow Interrupt Line 22 1 read-write BEUL Bit Error Uncorrected Interrupt Line 21 1 read-write BECL Bit Error Corrected Interrupt Line 20 1 read-write DRXL Message stored to Dedicated Rx Buffer Interrupt Line 19 1 read-write TOOL Timeout Occurred Interrupt Line 18 1 read-write MRAFL Message RAM Access Failure Interrupt Line 17 1 read-write TSWL Timestamp Wraparound Interrupt Line 16 1 read-write TEFLL Tx Event FIFO Event Lost Interrupt Line 15 1 read-write TEFFL Tx Event FIFO Full Interrupt Line 14 1 read-write TEFWL Tx Event FIFO Watermark Reached Interrupt Line 13 1 read-write TEFNL Tx Event FIFO New Entry Interrupt Line 12 1 read-write TFEL Tx FIFO Empty Interrupt Line 11 1 read-write TCFL Transmission Cancellation Finished Interrupt Line 10 1 read-write TCL Transmission Completed Interrupt Line 9 1 read-write HPML High Priority Message Interrupt Line 8 1 read-write RF1LL Rx FIFO 1 Message Lost Interrupt Line 7 1 read-write RF1FL Rx FIFO 1 Full Interrupt Line 6 1 read-write RF1WL Rx FIFO 1 Watermark Reached Interrupt Line 5 1 read-write RF1NL Rx FIFO 1 New Message Interrupt Line 4 1 read-write RF0LL Rx FIFO 0 Message Lost Interrupt Line 3 1 read-write RF0FL Rx FIFO 0 Full Interrupt Line 2 1 read-write RF0WL Rx FIFO 0 Watermark Reached Interrupt Line 1 1 read-write RF0NL Rx FIFO 0 New Message Interrupt Line 0 1 read-write ILE interrupt line enable 0x5c 32 0x00000000 0x00000003 EINT1 Enable Interrupt Line 1 0= Interrupt line m_can_int1 disabled 1= Interrupt line m_can_int1 enabled 1 1 read-write EINT0 Enable Interrupt Line 0 0= Interrupt line m_can_int0 disabled 1= Interrupt line m_can_int0 enabled 0 1 read-write GFC global filter configuration 0x80 32 0x00000000 0x0000003F ANFS Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 00= Accept in Rx FIFO 0 01= Accept in Rx FIFO 1 10= Reject 11= Reject 4 2 read-write ANFE Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 00= Accept in Rx FIFO 0 01= Accept in Rx FIFO 1 10= Reject 11= Reject 2 2 read-write RRFS Reject Remote Frames Standard 0= Filter remote frames with 11-bit standard IDs 1= Reject all remote frames with 11-bit standard IDs 1 1 read-write RRFE Reject Remote Frames Extended 0= Filter remote frames with 29-bit extended IDs 1= Reject all remote frames with 29-bit extended IDs 0 1 read-write SIDFC standard ID filter configuration 0x84 32 0x00000000 0x00FFFFFC LSS List Size Standard 0= No standard Message ID filter 1-128= Number of standard Message ID filter elements >128= Values greater than 128 are interpreted as 128 16 8 read-write FLSSA Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address) 2 14 read-write XIDFC extended ID filter configuration 0x88 32 0x00000000 0x007FFFFC LSE List Size Extended 0= No extended Message ID filter 1-64= Number of extended Message ID filter elements >64= Values greater than 64 are interpreted as 64 16 7 read-write FLESA Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address). 2 14 read-write XIDAM extended id and mask 0x90 32 0x1FFFFFFF 0x1FFFFFFF EIDM Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. 0 29 read-write HPMS high priority message status 0x94 32 0x00000000 0x0000FFFF FLST Filter List Indicates the filter list of the matching filter element. 0= Standard Filter List 1= Extended Filter List 15 1 read-only FIDX Filter Index Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. 8 7 read-only MSI Message Storage Indicator 00= No FIFO selected 01= FIFO message lost 10= Message stored in FIFO 0 11= Message stored in FIFO 1 6 2 read-only BIDX Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = ‘1’. 0 6 read-only NDAT1 new data1 0x98 32 0x00000000 0xFFFFFFFF ND1 New Data[31:0] The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message 0 32 read-write NDAT2 new data2 0x9c 32 0x00000000 0xFFFFFFFF ND2 New Data[63:32] The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message 0 32 read-write RXF0C rx fifo 0 configuration 0xa0 32 0x00000000 0xFF7FFFFC F0OM FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). 0= FIFO 0 blocking mode 1= FIFO 0 overwrite mode 31 1 read-write F0WM Rx FIFO 0 Watermark 0= Watermark interrupt disabled 1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) >64= Watermark interrupt disabled 24 7 read-write F0S Rx FIFO 0 Size 0= No Rx FIFO 0 1-64= Number of Rx FIFO 0 elements >64= Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to F0S-1 16 7 read-write F0SA Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address) 2 14 read-write RXF0S rx fifo 0 status 0xa4 32 0x00000000 0x033F3F7F RF0L Rx FIFO 0 Message Lost This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. 0= No Rx FIFO 0 message lost 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’ will not set this flag. 25 1 read-only F0F Rx FIFO 0 Full 0= Rx FIFO 0 not full 1= Rx FIFO 0 full 24 1 read-only F0PI Rx FIFO 0 Put Index Rx FIFO 0 write index pointer, range 0 to 63. 16 6 read-only F0GI Rx FIFO 0 Get Index Rx FIFO 0 read index pointer, range 0 to 63. 8 6 read-only F0FL Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0, range 0 to 64. 0 7 read-only RXF0A rx fifo0 acknowledge 0xa8 32 0x00000000 0x0000003F F0AI Rx FIFO 0 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. 0 6 read-write RXBC rx buffer configuration 0xac 32 0x00000000 0x0000FFFC RBSA Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C. 2 14 read-write RXF1C rx fifo1 configuration 0xb0 32 0x00000000 0xFF7FFFFC F1OM FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). 0= FIFO 1 blocking mode 1= FIFO 1 overwrite mode 31 1 read-write F1WM Rx FIFO 1 Watermark 0= Watermark interrupt disabled 1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) >64= Watermark interrupt disabled 24 7 read-write F1S Rx FIFO 1 Size 0= No Rx FIFO 1 1-64= Number of Rx FIFO 1 elements >64= Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to F1S - 1 16 7 read-write F1SA Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address) 2 14 read-write RXF1S rx fifo1 status 0xb4 32 0x00000000 0xC33F3F7F DMS Debug Message Status 00= Idle state, wait for reception of debug messages, DMA request is cleared 01= Debug message A received 10= Debug messages A, B received 11= Debug messages A, B, C received, DMA request is set 30 2 read-only RF1L Rx FIFO 1 Message Lost This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. 0= No Rx FIFO 1 message lost 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag. 25 1 read-only F1F Rx FIFO 1 Full 0= Rx FIFO 1 not full 1= Rx FIFO 1 full 24 1 read-only F1PI Rx FIFO 1 Put Index Rx FIFO 1 write index pointer, range 0 to 63. 16 6 read-only F1GI Rx FIFO 1 Get Index Rx FIFO 1 read index pointer, range 0 to 63. 8 6 read-only F1FL Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1, range 0 to 64. 0 7 read-only RXF1A rx fifo 1 acknowledge 0xb8 32 0x00000000 0x0000003F F1AI Rx FIFO 1 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. 0 6 read-write RXESC rx buffer/fifo element size configuration 0xbc 32 0x00000000 0x00000777 RBDS Rx Buffer Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field 8 3 read-write F1DS Rx FIFO 1 Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field 4 3 read-write F0DS Rx FIFO 0 Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. 0 3 read-write TXBC tx buffer configuration 0xc0 32 0x00000000 0x7F3FFFFC TFQM Tx FIFO/Queue Mode 0= Tx FIFO operation 1= Tx Queue operation 30 1 read-write TFQS Transmit FIFO/Queue Size 0= No Tx FIFO/Queue 1-32= Number of Tx Buffers used for Tx FIFO/Queue >32= Values greater than 32 are interpreted as 32 24 6 read-write NDTB Number of Dedicated Transmit Buffers 0= No Dedicated Tx Buffers 1-32= Number of Dedicated Tx Buffers >32= Values greater than 32 are interpreted as 32 16 6 read-write TBSA Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. 2 14 read-write TXFQS tx fifo/queue status 0xc4 32 0x00000000 0x003F1F3F TFQF Tx FIFO/Queue Full 0= Tx FIFO/Queue not full 1= Tx FIFO/Queue full 21 1 read-only TFQPI Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer, range 0 to 31. 16 5 read-only TFGI Tx FIFO Get Index Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’). 8 5 read-only TFFL Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. 0 6 read-only TXESC tx buffer element size configuration 0xc8 32 0x00000000 0x00000007 TBDS Tx Buffer Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes). 0 3 read-write TXBRP tx buffer request pending 0xcc 32 0x00000000 0xFFFFFFFF TRP Transmission Request Pending Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR. TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signalled via TXBCF ? after successful transmission together with the corresponding TXBTO bit ? when the transmission has not yet been started at the point of cancellation ? when the transmission has been aborted due to lost arbitration ? when an error occurred during frame transmission In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. 0= No transmission request pending 1= Transmission request pending Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. 0 32 read-only TXBAR tx buffer add request 0xd0 32 0x00000000 0xFFFFFFFF AR Add Request Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0= No transmission request added 1= Transmission requested added Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. 0 32 read-write TXBCR tx buffer cancellation request 0xd4 32 0x00000000 0xFFFFFFFF CR Cancellation Request Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. 0= No cancellation pending 1= Cancellation pending 0 32 read-write TXBTO tx buffer transmission occurred 0xd8 32 0x00000000 0xFFFFFFFF TO Transmission Occurred Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. 0= No transmission occurred 1= Transmission occurred 0 32 read-only TXBCF tx buffer cancellation finished 0xdc 32 0x00000000 0xFFFFFFFF CF Cancellation Finished Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. 0= No transmit buffer cancellation 1= Transmit buffer cancellation finished 0 32 read-only TXBTIE tx buffer transmission interrupt enable 0xe0 32 0x00000000 0xFFFFFFFF TIE Transmission Interrupt Enable Each Tx Buffer has its own Transmission Interrupt Enable bit. 0= Transmission interrupt disabled 1= Transmission interrupt enable 0 32 read-write TXBCIE tx buffer cancellation finished interrupt enable 0xe4 32 0x00000000 0xFFFFFFFF CFIE Cancellation Finished Interrupt Enable Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0= Cancellation finished interrupt disabled 1= Cancellation finished interrupt enabled 0 32 read-write TXEFC tx event fifo configuration 0xf0 32 0x00000000 0x3F3FFFFC EFWM Event FIFO Watermark 0= Watermark interrupt disabled 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) >32= Watermark interrupt disabled 24 6 read-write EFS Event FIFO Size 0= Tx Event FIFO disabled 1-32= Number of Tx Event FIFO elements >32= Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to EFS - 1 16 6 read-write EFSA Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address) 2 14 read-write TXEFS tx event fifo status 0xf4 32 0x00000000 0x031F1F3F TEFL Tx Event FIFO Element Lost This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. 0= No Tx Event FIFO element lost 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. 25 1 read-only EFF Event FIFO Full 0= Tx Event FIFO not full 1= Tx Event FIFO full 24 1 read-only EFPI Event FIFO Put Index Tx Event FIFO write index pointer, range 0 to 31. 16 5 read-only EFGI Event FIFO Get Index Tx Event FIFO read index pointer, range 0 to 31. 8 5 read-only EFFL Event FIFO Fill Level Number of elements stored in Tx Event FIFO, range 0 to 32. 0 6 read-only TXEFA tx event fifo acknowledge 0xf8 32 0x00000000 0x0000001F EFAI Event FIFO Acknowledge Index After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. 0 5 read-write 16 0x4 TS_SEL0,TS_SEL1,TS_SEL2,TS_SEL3,TS_SEL4,TS_SEL5,TS_SEL6,TS_SEL7,TS_SEL8,TS_SEL9,TS_SEL10,TS_SEL11,TS_SEL12,TS_SEL13,TS_SEL14,TS_SEL15 TS_SEL[%s] no description available 0x200 32 0x00000000 0xFFFFFFFF TS Timestamp Word TS default can save 16 timestamps with 32bit; if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. 0 32 read-only CREL core release register 0x240 32 0x00000000 0xFFFFFFFF REL Core Release One digit, BCD-coded 28 4 read-only STEP Step of Core Release One digit, BCD-coded. 24 4 read-only SUBSTEP Sub-step of Core Release One digit, BCD-coded 20 4 read-only YEAR Timestamp Year One digit, BCD-coded. This field is set by generic parameter on synthesis. 16 4 read-only MON Timestamp Month Two digits, BCD-coded. This field is set by generic parameter on synthesis. 8 8 read-only DAY Timestamp Day Two digits, BCD-coded. This field is set by generic parameter on synthesis. 0 8 read-only TSCFG timestamp configuration 0x244 32 0x00000000 0x0000FF0F TBPRE Timebase Prescaler 0x00 to 0xFF The value by which the oscillator frequency is divided for generating the timebase counter clock. Valid values for the Timebase Prescaler are 0 to 255. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Affects only the TSU internal timebase. When the internal timebase is excluded by synthesis, TBPRE[7:0] is fixed to 0x00, the Timestamp Prescaler is not used. 8 8 read-write EN64 set to use 64bit timestamp. when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. TSP can be used to select different one 3 1 read-write SCP Select Capturing Position 0: Capture Timestamp at EOF 1: Capture Timestamp at SOF 2 1 read-write TBCS Timebase Counter Select When the internal timebase is excluded by synthesis, TBCS is fixed to ‘1’. 0: Timestamp value captured from internal timebase counter, ATB.TB[31:0] is the internal timbase counter 1: Timestamp value captured from input tsu_tbin[31:0],ATB.TB[31:0] is tsu_tbin[31:0] 1 1 read-write TSUE Timestamp Unit Enable 0: TSU disabled 1: TSU enabled 0 1 read-write TSS1 timestamp status1 0x248 32 0x00000000 0xFFFFFFFF TSL Timestamp Lost Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related Timestamp register was overwritten before it was read. Reading a Timestamp register resets the related bit. 16 16 read-only TSN Timestamp New Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related Timestamp register. Reading a Timestamp register resets the related bit. 0 16 read-only TSS2 timestamp status2 0x24c 32 0x00000000 0x0000000F TSP Timestamp Pointer The Timestamp Pointer is incremented by one each time a timestamp is captured. From its maximum value (3, 7, or 15 depending on number_ts_g), it is incremented to 0. Value also signalled on output m_can_tsp[3:0]. 0 4 read-only ATB actual timebase 0x250 32 0x00000000 0xFFFFFFFF TB timebase for timestamp generation 31-0 0 32 read-only ATBH actual timebase high 0x254 32 0x00000000 0xFFFFFFFF TBH timebase for timestamp generation 63-32 0 32 read-only GLB_CTL global control 0x400 32 0x00000000 0xE0000003 M_CAN_STBY m_can standby control 31 1 read-write STBY_CLR_EN m_can standby clear control 0:controlled by software by standby bit[bit31] 1:auto clear standby by hardware when rx data is 0 30 1 read-write STBY_POL standby polarity selection 29 1 read-write TSU_TBIN_SEL external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1 0 2 read-write GLB_STATUS global status 0x404 32 0x00000000 0x0000000C M_CAN_INT1 m_can interrupt status1 3 1 read-only M_CAN_INT0 m_can interrupt status0 2 1 read-only 640 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,288,289,290,291,292,293,294,295,296,297,298,299,300,301,302,303,304,305,306,307,308,309,310,311,312,313,314,315,316,317,318,319,320,321,322,323,324,325,326,327,328,329,330,331,332,333,334,335,336,337,338,339,340,341,342,343,344,345,346,347,348,349,350,351,352,353,354,355,356,357,358,359,360,361,362,363,364,365,366,367,368,369,370,371,372,373,374,375,376,377,378,379,380,381,382,383,384,385,386,387,388,389,390,391,392,393,394,395,396,397,398,399,400,401,402,403,404,405,406,407,408,409,410,411,412,413,414,415,416,417,418,419,420,421,422,423,424,425,426,427,428,429,430,431,432,433,434,435,436,437,438,439,440,441,442,443,444,445,446,447,448,449,450,451,452,453,454,455,456,457,458,459,460,461,462,463,464,465,466,467,468,469,470,471,472,473,474,475,476,477,478,479,480,481,482,483,484,485,486,487,488,489,490,491,492,493,494,495,496,497,498,499,500,501,502,503,504,505,506,507,508,509,510,511,512,513,514,515,516,517,518,519,520,521,522,523,524,525,526,527,528,529,530,531,532,533,534,535,536,537,538,539,540,541,542,543,544,545,546,547,548,549,550,551,552,553,554,555,556,557,558,559,560,561,562,563,564,565,566,567,568,569,570,571,572,573,574,575,576,577,578,579,580,581,582,583,584,585,586,587,588,589,590,591,592,593,594,595,596,597,598,599,600,601,602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,633,634,635,636,637,638,639 MESSAGE_BUFF[%s] no description available 0x2000 32 0x00000000 0xFFFFFFFF DATA m_can message buffer 0 32 read-write MCAN1 MCAN1 MCAN 0xf0284000 MCAN2 MCAN2 MCAN 0xf0288000 MCAN3 MCAN3 MCAN 0xf028c000 MCAN4 MCAN4 MCAN 0xf0290000 MCAN5 MCAN5 MCAN 0xf0294000 MCAN6 MCAN6 MCAN 0xf0298000 MCAN7 MCAN7 MCAN 0xf029c000 PTPC PTPC PTPC 0xf02fc000 0x0 0x3004 registers 2 0x1000 0,1 PTPC[%s] no description available 0x0 Ctrl0 Control Register 0 0x0 32 0x00000000 0x000003FF SUBSEC_DIGITAL_ROLLOVER Format for ns counter rollover, 1-digital, overflow time 1000000000/0x3B9ACA00 0-binary, overflow time 0x7FFFFFFF 9 1 read-write CAPT_SNAP_KEEP set will keep capture snap till software read capt_snapl. If this bit is set, software should read capt_snaph first to avoid wrong result. If this bit is cleared, capture result will be updated at each capture event 8 1 read-write CAPT_SNAP_POS_EN set will use posege of input capture signal to latch timestamp value 7 1 read-write CAPT_SNAP_NEG_EN No description available 6 1 read-write COMP_EN set to enable compare, will be cleared by HW when compare event triggered 4 1 read-write UPDATE_TIMER update timer with +/- ts_updt, pulse, clear after set 3 1 write-only INIT_TIMER initial timer with ts_updt, pulse, clear after set 2 1 write-only FINE_COARSE_SEL 0: coarse update, ns counter add ss_incr[7:0] each clk 1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow 1 1 read-write TIMER_ENABLE No description available 0 1 read-write ctrl1 Control Register 1 0x4 32 0x00000000 0x000000FF SS_INCR constant value used to add ns counter; such as for 50MHz timer clock, set it to 8'd20 0 8 read-write timeh timestamp high 0x8 32 0x00000000 0xFFFFFFFF TIMESTAMP_HIGH No description available 0 32 read-only timel timestamp low 0xc 32 0x00000000 0xFFFFFFFF TIMESTAMP_LOW No description available 0 32 read-only ts_updth timestamp update high 0x10 32 0x00000000 0xFFFFFFFF SEC_UPDATE together with ts_updtl, used to initial or update timestamp 0 32 read-write ts_updtl timestamp update low 0x14 32 0x00000000 0xFFFFFFFF ADD_SUB 1 for sub; 0 for add, used only at update 31 1 read-write NS_UPDATE No description available 0 31 read-write addend No description available 0x18 32 0x00000000 0xFFFFFFFF ADDEND used in fine update mode only 0 32 read-write tarh No description available 0x1c 32 0x00000000 0xFFFFFFFF TARGET_TIME_HIGH used for generate compare signal if enabled 0 32 read-write tarl No description available 0x20 32 0x00000000 0xFFFFFFFF TARGET_TIME_LOW No description available 0 32 read-write pps_ctrl No description available 0x2c 32 0x00000000 0x0000000F PPS_CTRL No description available 0 4 read-write capt_snaph No description available 0x30 32 0x00000000 0xFFFFFFFF CAPT_SNAP_HIGH take snapshot for input capture signal, at pos or neg or both; the result can be kept or updated at each event according to cfg0.bit8 0 32 read-only capt_snapl No description available 0x34 32 0x00000000 0xFFFFFFFF CAPT_SNAP_LOW No description available 0 32 read-write time_sel No description available 0x2000 32 0x00000000 0x0000000F CAN3_TIME_SEL No description available 3 1 read-write CAN2_TIME_SEL No description available 2 1 read-write CAN1_TIME_SEL No description available 1 1 read-write CAN0_TIME_SEL set to use ptpc1 for canx clr to use ptpc0 for canx 0 1 read-write int_sts No description available 0x2004 32 0x00000000 0x00070007 COMP_INT_STS1 No description available 18 1 write-only CAPTURE_INT_STS1 No description available 17 1 write-only PPS_INT_STS1 No description available 16 1 write-only COMP_INT_STS0 No description available 2 1 write-only CAPTURE_INT_STS0 No description available 1 1 write-only PPS_INT_STS0 No description available 0 1 write-only int_en No description available 0x2008 32 0x00000000 0x00070007 COMP_INT_STS1 No description available 18 1 read-write CAPTURE_INT_STS1 No description available 17 1 read-write PPS_INT_STS1 No description available 16 1 read-write COMP_INT_STS0 No description available 2 1 read-write CAPTURE_INT_STS0 No description available 1 1 read-write PPS_INT_STS0 No description available 0 1 read-write ptpc_can_ts_sel No description available 0x3000 32 0x00000000 0xFFFFFF00 TSU_TBIN3_SEL No description available 26 6 read-write TSU_TBIN2_SEL No description available 20 6 read-write TSU_TBIN1_SEL No description available 14 6 read-write TSU_TBIN0_SEL No description available 8 6 read-write ENET0 ENET0 ENET 0xf1100000 0x0 0x3028 registers MACCFG MAC Configuration Register 0x0 32 0x00000000 0x7FFFFFFF SARC Source Address Insertion or Replacement Control This field controls the source address insertion or replacement for all transmitted frames. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: - 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. - 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. - 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. Note: - Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. 28 3 read-write TWOKPE IEEE 802.3as Support for 2K Packets When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. When Bit 20 is set, setting this bit has no effect on Giant Frame status. 27 1 read-write SFTERR SMII Force Transmit Error When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. 26 1 read-write CST CRC Stripping for Type Frames When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. 25 1 read-write TC Transmit Configuration in RGMII, SGMII, or SMII When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or SGMII port. When this bit is reset, no such information is driven to the PHY. This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. 24 1 read-write WD Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. 23 1 read-write JD Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. 22 1 read-write BE Frame Burst Enable When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. 21 1 read-write JE Jumbo Frame Enable When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. 20 1 read-write IFG Inter-Frame Gap These bits control the minimum IFG between frames during transmission. - 000: 96 bit times - 001: 88 bit times - 010: 80 bit times - ... - 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered. In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. 17 3 read-write DCRS Disable Carrier Sense During Transmission When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. 16 1 read-write PS Port Select This bit selects the Ethernet line speed. - 0: For 1000 Mbps operations - 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. 15 1 read-write FES Speed This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: - 0: 10 Mbps - 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. 14 1 read-write DO Disable Receive Own When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. 13 1 read-write LM Loopback Mode When this bit is set, the MAC operates in the loopback mode at GMII or MII. The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. 12 1 read-write DM Duplex Mode When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. 11 1 read-write IPC Checksum Offload When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset, this function is disabled. When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. 10 1 read-write DR Disable Retry When this bit is set, the MAC attempts only one transmission. When a collision occurs on the GMII or MII interface, the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). 9 1 read-write LUD Link Up or Down This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: - 0: Link Down - 1: Link Up 8 1 read-write ACS Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. 7 1 read-write BL Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. - 00: k= min (n, 10) - 01: k = min (n, 8) - 10: k = min (n, 4) - 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k 5 2 read-write DC Deferral Check When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0 and it is restarted. 4 1 read-write TE Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. 3 1 read-write RE Receiver Enable When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. 2 1 read-write PRELEN Preamble Length for Transmit frames These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode. - 2'b00: 7 bytes of preamble - 2'b01: 5 bytes of preamble - 2'b10: 3 bytes of preamble - 2'b11: Reserved 0 2 read-write MACFF MAC Frame Filter 0x4 32 0x00000000 0x803087FF RA Receive All When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes only those frames to the Application that pass the SA or DA address filter. 31 1 read-write DNTU Drop non-TCP/UDP over IP Frames When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. 21 1 read-write IPFE Layer 3 and Layer 4 Filter Enable When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. 20 1 read-write VTFE VLAN Tag Filter Enable When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. 15 1 read-write HPF Hash or Perfect Filter When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. 10 1 read-write SAF Source Address Filter Enable When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. 9 1 read-write SAIF SA Inverse Filtering When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. 8 1 read-write PCF Pass Control Frames These bits control the forwarding of all control frames (including unicast and multicast Pause frames). - 00: MAC filters all control frames from reaching the application. - 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. - 10: MAC forwards all control frames to application even if they fail the Address Filter. - 11: MAC forwards control frames that pass the Address Filter. The following conditions should be true for the Pause frames processing: - Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. - Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. - Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. Note: This field should be set to 01 only when the Condition 1 is true, that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. Otherwise, the Pause frame filtering may be inconsistent. When Condition 1 is false, the Pause frames are considered as generic control frames. Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, you should set the PCF field to 10 or 11 (as required by the application). 6 2 read-write DBF Disable Broadcast Frames When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. When this bit is reset, the AFM module passes all received broadcast frames. 5 1 read-write PM Pass All Multicast When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. When reset, filtering of multicast frame depends on HMC bit. 4 1 read-write DAIF DA Inverse Filtering When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset, normal filtering of frames is performed. 3 1 read-write HMC Hash Multicast When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. 2 1 read-write HUC Hash Unicast When set, the MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. 1 1 read-write PR Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. 0 1 read-write HASH_H Hash Table High Register 0x8 32 0x00000000 0xFFFFFFFF HTH Hash Table High This field contains the upper 32 bits of the Hash table. 0 32 read-write HASH_L Hash Table Low Register 0xc 32 0x00000000 0xFFFFFFFF HTL Hash Table Low This field contains the lower 32 bits of the Hash table. 0 32 read-write GMII_ADDR GMII Address Register 0x10 32 0x00000000 0x0000FFFF PA Physical Layer Address This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. 11 5 read-write GR GMII Register These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. 6 5 read-write CR CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. - 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. - 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. - 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. - 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. - 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. - 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. - 0110, 0111: Reserved When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the following values only if the interfacing chips support faster MDC clocks. - 1000: CSR clock/4 - 1001: CSR clock/6 - 1010: CSR clock/8 - 1011: CSR clock/10 - 1100: CSR clock/12 - 1101: CSR clock/14 - 1110: CSR clock/16 - 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. 2 4 read-write GW GMII Write When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, it indicates that this is a Read operation, that is, placing the data in the GMII Data register. 1 1 read-write GB GMII Busy This bit should read logic 0 before writing to Register 4 and Register 5. During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. Register 5 is invalid until this bit is cleared by the MAC. Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, there is no change in the functionality of this bit even when the PHY is not present. 0 1 read-write GMII_DATA GMII Data Register 0x14 32 0x00000000 0x0000FFFF GD GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. 0 16 read-write FLOWCTRL Flow Control Register 0x18 32 0x00000000 0xFFFF00BF PT Pause Time This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. 16 16 read-write DZPQ Disable Zero-Quanta Pause When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. 7 1 read-write PLT Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values: - 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). - 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). - 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). - 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. 4 2 read-write UP Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set, the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. When this bit is reset, the MAC only detects Pause frames with unique multicast address. 3 1 read-write RFE Receive Flow Control Enable When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. 2 1 read-write TFE Transmit Flow Control Enable In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. 1 1 read-write FCB_BPA Flow Control Busy or Backpressure Activate This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame, the Application must set this bit to 1'b1. During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. 0 1 read-write VLAN_TAG VLAN Tag Register 0x1c 32 0x00000000 0x000FFFFF VTHM VLAN Tag Hash Table Match Enable When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. 19 1 read-write ESVL Enable S-VLAN When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. 18 1 read-write VTIM VLAN Tag Inverse Match Enable When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. The frames with matched VLAN Tag are marked as matched. 17 1 read-write ETV Enable 12-Bit VLAN Tag Comparison When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. 16 1 read-write VL VLAN Tag Identifier for Receive Frames This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. The following list describes the bits of this field: - Bits [15:13]: User Priority - Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) - Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. 0 16 read-write RWKFRMFILT Remote Wake-Up Frame Filter Register 0x28 32 0x00000000 0xFFFFFFFF WKUPFRMFILT This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers 0 32 read-write PMT_CSR PMT Control and Status Register 0x2c 32 0x00000000 0x9F000267 RWKFILTRST Remote Wake-Up Frame Filter Register Pointer Reset When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. 31 1 read-write RWKPTR Remote Wake-up FIFO Pointer This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. 24 5 read-write GLBLUCAST Global Unicast When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. 9 1 read-write RWKPRCVD Remote Wake-Up Frame Received When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. 6 1 read-write MGKPRCVD Magic Packet Received When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. 5 1 read-write RWKPKTEN Remote Wake-Up Frame Enable When set, enables generation of a power management event because of remote wake-up frame reception. 2 1 read-write MGKPKTEN Magic Packet Enable When set, enables generation of a power management event because of magic packet reception. 1 1 read-write PWRDWN Power Down When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. This bit is then self-cleared and the power-down mode is disabled. The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. The frames, received by the MAC after this bit is cleared, are forwarded to the application. This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Up Frame Enable bit is set high. Note: You can gate-off the CSR clock during the power-down mode. However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. 0 1 read-write LPI_CSR LPI Control and Status Register 0x30 32 0x00000000 0x000F030F LPITXA LPI TX Automate This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), when the MAC is in the LPI mode, the MAC exits the LPI mode. When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. 19 1 read-write PLSEN PHY Link Status Enable This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. 18 1 read-write PLS PHY Link Status This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. When set, the link is considered to be okay (up) and when reset, the link is considered to be down. 17 1 read-write LPIEN LPI Enable When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. 16 1 read-write RLPIST Receive LPI State When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. 9 1 read-write TLPIST Transmit LPI State When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. 8 1 read-write RLPIEX Receive LPI Exit When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. 3 1 read-write RLPIEN Receive LPI Entry When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. 2 1 read-write TLPIEX Transmit LPI Exit When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. 1 1 read-write TLPIEN Transmit LPI Entry When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. 0 1 read-write LPI_TCR LPI Timers Control Register 0x34 32 0x00000000 0x03FFFFFF LST LPI LS TIMER This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. 16 10 read-write TWT LPI TW TIMER This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer. 0 16 read-write INTR_STATUS Interrupt Status Register 0x38 32 0x00000000 0x00000EFF GPIIS GPI Interrupt Status When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). When the GPIO feature is not enabled, this bit is reserved. 11 1 read-only LPIIS LPI Interrupt Status When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. 10 1 read-only TSIS Timestamp Interrupt Status When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: - The system time value equals or exceeds the value specified in the Target Time High and Low registers. - There is an overflow in the seconds register. - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). 9 1 read-only MMCRXIPIS MMC Receive Checksum Offload Interrupt Status This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. 7 1 read-only MMCTXIS MMC Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. 6 1 read-only MMCRXIS MMC Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. 5 1 read-only MMCIS MMC Interrupt Status This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. 4 1 read-only PMTIS PMT Interrupt Status This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. 3 1 read-only PCSANCIS PCS Auto-Negotiation Complete This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation to the AN Status register. 2 1 read-only PCSLCHGIS PCS Link Status Changed This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation on the AN Status register. 1 1 read-only RGSMIIIS RGMII or SMII Interrupt Status This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. 0 1 read-only INTR_MASK Interrupt Mask Register 0x3c 32 0x00000000 0x0000060F LPIIM LPI Interrupt Mask When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). 10 1 read-write TSIM Timestamp Interrupt Mask When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). 9 1 read-write PMTIM PMT Interrupt Mask When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). 3 1 read-write PCSANCIM PCS AN Completion Interrupt Mask When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). 2 1 read-write PCSLCHGIM PCS Link Status Interrupt Mask When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). 1 1 read-write RGSMIIIM RGMII or SMII Interrupt Mask When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). 0 1 read-write MAC_ADDR_0_HIGH MAC Address 0 High Register 0x40 32 0x00000000 0x8000FFFF AE Address Enable This bit is RO. The bit value is fixed at 1. 31 1 read-only ADDRHI MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. 0 16 read-write MAC_ADDR_0_LOW MAC Address 0 Low Register 0x44 32 0x00000000 0xFFFFFFFF ADDRLO MAC Address0 [31:0] This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. 0 32 read-write 4 0x8 1,2,3,4 MAC_ADDR[%s] no description available 0x48 HIGH MAC Address High Register 0x0 32 0x00000000 0xFF00FFFF AE Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. 31 1 read-write SA Source Address When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. 30 1 read-write MBC Mask Byte Control These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. 24 6 read-write ADDRHI MAC Address1 [47:32] This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. 0 16 read-write LOW MAC Address Low Register 0x4 32 0x00000000 0xFFFFFFFF ADDRLO MAC Address1 [31:0] This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. 0 32 read-write XMII_CSR SGMII/RGMII/SMII Control and Status Register 0xd8 32 0x00000000 0x0000003F FALSCARDET False Carrier Detected This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. 5 1 read-write JABTO Jabber Timeout This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. 4 1 read-write LNKSTS Link Status This bit indicates whether the link between the local PHY and the remote PHY is up or down. It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. 3 1 read-write LNKSPEED Link Speed This bit indicates the current speed of the link: - 00: 2.5 MHz - 01: 25 MHz - 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. 1 2 read-write LNKMOD Link Mode This bit indicates the current mode of operation of the link: - 1’b0: Half-duplex mode - 1’b1: Full-duplex mode 0 1 read-write WDOG_WTO Watchdog Timeout Register 0xdc 32 0x00000000 0x00013FFF PWE Programmable Watchdog Enable When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). 16 1 read-write WTO Watchdog Timeout When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. 0 14 read-write mmc_cntrl MMC Control establishes the operating mode of MMC. 0x100 32 0x00000000 0x0000013F UCDBC Update MMC Counters for Dropped Broadcast Frames When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). When reset, the MMC Counters are not updated for dropped Broadcast frames. 8 1 read-write CNTPRSTLVL Full-Half Preset When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half - 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half - 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full - 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full - 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. 5 1 read-write CNTPRST Counters Preset When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. 4 1 read-write CNTFREEZ MMC Counter Freeze When this bit is set, it freezes all MMC counters to their current value. Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. 3 1 read-write RSTONRD Reset on Read When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. 2 1 read-write CNTSTOPRO Counter Stop Rollover When this bit is set, the counter does not roll over to zero after reaching the maximum value. 1 1 read-write CNTRST Counters Reset When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle 0 1 read-write mmc_intr_rx MMC Receive Interrupt maintains the interrupt generated from all of the receive statistic counters. 0x104 32 0x00000000 0x03FFFFFF RXCTRLFIS MMC Receive Control Frame Counter Interrupt Status This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. 25 1 read-write RXRCVERRFIS MMC Receive Error Frame Counter Interrupt Status This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. 24 1 read-write RXWDOGFIS MMC Receive Watchdog Error Frame Counter Interrupt Status This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. 23 1 read-write RXVLANGBFIS MMC Receive VLAN Good Bad Frame Counter Interrupt Status This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. 22 1 read-write RXFOVFIS MMC Receive FIFO Overflow Frame Counter Interrupt Status This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. 21 1 read-write RXPAUSFIS MMC Receive Pause Frame Counter Interrupt Status This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. 20 1 read-write RXORANGEFIS MMC Receive Out Of Range Error Frame Counter Interrupt Status. This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. 19 1 read-write RXLENERFIS MMC Receive Length Error Frame Counter Interrupt Status This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. 18 1 read-write RXUCGFIS MMC Receive Unicast Good Frame Counter Interrupt Status This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. 17 1 read-write RX1024TMAXOCTGBFIS MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. 16 1 read-write RX512T1023OCTGBFIS MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. 15 1 read-write RX256T511OCTGBFIS MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. 14 1 read-write RX128T255OCTGBFIS MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. 13 1 read-write RX65T127OCTGBFIS MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. 12 1 read-write RX64OCTGBFIS MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. 11 1 read-write RXOSIZEGFIS MMC Receive Oversize Good Frame Counter Interrupt Status This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. 10 1 read-write RXUSIZEGFIS MMC Receive Undersize Good Frame Counter Interrupt Status This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. 9 1 read-write RXJABERFIS MMC Receive Jabber Error Frame Counter Interrupt Status This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. 8 1 read-write RXRUNTFIS MMC Receive Runt Frame Counter Interrupt Status This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. 7 1 read-write RXALGNERFIS MMC Receive Alignment Error Frame Counter Interrupt Status This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. 6 1 read-write RXCRCERFIS MMC Receive CRC Error Frame Counter Interrupt Status This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. 5 1 read-write RXMCGFIS MMC Receive Multicast Good Frame Counter Interrupt Status This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. 4 1 read-write RXBCGFIS MMC Receive Broadcast Good Frame Counter Interrupt Status This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. 3 1 read-write RXGOCTIS MMC Receive Good Octet Counter Interrupt Status This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. 2 1 read-write RXGBOCTIS MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. 1 1 read-write RXGBFRMIS MMC Receive Good Bad Frame Counter Interrupt Status This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. 0 1 read-write mmc_intr_tx MMC Transmit Interrupt maintains the interrupt generated from all of the transmit statistic counters 0x108 32 0x00000000 0x03FFFFFF TXOSIZEGFIS MMC Transmit Oversize Good Frame Counter Interrupt Status This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. 25 1 read-write TXVLANGFIS MMC Transmit VLAN Good Frame Counter Interrupt Status This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. 24 1 read-write TXPAUSFIS MMC Transmit Pause Frame Counter Interrupt Status This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. 23 1 read-write TXEXDEFFIS MMC Transmit Excessive Deferral Frame Counter Interrupt Status This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. 22 1 read-write TXGFRMIS MMC Transmit Good Frame Counter Interrupt Status This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. 21 1 read-write TXGOCTIS MMC Transmit Good Octet Counter Interrupt Status This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. 20 1 read-write TXCARERFIS MMC Transmit Carrier Error Frame Counter Interrupt Status This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. 19 1 read-write TXEXCOLFIS MMC Transmit Excessive Collision Frame Counter Interrupt Status This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. 18 1 read-write TXLATCOLFIS MMC Transmit Late Collision Frame Counter Interrupt Status This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. 17 1 read-write TXDEFFIS MMC Transmit Deferred Frame Counter Interrupt Status This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. 16 1 read-write TXMCOLGFIS MMC Transmit Multiple Collision Good Frame Counter Interrupt Status This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. 15 1 read-write TXSCOLGFIS MMC Transmit Single Collision Good Frame Counter Interrupt Status This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. 14 1 read-write TXUFLOWERFIS MMC Transmit Underflow Error Frame Counter Interrupt Status This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. 13 1 read-write TXBCGBFIS MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. 12 1 read-write TXMCGBFIS MMC Transmit Multicast Good Bad Frame Counter Interrupt Status The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. 11 1 read-write TXUCGBFIS MMC Transmit Unicast Good Bad Frame Counter Interrupt Status This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. 10 1 read-write TX1024TMAXOCTGBFIS MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. 9 1 read-write TX512T1023OCTGBFIS MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. 8 1 read-write TX256T511OCTGBFIS MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. 7 1 read-write TX128T255OCTGBFIS MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. 6 1 read-write TX65T127OCTGBFIS MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. 5 1 read-write TX64OCTGBFIS MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. 4 1 read-write TXMCGFIS MMC Transmit Multicast Good Frame Counter Interrupt Status This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. 3 1 read-write TXBCGFIS MMC Transmit Broadcast Good Frame Counter Interrupt Status This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. 2 1 read-write TXGBFRMIS MMC Transmit Good Bad Frame Counter Interrupt Status This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. 1 1 read-write TXGBOCTIS MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. 0 1 read-write mmc_intr_mask_rx MMC Receive Interrupt mask maintains the mask for the interrupt generated from all of the receive statistic counters 0x10c 32 0x00000000 0x03FFFFFE RXCTRLFIM MMC Receive Control Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. 25 1 read-write RXRCVERRFIM MMC Receive Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. 24 1 read-write RXWDOGFIM MMC Receive Watchdog Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. 23 1 read-write RXVLANGBFIM MMC Receive VLAN Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. 22 1 read-write RXFOVFIM MMC Receive FIFO Overflow Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. 21 1 read-write RXPAUSFIM MMC Receive Pause Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. 20 1 read-write RXORANGEFIM MMC Receive Out Of Range Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. 19 1 read-write RXLENERFIM MMC Receive Length Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. 18 1 read-write RXUCGFIM MMC Receive Unicast Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. 17 1 read-write RX1024TMAXOCTGBFIM MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. 16 1 read-write RX512T1023OCTGBFIM MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. 15 1 read-write RX256T511OCTGBFIM MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. 14 1 read-write RX128T255OCTGBFIM MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. 13 1 read-write RX65T127OCTGBFIM MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. 12 1 read-write RX64OCTGBFIM MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. 11 1 read-write RXOSIZEGFIM MMC Receive Oversize Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. 10 1 read-write RXUSIZEGFIM MMC Receive Undersize Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. 9 1 read-write RXJABERFIM MMC Receive Jabber Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. 8 1 read-write RXRUNTFIM MMC Receive Runt Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. 7 1 read-write RXALGNERFIM MMC Receive Alignment Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. 6 1 read-write RXCRCERFIM MMC Receive CRC Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. 5 1 read-write RXMCGFIM MMC Receive Multicast Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. 4 1 read-write RXBCGFIM MMC Receive Broadcast Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. 3 1 read-write RXGOCTIM MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. 2 1 read-write RXGBOCTIM MMC Receive Good Bad Octet Counter Interrupt Mask. Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. 1 1 read-write mmc_intr_mask_tx MMC Transmit Interrupt Mask 0x110 32 0x00000000 0x03FFFFFF TXOSIZEGFIM MMC Transmit Oversize Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. 25 1 read-write TXVLANGFIM MMC Transmit VLAN Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. 24 1 read-write TXPAUSFIM MMC Transmit Pause Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. 23 1 read-write TXEXDEFFIM MMC Transmit Excessive Deferral Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. 22 1 read-write TXGFRMIM MMC Transmit Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. 21 1 read-write TXGOCTIM MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. 20 1 read-write TXCARERFIM MMC Transmit Carrier Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. 19 1 read-write TXEXCOLFIM MMC Transmit Excessive Collision Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. 18 1 read-write TXLATCOLFIM MMC Transmit Late Collision Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. 17 1 read-write TXDEFFIM MMC Transmit Deferred Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. 16 1 read-write TXMCOLGFIM MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. 15 1 read-write TXSCOLGFIM MMC Transmit Single Collision Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. 14 1 read-write TXUFLOWERFIM MMC Transmit Underflow Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. 13 1 read-write TXBCGBFIM MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. 12 1 read-write TXMCGBFIM MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. 11 1 read-write TXUCGBFIM MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. 10 1 read-write TX1024TMAXOCTGBFIM MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. 9 1 read-write TX512T1023OCTGBFIM MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. 8 1 read-write TX256T511OCTGBFIM MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. 7 1 read-write TX128T255OCTGBFIM MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. 6 1 read-write TX65T127OCTGBFIM MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. 5 1 read-write TX64OCTGBFIM MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. 4 1 read-write TXMCGFIM MMC Transmit Multicast Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. 3 1 read-write TXBCGFIM MMC Transmit Broadcast Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. 2 1 read-write TXGBFRMIM MMC Transmit Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. 1 1 read-write TXGBOCTIM MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. 0 1 read-write txoctetcount_gb Number of bytes transmitted, exclusive of preamble and retried bytes, in good and bad frames. 0x114 32 0x00000000 0xFFFFFFFF BYTECNT Number of bytes transmitted, exclusive of preamble and retried bytes, in good and bad frames. 0 32 read-write txframecount_gb Number of good and bad frames transmitted, exclusive of retried frames. 0x118 32 0x00000000 0xFFFFFFFF FRMCNT Number of good and bad frames transmitted, exclusive of retried frames. 0 32 read-write txbroadcastframes_g Number of good broadcast frames transmitted 0x11c 32 0x00000000 0xFFFFFFFF FRMCNT Number of good broadcast frames transmitted. 0 32 read-write txmlticastframes_g Number of good multicast frames transmitted 0x120 32 0x00000000 0xFFFFFFFF FRMCNT Number of good multicast frames transmitted. 0 32 read-write tx64octets_gb Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. 0x124 32 0x00000000 0xFFFFFFFF FRMCNT Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. 0 32 read-write tx65to127octets_gb Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. 0x128 32 0x00000000 0xFFFFFFFF FRMCNT Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. 0 32 read-write tx128to255octets_gb Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. 0x12c 32 0x00000000 0xFFFFFFFF FRMCNT Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. 0 32 read-write tx256to511octets_gb Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. 0x130 32 0x00000000 0xFFFFFFFF FRMCNT Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. 0 32 read-write tx512to1023octets_gb Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. 0x134 32 0x00000000 0xFFFFFFFF FRMCNT Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. 0 32 read-write tx1024tomaxoctets_gb Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. 0x138 32 0x00000000 0xFFFFFFFF FRMCNT Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. 0 32 read-write rxframecount_gb Number of good and bad frames received 0x180 32 0x00000000 0xFFFFFFFF FRMCNT Number of good and bad frames received. 0 32 read-write mmc_ipc_intr_mask_rx MMC IPC Receive Checksum Offload Interrupt Mask maintains the mask for the interrupt generated from the receive IPC statistic counters. 0x200 32 0x00000000 0x3FFF3FFF RXICMPEROIM MMC Receive ICMP Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. 29 1 read-write RXICMPGOIM MMC Receive ICMP Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. 28 1 read-write RXTCPEROIM MMC Receive TCP Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. 27 1 read-write RXTCPGOIM MMC Receive TCP Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. 26 1 read-write RXUDPEROIM MMC Receive UDP Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. 25 1 read-write RXUDPGOIM MMC Receive IPV6 No Payload Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. 24 1 read-write RXIPV6NOPAYOIM MMC Receive IPV6 Header Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. 23 1 read-write RXIPV6HEROIM MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. 22 1 read-write RXIPV6GOIM MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. 21 1 read-write RXIPV4UDSBLOIM MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. 20 1 read-write RXIPV4FRAGOIM MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. 19 1 read-write RXIPV4NOPAYOIM MMC Receive IPV4 No Payload Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. 18 1 read-write RXIPV4HEROIM MMC Receive IPV4 Header Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. 17 1 read-write RXIPV4GOIM MMC Receive IPV4 Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. 16 1 read-write RXICMPERFIM MMC Receive ICMP Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. 13 1 read-write RXICMPGFIM MMC Receive ICMP Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. 12 1 read-write RXTCPERFIM MMC Receive TCP Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. 11 1 read-write RXTCPGFIM MMC Receive TCP Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. 10 1 read-write RXUDPERFIM MMC Receive UDP Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. 9 1 read-write RXUDPGFIM MMC Receive UDP Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. 8 1 read-write RXIPV6NOPAYFIM MMC Receive IPV6 No Payload Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. 7 1 read-write RXIPV6HERFIM MMC Receive IPV6 Header Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. 6 1 read-write RXIPV6GFIM MMC Receive IPV6 Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. 5 1 read-write RXIPV4UDSBLFIM MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. 4 1 read-write RXIPV4FRAGFIM MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. 3 1 read-write RXIPV4NOPAYFIM MMC Receive IPV4 No Payload Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. 2 1 read-write RXIPV4HERFIM MMC Receive IPV4 Header Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. 1 1 read-write RXIPV4GFIM MMC Receive IPV4 Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. 0 1 read-write mmc_ipc_intr_rx MMC Receive Checksum Offload Interrupt maintains the interrupt that the receive IPC statistic counters generate. See Table 4-25 for further detail. 0x208 32 0x00000000 0x3FFF3FFF RXICMPEROIS MMC Receive ICMP Error Octet Counter Interrupt Status This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. 29 1 read-write RXICMPGOIS MMC Receive ICMP Good Octet Counter Interrupt Status This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. 28 1 read-write RXTCPEROIS MMC Receive TCP Error Octet Counter Interrupt Status This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. 27 1 read-write RXTCPGOIS MMC Receive TCP Good Octet Counter Interrupt Status This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value 26 1 read-write RXUDPEROIS MMC Receive UDP Error Octet Counter Interrupt Status This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. 25 1 read-write RXUDPGOIS MMC Receive UDP Good Octet Counter Interrupt Status This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. 24 1 read-write RXIPV6NOPAYOIS MMC Receive IPV6 No Payload Octet Counter Interrupt Status This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. 23 1 read-write RXIPV6HEROIS MMC Receive IPV6 Header Error Octet Counter Interrupt Status This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. 22 1 read-write RXIPV6GOIS MMC Receive IPV6 Good Octet Counter Interrupt Status This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. 21 1 read-write RXIPV4UDSBLOIS MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. 20 1 read-write RXIPV4FRAGOIS MMC Receive IPV4 Fragmented Octet Counter Interrupt Status This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. 19 1 read-write RXIPV4NOPAYOIS MMC Receive IPV4 No Payload Octet Counter Interrupt Status This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. 18 1 read-write RXIPV4HEROIS MMC Receive IPV4 Header Error Octet Counter Interrupt Status This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. 17 1 read-write RXIPV4GOIS MMC Receive IPV4 Good Octet Counter Interrupt Status This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. 16 1 read-write RXICMPERFIS MMC Receive ICMP Error Frame Counter Interrupt Status This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. 13 1 read-write RXICMPGFIS MMC Receive ICMP Good Frame Counter Interrupt Status This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. 12 1 read-write RXTCPERFIS MMC Receive TCP Error Frame Counter Interrupt Status This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. 11 1 read-write RXTCPGFIS MMC Receive TCP Good Frame Counter Interrupt Status This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. 10 1 read-write RXUDPERFIS MMC Receive UDP Error Frame Counter Interrupt Status This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. 9 1 read-write RXUDPGFIS MMC Receive UDP Good Frame Counter Interrupt Status This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. 8 1 read-write RXIPV6NOPAYFIS MMC Receive IPV6 No Payload Frame Counter Interrupt Status This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. 7 1 read-write RXIPV6HERFIS MMC Receive IPV6 Header Error Frame Counter Interrupt Status This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. 6 1 read-write RXIPV6GFIS MMC Receive IPV6 Good Frame Counter Interrupt Status This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. 5 1 read-write RXIPV4UDSBLFIS MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. 4 1 read-write RXIPV4FRAGFIS MMC Receive IPV4 Fragmented Frame Counter Interrupt Status This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. 3 1 read-write RXIPV4NOPAYFIS MMC Receive IPV4 No Payload Frame Counter Interrupt Status This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. 2 1 read-write RXIPV4HERFIS MMC Receive IPV4 Header Error Frame Counter Interrupt Status This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. 1 1 read-write RXIPV4GFIS MMC Receive IPV4 Good Frame Counter Interrupt Status This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. 0 1 read-write rxipv4_gd_fms Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload 0x210 32 0x00000000 0xFFFFFFFF FRMCNT Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload 0 32 read-write 1 0x20 0 L3_L4_CFG[%s] no description available 0x400 L3_L4_CTRL Layer 3 and Layer 4 Control Register 0x0 32 0x00000000 0x003DFFFD L4DPIM0 Layer 4 Destination Port Inverse Match Enable When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. 21 1 read-write L4DPM0 Layer 4 Destination Port Match Enable When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. 20 1 read-write L4SPIM0 Layer 4 Source Port Inverse Match Enable When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. 19 1 read-write L4SPM0 Layer 4 Source Port Match Enable When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. 18 1 read-write L4PEN0 Layer 4 Protocol Enable When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. 16 1 read-write L3HDBM0 Layer 3 IP DA Higher Bits Match IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: - 0: No bits are masked. - 1: LSb[0] is masked. - 2: Two LSbs [1:0] are masked. - ... - 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: - 0: No bits are masked. - 1: LSb[0] is masked. - 2: Two LSbs [1:0] are masked. - … - 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. 11 5 read-write L3HSBM0 Layer 3 IP SA Higher Bits Match IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: - 0: No bits are masked. - 1: LSb[0] is masked. - 2: Two LSbs [1:0] are masked. - ... - 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. 6 5 read-write L3DAIM0 Layer 3 IP DA Inverse Match Enable When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. 5 1 read-write L3DAM0 Layer 3 IP DA Match Enable When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. 4 1 read-write L3SAIM0 Layer 3 IP SA Inverse Match Enable When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. 3 1 read-write L3SAM0 Layer 3 IP SA Match Enable When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. 2 1 read-write L3PEN0 Layer 3 Protocol Enable When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. 0 1 read-write L4_Addr Layer 4 Address Register 0x4 32 0x00000000 0xFFFFFFFF L4DP0 Layer 4 Destination Port Number Field When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. 16 16 read-write L4SP0 Layer 4 Source Port Number Field When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. 0 16 read-write L3_Addr_0 Layer 3 Address 0 Register 0x10 32 0x00000000 0xFFFFFFFF L3A00 Layer 3 Address 0 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. 0 32 read-write L3_Addr_1 Layer 3 Address 1 Register 0x14 32 0x00000000 0xFFFFFFFF L3A10 Layer 3 Address 1 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. 0 32 read-write L3_Addr_2 Layer 3 Address 2 Register 0x18 32 0x00000000 0xFFFFFFFF L3A20 Layer 3 Address 2 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. 0 32 read-write L3_Addr_3 Layer 3 Address 3 Register 0x1c 32 0x00000000 0xFFFFFFFF L3A30 Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. 0 32 read-write VLAN_TAG_INC_RPL VLAN Tag Inclusion or Replacement Register 0x584 32 0x00000000 0x000FFFFF CSVL C-VLAN or S-VLAN When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. 19 1 read-write VLP VLAN Priority Control When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. 18 1 read-write VLC VLAN Tag Control in Transmit Frames - 2’b00: No VLAN tag deletion, insertion, or replacement - 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. - 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. - 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). Note: Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. 16 2 read-write VLT VLAN Tag for Transmit Frames This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. 0 16 read-write VLAN_HASH VLAN Hash Table Register 0x588 32 0x00000000 0x0000FFFF VLHT VLAN Hash Table This field contains the 16-bit VLAN Hash Table. 0 16 read-write TS_CTRL Timestamp Control Register 0x700 32 0x00000000 0x1F07FF3F ATSEN3 Auxiliary Snapshot 3 Enable This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. 28 1 read-write ATSEN2 Auxiliary Snapshot 2 Enable This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. 27 1 read-write ATSEN1 Auxiliary Snapshot 1 Enable This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. 26 1 read-write ATSEN0 Auxiliary Snapshot 0 Enable This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. 25 1 read-write ATSFC Auxiliary Snapshot FIFO Clear When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. 24 1 read-write TSENMACADDR Enable MAC address for PTP Frame Filtering When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. 18 1 read-write SNAPTYPSEL Select PTP packets for Taking Snapshots These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. 16 2 read-write TSMSTRENA Enable Snapshot for Messages Relevant to Master When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. 15 1 read-write TSEVNTENA Enable Timestamp Snapshot for Event Messages When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. 14 1 read-write TSIPV4ENA Enable Processing of PTP Frames Sent over IPv4-UDP When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. 13 1 read-write TSIPV6ENA Enable Processing of PTP Frames Sent over IPv6-UDP When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. 12 1 read-write TSIPENA Enable Processing of PTP over Ethernet Frames When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets 11 1 read-write TSVER2ENA Enable PTP packet Processing for Version 2 Format When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. 10 1 read-write TSCTRLSSR Timestamp Digital or Binary Rollover Control When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. 9 1 read-write TSENALL Enable Timestamp for All Frames When set, the timestamp snapshot is enabled for all frames received by the MAC. 8 1 read-write TSADDREG Addend Reg Update When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. 5 1 read-write TSTRIG Timestamp Interrupt Trigger Enable When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. This bit is reset after the generation of the Timestamp Trigger Interrupt. 4 1 read-write TSUPDT Timestamp Update When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. 3 1 read-write TSINIT Timestamp Initialize When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the initialization is complete. The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. 2 1 read-write TSCFUPDT Timestamp Fine or Coarse Update When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. 1 1 read-write TSENA Timestamp Enable When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. 0 1 read-write SUB_SEC_INCR Sub-Second Increment Register 0x704 32 0x00000000 0x000000FF SSINC Sub-second Increment Value The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. 0 8 read-write SYST_SEC System Time - Seconds Register 0x708 32 0x00000000 0xFFFFFFFF TSS Timestamp Second The value in this field indicates the current value in seconds of the System Time maintained by the MAC. 0 32 read-only SYST_NSEC System Time - Nanoseconds Register 0x70c 32 0x00000000 0x7FFFFFFF TSSS Timestamp Sub Seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. 0 31 read-only SYST_SEC_UPD System Time - Seconds Update Register 0x710 32 0x00000000 0xFFFFFFFF TSS Timestamp Second The value in this field indicates the time in seconds to be initialized or added to the system time. 0 32 read-write SYST_NSEC_UPD System Time - Nanoseconds Update Register 0x714 32 0x00000000 0xFFFFFFFF ADDSUB Add or Subtract Time When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. 31 1 read-write TSSS Timestamp Sub Seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. 0 31 read-write TS_ADDEND Timestamp Addend Register 0x718 32 0x00000000 0xFFFFFFFF TSAR Timestamp Addend Register This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. 0 32 read-write TGTTM_SEC Target Time Seconds Register 0x71c 32 0x00000000 0xFFFFFFFF TSTR Target Time Seconds Register This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). 0 32 read-write TGTTM_NSEC Target Time Nanoseconds Register 0x720 32 0x00000000 0xFFFFFFFF TRGTBUSY Target Time Register Busy The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. 31 1 read-write TTSLO Target Timestamp Low Register This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. 0 31 read-write SYSTM_H_SEC System Time - Higher Word Seconds Register 0x724 32 0x00000000 0x0000FFFF TSHWR Timestamp Higher Word Register This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. 0 16 read-write TS_STATUS Timestamp Status Register 0x728 32 0x00000000 0x3F0F03FF ATSNS Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. 25 5 read-only ATSSTM Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. 24 1 read-only ATSSTN Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. These bits are applicable only if the number of Auxiliary snapshots is more than one. One bit is assigned for each trigger as shown in the following list: - Bit 16: Auxiliary trigger 0 - Bit 17: Auxiliary trigger 1 - Bit 18: Auxiliary trigger 2 - Bit 19: Auxiliary trigger 3 The software can read this register to find the triggers that are set when the timestamp is taken. 16 4 read-only TSTRGTERR3 Timestamp Target Time Error This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. 9 1 read-only TSTARGT3 Timestamp Target Time Reached for Target Time PPS3 When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). 8 1 read-only TSTRGTERR2 No description available 7 1 read-only TSTARGT2 No description available 6 1 read-only TSTRGTERR1 No description available 5 1 read-only TSTARGT1 No description available 4 1 read-only TSTRGTERR No description available 3 1 read-only AUXTSTRIG No description available 2 1 read-only TSTARGT No description available 1 1 read-only TSSOVF No description available 0 1 read-only PPS_CTRL PPS Control Register 0x72c 32 0x00000000 0x6767777F TRGTMODSEL3 Target Time Register Mode for PPS3 Output This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. 29 2 read-write PPSCMD3 Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. 24 3 read-write TRGTMODSEL2 Target Time Register Mode for PPS2 Output This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. 21 2 read-write PPSCMD2 Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. 16 3 read-write TRGTMODSEL1 Target Time Register Mode for PPS1 Output This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. 13 2 read-write PPSEN1 Flexible PPS1 Output Mode Enable When set high, Bits[10:8] function as PPSCMD. 12 1 read-write PPSCMD1 Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. 8 3 read-write TRGTMODSEL0 Target Time Register Mode for PPS0 Output This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: - 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. - 01: Reserved - 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. - 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. 5 2 read-write PPSEN0 Flexible PPS Output Mode Enable When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. 4 1 read-write PPSCTRLCMD0 PPSCTRL0: PPS0 Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: - 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. - 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. - 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. - 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... - 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - One clock of 50 percent duty cycle and 537 ms period - Second clock of 463 ms period (268 ms low and 195 ms high) - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - Three clocks of 50 percent duty cycle and 268 ms period - Fourth clock of 195 ms period (134 ms low and 61 ms high) PPSCMD0: Flexible PPS0 Output Control 0000: No Command 0001: START Single Pulse This command generates single pulse rising at the start point defined in Target Time Registers and of a duration defined in the PPS0 Width Register. 0010: START Pulse Train This command generates the train of pulses rising at the start point defined in the Target Time Registers and of a duration defined in the PPS0 Width Register and repeated at interval defined in the PPS Interval Register. By default, the PPS pulse train is free-running unless stopped by ‘STOP Pulse train at time’ or ‘STOP Pulse Train immediately’ commands. 0011: Cancel START This command cancels the START Single Pulse and START Pulse Train commands if the system time has not crossed the programmed start time. 0100: STOP Pulse train at time This command stops the train of pulses initiated by the START Pulse Train command (PPSCMD = 0010) after the time programmed in the Target Time registers elapses. 0101: STOP Pulse Train immediately This command immediately stops the train of pulses initiated by the START Pulse Train command (PPSCMD = 0010). 0110: Cancel STOP Pulse train This command cancels the STOP pulse train at time command if the programmed stop time has not elapsed. The PPS pulse train becomes free-running on the successful execution of this command. 0111-1111: Reserved Note: These bits get cleared automatically 0 4 read-write AUX_TS_NSEC Auxiliary Timestamp - Nanoseconds Register 0x730 32 0x00000000 0x7FFFFFFF AUXTSLO Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. 0 31 read-only AUX_TS_SEC Auxiliary Timestamp - Seconds Register 0x734 32 0x00000000 0xFFFFFFFF AUXTSHI Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. 0 32 read-only PPS0_INTERVAL PPS0 Interval Register 0x760 32 0x00000000 0xFFFFFFFF PPSINT PPS0 Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS0 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. 0 32 read-write PPS0_WIDTH PPS0 Width Register 0x764 32 0x00000000 0xFFFFFFFF PPSWIDTH PPS0 Output Signal Width These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. 0 32 read-write 3 0x20 1,2,3 PPS[%s] no description available 0x780 TGTTM_SEC PPS Target Time Seconds Register 0x0 32 0x00000000 0xFFFFFFFF TSTRH1 PPS1 Target Time Seconds Register This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). 0 32 read-write TGTTM_NSEC PPS Target Time Nanoseconds Register 0x4 32 0x00000000 0xFFFFFFFF TRGTBUSY1 PPS1 Target Time Register Busy The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. 31 1 read-write TTSL1 Target Time Low for PPS1 Register This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. 0 31 read-write INTERVAL PPS Interval Register 0x8 32 0x00000000 0xFFFFFFFF PPSINT PPS1 Output Signal Interval These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. 0 32 read-write WIDTH PPS Width Register 0xc 32 0x00000000 0xFFFFFFFF PPSWIDTH PPS1 Output Signal Width These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. 0 32 read-write DMA_BUS_MODE Bus Mode Register 0x1000 32 0x00000000 0xBFFFFFFF RIB Rebuild INCRx Burst When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. 31 1 read-write PRWG Channel Priority Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. - 00: The priority weight is 1. - 01: The priority weight is 2. - 10: The priority weight is 3. - 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). 28 2 read-write TXPR Transmit Priority When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). 27 1 read-write MB Mixed Burst When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. 26 1 read-write AAL Address-Aligned Beats When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. 25 1 read-write PBLX8 PBLx8 Mode When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. 24 1 read-write USP Use Separate PBL When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. 23 1 read-write RPBL Rx DMA PBL This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write. The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP is set high. 17 6 read-write FB Fixed Burst This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. 16 1 read-write PR Priority Ratio These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. - 00: The Priority Ratio is 1:1. - 01: The Priority Ratio is 2:1. - 10: The Priority Ratio is 3:1. - 11: The Priority Ratio is 4:1. 14 2 read-write PBL Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA transaction. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. 8 6 read-write ATDS Alternate Descriptor Size When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: - Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). 7 1 read-write DSL Descriptor Skip Length This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. 2 5 read-write DA DMA Arbitration Scheme This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. - 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). - 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. 1 1 read-write SWR Software Reset When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. Note: - The Software reset function is driven only by this bit. Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. - The reset operation is completed only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock. 0 1 read-write DMA_TX_POLL_DEMAND Transmit Poll Demand Register 0x1004 32 0x00000000 0xFFFFFFFF TPD Transmit Poll Demand When these bits are written with any value, the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. If the descriptor is available, the transmission resumes. 0 32 read-write DMA_RX_POLL_DEMAND Receive Poll Demand Register 0x1008 32 0x00000000 0xFFFFFFFF RPD Receive Poll Demand When these bits are written with any value, the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. If the descriptor is available, the Rx DMA returns to the active state. 0 32 read-write DMA_RX_DESC_LIST_ADDR Receive Descriptor List Address Register 0x100c 32 0x00000000 0xFFFFFFFF RDESLA Start of Receive List This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). 0 32 read-write DMA_TX_DESC_LIST_ADDR Transmit Descriptor List Address Register 0x1010 32 0x00000000 0xFFFFFFFF TDESLA Start of Transmit List This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). 0 32 read-write DMA_STATUS Status Register 0x1014 32 0x00000000 0x7FFFE7FF GLPII GLPII: GMAC LPI Interrupt (for Channel 0) This bit indicates an interrupt event in the LPI logic of the MAC. To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. -or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. 30 1 read-write TTI Timestamp Trigger Interrupt This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. 29 1 read-write GPI GMAC PMT Interrupt This bit indicates an interrupt event in the PMT module of the DWC_gmac. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the Power Management feature is enabled. Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. 28 1 read-write GMI GMAC MMC Interrupt This bit reflects an interrupt event in the MMC module of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. 27 1 read-write GLI GMAC Line Interface Interrupt When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): - PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event - SMII or RGMII: Link change event - General Purpose Input Status (GPIS): Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), read any of the following corresponding registers: - PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) - SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) - General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. 26 1 read-write EB Error Bits This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. - 0 0 0: Error during Rx DMA Write Data Transfer - 0 1 1: Error during Tx DMA Read Data Transfer - 1 0 0: Error during Rx DMA Descriptor Write Access - 1 0 1: Error during Tx DMA Descriptor Write Access - 1 1 0: Error during Rx DMA Descriptor Read Access - 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. 23 3 read-write TS Transmit Process State This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. - 3’b000: Stopped; Reset or Stop Transmit Command issued - 3’b001: Running; Fetching Transmit Transfer Descriptor - 3’b010: Running; Waiting for status - 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) - 3’b100: TIME_STAMP write state - 3’b101: Reserved for future use - 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow - 3’b111: Running; Closing Transmit Descriptor 20 3 read-write RS Receive Process State This field indicates the Receive DMA FSM state. This field does not generate an interrupt. - 3’b000: Stopped: Reset or Stop Receive Command issued - 3’b001: Running: Fetching Receive Transfer Descriptor - 3’b010: Reserved for future use - 3’b011: Running: Waiting for receive packet - 3’b100: Suspended: Receive Descriptor Unavailable - 3’b101: Running: Closing Receive Descriptor - 3’b110: TIME_STAMP write state - 3’b111: Running: Transferring the receive packet data from receive buffer to host memory 17 3 read-write NIS Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. 16 1 read-write AIS Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive FIFO Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. 15 1 read-write ERI Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). 14 1 read-write FBI Fatal Bus Error Interrupt This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. 13 1 read-write ETI Early Transmit Interrupt This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. 10 1 read-write RWT Receive Watchdog Timeout When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. 9 1 read-write RPS Receive Process Stopped This bit is asserted when the Receive Process enters the Stopped state. 8 1 read-write RU Receive Buffer Unavailable This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA. 7 1 read-write RI Receive Interrupt This bit indicates that the frame reception is complete. When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, and the specific frame status information is updated in the descriptor. The reception remains in the Running state. 6 1 read-write UNF Transmit Underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. 5 1 read-write OVF Receive Overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. 4 1 read-write TJT Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. 3 1 read-write TU Transmit Buffer Unavailable This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. 2 1 read-write TPS Transmit Process Stopped This bit is set when the transmission is stopped. 1 1 read-write TI Transmit Interrupt This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. 0 1 read-write DMA_OP_MODE Operation Mode Register 0x1018 32 0x00000000 0x13F1FFFE DT Disable Dropping of TCP/IP Checksum Error Frames When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). 28 1 read-write RSF Receive Store and Forward When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. 25 1 read-write DFF Disable Flushing of Received Frames When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) 24 1 read-write RFA_2 MSB of Threshold for Activating Flow Control If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: - 100: Full minus 5 KB, that is, FULL — 5 KB - 101: Full minus 6 KB, that is, FULL — 6 KB - 110: Full minus 7 KB, that is, FULL — 7 KB - 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. 23 1 read-write RFD_2 MSB of Threshold for Deactivating Flow Control If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: - 100: Full minus 5 KB, that is, FULL — 5 KB - 101: Full minus 6 KB, that is, FULL — 6 KB - 110: Full minus 7 KB, that is, FULL — 7 KB - 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. 22 1 read-write TSF Transmit Store and Forward When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set, the TTC values specified in Bits [16:14] are ignored. This bit should be changed only when the transmission is stopped. 21 1 read-write FTF Flush Transmit FIFO When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt frame transmission. 20 1 read-write TTC Transmit Threshold Control These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when Bit 21 (TSF) is reset. - 000: 64 - 001: 128 - 010: 192 - 011: 256 - 100: 40 - 101: 32 - 110: 24 - 111: 16 14 3 read-write ST Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), or from the position retained when transmission was stopped previously. If the DMA does not own the current descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and it becomes the current position when transmission is restarted. To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. 13 1 read-write RFD Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. - 00: Full minus 1 KB, that is, FULL — 1 KB - 01: Full minus 2 KB, that is, FULL — 2 KB - 10: Full minus 3 KB, that is, FULL — 3 KB - 11: Full minus 4 KB, that is, FULL — 4 KB The de-assertion is effective only after flow control is asserted. If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. 11 2 read-write RFA Threshold for Activating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. - 00: Full minus 1 KB, that is, FULL—1KB. - 01: Full minus 2 KB, that is, FULL—2KB. - 10: Full minus 3 KB, that is, FULL—3KB. - 11: Full minus 4 KB, that is, FULL—4KB. These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition 9 2 read-write EFC Enable HW Flow Control When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. When reset, the flow control operation is disabled. This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. 8 1 read-write FEF Forward Error Frames When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, then the frame is dropped irrespective of the FEF bit setting. However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: - The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - The advanced timestamp feature is not selected but the extended status is selected. The extended status is available with the following features: - L3-L4 filter in GMAC-CORE or GMAC-MTL configurations - Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. 7 1 read-write FUF Forward Undersized Good Frames When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC. When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. 6 1 read-write DGF Drop Giant Frames When set, the MAC drops the received giant frames in the Rx FIFO, that is, frames that are larger than the computed giant frame limit. When reset, the MAC does not drop the giant frames in the Rx FIFO. Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: - Configurations in which IP Checksum Offload (Type 1) is selected in Rx - Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format - Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). 5 1 read-write RTC Receive Threshold Control These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with length less than the threshold are automatically transferred. The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. - 00: 64 - 01: 32 - 10: 96 - 11: 128 3 2 read-write OSF Operate on Second Frame When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. 2 1 read-write SR Start or Stop Receive When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. The descriptor acquisition is attempted from the current position in the list, which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. The Start Receive command is effective only when the reception has stopped. If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. 1 1 read-write DMA_INTR_EN Interrupt Enable Register 0x101c 32 0x00000000 0x0001E7FF NIE Normal Interrupt Summary Enable When this bit is set, normal interrupt summary is enabled. When this bit is reset, normal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt 16 1 read-write AIE Abnormal Interrupt Summary Enable When this bit is set, abnormal interrupt summary is enabled. When this bit is reset, the abnormal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error 15 1 read-write ERE Early Receive Interrupt Enable When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. 14 1 read-write FBE Fatal Bus Error Enable When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. 13 1 read-write ETE Early Transmit Interrupt Enable When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. 10 1 read-write RWE Receive Watchdog Timeout Enable When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. 9 1 read-write RSE Receive Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. 8 1 read-write RUE Receive Buffer Unavailable Enable When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. 7 1 read-write RIE Receive Interrupt Enable When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. 6 1 read-write UNE Underflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. 5 1 read-write OVE Overflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. 4 1 read-write TJE Transmit Jabber Timeout Enable When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. 3 1 read-write TUE Transmit Buffer Unavailable Enable When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. 2 1 read-write TSE Transmit Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. 1 1 read-write TIE Transmit Interrupt Enable When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. 0 1 read-write DMA_MISS_OVF_CNT Missed Frame And Buffer Overflow Counter Register 0x1020 32 0x00000000 0x1FFFFFFF ONFCNTOVF Overflow Bit for FIFO Overflow Counter This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, that is, the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. 28 1 read-write OVFFRMCNT Overflow Frame Counter This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. 17 11 read-write MISCNTOVF Overflow Bit for Missed Frame Counter This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. 16 1 read-write MISFRMCNT Missed Frame Counter This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. 0 16 read-write DMA_RX_INTR_WDOG Receive Interrupt Watchdog Timer Register 0x1024 32 0x00000000 0x000000FF RIWT RI Watchdog Timer Count This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. 0 8 read-write DMA_AXI_MODE AXI Bus Mode Register 0x1028 32 0x00000000 0xC0FF30FF EN_LPI Enable Low Power Interface (LPI) When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. 31 1 read-write LPI_XIT_FRM Unlock on Magic Packet or Remote Wake-Up Frame When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. 30 1 read-write WR_OSR_LMT AXI Maximum Write Outstanding Request Limit This value limits the maximum outstanding request on the AXI write interface. Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. 20 4 read-write RD_OSR_LMT AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. 16 4 read-write ONEKBBE 1 KB Boundary Crossing Enable for the GMAC-AXI Master When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. 13 1 read-write AXI_AAL Address-Aligned Beats This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. 12 1 read-write BLEN256 AXI Burst Length 256 When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). 7 1 read-write BLEN128 AXI Burst Length 128 When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). 6 1 read-write BLEN64 AXI Burst Length 64 When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). 5 1 read-write BLEN32 AXI Burst Length 32 When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). 4 1 read-write BLEN16 AXI Burst Length 16 When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. 3 1 read-write BLEN8 AXI Burst Length 8 When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. 2 1 read-write BLEN4 AXI Burst Length 4 When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. 1 1 read-write UNDEF AXI Undefined Burst Length This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). - When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. - When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. 0 1 read-write DMA_BUS_STATUS AHB or AXI Status Register 0x102c 32 0x00000000 0x00000003 AXIRDSTS AXI Master Read Channel Status When high, it indicates that AXI master's read channel is active and transferring data. 1 1 read-write AXWHSTS AXI Master Write Channel or AHB Master Status When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, it indicates that the AHB master interface FSMs are in the non-idle state. 0 1 read-write DMA_CURR_HOST_TX_DESC Current Host Transmit Descriptor Register 0x1048 32 0x00000000 0xFFFFFFFF CURTDESAPTR Host Transmit Descriptor Address Pointer Cleared on Reset. Pointer updated by the DMA during operation. 0 32 read-write DMA_CURR_HOST_RX_DESC Current Host Receive Descriptor Register 0x104c 32 0x00000000 0xFFFFFFFF CURRDESAPTR Host Receive Descriptor Address Pointer Cleared on Reset. Pointer updated by the DMA during operation. 0 32 read-write DMA_CURR_HOST_TX_BUF Current Host Transmit Buffer Address Register 0x1050 32 0x00000000 0xFFFFFFFF CURTBUFAPTR Host Transmit Buffer Address Pointer Cleared on Reset. Pointer updated by the DMA during operation. 0 32 read-write DMA_CURR_HOST_RX_BUF Current Host Receive Buffer Address Register 0x1054 32 0x00000000 0xFFFFFFFF CURRBUFAPTR Host Receive Buffer Address Pointer Cleared on Reset. Pointer updated by the DMA during operation. 0 32 read-write CTRL0 Control Register 0 0x3000 32 0x00000000 0x00003F3F ENET0_RXCLK_DLY_SEL No description available 8 6 read-write ENET0_TXCLK_DLY_SEL No description available 0 6 read-write CTRL2 Control Register 1 0x3008 32 0x00000000 0x2008F400 ENET0_LPI_IRQ_EN lowpower interrupt enable, for internal use only, user should use core registers for enable/disable interrupt 29 1 read-write ENET0_REFCLK_OE set to enable output 50MHz clock to rmii phy. User should set it if use soc internal clock as refclk 19 1 read-write ENET0_PHY_INF_SEL PHY mode select 000MII; 001RGMII; 100RMII; should be set before config IOMUX, otherwise may cause glitch for RGMII 13 3 read-write ENET0_FLOWCTRL flow control request 12 1 read-write ENET0_RMII_TXCLK_SEL RMII mode output clock pad select set to use txck as RMII refclk; clr to use rxck as RMII refclk; default 0(rxck) refclk is always from pad, can use external clock from pad, or use internal clock output to pad then loopback. 10 1 read-write USB0 USB0 USB 0xf1120000 0x80 0x1a8 registers GPTIMER0LD General Purpose Timer #0 Load Register 0x80 32 0x00000000 0x00FFFFFF GPTLD GPTLD General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. This value represents the time in microseconds minus 1 for the timer duration. Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. NOTE: Max value is 0xFFFFFF or 16.777215 seconds. 0 24 read-write GPTIMER0CTRL General Purpose Timer #0 Controller Register 0x84 32 0x00000000 0xC1FFFFFF GPTRUN GPTRUN General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. 0 - Stop counting 1 - Run 31 1 read-write GPTRST GPTRST General Purpose Timer Reset 0 - No action 1 - Load counter value from GPTLD bits in n_GPTIMER0LD 30 1 write-only GPTMODE GPTMODE General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software; In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again. 0 - One Shot Mode 1 - Repeat Mode 24 1 read-write GPTCNT GPTCNT General Purpose Timer Counter. This field is the count value of the countdown timer. 0 24 read-only GPTIMER1LD General Purpose Timer #1 Load Register 0x88 32 0x00000000 0x00FFFFFF GPTLD GPTLD General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. This value represents the time in microseconds minus 1 for the timer duration. Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. NOTE: Max value is 0xFFFFFF or 16.777215 seconds. 0 24 read-write GPTIMER1CTRL General Purpose Timer #1 Controller Register 0x8c 32 0x00000000 0xC1FFFFFF GPTRUN GPTRUN General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. 0 - Stop counting 1 - Run 31 1 read-write GPTRST GPTRST General Purpose Timer Reset 0 - No action 1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD 30 1 write-only GPTMODE GPTMODE General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again. 0 - One Shot Mode 1 - Repeat Mode 24 1 read-write GPTCNT GPTCNT General Purpose Timer Counter. This field is the count value of the countdown timer. 0 24 read-only SBUSCFG System Bus Config Register 0x90 32 0x00000000 0x00000007 AHBBRST AHBBRST AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority). NOTE: This register overrides n_BURSTSIZE register when its value is not zero. 000 - Incremental burst of unspecified length only 001 - INCR4 burst, then single transfer 010 - INCR8 burst, INCR4 burst, then single transfer 011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer 100 - Reserved, don't use 101 - INCR4 burst, then incremental burst of unspecified length 110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length 111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length 0 3 read-write USBCMD USB Command Register 0x140 32 0x00080000 0x00FFFB7F ITC ITC Interrupt Threshold Control -Read/Write. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. Value Maximum Interrupt Interval 00000000 - Immediate (no threshold) 00000001 - 1 micro-frame 00000010 - 2 micro-frames 00000100 - 4 micro-frames 00001000 - 8 micro-frames 00010000 - 16 micro-frames 00100000 - 32 micro-frames 01000000 - 64 micro-frames 16 8 read-write FS_2 FS_2 Frame List Size - (Read/Write or Read Only). [host mode only] This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. NOTE: This field is made up from USBCMD bits 15, 3 and 2. Value Meaning 0b000 - 1024 elements (4096 bytes) Default value 0b001 - 512 elements (2048 bytes) 0b010 - 256 elements (1024 bytes) 0b011 - 128 elements (512 bytes) 0b100 - 64 elements (256 bytes) 0b101 - 32 elements (128 bytes) 0b110 - 16 elements (64 bytes) 0b111 - 8 elements (32 bytes) 15 1 read-write ATDTW ATDTW Add dTD TripWire - Read/Write. [device mode only] This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software. This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized. 14 1 read-write SUTW SUTW Setup TripWire - Read/Write. [device mode only] This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then there is a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software. This bit would also be cleared by hardware when a hazard detected. 13 1 read-write PRM Asynchronous Schedule start- Write only， host mode only。 this bit is used to notify hostcontroller to start async schedule immediately. 12 1 write-only ASPE ASPE Asynchronous Schedule Park Mode Enable - Read/Write. If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. NOTE: ASPE bit reset value: '0b' for OTG controller . 11 1 read-write ASP ASP Asynchronous Schedule Park Mode Count - Read/Write. If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. This field is set to 3h in all controller core. 8 2 read-write IAA IAA Interrupt on Async Advance Doorbell - Read/Write. This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. 6 1 read-write ASE ASE Asynchronous Schedule Enable - Read/Write. Default 0b. This bit controls whether the host controller skips processing the Asynchronous Schedule. Only the host controller uses this bit. Values Meaning 0 - Do not process the Asynchronous Schedule. 1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. 5 1 read-write PSE PSE Periodic Schedule Enable- Read/Write. Default 0b. This bit controls whether the host controller skips processing the Periodic Schedule. Only the host controller uses this bit. Values Meaning 0 - Do not process the Periodic Schedule 1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. 4 1 read-write FS_1 FS_1 See description at bit 15 2 2 read-write RST RST Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. Host operation mode: When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior. Device operation mode: When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. 1 1 read-write RS RS Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. Host operation mode: When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). Device operation mode: Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. 0 1 read-write USBSTS USB Status Register 0x144 32 0x00000000 0x030DF1FF TI1 TI1 General Purpose Timer Interrupt 1(GPTINT1)--R/WC. This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this bit will clear it. 25 1 read-write TI0 TI0 General Purpose Timer Interrupt 0(GPTINT0)--R/WC. This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this bit clears it. 24 1 read-write UPI USB Host Periodic Interrupt – RWC. Default = 0b. This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than expected. This bit is not used by the device controller and will always be zero. 19 1 read-write UAI USB Host Asynchronous Interrupt – RWC. Default = 0b. This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than expected. This bit is not used by the device controller and will always be zero 18 1 read-write NAKI NAKI NAK Interrupt Bit--RO. This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware when all Enabled TX/RX Endpoint NAK bits are cleared. 16 1 read-only AS AS Asynchronous Schedule Status - Read Only. This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). Only used in the host operation mode. 15 1 read-only PS PS Periodic Schedule Status - Read Only. This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). Only used in the host operation mode. 14 1 read-only RCL RCL Reclamation - Read Only. This is a read-only status bit used to detect an empty asynchronous schedule. Only used in the host operation mode. 13 1 read-only HCH HCH HCHaIted - Read Only. This bit is a zero whenever the Run/Stop bit is a one. The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Controller hardware (for example, an internal error). Only used in the host operation mode. Default value is '0b' for OTG core . This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE register. NOTE: HCH bit reset value: '0b' for OTG controller core . 12 1 read-only SLI SLI DCSuspend - R/WC. When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. Only used in device operation mode. 8 1 read-write SRI SRI SOF Received - R/WC. When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. Software writes a 1 to this bit to clear it. 7 1 read-write URI URI USB Reset Received - R/WC. When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. Software can write a 1 to this bit to clear the USB Reset Received status bit. Only used in device operation mode. 6 1 read-write AAI AAI Interrupt on Async Advance - R/WC. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. Only used in host operation mode. 5 1 read-write SEI System Error – RWC. Default = 0b. In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) 4 1 read-write FRI FRI Frame List Rollover - R/WC. The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FHINDEX [12] toggles. Only used in host operation mode. 3 1 read-write PCI PCI Port Change Detect - R/WC. The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. 2 1 read-write UEI UEI USB Error Interrupt (USBERRINT) - R/WC. When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. 1 1 read-write UI UI USB Interrupt (USBINT) - R/WC. This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes. 0 1 read-write USBINTR Interrupt Enable Register 0x148 32 0x00000000 0x030D01FF TIE1 TIE1 General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. 25 1 read-write TIE0 TIE0 General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. 24 1 read-write UPIE UPIE USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold. 19 1 read-write UAIE UAIE USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold. 18 1 read-write NAKE NAKE NAK Interrupt Enable When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. 16 1 read-only SLE SLE Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. Only used in device operation mode. 8 1 read-write SRE SRE SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. 7 1 read-write URE URE USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in device operation mode. 6 1 read-write AAE AAE Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in host operation mode. 5 1 read-write SEE SEE System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in host operation mode. 4 1 read-write FRE FRE Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in host operation mode. 3 1 read-write PCE PCE Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. 2 1 read-write UEE UEE USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. 1 1 read-write UE UE USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. 0 1 read-write FRINDEX USB Frame Index Register 0x14c 32 0x00000000 0x00003FFF FRINDEX FRINDEX Frame Index. The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. USBCMD [Frame List Size] Number Elements N In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. In either mode bits 2:0 indicate the current microframe. The bit field values description below is represented as (Frame List Size) Number Elements N. 00000000000000 - (1024) 12 00000000000001 - (512) 11 00000000000010 - (256) 10 00000000000011 - (128) 9 00000000000100 - (64) 8 00000000000101 - (32) 7 00000000000110 - (16) 6 00000000000111 - (8) 5 0 14 read-write DEVICEADDR Device Address Register UNION_154 0x154 32 0x00000000 0xFF000000 USBADR USBADR Device Address. These bits correspond to the USB device address 25 7 read-write USBADRA USBADRA Device Address Advance. Default=0. When this bit is '0', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: 1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). 3) Device Reset occurs (USBADR is reset to 0). NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. 24 1 read-write PERIODICLISTBASE Frame List Base Address Register UNION_154 0x154 32 0x00000000 0xFFFFF000 BASEADR BASEADR Base Address (Low). These bits correspond to memory address signals [31:12], respectively. Only used by the host controller. 12 20 read-write ASYNCLISTADDR Next Asynch. Address Register UNION_158 0x158 32 0x00000000 0xFFFFFFE0 ASYBASE ASYBASE Link Pointer Low (LPL). These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (QH). Only used by the host controller. 5 27 read-write ENDPTLISTADDR Endpoint List Address Register UNION_158 0x158 32 0x00000000 0xFFFFF800 EPBASE EPBASE Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). 11 21 read-write BURSTSIZE Programmable Burst Size Register 0x160 32 0x00000000 0x0000FFFF TXPBURST TXPBURST Programmable TX Burst Size. Default value is determined by TXBURST bits in n_HWTXBUF. This register represents the maximum length of a the burst in 32-bit words while moving data from system memory to the USB bus. 8 8 read-write RXPBURST RXPBURST Programmable RX Burst Size. Default value is determined by TXBURST bits in n_HWRXBUF. This register represents the maximum length of a the burst in 32-bit words while moving data from the USB bus to system memory. 0 8 read-write TXFILLTUNING TX FIFO Fill Tuning Register 0x164 32 0x00000000 0x003F1F7F TXFIFOTHRES TXFIFOTHRES FIFO Burst Threshold. (Read/Write) This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. 16 6 read-write TXSCHHEALTH TXSCHHEALTH Scheduler Health Counter. (Read/Write To Clear) Table continues on the next page This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31. 8 5 read-write TXSCHOH TXSCHOH Scheduler Overhead. (Read/Write) [Default = 0] This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. Default value is '08h' for OTG controller core . 0 7 read-write ENDPTNAK Endpoint NAK Register 0x178 32 0x00000000 0xFFFFFFFF EPTN EPTN TX Endpoint NAK - R/WC. Each TX endpoint has 1 bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit [N] - Endpoint #[N], N is 0-7 16 16 read-write EPRN EPRN RX Endpoint NAK - R/WC. Each RX endpoint has 1 bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit [N] - Endpoint #[N], N is 0-7 0 16 read-write ENDPTNAKEN Endpoint NAK Enable Register 0x17c 32 0x00000000 0xFFFFFFFF EPTNE EPTNE TX Endpoint NAK Enable - R/W. Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. Bit [N] - Endpoint #[N], N is 0-7 16 16 read-write EPRNE EPRNE RX Endpoint NAK Enable - R/W. Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. Bit [N] - Endpoint #[N], N is 0-7 0 16 read-write PORTSC1 Port Status & Control 0x184 32 0x00000000 0x3DFF1FFF STS STS Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. 29 1 read-write PTW PTW Parallel Transceiver Width This bit has no effect if serial interface engine is used. 0 - Select the 8-bit UTMI interface [60MHz] 1 - Select the 16-bit UTMI interface [30MHz] 28 1 read-write PSPD PSPD Port Speed - Read Only. This register field indicates the speed at which the port is operating. 00 - Full Speed 01 - Low Speed 10 - High Speed 11 - Undefined 26 2 read-only PFSC PFSC Port Force Full Speed Connect - Read/Write. Default = 0b. When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp sequence that allows the port to identify itself as High Speed. 0 - Normal operation 1 - Forced to full speed 24 1 read-write PHCD PHCD PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY clock. NOTE: The PHY clock cannot be disabled if it is being used as the system clock. In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend will be cleared automatically when the host initials resume. Before forcing a resume from the device, the device controller driver must clear this bit. In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0 - Enable PHY clock 1 - Disable PHY clock 23 1 read-write WKOC WKOC Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. This field is zero if Port Power(PORTSC1) is zero. 22 1 read-write WKDC WKDC Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. This field is zero if Port Power(PORTSC1) is zero or in device mode. 21 1 read-write WKCN WKCN Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. This field is zero if Port Power(PORTSC1) is zero or in device mode. 20 1 read-write PTC PTC Port Test Control - Read/Write. Default = 0000b. Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. NOTE: Low speed operations are not supported as a peripheral device. Any other value than zero indicates that the port is operating in test mode. Value Specific Test 0000 - TEST_MODE_DISABLE 0001 - J_STATE 0010 - K_STATE 0011 - SE0 (host) / NAK (device) 0100 - Packet 0101 - FORCE_ENABLE_HS 0110 - FORCE_ENABLE_FS 0111 - FORCE_ENABLE_LS 1000-1111 - Reserved 16 4 read-write PP PP Port Power (PP)-Read/Write or Read Only. The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: PPC PP Operation 0 1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. 1 1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). This feature is implemented in all controller cores (PPC = 1). 12 1 read-write LS LS Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because the port controller state machine and the port routing manage the connection of LS and FS. In device mode, the use of linestate by the device controller driver is not necessary. The encoding of the bits are: Bits [11:10] Meaning 00 - SE0 01 - K-state 10 - J-state 11 - Undefined 10 2 read-only HSP HSP High-Speed Port - Read Only. Default = 0b. When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the host/device connected to the port is not in a high-speed mode. NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. 9 1 read-only PR PR Port Reset - Read/Write or Read Only. Default = 0b. In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. 8 1 read-write SUSP SUSP Suspend - Read/Write or Read Only. Default = 0b. 1=Port in suspend state. 0=Port not in suspend state. In Host Mode: Read/Write. Port Enabled Bit and Suspend bit of this register define the port states as follows: Bits [Port Enabled, Suspend] Port State 0x Disable 10 Enable 11 Suspend When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: Read Only. In device mode this bit is a read only status bit. 7 1 read-write FPR FPR Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. In Host Mode: Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. This field is zero if Port Power(PORTSC1) is zero in host mode. This bit is not-EHCI compatible. In Device mode: After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. 6 1 read-write OCC OCC Over-current Change-R/WC. Default=0. This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. 5 1 read-write OCA OCA Over-current Active-Read Only. Default 0. This bit will automatically transition from one to zero when the over current condition is removed. 0 - This port does not have an over-current condition. 1 - This port currently has an over-current condition 4 1 read-only PEC PEC Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. In Host Mode: For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This field is zero if Port Power(PORTSC1) is zero. In Device mode: The device port is always enabled, so this bit is always '0b'. 3 1 read-write PE PE Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. In Host Mode: Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled, (0b) downstream propagation of data is blocked except for reset. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: The device port is always enabled, so this bit is always '1b'. 2 1 read-write CSC CSC Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. In Host Mode: Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: This bit is undefined in device controller mode. 1 1 read-write CCS CCS Current Connect Status-Read Only. In Host Mode: 1=Device is present on port. 0=No device is present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: 1=Attached. 0=Not Attached. Default=0. A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or Suspended. 0 1 read-write OTGSC On-The-Go Status & control Register 0x1a4 32 0x00000000 0x07070723 ASVIE ASVIE A Session Valid Interrupt Enable - Read/Write. 26 1 read-write AVVIE AVVIE A VBus Valid Interrupt Enable - Read/Write. Setting this bit enables the A VBus valid interrupt. 25 1 read-write IDIE IDIE USB ID Interrupt Enable - Read/Write. Setting this bit enables the USB ID interrupt. 24 1 read-write ASVIS ASVIS A Session Valid Interrupt Status - Read/Write to Clear. This bit is set when VBus has either risen above or fallen below the A session valid threshold. Software must write a one to clear this bit. 18 1 read-write AVVIS AVVIS A VBus Valid Interrupt Status - Read/Write to Clear. This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. Software must write a one to clear this bit. 17 1 read-write IDIS IDIS USB ID Interrupt Status - Read/Write. This bit is set when a change on the ID input has been detected. Software must write a one to clear this bit. 16 1 read-write ASV ASV A Session Valid - Read Only. Indicates VBus is above the A session valid threshold. 10 1 read-only AVV AVV A VBus Valid - Read Only. Indicates VBus is above the A VBus valid threshold. 9 1 read-only ID ID USB ID - Read Only. 0 = A device, 1 = B device 8 1 read-only IDPU IDPU ID Pullup - Read/Write This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input will not be sampled. 5 1 read-write VC VC VBUS Charge - Read/Write. Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. 1 1 read-write VD VD VBUS_Discharge - Read/Write. Setting this bit causes VBus to discharge through a resistor. 0 1 read-write USBMODE USB Device Mode Register 0x1a8 32 0x00000000 0x0000001F SDIS SDIS Stream Disable Mode. (0 - Inactive [default]; 1 - Active) Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for the scheduler when using this feature. NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. 4 1 read-write SLOM SLOM Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . 0 - Setup Lockouts On (default); 1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. 3 1 read-write ES ES Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected by the value of this bit because they are based upon the 32-bit word. Bit Meaning 0 - Little Endian [Default] 1 - Big Endian 2 1 read-write CM CM Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only implementations. For those designs that contain both host & device capability, the controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ device controllers, this register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. For OTG controller core, reset value is '00b'. 00 - Idle [Default for combination host/device] 01 - Reserved 10 - Device Controller [Default for device only controller] 11 - Host Controller [Default for host only controller] 0 2 read-write ENDPTSETUPSTAT Endpoint Setup Status Register 0x1ac 32 0x00000000 0x0000FFFF ENDPTSETUPSTAT ENDPTSETUPSTAT Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. This register is only used in device mode. 0 16 read-write ENDPTPRIME Endpoint Prime Register 0x1b0 32 0x00000000 0xFFFFFFFF PETB PETB Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. PETB[N] - Endpoint #N, N is in 0..7 16 16 read-write PERB PERB Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. PERB[N] - Endpoint #N, N is in 0..7 0 16 read-write ENDPTFLUSH Endpoint Flush Register 0x1b4 32 0x00000000 0xFFFFFFFF FETB FETB Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. Hardware clears this register after the endpoint flush operation is successful. FETB[N] - Endpoint #N, N is in 0..7 16 16 read-write FERB FERB Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. Hardware clears this register after the endpoint flush operation is successful. FERB[N] - Endpoint #N, N is in 0..7 0 16 read-write ENDPTSTAT Endpoint Status Register 0x1b8 32 0x00000000 0xFFFFFFFF ETBR ETBR Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. ETBR[N] - Endpoint #N, N is in 0..7 16 16 read-only ERBR ERBR Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. ERBR[N] - Endpoint #N, N is in 0..7 0 16 read-only ENDPTCOMPLETE Endpoint Complete Register 0x1bc 32 0x00000000 0xFFFFFFFF ETCE ETCE Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. ETCE[N] - Endpoint #N, N is in 0..7 16 16 read-write ERCE ERCE Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. ERCE[N] - Endpoint #N, N is in 0..7 0 16 read-write 16 0x4 ENDPTCTRL0,ENDPTCTRL1,ENDPTCTRL2,ENDPTCTRL3,ENDPTCTRL4,ENDPTCTRL5,ENDPTCTRL6,ENDPTCTRL7,ENDPTCTRL8,ENDPTCTRL9,ENDPTCTRL10,ENDPTCTRL11,ENDPTCTRL12,ENDPTCTRL13,ENDPTCTRL14,ENDPTCTRL15 ENDPTCTRL[%s] no description available 0x1c0 32 0x00000000 0x00CD00CD TXE TXE TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured. 23 1 read-write TXR TXR TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device. 22 1 write-only TXT TXT TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt 18 2 read-write TXS TXS TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. 16 1 read-write RXE RXE RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured. 7 1 read-write RXR RXR RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device. 6 1 write-only RXT RXT RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt 2 2 read-write RXS RXS RX Endpoint Stall - Read/Write 0 End Point OK. [Default] 1 End Point Stalled This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. 0 1 read-write OTG_CTRL0 No description available 0x200 32 0x00000000 0x020B3F90 OTG_WKDPDMCHG_EN No description available 25 1 read-write AUTORESUME_EN No description available 19 1 read-write OTG_VBUS_WAKEUP_EN No description available 17 1 read-write OTG_ID_WAKEUP_EN No description available 16 1 read-write OTG_VBUS_SOURCE_SEL No description available 13 1 read-write OTG_UTMI_SUSPENDM_SW default 0 for naneng usbphy 12 1 read-write OTG_UTMI_RESET_SW default 1 for naneng usbphy 11 1 read-write OTG_WAKEUP_INT_ENABLE No description available 10 1 read-write OTG_POWER_MASK No description available 9 1 read-write OTG_OVER_CUR_POL No description available 8 1 read-write OTG_OVER_CUR_DIS No description available 7 1 read-write SER_MODE_SUSPEND_EN for naneng usbphy, only switch to serial mode when suspend 4 1 read-write PHY_CTRL0 No description available 0x210 32 0x00000000 0x02007007 GPIO_ID_SEL_N No description available 25 1 read-write ID_DIG_OVERRIDE No description available 14 1 read-write SESS_VALID_OVERRIDE No description available 13 1 read-write VBUS_VALID_OVERRIDE No description available 12 1 read-write ID_DIG_OVERRIDE_EN No description available 2 1 read-write SESS_VALID_OVERRIDE_EN No description available 1 1 read-write VBUS_VALID_OVERRIDE_EN No description available 0 1 read-write PHY_CTRL1 No description available 0x214 32 0x00000000 0x00100002 UTMI_CFG_RST_N No description available 20 1 read-write UTMI_OTG_SUSPENDM OTG suspend, not utmi_suspendm 1 1 read-write TOP_STATUS No description available 0x220 32 0x00000000 0x80000000 WAKEUP_INT_STATUS No description available 31 1 read-write PHY_STATUS No description available 0x224 32 0x00000000 0x800000F5 UTMI_CLK_VALID No description available 31 1 read-write LINE_STATE No description available 6 2 read-write HOST_DISCONNECT No description available 5 1 read-write ID_DIG No description available 4 1 read-write UTMI_SESS_VALID No description available 2 1 read-write VBUS_VALID No description available 0 1 read-write SDXC0 SDXC0 SDXC 0xf1130000 0x0 0x3008 registers SDMASA No description available 0x0 32 0x00000000 0xFFFFFFFF BLOCKCNT_SDMASA 32-bit Block Count (SDMA System Address) - SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. It can be accessed only if no transaction is executing. Reading this register during data transfers may return an invalid value. - 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. Following are the values for BLOCKCNT_SDMASA: - 0xFFFF_FFFF: 4G - 1 Block - - 0x0000_0002: 2 Blocks - 0x0000_0001: 1 Block - 0x0000_0000: Stop Count Note: - For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. The system address must be programmed in the ADMA System Address register. - For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. Auto CMD23 cannot be used with SDMA. - This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. 0 32 read-write BLK_ATTR No description available 0x4 32 0x00020210 0xFFFF7FFF BLOCK_CNT 16-bit Block Count - If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. - If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. Following are the values for BLOCK_CNT: - 0x0: Stop Count - 0x1: 1 Block - 0x2: 2 Blocks - . - 0xFFFF: 65535 Blocks Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. 16 16 read-write SDMA_BUF_BDARY SDMA Buffer Boundary These bits specify the size of contiguous buffer in system memory. The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. Values: - 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary - 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary - 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary - 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary - 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary - 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary - 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary - 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary 12 3 read-write XFER_BLOCK_SIZE Transfer Block Size These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: - 0x1: 1 byte - 0x2: 2 bytes - 0x3: 3 bytes - . - 0x1FF: 511 byte - 0x200: 512 byt es - . - 0x800: 2048 bytes Note: This register must be programmed with a non-zero value for data transfer. 0 12 read-write CMD_ARG No description available 0x8 32 0x00000000 0xFFFFFFFF ARGUMNET Command Argument These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. 0 32 read-write CMD_XFER No description available 0xc 32 0x00000000 0x3FFF01FF CMD_INDEX Command Index These bits are set to the command number that is specified in bits 45-40 of the Command Format. 24 6 read-write CMD_TYPE Command Type These bits indicate the command type. Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. Values: 0x3 (ABORT_CMD): Abort 0x2 (RESUME_CMD): Resume 0x1 (SUSPEND_CMD): Suspend 0x0 (NORMAL_CMD): Normal 22 2 read-write DATA_PRESENT_SEL Data Present Select This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: Command using the CMD line Command with no data transfer but using busy signal on the DAT[0] line Resume Command Values: 0x0 (NO_DATA): No Data Present 0x1 (DATA): Data Present 21 1 read-write CMD_IDX_CHK_ENABLE Command Index Check Enable This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. If the value is not the same, it is reported as a Command Index error. Note: Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. For the tuning command, this bit must always be set to enable the index check. Values: 0x0 (DISABLED): Disable 0x1 (ENABLED): Enable 20 1 read-write CMD_CRC_CHK_ENABLE Command CRC Check Enable This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. Note: CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. For the tuning command, this bit must always be set to 1 to enable the CRC check. Values: 0x0 (DISABLED): Disable 0x1 (ENABLED): Enable 19 1 read-write SUB_CMD_FLAG Sub Command Flag This bit distinguishes between a main command and a sub command. Values: 0x0 (MAIN): Main Command 0x1 (SUB): Sub Command 18 1 read-write RESP_TYPE_SELECT Response Type Select This bit indicates the type of response expected from the card. Values: 0x0 (NO_RESP): No Response 0x1 (RESP_LEN_136): Response Length 136 0x2 (RESP_LEN_48): Response Length 48 0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response 16 2 read-write RESP_INT_DISABLE Response Interrupt Disable The Host Controller supports response check function to avoid overhead of response error check by the Host driver. Response types of only R1 and R5 can be checked by the Controller. If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. Values: - 0x0 (ENABLED): Response Interrupt is enabled - 0x1 (DISABLED): Response Interrupt is disabled 8 1 read-write RESP_ERR_CHK_ENABLE Response Error Check Enable The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. Note: - Response error check must not be enabled for any response type other than R1 and R5. - Response check must not be enabled for the tuning command. Values: - 0x0 (DISABLED): Response Error Check is disabled - 0x1 (ENABLED): Response Error Check is enabled 7 1 read-write RESP_TYPE Response Type R1/R5 This bit selects either R1 or R5 as a response type when the Response Error Check is selected. Error statuses checked in R1: OUT_OF_RANGE ADDRESS_ERROR BLOCK_LEN_ERROR WP_VIOLATION CARD_IS_LOCKED COM_CRC_ERROR CARD_ECC_FAILED CC_ERROR ERROR Response Flags checked in R5: COM_CRC_ERROR ERROR FUNCTION_NUMBER OUT_OF_RANGE Values: 0x0 (RESP_R1): R1 (Memory) 0x1 (RESP_R5): R5 (SDIO) 6 1 read-write MULTI_BLK_SEL Multi/Single Block Select This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. Values: 0x0 (SINGLE): Single Block 0x1 (MULTI): Multiple Block 5 1 read-write DATA_XFER_DIR Data Transfer Direction Select This bit defines the direction of DAT line data transfers. This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. Values: 0x1 (READ): Read (Card to Host) 0x0 (WRITE): Write (Host to Card) 4 1 read-write AUTO_CMD_ENABLE Auto Command Enable This field determines use of Auto Command functions. Note: In SDIO, this field must be set as 00b (Auto Command Disabled). Values: 0x0 (AUTO_CMD_DISABLED): Auto Command Disabled 0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable 0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable 0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel 2 2 read-write BLOCK_COUNT_ENABLE Block Count Enable This bit is used to enable the Block Count register, which is relevant for multiple block transfers. If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. The Host Driver must set this bit to 0 when ADMA is used. Values: 0x1 (ENABLED): Enable 0x0 (DISABLED): Disable 1 1 read-write DMA_ENABLE DMA Enable This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. You can select one of the DMA modes by using DMA Select in the Host Control 1 register. Values: 0x1 (ENABLED): DMA Data transfer 0x0 (DISABLED): No data transfer or Non-DMA data transfer 0 1 read-write 4 0x4 RESP01,RESP23,RESP45,RESP67 RESP[%s] no description available 0x10 32 0x00000000 0xFFFFFFFF RESP01 Command Response These bits reflect 39-8 bits of SD/eMMC Response Field. Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP[RESP67] register. 0 32 read-only BUF_DATA No description available 0x20 32 0x00000000 0xFFFFFFFF BUF_DATA Buffer Data These bits enable access to the Host Controller packet buffer. 0 32 read-write PSTATE No description available 0x24 32 0x00000000 0x19FF0FFF SUB_CMD_STAT Sub Command Status This bit is used to distinguish between a main command and a sub command status. Values: 0x0 (FALSE): Main Command Status 0x1 (TRUE): Sub Command Status 28 1 read-only CMD_ISSUE_ERR Command Not Issued by Error This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. Values: 0x0 (FALSE): No error for issuing a command 0x1 (TRUE): Command cannot be issued 27 1 read-only CMD_LINE_LVL Command-Line Signal Level This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. 24 1 read-only DAT_3_0 DAT[3:0] Line Signal Level This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. 20 4 read-only WR_PROTECT_SW_LVL Write Protect Switch Pin Level This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. Values: 0x0 (FALSE): Write protected 0x1 (TRUE): Write enabled 19 1 read-only CARD_DETECT_PIN_LEVEL Card Detect Pin Level This bit reflects the inverse synchronized value of the card_detect_n signal. Values: 0x0 (FALSE): No card present 0x1 (TRUE): Card Present 18 1 read-only CARD_STABLE Card Stable This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. Values: 0x0 (FALSE): Reset or Debouncing 0x1 (TRUE): No Card or Inserted 17 1 read-only CARD_INSERTED Card Inserted This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. Values: 0x0 (FALSE): Reset, Debouncing, or No card 0x1 (TRUE): Card Inserted 16 1 read-only BUF_RD_ENABLE Buffer Read Enable This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. Values: 0x0 (DISABLED): Read disable 0x1 (ENABLED): Read enable 11 1 read-only BUF_WR_ENABLE Buffer Write Enable This bit is used for non-DMA transfers. This bit is set if space is available for writing data. Values: 0x0 (DISABLED): Write disable 0x1 (ENABLED): Write enable 10 1 read-only RD_XFER_ACTIVE Read Transfer Active This bit indicates whether a read transfer is active for SD/eMMC mode. Values: 0x0 (INACTIVE): No valid data 0x1 (ACTIVE): Transferring data 9 1 read-only WR_XFER_ACTIVE Write Transfer Active This status indicates whether a write transfer is active for SD/eMMC mode. Values: 0x0 (INACTIVE): No valid data 0x1 (ACTIVE): Transferring data 8 1 read-only DAT_7_4 DAT[7:4] Line Signal Level This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. 4 4 read-only RE_TUNE_REQ Re-Tuning Request SDXC does not generate retuning request. The software must maintain the Retuning timer. 3 1 read-only DAT_LINE_ACTIVE DAT Line Active ( This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. Values: 0x0 (INACTIVE): DAT Line Inactive 0x1 (ACTIVE): DAT Line Active 2 1 read-only DAT_INHIBIT Command Inhibit (DAT) This bit is generated if either DAT line active or Read transfer active is set to 1. If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. Values: 0x0 (READY): Can issue command which used DAT line 0x1 (NOT_READY): Cannot issue command which used DAT line 1 1 read-only CMD_INHIBIT Command Inhibit (CMD) This bit indicates the following : If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. This bit is set when the command register is written. This bit is cleared when the command response is received. This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. Values: 0x0 (READY): Host Controller is ready to issue a command 0x1 (NOT_READY): Host Controller is not ready to issue a command 0 1 read-only PROT_CTRL No description available 0x28 32 0x00000000 0x070F0F3E CARD_REMOVAL Wakeup Event Enable on SD Card Removal This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. Values: 0x0 (DISABLED): Disable 0x1 (ENABLED): Enable 26 1 read-write CARD_INSERT Wakeup Event Enable on SD Card Insertion This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. FN_WUS (Wake Up Support) in CIS does not affect this bit. Values: 0x0 (DISABLED): Disable 0x1 (ENABLED): Enable 25 1 read-write CARD_INT Wakeup Event Enable on Card Interrupt This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. Values: 0x0 (DISABLED): Disable 0x1 (ENABLED): Enable 24 1 read-write INT_AT_BGAP Interrupt At Block Gap This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. Values: 0x0 (DISABLE): Disabled 0x1 (ENABLE): Enabled 19 1 read-write RD_WAIT_CTRL Read Wait Control This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. Values: 0x0 (DISABLE): Disable Read Wait Control 0x1 (ENABLE): Enable Read Wait Control 18 1 read-write CONTINUE_REQ Continue Request This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. The Host Controller automatically clears this bit when the transaction restarts. If stop at block gap request is set to 1, any write to this bit is ignored. Values: 0x0 (NO_AFFECT): No Affect 0x1 (RESTART): Restart 17 1 read-write STOP_BG_REQ Stop At Block Gap Request This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. Values: 0x0 (XFER): Transfer 0x1 (STOP): Stop 16 1 read-write SD_BUS_VOL_VDD1 SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD These bits enable the Host Driver to select the voltage level for an SD/eMMC card. Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. SD Bus Voltage Select options: 0x7 : 3.3V(Typical) 0x6 : 3.0V(Typical) 0x5 : 1.8V(Typical) for Embedded 0x4 : 0x0 - Reserved eMMC Bus Voltage Select options: 0x7 : 3.3V(Typical) 0x6 : 1.8V(Typical) 0x5 : 1.2V(Typical) 0x4 : 0x0 - Reserved Values: 0x7 (V_3_3): 3.3V (Typ.) 0x6 (V_3_0): 3.0V (Typ.) 0x5 (V_1_8): 1.8V (Typ.) for Embedded 0x4 (RSVD4): Reserved 0x3 (RSVD3): Reserved 0x2 (RSVD2): Reserved 0x1 (RSVD1): Reserved 0x0 (RSVD0): Reserved 9 3 read-write SD_BUS_PWR_VDD1 SD Bus Power for VDD1 This bit enables VDD1 power of the card. This setting is available on the sd_vdd1_on output of SDXC so that it can be used to control the VDD1 power supply of the card. Before setting this bit, the SD Host Driver sets the SD Bus Voltage Select bit. If the Host Controller detects a No Card state, this bit is cleared. In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_EN bit in the SYS_CTRL register. Values: 0x0 (OFF): Power off 0x1 (ON): Power on 8 1 read-write EXT_DAT_XFER Extended Data Transfer Width This bit controls 8-bit bus width mode of embedded device. Values: 0x1 (EIGHT_BIT): 8-bit Bus Width 0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width 5 1 read-write DMA_SEL DMA Select This field is used to select the DMA type. When Host Version 4 Enable is 1 in Host Control 2 register: 0x0 : SDMA is selected 0x1 : Reserved 0x2 : ADMA2 is selected 0x3 : ADMA2 or ADMA3 is selected When Host Version 4 Enable is 0 in Host Control 2 register: 0x0 : SDMA is selected 0x1 : Reserved 0x2 : 32-bit Address ADMA2 is selected 0x3 : 64-bit Address ADMA2 is selected Values: 0x0 (SDMA): SDMA is selected 0x1 (RSVD_BIT): Reserved 0x2 (ADMA2): ADMA2 is selected 0x3 (ADMA2_3): ADMA2 or ADMA3 is selected 3 2 read-write HIGH_SPEED_EN High Speed Enable this bit is used to determine the selection of preset value for High Speed mode. Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. Values: 0x1 (HIGH_SPEED): High Speed mode 0x0 (NORMAL_SPEED): Normal Speed mode 2 1 read-write DAT_XFER_WIDTH Data Transfer Width For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. Values: 0x1 (FOUR_BIT): 4-bit mode 0x0 (ONE_BIT): 1-bit mode 1 1 read-write SYS_CTRL No description available 0x2c 32 0x00000000 0x070FFFEF SW_RST_DAT Software Reset For DAT line This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. The following registers and bits are cleared by this bit: Buffer Data Port register -Buffer is cleared and initialized. Present state register -Buffer Read Enable -Buffer Write Enable -Read Transfer Active -Write Transfer Active -DAT Line Active -Command Inhibit (DAT) Block Gap Control register -Continue Request -Stop At Block Gap Request Normal Interrupt status register -Buffer Read Ready -Buffer Write Ready -DMA Interrupt -Block Gap Event -Transfer Complete In UHS-II mode, this bit shall be set to 0 Values: 0x0 (FALSE): Work 0x1 (TRUE): Reset 26 1 read-write SW_RST_CMD Software Reset For CMD line This bit resets only a part of the command circuit to be able to issue a command. It bit is also used to initialize a UHS-II command circuit. This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. The following registers and bits are cleared by this bit: Present State register : Command Inhibit (CMD) bit Normal Interrupt Status register : Command Complete bit Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit Values: 0x0 (FALSE): Work 0x1 (TRUE): Reset 25 1 read-write SW_RST_ALL Software Reset For All This reset affects the entire Host Controller except for the card detection circuit. During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. All registers are reset except the capabilities register. If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. Values: 0x0 (FALSE): Work 0x1 (TRUE): Reset 24 1 read-write TOUT_CNT Data Timeout Counter Value. This value determines the interval by which DAT line timeouts are detected. The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). The values for these bits are: 0xF : Reserved 0xE : TMCLK x 2^27 ......... 0x1 : TMCLK x 2^14 0x0 : TMCLK x 2^13 Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. 16 4 read-write FREQ_SEL SDCLK/RCLK Frequency Select These bits are used to select the frequency of the SDCLK signal. These bits depend on setting of Preset Value Enable in the Host Control 2 register. If Preset Value Enable = 0, these bits are set by the Host Driver. If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. 10-bit Divided Clock Mode: 0x3FF : 1/2046 Divided clock .......... N : 1/2N Divided Clock .......... 0x002 : 1/4 Divided Clock 0x001 : 1/2 Divided Clock 0x000 : Base clock (10MHz - 255 MHz) Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: 0x3FF : Base clock * M /1024 .......... N-1 : Base clock * M /N .......... 0x002 : Base clock * M /3 0x001 : Base clock * M /2 0x000 : Base clock * M 8 8 read-write UPPER_FREQ_SEL These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. 6 2 read-write CLK_GEN_SELECT Clock Generator Select This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. If Preset Value Enable = 0, this bit is set by the Host Driver. If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. The value is reflected on the card_clk_gen_sel signal. Values: 0x0 (FALSE): Divided Clock Mode 0x1 (TRUE): Programmable Clock Mode 5 1 read-write PLL_ENABLE PLL Enable This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . Values: 0x0 (FALSE): PLL is in low power mode 0x1 (TRUE): PLL is enabled 3 1 read-write SD_CLK_EN SD/eMMC Clock Enable This bit stops the SDCLK or RCLK when set to 0. The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. The value is reflected on the clk2card_on pin. Values: 0x0 (FALSE): Disable providing SDCLK/RCLK 0x1 (TRUE): Enable providing SDCLK/RCLK 2 1 read-write INTERNAL_CLK_STABLE Internal Clock Stable This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. Values: 0x0 (FALSE): Not Ready 0x1 (TRUE): Ready 1 1 read-write INTERNAL_CLK_EN Internal Clock Enable This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. The Host Controller must stop its internal clock to enter a very low power state. However, registers can still be read and written to. The value is reflected on the intclk_en signal. Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . Values: 0x0 (FALSE): Stop 0x1 (TRUE): Oscillate 0 1 read-write INT_STAT No description available 0x30 32 0x00000000 0x1FFFF1FF BOOT_ACK_ERR Boot Acknowledgment Error This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. In SD/UHS-II mode, this bit is irrelevant. 28 1 read-write RESP_ERR Response Error Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. Values: 0x0 (FALSE): No error 0x1 (TRUE): Error 27 1 read-write TUNING_ERR Tuning Error This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure (occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. The Tuning Error is higher priority than the other error interrupts generated during data transfer. By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. This is applicable in SD/eMMC mode. Values: 0x0 (FALSE): No error 0x1 (TRUE): Error 26 1 read-write ADMA_ERR ADMA Error This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: Error response received from System bus (Master I/F) ADMA3,ADMA2 Descriptors invalid CQE Task or Transfer descriptors invalid When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. In eMMC CQE mode: The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. The Host Driver may find that Valid bit is not set at the error descriptor. Values: 0x0 (FALSE): No error 0x1 (TRUE): Error 25 1 read-write AUTO_CMD_ERR Auto CMD Error This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. Values: 0x0 (FALSE): No error 0x1 (TRUE): Error 24 1 read-write CUR_LMT_ERR Current Limit Error By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. The Host Controller may require some sampling time to detect the current limit. SDXC Host Controller does not support this function, this bit is always set to 0. Values: 0x0 (FALSE): No error 0x1 (TRUE): Power Fail 23 1 read-write DATA_END_BIT_ERR Data End Bit Error This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. Values: 0x0 (FALSE): No error 0x1 (TRUE): Error 22 1 read-write DATA_CRC_ERR Data CRC Error This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. Values: 0x0 (FALSE): No error 0x1 (TRUE): Error 21 1 read-write DATA_TOUT_ERR Data Timeout Error This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: Busy timeout for R1b, R5b type Busy timeout after Write CRC status Write CRC Status timeout Read Data timeout Values: 0x0 (FALSE): No error 0x1 (TRUE): Time out 20 1 read-write CMD_IDX_ERR Command Index Error This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. Values: 0x0 (FALSE): No error 0x1 (TRUE): Error 19 1 read-write CMD_END_BIT_ERR Command End Bit Error This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. Values: 0x0 (FALSE): No error 0x1 (TRUE): End Bit error generated 18 1 read-write CMD_CRC_ERR Command CRC Error Command CRC Error is generated in SD/eMMC mode for following two cases. If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. If the Host Controller drives the CMD line to 1 level, but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. Values: 0x0 (FALSE): No error 0x1 (TRUE): CRC error generated 17 1 read-write CMD_TOUT_ERR Command Timeout Error In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. Values: 0x0 (FALSE): No error 0x1 (TRUE): Time out 16 1 read-write ERR_INTERRUPT Error Interrupt If any of the bits in the Error Interrupt Status register are set, then this bit is set. Values: 0x0 (FALSE): No Error 0x1 (TRUE): Error 15 1 read-only CQE_EVENT Command Queuing Event This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. Values: 0x0 (FALSE): No Event 0x1 (TRUE): Command Queuing Event is detected 14 1 read-write FX_EVENT FX Event This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. Values: 0x0 (FALSE): No Event 0x1 (TRUE): FX Event is detected 13 1 read-only RE_TUNE_EVENT Re-tuning Event This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. 12 1 read-only CARD_INTERRUPT Card Interrupt This bit reflects the synchronized value of: DAT[1] Interrupt Input for SD Mode DAT[2] Interrupt Input for UHS-II Mode Values: 0x0 (FALSE): No Card Interrupt 0x1 (TRUE): Generate Card Interrupt 8 1 read-only CARD_REMOVAL Card Removal This bit is set if the Card Inserted in the Present State register changes from 1 to 0. Values: 0x0 (FALSE): Card state stable or Debouncing 0x1 (TRUE): Card Removed 7 1 read-write CARD_INSERTION Card Insertion This bit is set if the Card Inserted in the Present State register changes from 0 to 1. Values: 0x0 (FALSE): Card state stable or Debouncing 0x1 (TRUE): Card Inserted 6 1 read-write BUF_RD_READY Buffer Read Ready This bit is set if the Buffer Read Enable changes from 0 to 1. Values: 0x0 (FALSE): Not ready to read buffer 0x1 (TRUE): Ready to read buffer 5 1 read-write BUF_WR_READY Buffer Write Ready This bit is set if the Buffer Write Enable changes from 0 to 1. Values: 0x0 (FALSE): Not ready to write buffer 0x1 (TRUE): Ready to write buffer 4 1 read-write DMA_INTERRUPT DMA Interrupt This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. This interrupt is not generated after a Transfer Complete. Values: 0x0 (FALSE): No DMA Interrupt 0x1 (TRUE): DMA Interrupt is generated 3 1 read-write BGAP_EVENT Block Gap Event This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. Values: 0x0 (FALSE): No Block Gap Event 0x1 (TRUE): Transaction stopped at block gap 2 1 read-write XFER_COMPLETE Transfer Complete This bit is set when a read/write transfer and a command with status busy is completed. Values: 0x0 (FALSE): Not complete 0x1 (TRUE): Command execution is completed 1 1 read-write CMD_COMPLETE Command Complete In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. Values: 0x0 (FALSE): No command complete 0x1 (TRUE): Command Complete 0 1 read-write INT_STAT_EN No description available 0x34 32 0x00000000 0x1FFF71FF BOOT_ACK_ERR_STAT_EN Boot Acknowledgment Error (eMMC Mode only) Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (INT_STAT). Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 28 1 read-write RESP_ERR_STAT_EN Response Error Status Enable (SD Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 27 1 read-write TUNING_ERR_STAT_EN Tuning Error Status Enable (UHS-I Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 26 1 read-write ADMA_ERR_STAT_EN ADMA Error Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 25 1 read-write AUTO_CMD_ERR_STAT_EN Auto CMD Error Status Enable (SD/eMMC Mode only). Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 24 1 read-write CUR_LMT_ERR_STAT_EN Current Limit Error Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 23 1 read-write DATA_END_BIT_ERR_STAT_EN Data End Bit Error Status Enable (SD/eMMC Mode only). Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 22 1 read-write DATA_CRC_ERR_STAT_EN Data CRC Error Status Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 21 1 read-write DATA_TOUT_ERR_STAT_EN Data Timeout Error Status Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 20 1 read-write CMD_IDX_ERR_STAT_EN Command Index Error Status Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 19 1 read-write CMD_END_BIT_ERR_STAT_EN Command End Bit Error Status Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 18 1 read-write CMD_CRC_ERR_STAT_EN Command CRC Error Status Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 17 1 read-write CMD_TOUT_ERR_STAT_EN Command Timeout Error Status Enable (SD/eMMC Mode only). Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 16 1 read-write CQE_EVENT_STAT_EN CQE Event Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 14 1 read-write FX_EVENT_STAT_EN FX Event Status Enable This bit is added from Version 4.10. Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 13 1 read-write RE_TUNE_EVENT_STAT_EN Re-Tuning Event (UHS-I only) Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 12 1 read-write CARD_INTERRUPT_STAT_EN Card Interrupt Status Enable If this bit is set to 0, the Host Controller clears the interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 8 1 read-write CARD_REMOVAL_STAT_EN Card Removal Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 7 1 read-write CARD_INSERTION_STAT_EN Card Insertion Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 6 1 read-write BUF_RD_READY_STAT_EN Buffer Read Ready Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 5 1 read-write BUF_WR_READY_STAT_EN Buffer Write Ready Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 4 1 read-write DMA_INTERRUPT_STAT_EN DMA Interrupt Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 3 1 read-write BGAP_EVENT_STAT_EN Block Gap Event Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 2 1 read-write XFER_COMPLETE_STAT_EN Transfer Complete Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 1 1 read-write CMD_COMPLETE_STAT_EN Command Complete Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 0 1 read-write INT_SIGNAL_EN No description available 0x38 32 0x00000000 0x1FFF71FF BOOT_ACK_ERR_SIGNAL_EN Boot Acknowledgment Error (eMMC Mode only). Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgment Error in Error Interrupt Status register is set. Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 28 1 read-write RESP_ERR_SIGNAL_EN Response Error Signal Enable (SD Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 27 1 read-write TUNING_ERR_SIGNAL_EN Tuning Error Signal Enable (UHS-I Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 26 1 read-write ADMA_ERR_SIGNAL_EN ADMA Error Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 25 1 read-write AUTO_CMD_ERR_SIGNAL_EN Auto CMD Error Signal Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 24 1 read-write CUR_LMT_ERR_SIGNAL_EN Current Limit Error Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 23 1 read-write DATA_END_BIT_ERR_SIGNAL_EN Data End Bit Error Signal Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 22 1 read-write DATA_CRC_ERR_SIGNAL_EN Data CRC Error Signal Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 21 1 read-write DATA_TOUT_ERR_SIGNAL_EN Data Timeout Error Signal Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 20 1 read-write CMD_IDX_ERR_SIGNAL_EN Command Index Error Signal Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): No error 0x1 (TRUE): Error 19 1 read-write CMD_END_BIT_ERR_SIGNAL_EN Command End Bit Error Signal Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 18 1 read-write CMD_CRC_ERR_SIGNAL_EN Command CRC Error Signal Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 17 1 read-write CMD_TOUT_ERR_SIGNAL_EN Command Timeout Error Signal Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 16 1 read-write CQE_EVENT_SIGNAL_EN Command Queuing Engine Event Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 14 1 read-write FX_EVENT_SIGNAL_EN FX Event Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 13 1 read-write RE_TUNE_EVENT_SIGNAL_EN Re-Tuning Event (UHS-I only) Signal Enable. Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 12 1 read-write CARD_INTERRUPT_SIGNAL_EN Card Interrupt Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 8 1 read-write CARD_REMOVAL_SIGNAL_EN Card Removal Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 7 1 read-write CARD_INSERTION_SIGNAL_EN Card Insertion Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 6 1 read-write BUF_RD_READY_SIGNAL_EN Buffer Read Ready Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 5 1 read-write BUF_WR_READY_SIGNAL_EN Buffer Write Ready Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 4 1 read-write DMA_INTERRUPT_SIGNAL_EN DMA Interrupt Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 3 1 read-write BGAP_EVENT_SIGNAL_EN Block Gap Event Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 2 1 read-write XFER_COMPLETE_SIGNAL_EN Transfer Complete Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 1 1 read-write CMD_COMPLETE_SIGNAL_EN Command Complete Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled 0 1 read-write AC_HOST_CTRL No description available 0x3c 32 0x00000000 0xDCCF00BF PRESET_VAL_ENABLE Preset Value Enable This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. These values are selected from set of Preset Value registers based on selected speed mode. Values: 0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver 0x1 (TRUE): Automatic Selection by Preset Value are Enabled 31 1 read-write ASYNC_INT_ENABLE Asynchronous Interrupt Enable This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. Values: 0x0 (FALSE): Disabled 0x1 (TRUE): Enabled 30 1 read-write HOST_VER4_ENABLE Host Version 4 Enable This bit selects either Version 3.00 compatible mode or Version 4 mode. Functions of following fields are modified for Host Version 4 mode: SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register 64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register 32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). Values: 0x0 (FALSE): Version 3.00 compatible mode 0x1 (TRUE): Version 4 mode 28 1 read-write CMD23_ENABLE CMD23 Enable If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. Values: 0x0 (FALSE): Auto CMD23 is disabled 0x1 (TRUE): Auto CMD23 is enabled 27 1 read-write ADMA2_LEN_MODE ADMA2 Length Mode This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. Values: 0x0 (FALSE): 16-bit Data Length Mode 0x1 (TRUE): 26-bit Data Length Mode 26 1 read-write SAMPLE_CLK_SEL Sampling Clock Select This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. The value is reflected on the sample_cclk_sel pin. Values: 0x0 (FALSE): Fixed clock is used to sample data 0x1 (TRUE): Tuned clock is used to sample data 23 1 read-write EXEC_TUNING Execute Tuning This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. Values: 0x0 (FALSE): Not Tuned or Tuning completed 0x1 (TRUE): Execute Tuning 22 1 read-write SIGNALING_EN 1.8V Signaling Enable This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). Values: 0x0 (V_3_3): 3.3V Signalling 0x1 (V_1_8): 1.8V Signalling 19 1 read-write UHS_MODE_SEL UHS Mode/eMMC Speed Mode Select These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. UHS Mode (SD/UHS-II mode only): 0x0 (SDR12): SDR12/Legacy 0x1 (SDR25): SDR25/High Speed SDR 0x2 (SDR50): SDR50 0x3 (SDR104): SDR104/HS200 0x4 (DDR50): DDR50/High Speed DDR 0x5 (RSVD5): Reserved 0x6 (RSVD6): Reserved 0x7 (UHS2): UHS-II/HS400 eMMC Speed Mode (eMMC mode only): 0x0: Legacy 0x1: High Speed SDR 0x2: Reserved 0x3: HS200 0x4: High Speed DDR 0x5: Reserved 0x6: Reserved 0x7: HS400 16 3 read-write CMD_NOT_ISSUED_AUTO_CMD12 Command Not Issued By Auto CMD12 Error If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. Values: 0x1 (TRUE): Not Issued 0x0 (FALSE): No Error 7 1 read-only AUTO_CMD_RESP_ERR Auto CMD Response Error This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. This status is ignored if any bit between D00 to D04 is set to 1. Values: 0x1 (TRUE): Error 0x0 (FALSE): No Error 5 1 read-only AUTO_CMD_IDX_ERR Auto CMD Index Error This bit is set if the command index error occurs in response to a command. Values: 0x1 (TRUE): Error 0x0 (FALSE): No Error 4 1 read-only AUTO_CMD_EBIT_ERR Auto CMD End Bit Error This bit is set when detecting that the end bit of command response is 0. Values: 0x1 (TRUE): End Bit Error Generated 0x0 (FALSE): No Error 3 1 read-only AUTO_CMD_CRC_ERR Auto CMD CRC Error This bit is set when detecting a CRC error in the command response. Values: 0x1 (TRUE): CRC Error Generated 0x0 (FALSE): No Error 2 1 read-only AUTO_CMD_TOUT_ERR Auto CMD Timeout Error This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. If this bit is set to 1, error status bits (D04-D01) are meaningless. Values: 0x1 (TRUE): Time out 0x0 (FALSE): No Error 1 1 read-only AUTO_CMD12_NOT_EXEC Auto CMD12 Not Executed If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. If this bit is set to 1, error status bits (D04-D01) is meaningless. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. Values: 0x1 (TRUE): Not Executed 0x0 (FALSE): Executed 0 1 read-only CAPABILITIES1 No description available 0x40 32 0x00000000 0xE7EFFFBF SLOT_TYPE_R Slot Type These bits indicate usage of a slot by a specific Host System. Values: 0x0 (REMOVABLE_SLOT): Removable Card Slot 0x1 (EMBEDDED_SLOT): Embedded Slot for one Device 0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) 0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices 30 2 read-only ASYNC_INT_SUPPORT Asynchronous Interrupt Support (SD Mode only) Values: 0x0 (FALSE): Asynchronous Interrupt Not Supported 0x1 (TRUE): Asynchronous Interrupt Supported 29 1 read-only VOLT_18 Voltage Support for 1.8V Values: 0x0 (FALSE): 1.8V Not Supported 0x1 (TRUE): 1.8V Supported 26 1 read-only VOLT_30 Voltage Support for SD 3.0V or Embedded 1.2V Values: 0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported 0x1 (TRUE): SD 3.0V or Embedded Supported 25 1 read-only VOLT_33 Voltage Support for 3.3V Values: 0x0 (FALSE): 3.3V Not Supported 0x1 (TRUE): 3.3V Supported 24 1 read-only SUS_RES_SUPPORT Suspense/Resume Support This bit indicates whether the Host Controller supports Suspend/Resume functionality. If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. Values: 0x0 (FALSE): Not Supported 0x1 (TRUE): Supported 23 1 read-only SDMA_SUPPORT SDMA Support This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. Values: 0x0 (FALSE): SDMA not Supported 0x1 (TRUE): SDMA Supported 22 1 read-only HIGH_SPEED_SUPPORT High Speed Support This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. Values: 0x0 (FALSE): High Speed not Supported 0x1 (TRUE): High Speed Supported 21 1 read-only ADMA2_SUPPORT ADMA2 Support This bit indicates whether the Host Controller is capable of using ADMA2. Values: 0x0 (FALSE): ADMA2 not Supported 0x1 (TRUE): ADMA2 Supported 19 1 read-only EMBEDDED_8_BIT 8-bit Support for Embedded Device This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. Values: 0x0 (FALSE): 8-bit Bus Width not Supported 0x1 (TRUE): 8-bit Bus Width Supported 18 1 read-only MAX_BLK_LEN Maximum Block Length This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit Values: 0x0 (ZERO): 512 Byte 0x1 (ONE): 1024 Byte 0x2 (TWO): 2048 Byte 0x3 (THREE): Reserved 16 2 read-only BASE_CLK_FREQ Base Clock Frequency for SD clock These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. 6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. -0x00 : Get information through another method -0x01 : 1 MHz -0x02 : 2 MHz -............. -0x3F : 63 MHz -0x40-0xFF : Not Supported 8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. -0x00 : Get information through another method -0x01 : 1 MHz -0x02 : 2 MHz -............ -0xFF : 255 MHz If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. If these bits are all 0, the Host system has to get information using a different method. 8 8 read-only TOUT_CLK_UNIT Timeout Clock Unit This bit shows the unit of base clock frequency used to detect Data TImeout Error. Values: 0x0 (KHZ): KHz 0x1 (MHZ): MHz 7 1 read-only TOUT_CLK_FREQ Timeout Clock Frequency This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. 0x00 : Get information through another method 0x01 : 1KHz / 1MHz 0x02 : 2KHz / 2MHz 0x03 : 3KHz / 3MHz ........... 0x3F : 63KHz / 63MHz 0 6 read-only CAPABILITIES2 No description available 0x44 32 0x00000000 0x18FFEF7F VDD2_18V_SUPPORT 1.8V VDD2 Support This bit indicates support of VDD2 for the Host System. 0x0 (FALSE): 1.8V VDD2 is not Supported 0x1 (TRUE): 1.8V VDD2 is Supported 28 1 read-only ADMA3_SUPPORT ADMA3 Support This bit indicates whether the Host Controller is capable of using ADMA3. Values: 0x0 (FALSE): ADMA3 not Supported 0x1 (TRUE): ADMA3 Supported 27 1 read-only CLK_MUL Clock Multiplier These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. 0x0: Clock Multiplier is not Supported 0x1: Clock Multiplier M = 2 0x2: Clock Multiplier M = 3 ......... 0xFF: Clock Multiplier M = 256 16 8 read-only RE_TUNING_MODES Re-Tuning Modes (UHS-I only) These bits select the re-tuning method and limit the maximum data length. Values: 0x0 (MODE1): Timer 0x1 (MODE2): Timer and Re-Tuning Request (Not supported) 0x2 (MODE3): Auto Re-Tuning (for transfer) 0x3 (RSVD_MODE): Reserved 14 2 read-only USE_TUNING_SDR50 Use Tuning for SDR50 (UHS-I only) Values: 0x0 (ZERO): SDR50 does not require tuning 0x1 (ONE): SDR50 requires tuning 13 1 read-only RETUNE_CNT Timer Count for Re-Tuning (UHS-I only) 0x0: Re-Tuning Timer disabled 0x1: 1 seconds 0x2: 2 seconds 0x3: 4 seconds ........ 0xB: 1024 seconds 0xC: Reserved 0xD: Reserved 0xE: Reserved 0xF: Get information from other source 8 4 read-only DRV_TYPED Driver Type D Support (UHS-I only) This bit indicates support of Driver Type D for 1.8 Signaling. Values: 0x0 (FALSE): Driver Type D is not supported 0x1 (TRUE): Driver Type D is supported 6 1 read-only DRV_TYPEC Driver Type C Support (UHS-I only) This bit indicates support of Driver Type C for 1.8 Signaling. Values: 0x0 (FALSE): Driver Type C is not supported 0x1 (TRUE): Driver Type C is supported 5 1 read-only DRV_TYPEA Driver Type A Support (UHS-I only) This bit indicates support of Driver Type A for 1.8 Signaling. Values: 0x0 (FALSE): Driver Type A is not supported 0x1 (TRUE): Driver Type A is supported 4 1 read-only UHS2_SUPPORT UHS-II Support (UHS-II only) This bit indicates whether Host Controller supports UHS-II. Values: 0x0 (FALSE): UHS-II is not supported 0x1 (TRUE): UHS-II is supported 3 1 read-only DDR50_SUPPORT DDR50 Support (UHS-I only) Values: 0x0 (FALSE): DDR50 is not supported 0x1 (TRUE): DDR50 is supported 2 1 read-only SDR104_SUPPORT SDR104 Support (UHS-I only) This bit mentions that SDR104 requires tuning. Values: 0x0 (FALSE): SDR104 is not supported 0x1 (TRUE): SDR104 is supported 1 1 read-only SDR50_SUPPORT SDR50 Support (UHS-I only) This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. Values: 0x0 (FALSE): SDR50 is not supported 0x1 (TRUE): SDR50 is supported 0 1 read-only CURR_CAPABILITIES1 No description available 0x48 32 0x00000000 0x00FFFFFF MAX_CUR_18V Maximum Current for 1.8V This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. 0: Get information through another method 1: 4mA 2: 8mA 3: 13mA ....... 255: 1020mA 16 8 read-only MAX_CUR_30V Maximum Current for 3.0V This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. 0: Get information through another method 1: 4mA 2: 8mA 3: 13mA ....... 255: 1020mA 8 8 read-only MAX_CUR_33V Maximum Current for 3.3V This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. 0: Get information through another method 1: 4mA 2: 8mA 3: 13mA ....... 255: 1020mA 0 8 read-only CURR_CAPABILITIES2 No description available 0x4c 32 0x00000000 0x000000FF MAX_CUR_VDD2_18V Maximum Current for 1.8V VDD2 This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. 0: Get information through another method 1: 4mA 2: 8mA 3: 13mA ....... 255: 1020mA 0 8 read-only FORCE_EVENT No description available 0x50 32 0x00000000 0x1FFF00BF FORCE_BOOT_ACK_ERR Force Event for Boot Ack error Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Boot ack Error Status is set 28 1 write-only FORCE_RESP_ERR Force Event for Response Error (SD Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Response Error Status is set 27 1 write-only FORCE_TUNING_ERR Force Event for Tuning Error (UHS-I Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Tuning Error Status is set 26 1 write-only FORCE_ADMA_ERR Force Event for ADMA Error Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): ADMA Error Status is set 25 1 write-only FORCE_AUTO_CMD_ERR Force Event for Auto CMD Error (SD/eMMC Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Auto CMD Error Status is set 24 1 write-only FORCE_CUR_LMT_ERR Force Event for Current Limit Error Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Current Limit Error Status is set 23 1 write-only FORCE_DATA_END_BIT_ERR Force Event for Data End Bit Error (SD/eMMC Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Data End Bit Error Status is set 22 1 write-only FORCE_DATA_CRC_ERR Force Event for Data CRC Error (SD/eMMC Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Data CRC Error Status is set 21 1 write-only FORCE_DATA_TOUT_ERR Force Event for Data Timeout Error (SD/eMMC Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Data Timeout Error Status is set 20 1 write-only FORCE_CMD_IDX_ERR Force Event for Command Index Error (SD/eMMC Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Command Index Error Status is set 19 1 write-only FORCE_CMD_END_BIT_ERR Force Event for Command End Bit Error (SD/eMMC Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Command End Bit Error Status is set 18 1 write-only FORCE_CMD_CRC_ERR Force Event for Command CRC Error (SD/eMMC Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Command CRC Error Status is set 17 1 write-only FORCE_CMD_TOUT_ERR Force Event for Command Timeout Error (SD/eMMC Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Command Timeout Error Status is set 16 1 write-only FORCE_CMD_NOT_ISSUED_AUTO_CMD12 Force Event for Command Not Issued By Auto CMD12 Error Values: 0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set 0x0 (FALSE): Not Affected 7 1 write-only FORCE_AUTO_CMD_RESP_ERR Force Event for Auto CMD Response Error Values: 0x1 (TRUE): Auto CMD Response Error Status is set 0x0 (FALSE): Not Affected 5 1 write-only FORCE_AUTO_CMD_IDX_ERR Force Event for Auto CMD Index Error Values: 0x1 (TRUE): Auto CMD Index Error Status is set 0x0 (FALSE): Not Affected 4 1 write-only FORCE_AUTO_CMD_EBIT_ERR Force Event for Auto CMD End Bit Error Values: 0x1 (TRUE): Auto CMD End Bit Error Status is set 0x0 (FALSE): Not Affected 3 1 write-only FORCE_AUTO_CMD_CRC_ERR Force Event for Auto CMD CRC Error Values: 0x1 (TRUE): Auto CMD CRC Error Status is set 0x0 (FALSE): Not Affected 2 1 write-only FORCE_AUTO_CMD_TOUT_ERR Force Event for Auto CMD Timeout Error Values: 0x1 (TRUE): Auto CMD Timeout Error Status is set 0x0 (FALSE): Not Affected 1 1 write-only FORCE_AUTO_CMD12_NOT_EXEC Force Event for Auto CMD12 Not Executed Values: 0x1 (TRUE): Auto CMD12 Not Executed Status is set 0x0 (FALSE): Not Affected 0 1 write-only ADMA_ERR_STAT No description available 0x54 32 0x00000000 0x00000007 ADMA_LEN_ERR ADMA Length Mismatch Error States This error occurs in the following instances: While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length When the total data length cannot be divided by the block length Values: 0x0 (NO_ERR): No Error 0x1 (ERROR): Error 2 1 read-only ADMA_ERR_STATES ADMA Error States These bits indicate the state of ADMA when an error occurs during ADMA data transfer. Values: 0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor 0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor 0x2 (UNUSED): Never set this state 0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor 0 2 read-only ADMA_SYS_ADDR No description available 0x58 32 0x00000000 0xFFFFFFFF ADMA_SA ADMA System Address These bits indicate the lower 32 bits of the ADMA system address. SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location ADMA2: This register stores the byte address of the executing command of the descriptor table ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. 0 32 read-write 9 0x2 INIT,DS,HS,SDR12,SDR25,SDR50,SDR104,DDR50,rsv8,rsv9,UHS2 PRESET[%s] no description available 0x60 16 0x0000 0x07FF CLK_GEN_SEL_VAL Clock Generator Select Value This bit is effective when the Host Controller supports a programmable clock generator. Values: 0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator 0x1 (PROG): Programmable Clock Generator 10 1 read-only FREQ_SEL_VAL SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. 0 10 read-only ADMA_ID_ADDR No description available 0x78 32 0x00000000 0xFFFFFFFF ADMA_ID_ADDR ADMA Integrated Descriptor Address These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. The start address of Integrated Descriptor is set to these register bits. The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. 0 32 read-write P_EMBEDDED_CNTRL No description available 0xe6 16 0x0000 0x0FFF REG_OFFSET_ADDR Offset Address of Embedded Control register. 0 12 read-only P_VENDOR_SPECIFIC_AREA No description available 0xe8 16 0x0000 0x0FFF REG_OFFSET_ADDR Base offset Address for Vendor-Specific registers. 0 12 read-only P_VENDOR2_SPECIFIC_AREA No description available 0xea 16 0x0000 0xFFFF REG_OFFSET_ADDR Base offset Address for Command Queuing registers. 0 16 read-only SLOT_INTR_STATUS No description available 0xfc 16 0x0000 0x00FF INTR_SLOT Interrupt signal for each Slot These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. Bit 00: Slot 1 Bit 01: Slot 2 Bit 02: Slot 3 .......... .......... Bit 07: Slot 8 Note: MSHC Host Controller support single card slot. This register shall always return 0. 0 8 read-only CQVER No description available 0x180 32 0x00000000 0x00000FFF EMMC_VER_MAHOR This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. 8 4 read-only EMMC_VER_MINOR This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. 4 4 read-only EMMC_VER_SUFFIX This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. 0 4 read-only CQCAP No description available 0x184 32 0x00000000 0x1000F3FF CRYPTO_SUPPORT Crypto Support This bit indicates whether the Host Controller supports cryptographic operations. Values: 0x0 (FALSE): Crypto not Supported 0x1 (TRUE): Crypto Supported 28 1 read-only ITCFMUL Internal Timer Clock Frequency Multiplier (ITCFMUL) This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. Values: 0x0 (CLK_1KHz): 1KHz clock 0x1 (CLK_10KHz): 10KHz clock 0x2 (CLK_100KHz): 100KHz clock 0x3 (CLK_1MHz): 1MHz clock 0x4 (CLK_10MHz): 10MHz clock 12 4 read-only ITCFVAL Internal Timer Clock Frequency Value (ITCFVAL) This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. 0 10 read-only CQCFG No description available 0x188 32 0x00000000 0x00001101 DCMD_EN This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. Values: 0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor 0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor 12 1 read-write TASK_DESC_SIZE Bit Value Description This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). Values: 0x1 (TASK_DESC_128b): Task descriptor size is 128 bits 0x0 (TASK_DESC_64b): Task descriptor size is 64 bit 8 1 read-write CQ_EN No description available 0 1 read-write CQCTL No description available 0x18c 32 0x00000000 0x00000101 CLR_ALL_TASKS Clear all tasks This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. Values: 0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller 0x0 (NO_EFFECT): Programming 0 has no effect 8 1 read-write HALT Halt request and resume Values: 0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. For example, issuing a Discard Task command (CMDQ_TASK_MGMT). When the software writes 1, CQE completes the ongoing task (if any in progress). After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. 0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity 0 1 read-write CQIS No description available 0x190 32 0x00000000 0x0000000F TCL Task cleared interrupt This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). A value of 1 clears this status bit. Values: 0x1 (SET): TCL Interrupt is set 0x0 (NOTSET): TCL Interrupt is not set 3 1 read-write RED Response error detected interrupt This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. A value of 1 clears this status bit. Values: 0x1 (SET): RED Interrupt is set 0x0 (NOTSET): RED Interrupt is not set 2 1 read-write TCC Task complete interrupt This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: A task is completed and the INT bit is set in its Task Descriptor Interrupt caused by Interrupt Coalescing logic due to timeout Interrupt Coalescing logic reached the configured threshold A value of 1 clears this status bit 1 1 read-write HAC Halt complete interrupt This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. A value of 1 clears this status bit. Values: 0x1 (SET): HAC Interrupt is set 0x0 (NOTSET): HAC Interrupt is not set 0 1 read-write CQISE No description available 0x194 32 0x00000000 0x0000000F TCL_STE Task cleared interrupt status enable Values: 0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active 0x0 (INT_STS_DISABLE): CQIS.TCL is disabled 3 1 read-write RED_STE Response error detected interrupt status enable Values: 0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active 0x0 (INT_STS_DISABLE): CQIS.RED is disabled 2 1 read-write TCC_STE Task complete interrupt status enable Values: 0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active 0x0 (INT_STS_DISABLE): CQIS.TCC is disabled 1 1 read-write HAC_STE Halt complete interrupt status enable Values: 0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active 0x0 (INT_STS_DISABLE): CQIS.HAC is disabled 0 1 read-write CQISGE No description available 0x198 32 0x00000000 0x0000000F TCL_SGE Task cleared interrupt signal enable Values: 0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active 0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled 3 1 read-write RED_SGE Response error detected interrupt signal enable Values: 0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active 0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled 2 1 read-write TCC_SGE Task complete interrupt signal enable Values: 0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active 0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled 1 1 read-write HAC_SGE Halt complete interrupt signal enable Values: 0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active 0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled 0 1 read-write CQIC No description available 0x19c 32 0x00000000 0x80119FFF INTC_EN Interrupt Coalescing Enable Bit Values: 0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated 0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) 31 1 read-write INTC_STAT Interrupt Coalescing Status Bit This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt coalescing (that is, this is set if and only if INTC counter > 0). Values: 0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) 0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) 20 1 read-only INTC_RST Counter and Timer Reset When host driver writes 1, the interrupt coalescing timer and counter are reset. Values: 0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset 0x0 (NO_EFFECT): No Effect 16 1 write-only INTC_TH_WEN Interrupt Coalescing Counter Threshold Write Enable When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. Values: 0x1 (WEN_SET): Sets INTC_TH_WEN 0x0 (WEN_CLR): Clears INTC_TH_WEN 15 1 write-only INTC_TH Interrupt Coalescing Counter Threshold filed Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. The counter is reset by software during the interrupt service routine. The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. 0x0: Interrupt coalescing feature disabled 0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes 0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes ........ 0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes To write to this field, the INTC_TH_WEN bit must be set during the same write operation. 8 5 write-only TOUT_VAL_WEN When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. Values: 0x1 (WEN_SET): Sets TOUT_VAL_WEN 0x0 (WEN_CLR): clears TOUT_VAL_WEN 7 1 write-only TOUT_VAL Interrupt Coalescing Timeout Value Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. Timer Operation: The timer is reset by software during the interrupt service routine. It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. 0x0: Timer is disabled. Timeout-based interrupt is not generated 0x1: Timeout on 01x1024 cycles of timer clock frequency 0x2: Timeout on 02x1024 cycles of timer clock frequency ........ 0x7f: Timeout on 127x1024 cycles of timer clock frequency In order to write to this field, the TOUT_VAL_WEN bit must be set at the same write operation. 0 7 read-write CQTDLBA No description available 0x1a0 32 0x00000000 0xFFFFFFFF TDLBA This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE 0 32 read-write CQTDBR No description available 0x1a8 32 0x00000000 0xFFFFFFFF DBR The software configures TDLBA and TDLBAU, and enable CQE in CQCFG before using this register. Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. The corresponding bit is cleared to 0 by CQE in one of the following events: A task execution is completed (with success or error). The task is cleared using CQTCLR register. All tasks are cleared using CQCTL register. CQE is disabled using CQCFG register. Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. 0 32 read-write CQTCN No description available 0x1ac 32 0x00000000 0xFFFFFFFF TCN Task Completion Notification Each of the 32 bits are bit mapped to the 32 tasks. Bit-N(1): Task-N has completed execution (with success or errors) Bit-N(0): Task-N has not completed, could be pending or not submitted. On task completion, software may read this register to know tasks that have completed. After reading this register, software may clear the relevant bit fields by writing 1 to the corresponding bits. 0 32 read-write CQDQS No description available 0x1b0 32 0x00000000 0xFFFFFFFF DQS Device Queue Status Each of the 32 bits are bit mapped to the 32 tasks. Bit-N(1): Device has marked task N as ready for execution Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. Host controller updates this register with response of the Device Queue Status command. 0 32 read-write CQDPT No description available 0x1b4 32 0x00000000 0xFFFFFFFF DPT Device-Pending Tasks Each of the 32 bits are bit mapped to the 32 tasks. Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution Bit-N(0): Task-N is not yet queued. Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. Software reads this register in the task-discard procedure to determine if the task is queued in the device 0 32 read-write CQTCLR No description available 0x1b8 32 0x00000000 0xFFFFFFFF TCLR Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. 0 32 read-write CQSSC1 No description available 0x1c0 32 0x00000000 0x000FFFFF SQSCMD_BLK_CNT This field indicates when SQS CMD is sent while data transfer is in progress. A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. 0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. 0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. 0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. 0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. ........ 0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. Should be programmed only when CQCFG.CQ_EN is 0 16 4 read-write SQSCMD_IDLE_TMR This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. Should be programmed only when CQCFG.CQ_EN is '0' 0 16 read-write CQSSC2 No description available 0x1c4 32 0x00000000 0x0000FFFF SQSCMD_RCA This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. 0 16 read-write CQCRDCT No description available 0x1c8 32 0x00000000 0xFFFFFFFF DCMD_RESP This register contains the response of the command generated by the last direct command (DCMD) task that was sent. Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. 0 32 read-only CQRMEM No description available 0x1d0 32 0x00000000 0xFFFFFFFF RESP_ERR_MASK The bits of this field are bit mapped to the device response. This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. 1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. 0: When a R1/R1b response is received, bit i in the device status is ignored. The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. 0 32 read-write CQTERRI No description available 0x1d4 32 0x00000000 0x1F3F9F3F TRANS_ERR_TASKID This field captures the ID of the task that was executed and whose data transfer has errors. 24 5 read-only TRANS_ERR_CMD_INDX This field captures the index of the command that was executed and whose data transfer has errors. 16 6 read-only RESP_ERR_FIELDS_VALID This bit is updated when an error is detected while a command transaction was in progress. Values: 0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields 0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX 15 1 read-only RESP_ERR_TASKID This field captures the ID of the task which was executed on the command line when the error occurred. 8 5 read-only RESP_ERR_CMD_INDX This field captures the index of the command that was executed on the command line when the error occurred 0 6 read-only CQCRI No description available 0x1d8 32 0x00000000 0x0000003F CMD_RESP_INDX Last Command Response index This field stores the index of the last received command response. Controller updates the value every time a command response is received 0 6 read-only CQCRA No description available 0x1dc 32 0x00000000 0xFFFFFFFF CMD_RESP_ARG Last Command Response argument This field stores the argument of the last received command response. Controller updates the value every time a command response is received. 0 32 read-only MSHC_VER_ID No description available 0x500 32 0x00000000 0xFFFFFFFF VER_ID No description available 0 32 read-only MSHC_VER_TYPE No description available 0x504 32 0x00000000 0xFFFFFFFF VER_TYPE No description available 0 32 read-only EMMC_BOOT_CTRL No description available 0x52c 32 0x00000000 0xF181070F BOOT_TOUT_CNT Boot Ack Timeout Counter Value. This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. 0xF : Reserved 0xE : TMCLK x 2^27 ............ 0x1 : TMCLK x 2^14 0x0 : TMCLK x 2^13 28 4 read-write BOOT_ACK_ENABLE Boot Acknowledge Enable When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. Values: 0x1 (TRUE): Boot Ack enable 0x0 (FALSE): Boot Ack disable 24 1 read-write VALIDATE_BOOT Validate Mandatory Boot Enable bit This bit is used to validate the MAN_BOOT_EN bit. Values: 0x1 (TRUE): Validate Mandatory boot enable bit 0x0 (FALSE): Ignore Mandatory boot Enable bit 23 1 write-only MAN_BOOT_EN Mandatory Boot Enable This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. Values: 0x1 (MAN_BOOT_EN): Mandatory boot enable 0x0 (MAN_BOOT_DIS): Mandatory boot disable 16 1 read-write CQE_PREFETCH_DISABLE Enable or Disable CQE's PREFETCH feature This field allows Software to disable CQE's data prefetch feature when set to 1. Values: 0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers 0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled 10 1 read-write CQE_ALGO_SEL Scheduler algorithm selected for execution This bit selects the Algorithm used for selecting one of the many ready tasks for execution. Values: 0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks 0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings 9 1 read-write ENH_STROBE_ENABLE Enhanced Strobe Enable This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. Values: 0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode 0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode 8 1 read-write EMMC_RST_N_OE Output Enable control for EMMC Device Reset signal PAD control. This field drived sd_rst_n_oe output of SDXC Values: 0x1 (ENABLE): sd_rst_n_oe is 1 0x0 (DISABLE): sd_rst_n_oe is 0 3 1 read-write EMMC_RST_N EMMC Device Reset signal control. This register field controls the sd_rst_n output of SDXC Values: 0x1 (RST_DEASSERT): Reset to eMMC device is deasserted 0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) 2 1 read-write DISABLE_DATA_CRC_CHK Disable Data CRC Check This bit controls masking of CRC16 error for Card Write in eMMC mode. This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, which may generate CRC error. This CRC error can be masked using this bit during bus testing. Values: 0x1 (DISABLE): DATA CRC check is disabled 0x0 (ENABLE): DATA CRC check is enabled 1 1 read-write CARD_IS_EMMC eMMC Card present This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. Values: 0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card 0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card 0 1 read-write AUTO_TUNING_CTRL No description available 0x540 32 0x00000000 0x7F1F0F1F SWIN_TH_VAL Sampling window threshold value setting The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps can use values from 0x0 to 0x1F. This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' 0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. 0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. 0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. ........ 0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. 24 7 read-write POST_CHANGE_DLY Time taken for phase switching and stable clock output. Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. Values: 0x0 (LATENCY_LT_1): Less than 1-cycle latency 0x1 (LATENCY_LT_2): Less than 2-cycle latency 0x2 (LATENCY_LT_3): Less than 3-cycle latency 0x3 (LATENCY_LT_4): Less than 4-cycle latency 19 2 read-write PRE_CHANGE_DLY Maximum Latency specification between cclk_tx and cclk_rx. Values: 0x0 (LATENCY_LT_1): Less than 1-cycle latency 0x1 (LATENCY_LT_2): Less than 2-cycle latency 0x2 (LATENCY_LT_3): Less than 3-cycle latency 0x3 (LATENCY_LT_4): Less than 4-cycle latency 17 2 read-write TUNE_CLK_STOP_EN Clock stopping control for Tuning and auto-tuning circuit. When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. Values: 0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change 0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching 16 1 read-write WIN_EDGE_SEL This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. 0x0: User selection disabled. Tuning calculated edges are used. 0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. 0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess ... 0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. 8 4 read-write SW_TUNE_EN This fields enables software-managed tuning flow. Values: 0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AUTO_TUNING_STAT.CENTER_PH_CODE Field is now writable. 0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled 4 1 read-write RPT_TUNE_ERR Framing errors are not generated when executing tuning. This debug bit allows users to report these errors. Values: 0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors 0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. 3 1 read-write SWIN_TH_EN Sampling window Threshold enable Selects the tuning mode Field should be programmed only when SAMPLE_CLK_SEL is '0' Values: 0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold set by SWIN_TH_VAL field 0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window 2 1 read-write CI_SEL Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. Values: 0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval 0x1 (WHEN_IN_IDLE): Driven at the end of the transfer 1 1 read-write AT_EN Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. This field should be programmed only when SYS_CTRL.SD_CLK_EN is 0. Values: 0x1 (AT_ENABLE): AutoTuning is enabled 0x0 (AT_DISABLE): AutoTuning is disabled 0 1 read-write AUTO_TUNING_STAT No description available 0x544 32 0x00000000 0x00FFFFFF L_EDGE_PH_CODE Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. 16 8 read-only R_EDGE_PH_CODE Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. 8 8 read-only CENTER_PH_CODE Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AUTO_TUNING_CTRL.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel 0 8 read-write MISC_CTRL0 No description available 0x3000 32 0x00000000 0x10020FFF CARDCLK_INV_EN set to invert card_clk, for slow speed card to meet 5ns setup timing. May cause glitch on clock, should be set before enable clk(in core cfg) 28 1 read-write PAD_CLK_SEL_B set to use internal clock directly, may have timing issue; clr to use clock loopback from pad. 17 1 read-write FREQ_SEL_SW_EN set to use FREQ_SEL_SW as card clock divider; clear to use core logic as clock divider. 11 1 read-write TMCLK_EN set to force enable tmclk; clear to use core signal intclk_en to control it 10 1 read-write FREQ_SEL_SW software card clock divider, it will be used only when FREQ_SEL_SW_EN is set 0 10 read-write MISC_CTRL1 No description available 0x3004 32 0x00000000 0xB3F3F000 CARD_ACTIVE SW write 1 to start card clock delay counter(delay time is configed by CARD_ACTIVE_PERIOD_SEL). When counter finished, this bit will be cleared by hardware. Write 1 when this bit is 1 will cause unknown result(actually no use except write at exact finish time) 31 1 read-write CARD_ACTIVE_PERIOD_SEL card clock delay config. 00 for 100 cycle; 01 for 74 cycle; 10 for 128 cycle; 11 for 256 cycle 28 2 read-write CARDCLK_DLYSEL for card clock DLL, default 0 20 6 read-write STROBE_DLYSEL for strobe DLL, default 7taps(1ns) 12 6 read-write SDXC1 SDXC1 SDXC 0xf1134000 DDRCTL DDRCTL DDRCTL 0xf3010000 0x0 0xf34 registers MSTR Description: Master Register 0x0 32 0x03040001 0x0F0FB601 ACTIVE_RANKS Description: Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are present. 1 - populated 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: 01 - One rank 11 - Two ranks Others - Reserved. For 4 ranks following combinations are legal: 0001 - One rank 0011 - Two ranks 1111 - Four ranks Value After Reset: "(MEMC_NUM_RANKS==4) ? 0xF :((MEMC_NUM_RANKS==2) ? 0x3 : 0x1)" Exists: MEMC_NUM_RANKS>1 24 4 read-write BURST_RDWR Description: SDRAM burst length used: 0001 - Burst length of 2 (only supported for mDDR) 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for mDDR and LPDDR2) All other values are reserved. This controls the burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH is 8. Value After Reset: 0x4 Exists: Always 16 4 read-write DLL_OFF_MODE Description: Set to 1 when uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for normal frequency operation. Value After Reset: 0x0 Exists: MEMC_DDR3_OR_4==1 15 1 read-write DATA_BUS_WIDTH Description: Selects proportion of DQ bus width that is used by the SDRAM 00 - Full DQ bus width to SDRAM 01 - Half DQ bus width to SDRAM 10 - Quarter DQ bus width to SDRAM 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus width is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width). Value After Reset: 0x0 Exists: Always 12 2 read-write EN_2T_TIMING_MODE Description: If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in LPDDR2/LPDDR3 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T timing is not supported in DDR4 geardown mode. Value After Reset: 0x0 Exists: MEMC_CMD_RTN2IDLE==0 10 1 read-write BURSTCHOP Description: When set, enable burst-chop in DDR3/DDR4. This is only supported in full bus width mode (MSTR.data_bus_width = 00). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0' Value After Reset: 0x0 Exists: MEMC_DDR3==1 || MEMC_DDR4==1 9 1 read-write DDR3 Description: Select DDR3 SDRAM 1 - DDR3 SDRAM device in use 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3. Value After Reset: "(MEMC_DDR3_EN==1) ? 0x1 : 0x0" Exists: MEMC_DDR3==1 0 1 read-write STAT Description: Operating Mode Status Register 0x4 32 0x00000000 0x00000037 SELFREF_TYPE Description: Flags if Self Refresh is entered and if it was under Automatic Self Refresh control only or not. 00 - SDRAM is not in Self Refresh 11 - SDRAM is in Self Refresh and Self Refresh was caused by Automatic Self Refresh only 10 - SDRAM is in Self Refresh and Self Refresh was not caused solely under Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software (reg_ddrc_selfref_sw). Value After Reset: 0x0 Exists: Always 4 2 read-only OPERATING_MODE Description: Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/DDR4 support and 2-bits in all other configurations. non-mDDR/LPDDR2/LPDDR3 and non-DDR4 designs: 00 - Init 01 - Normal 10 - Power-down 11 - Self refresh mDDR/LPDDR2/LPDDR3 or DDR4 designs: 000 - Init 001 - Normal 010 - Power-down 011 - Self refresh 1XX - Deep power-down / Maximum Power Saving Mode Value After Reset: 0x0 Exists: Always 0 3 read-only MRCTRL0 Description: Mode Register Read/Write Control Register 0 0x10 32 0x00000030 0x8000F0F0 MR_WR Description: Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL2 automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power- down or MPSM operating modes. Value After Reset: 0x0 Exists: Always 31 1 read-write MR_ADDR Description: Address of the mode register that is to be written to. 0000 - MR0 0001 - MR1 0010 - MR2 0011 - MR3 0100 - MR4 0101 - MR5 0110 - MR6 0111 - MR7 Don't Care for LPDDR2/LPDDR3 (see MRCTRL1.mr_data for mode register addressing in LPDDR2/LPDDR3) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank address bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well as the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of RDIMMs. Value After Reset: 0x0 Exists: Always 12 4 read-write MR_RANK Description: Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. Examples (assume uMCTL2 is configured for 4 ranks): 0x1 - select rank 0 only 0x2 - select rank 1 only 0x5 - select ranks 0 and 2 0xA - select ranks 1 and 3 0xF - select ranks 0, 1, 2 and 3 Value After Reset: "(MEMC_NUM_RANKS==4) ? 0xF :((MEMC_NUM_RANKS==2) ? 0x3 : 0x1)" Exists: Always 4 4 read-write MRCTRL1 Description: Mode Register Read/Write Control Register 1 0x14 32 0x00000000 0x0003FFFF MR_DATA Description: Mode register write data for all non- LPDDR2/non-LPDDR3 modes. For LPDDR2/LPDDR3, MRCTRL1[15:0] are interpreted as [15:8] MR Address and [7:0] MR data for writes, don't care for reads. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Value After Reset: 0x0 Exists: Always 0 18 read-write MRSTAT Description: Mode Register Read/Write Status Register 0x18 32 0x00000000 0x00000001 MR_WR_BUSY Description: The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when 'MRSTAT.mr_wr_busy' is high. 0 - Indicates that the SoC core can initiate a mode register write operation 1 - Indicates that mode register write operation is in progress Value After Reset: 0x0 Exists: Always 0 1 read-only PWRCTL Description: Low Power Control Register 0x30 32 0x00000000 0x0000002B SELFREF_SW Description: A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. 1 - Software Entry to Self Refresh 0 - Software Exit from Self Refresh Value After Reset: 0x0 Exists: Always 5 1 read-write EN_DFI_DRAM_CLK_DISABLE Description: Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DDR4, can be asserted in following: in Self Refresh. in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in following: in Self Refresh in Power Down in Deep Power Down during Normal operation (Clock Stop) Value After Reset: 0x0 Exists: Always 3 1 read-write POWERDOWN_EN Description: If true then the uMCTL2 goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation. Value After Reset: 0x0 Exists: Always 1 1 read-write SELFREF_EN Description: If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re- programmed during the course of normal operation. Value After Reset: 0x0 Exists: Always 0 1 read-write PWRTMG Description: Low Power Timing Register 0x34 32 0x00400010 0x00FF001F SELFREF_TO_X32 Description: After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. Value After Reset: 0x40 Exists: Always 16 8 read-write POWERDOWN_TO_X32 Description: After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. Value After Reset: 0x10 Exists: Always 0 5 read-write HWLPCTL Description: Hardware Low Power Control Register 0x38 32 0x00000003 0x0FFF0003 HW_LP_IDLE_X32 Description: Hardware idle period. The cactive_ddrc output is driven low if the system is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The hardware idle function is disabled when hw_lp_idle_x32=0. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. Value After Reset: 0x0 Exists: Always 16 12 read-write HW_LP_EXIT_IDLE_EN Description: When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it will not cause exit of Self-Refresh that was caused by Hardware Low Power Interface and/or Software (PWRCTL.selfref_sw). Value After Reset: 0x1 Exists: Always 1 1 read-write HW_LP_EN Description: Enable for Hardware Low Power Interface. Value After Reset: 0x1 Exists: Always 0 1 read-write RFSHCTL0 Description: Refresh Control Register 0 0x50 32 0x00210000 0x00F1F1F0 REFRESH_MARGIN Description: Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3, internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks. Value After Reset: 0x2 Exists: Always 20 4 read-write REFRESH_TO_X32 Description: If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the uMCTL2. FOR PERFORMANCE ONLY. Value After Reset: 0x10 Exists: Always 12 5 read-write REFRESH_BURST Description: The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 - single refresh 1 - burst-of-2 refresh 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per- bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granuarity feature, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiated update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY- initiated update is complete. Value After Reset: 0x0 Exists: Always 4 5 read-write RFSHCTL1 Description: Refresh Control Register 1 0x54 32 0x00000000 0x0FFF0FFF REFRESH_TIMER1_START_VALUE_X32 Description: Refresh timer start for rank 1 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. Value After Reset: 0x0 Exists: MEMC_NUM_RANKS>1 16 12 read-write REFRESH_TIMER0_START_VALUE_X32 Description: Refresh timer start for rank 0 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. Value After Reset: 0x0 Exists: MEMC_NUM_RANKS>1 0 12 read-write RFSHCTL3 Description: Refresh Control Register 0 0x60 32 0x00000000 0x00000003 REFRESH_UPDATE_LEVEL Description: Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value is automatically updated when exiting soft reset, so it does not need to be toggled initially. Value After Reset: 0x0 Exists: Always 1 1 read-write DIS_AUTO_REFRESH Description: When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes using the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto- refresh is not supported, and this bit must be set to '0'. This register field is changeable on the fly. Value After Reset: 0x0 Exists: Always 0 1 read-write RFSHTMG Description: Refresh Timing Register 0x64 32 0x0062008C 0x0FFF01FF T_RFC_NOM_X32 Description: tREFI: Average time interval between refreshes per rank (specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2 and LPDDR3). For LPDDR2/LPDDR3: if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tREFIab if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should be set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min. Unit: Multiples of 32 clocks. Value After Reset: 0x62 Exists: Always 16 12 read-write T_RFC_MIN Description: tRFC (min): Minimum time from refresh to refresh or activate. For LPDDR2/LPDDR3: if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRFCab if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should be set to tRFCpb For configurations with MEMC_FREQ_RATIO=2, program this to tRFC(min)/2 and round up to next integer value. In DDR4 mode, tRFC(min) value is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the appropriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks. Value After Reset: 0x8c Exists: Always 0 9 read-write ECCUADDR0 Description: ECC Uncorrected Error Address Register 0 0xa4 32 0x00000000 0x0303FFFF ECC_UNCORR_RANK Description: Rank number of a read resulting in an uncorrected ECC error Value After Reset: 0x0 Exists: MEMC_NUM_RANKS>1 24 2 read-only ECC_UNCORR_ROW Description: Page/row number of a read resulting in an uncorrected ECC error. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Value After Reset: 0x0 Exists: Always 0 18 read-only CRCPARCTL0 Description: CRC Parity Control Register0 0xc0 32 0x00000000 0x00000007 DFI_ALERT_ERR_CNT_CLR Description: DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit will clear the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the uMCTL2 automatically clears this bit. Value After Reset: 0x0 Exists: Always 2 1 read-write DFI_ALERT_ERR_INT_CLR Description: Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int will be cleared. When the clear operation is complete, the uMCTL2 automatically clears this bit. Value After Reset: 0x0 Exists: Always 1 1 read-write DFI_ALERT_ERR_INT_EN Description: Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input will result in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. Value After Reset: 0x0 Exists: Always 0 1 read-write CRCPARSTAT Description: CRC Parity Status Register 0xcc 32 0x00000000 0x0001FFFF DFI_ALERT_ERR_INT Description: DFI alert error interrupt. If a parity/CRC error is detected on dfi_alert_n, and the interrupt is enabled by CRCPARCTL0.dfi_alert_err_int_en, this interrupt bit will be set. It will remain set until cleared by CRCPARCTL0.dfi_alert_err_int_clr Value After Reset: 0x0 Exists: Always 16 1 read-only DFI_ALERT_ERR_CNT Description: DFI alert error count. If a parity/CRC error is detected on dfi_alert_n, this counter be incremented. This is independent of the setting of CRCPARCTL0.dfi_alert_err_int_en. It will saturate at 0xFFFF, and can be cleared by asserting CRCPARCTL0.dfi_alert_err_cnt_clr. Value After Reset: 0x0 Exists: Always 0 16 read-only INIT0 Description: SDRAM Initialization Register 0 0xd0 32 0x0002004E 0xC3FF03FF SKIP_DRAM_INIT Description: If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed 00 - SDRAM Initialization routine is run after power-up 01 - SDRAM Initialization routine is skipped after power- up. Controller starts up in Normal Mode 11 - SDRAM Initialization routine is skipped after power- up. Controller starts up in Self-refresh Mode 10 - SDRAM Initialization routine is run after power-up. Value After Reset: 0x0 Exists: Always 30 2 read-write POST_CKE_X1024 Description: Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be programmed for a delay of 200 us. For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value. Value After Reset: 0x2 Exists: Always 16 10 read-write PRE_CKE_X1024 Description: Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2 specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value. Value After Reset: 0x4e Exists: Always 0 10 read-write INIT1 Description: SDRAM Initialization Register 1 0xd4 32 0x00000000 0x00FF7F0F DRAM_RSTN_X1024 Description: Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3/DDR4 devices. For use with a Synopsys DDR PHY, this should be set to a minimum of 1 Value After Reset: 0x0 Exists: MEMC_DDR3==1 || MEMC_DDR4==1 16 8 read-write FINAL_WAIT_X32 Description: Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a global timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero. Value After Reset: 0x0 Exists: Always 8 7 read-write PRE_OCD_X32 Description: Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero. Value After Reset: 0x0 Exists: Always 0 4 read-write INIT3 Description: SDRAM Initialization Register 3 0xdc 32 0x00000510 0xFFFFFFFF MR Description: DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3 - Value to write to MR1 register Value After Reset: 0x0 Exists: Always 16 16 read-write EMR Description: DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3 - Value to write to MR2 register Value After Reset: 0x510 Exists: Always 0 16 read-write INIT4 Description: SDRAM Initialization Register 4 0xe0 32 0x00000000 0xFFFFFFFF EMR2 Description: DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3: Value to write to MR3 register mDDR: Unused Value After Reset: 0x0 Exists: Always 16 16 read-write EMR3 Description: DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused Value After Reset: 0x0 Exists: Always 0 16 read-write INIT5 Description: SDRAM Initialization Register 5 0xe4 32 0x00100000 0x00FF0000 DEV_ZQINIT_X32 Description: ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us. Value After Reset: 0x10 Exists: MEMC_DDR3==1 || MEMC_DDR4 == 1 || MEMC_LPDDR2==1 16 8 read-write DIMMCTL Description: DIMM Control Register 0xf0 32 0x00000000 0x00000003 DIMM_ADDR_MIRR_EN Description: Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures that, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compensate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2 or LPDDR3 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1. 1 - For odd ranks, implement address mirroring for MRS commands to during initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) 0 - Do not implement address mirroring Value After Reset: 0x0 Exists: Always 1 1 read-write DIMM_STAGGER_CS_EN Description: Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for DDR4, mDDR, LPDDR2 or LPDDR3 SDRAMs. 1 - Stagger accesses to even and odd ranks 0 - Do not stagger accesses Value After Reset: 0x0 Exists: Always 0 1 read-write RANKCTL Description: Rank Control Register 0xf4 32 0x0000066F 0x00000FFF DIFF_RANK_WR_GAP Description: Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. The value programmed in this register takes care of the ODT switch off timing requirement when switching ranks during writes. For configurations with MEMC_FREQ_RATIO=2, program this to (N/2) and round it up to the next integer value. N is value required by PHY, in terms of PHY clocks. Value After Reset: 0x6 Exists: MEMC_NUM_RANKS>1 8 4 read-write DIFF_RANK_RD_GAP Description: Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. The value programmed in this register takes care of the ODT switch off timing requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=2, program this to (N/2) and round it up to the next integer value. N is value required by PHY, in terms of PHY clocks. Value After Reset: 0x6 Exists: MEMC_NUM_RANKS>1 4 4 read-write MAX_RANK_RD Description: Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus contention as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on diff_rank_rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutively to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as long as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0xF. Feature limitation: max_rank_rd feature works as described only in the mode in which one command at the DDRC input results in one DFI command at the output. An example of this mode is: BL8 hardware configuration (MEMC_BURST_LENGTH=8) and Full bus width mode (MSTR.data_bus_width=2'b00) and BL8 mode of operation (MSTR.burst_rdwr=4'b0100). In modes where single HIF command results in multiple DFI commands (eg: Half Bus Width, BL4 etc.), the same rank commands would be serviced for as long as they are available, which is equivalent to this feature being disabled. FOR PERFORMANCE ONLY. Value After Reset: 0xf Exists: MEMC_NUM_RANKS>1 0 4 read-write DRAMTMG0 Description: SDRAM Timing Register 0 0x100 32 0x0F101B0F 0x7F3F7F3F WR2PRE Description: Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies where: WL = write latency BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3 for this parameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode, divide the above value by 2 and add 1. No rounding up. Value After Reset: 0xf Exists: Always 24 7 read-write T_FAW Description: tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next integer value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks Value After Reset: 0x10 Exists: Always 16 6 read-write T_RAS_MAX Description: tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of 1024 clocks. Value After Reset: 0x1b Exists: Always 8 7 read-write T_RAS_MIN Description: tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode, program this to (tRAS(min)/2 + 1). No rounding up of the division operation. Unit: Clocks Value After Reset: 0xf Exists: Always 0 6 read-write DRAMTMG1 Description: SDRAM Timing Register 1 0x104 32 0x00080414 0x001F1F7F T_XP Description: tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it up to the next integer value. Units: Clocks Value After Reset: 0x8 Exists: Always 16 5 read-write RD2PRE Description: tRTP: Minimum time from read to precharge of same bank. DDR2: tAL + BL/2 + max(tRTP, 2) - 2 DDR3: tAL + max (tRTP, 4) DDR4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. mDDR: BL/2 LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. LPDDR3: BL/2 + max(tRTP,4) - 4 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode, divide the above value by 2 and add 1. No rounding up of division operation. Unit: Clocks. Value After Reset: 0x4 Exists: Always 8 5 read-write T_RC Description: tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next integer value. Unit: Clocks. Value After Reset: 0x14 Exists: Always 0 7 read-write DRAMTMG2 Description: SDRAM Timing Register 2 0x108 32 0x0000060D 0x00001F3F RD2WR Description: DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL. Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: WL = write latency BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM RL = read latency = CAS latency WR_PREAMBLE = write preamble. This is unique to DDR4. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. Value After Reset: 0x6 Exists: Always 8 5 read-write WR2RD Description: DDR4: WL + BL/2 + tWTR_L Others: WL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same bank group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: WL = write latency BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM tWTR_L = internal write to read command delay for same bank group. This comes directly from the SDRAM specification. tWTR = internal write to read command delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3 operation. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. Value After Reset: 0xd Exists: Always 0 6 read-write DRAMTMG3 Description: SDRAM Timing Register 3 0x10c 32 0x0000400C 0x0003F3FF T_MRD Description: tMRD: Cycles between load mode commands. If MEMC_DDR3_OR_4 = 0, this parameter is also used to define the cycles between load mode command and following non-load mode command. For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead Value After Reset: 0x4 Exists: Always 12 6 read-write T_MOD Description: tMOD: Present if MEMC_DDR3_OR_4 = 1. Cycles between load mode command and following non-load mode command. This is required to be programmed even when a design that supports DDR3/4 is running in DDR2 mode. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip Value After Reset: "(MEMC_DDR3_EN==1 || MEMC_DDR4_EN==1 ) ? 0xc : 0x0" Exists: MEMC_DDR3==1 || MEMC_DDR4==1 0 10 read-write DRAMTMG4 Description: SDRAM Timing Register 4 0x110 32 0x05040405 0x1F070F1F T_RCD Description: tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which implies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. Value After Reset: 0x5 Exists: Always 24 5 read-write T_CCD Description: DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. Unit: clocks. Value After Reset: 0x4 Exists: Always 16 3 read-write T_RRD Description: DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. Others: tRRD: Minimum time between activates from bank "a" to bank "b" For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Unit: Clocks. Value After Reset: 0x4 Exists: Always 8 4 read-write T_RP Description: tRP: Minimum time from precharge to activate of same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRP/2 + 1). No round up of the fraction. Unit: Clocks. Value After Reset: 0x5 Exists: Always 0 5 read-write DRAMTMG5 Description: SDRAM Timing Register 5 0x114 32 0x05050403 0x0F0F3F1F T_CKSRX Description: This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: mDDR: 1 LPDDR2: 2 LPDDR3: 2 DDR2: 1 DDR3: tCKSRX DDR4: tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next integer. Value After Reset: 0x5 Exists: Always 24 4 read-write T_CKSRE Description: This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: mDDR: 0 LPDDR2: 2 LPDDR3: 2 DDR2: 1 DDR3: max (10 ns, 5 tCK) DDR4: max (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next integer. Value After Reset: 0x5 Exists: Always 16 4 read-write T_CKESR Description: Minimum CKE low width for Self refresh entry to exit timing im memory clock cycles. Recommended settings: mDDR: tRFC LPDDR2: tCKESR LPDDR3: tCKESR DDR2: tCKE DDR3: tCKE + 1 DDR4: tCKE + 1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next integer. Value After Reset: 0x4 Exists: Always 8 6 read-write T_CKE Description: Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR Non-LPDDR2/non-LPDDR3 designs: Set this to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to the next integer value. Unit: Clocks. Value After Reset: 0x3 Exists: Always 0 5 read-write DRAMTMG8 Description: SDRAM Timing Register 8 0x120 32 0x00004405 0x00007F7F T_XS_DLL_X32 Description: tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: In LPDDR2/LPDDR3/Mobile DDR mode, t_xs_x32 and t_xs_dll_x32 must be set the same values derived from tXSR. Value After Reset: 0x44 Exists: Always 8 7 read-write T_XS_X32 Description: tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: In LPDDR2/LPDDR3/Mobile DDR mode, t_xs_x32 and t_xs_dll_x32 must be set the same values derived from tXSR. Value After Reset: 0x5 Exists: Always 0 7 read-write ZQCTL0 Description: ZQ Control Register 0 0x180 32 0x02000040 0xE3FF03FF DIS_AUTO_ZQ Description: 1 - Disable uMCTL2 generation of ZQCS command. Register reg_ddrc_zq_calib_short can be used instead to control ZQ calibration commands. 0 - Internally generate ZQCS commands based on ZQCTL1.t_zq_short_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. Value After Reset: 0x0 Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 31 1 read-write DIS_SRX_ZQCL Description: 1 - Disable issuing of ZQCL command at Self-Refresh exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 mode. 0 - Enable issuing of ZQCL command at Self-Refresh exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 mode. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. Value After Reset: 0x0 Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 30 1 read-write ZQ_RESISTOR_SHARED Description: 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS timing met between commands so that commands to different ranks do not overlap. 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. Value After Reset: 0x0 Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 29 1 read-write T_ZQ_LONG_NOP Description: tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. Value After Reset: 0x200 Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 16 10 read-write T_ZQ_SHORT_NOP Description: tZQCS: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. Value After Reset: 0x40 Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 0 10 read-write ZQCTL1 Description: ZQ Control Register 1 0x184 32 0x00000100 0x000FFFFF T_ZQ_SHORT_INTERVAL_X1024 Description: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3/DDR4/LPDDR2/LPDDR3 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. Value After Reset: 0x100 Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 0 20 read-write ZQSTAT Description: ZQ Status Register 0x18c 32 0x00000000 0x00000001 ZQ_RESET_BUSY Description: SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. 0 - Indicates that the SoC core can initiate a ZQ Reset operation 1 - Indicates that ZQ Reset operation is in progress Value After Reset: 0x0 Exists: Always 0 1 read-only DFITMG0 Description: DFI Timing Register 0 0x190 32 0x07020002 0x1FBFBF3F DFI_T_CTRL_DELAY Description: Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, depending on the PHY, it may be necessary to increment this parameter by 1. This is to compensate for the extra cycle of latency through the RDIMM Value After Reset: 0x7 Exists: Always 24 5 read-write DFI_RDDATA_USE_SDR Description: Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: 0 in terms of HDR clock cycles 1 in terms of SDR clock cycles Refer to PHY specification for correct value. Value After Reset: 0x0 Exists: MEMC_FREQ_RATIO==2 23 1 read-write DFI_T_RDDATA_EN Description: Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle of latency through the RDIMM. Unit: Clocks Value After Reset: 0x2 Exists: Always 16 6 read-write DFI_WRDATA_USE_SDR Description: Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or HDR clock cycles 0 in terms of HDR clock cycles 1 in terms of SDR clock cycles Refer to PHY specification for correct value. Value After Reset: 0x0 Exists: MEMC_FREQ_RATIO==2 15 1 read-write DFI_TPHY_WRDATA Description: Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. Unit: Clocks Value After Reset: 0x0 Exists: Always 8 6 read-write DFI_TPHY_WRLAT Description: Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. The minimum supported value is as follows: 0 for configurations with MEMC_WL0 = 1 1 for configurations with MEMC_WL0 = 0 Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency through the RDIMM. Value After Reset: 0x2 Exists: Always 0 6 read-write DFITMG1 Description: DFI Timing Register 1 0x194 32 0x00000404 0x001F0F0F DFI_T_WRDATA_DELAY Description: Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks Value After Reset: 0x0 Exists: Always 16 5 read-write DFI_T_DRAM_CLK_DISABLE Description: Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY- DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. Value After Reset: 0x4 Exists: Always 8 4 read-write DFI_T_DRAM_CLK_ENABLE Description: Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. Value After Reset: 0x4 Exists: Always 0 4 read-write DFILPCFG0 Description: DFI Low Power Configuration Register 0 0x198 32 0x07000000 0x0F00F1F1 DFI_TLP_RESP Description: Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always. Value After Reset: 0x7 Exists: Always 24 4 read-write DFI_LP_WAKEUP_SR Description: Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: 0x0 - 16 cycles 0x1 - 32 cycles 0x2 - 64 cycles 0x3 - 128 cycles 0x4 - 256 cycles 0x5 - 512 cycles 0x6 - 1024 cycles 0x7 - 2048 cycles 0x8 - 4096 cycles 0x9 - 8192 cycles 0xA - 16384 cycles 0xB - 32768 cycles 0xC - 65536 cycles 0xD - 131072 cycles 0xE - 262144 cycles 0xF - Unlimited Value After Reset: 0x0 Exists: Always 12 4 read-write DFI_LP_EN_SR Description: Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. 0 - Disabled 1 - Enabled Value After Reset: 0x0 Exists: Always 8 1 read-write DFI_LP_WAKEUP_PD Description: Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: 0x0 - 16 cycles 0x1 - 32 cycles 0x2 - 64 cycles 0x3 - 128 cycles 0x4 - 256 cycles 0x5 - 512 cycles 0x6 - 1024 cycles 0x7 - 2048 cycles 0x8 - 4096 cycles 0x9 - 8192 cycles 0xA - 16384 cycles 0xB - 32768 cycles 0xC - 65536 cycles 0xD - 131072 cycles 0xE - 262144 cycles 0xF - Unlimited Value After Reset: 0x0 Exists: Always 4 4 read-write DFI_LP_EN_PD Description: Enables DFI Low Power interface handshaking during Power Down Entry/Exit. 0 - Disabled 1 - Enabled Value After Reset: 0x0 Exists: Always 0 1 read-write DFIUPD0 Description: DFI Update Register 0 0x1a0 32 0x00400003 0x83FF03FF DIS_AUTO_CTRLUPD Description: When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2. The core must issue the dfi_ctrlupd_req signal using register reg_ddrc_ctrlupd. This register field is changeable on the fly. When '0', uMCTL2 issues dfi_ctrlupd_req periodically. Value After Reset: 0x0 Exists: Always 31 1 read-write DFI_T_CTRLUP_MAX Description: Specifies the maximum number of clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. Unit: Clocks Value After Reset: 0x40 Exists: Always 16 10 read-write DFI_T_CTRLUP_MIN Description: Specifies the minimum number of clock cycles that the dfi_ctrlupd_req signal must be asserted. The uMCTL2 expects the PHY to respond within this time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. Unit: Clocks Value After Reset: 0x3 Exists: Always 0 10 read-write DFIUPD1 Description: DFI Update Register 1 0x1a4 32 0x00000000 0x00FF00FF DFI_T_CTRLUPD_INTERVAL_MIN_X1024 Description: This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the uMCTL2 is idle. Unit: 1024 clocks Value After Reset: 0x0 Exists: Always 16 8 read-write DFI_T_CTRLUPD_INTERVAL_MAX_X1024 Description: This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 clocks Value After Reset: 0x0 Exists: Always 0 8 read-write DFIUPD2 Description: DFI Update Register 2 0x1a8 32 0x80100010 0x8FFF0FFF DFI_PHYUPD_EN Description: Enables the support for acknowledging PHY- initiated updates: 0 - Disabled 1 - Enabled Value After Reset: 0x1 Exists: Always 31 1 read-write DFI_PHYUPD_TYPE1 Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b01. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. Value After Reset: 0x10 Exists: Always 16 12 read-write DFI_PHYUPD_TYPE0 Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b00. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. Value After Reset: 0x10 Exists: Always 0 12 read-write DFIUPD3 Description: DFI Update Register 3 0x1ac 32 0x00100010 0x0FFF0FFF DFI_PHYUPD_TYPE3 Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b11. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. Value After Reset: 0x10 Exists: Always 16 12 read-write DFI_PHYUPD_TYPE2 Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b10. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. Value After Reset: 0x10 Exists: Always 0 12 read-write DFIMISC Description: DFI Miscellaneous Control Register 0x1b0 32 0x00000001 0x00000001 DFI_INIT_COMPLETE_EN Description: PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisation Value After Reset: 0x1 Exists: Always 0 1 read-write DFITMG2 Description: DFI Timing Register 2 0x1b4 32 0x00000202 0x00003F3F DFI_TPHY_RDCSLAT Description: Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs_n signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. Value After Reset: 0x2 Exists: Always 8 6 read-write DFI_TPHY_WRCSLAT Description: Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs_n signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. The minimum supported value is as follows: 0 for configurations with MEMC_WL0 = 1 1 for configurations with MEMC_WL0 = 0 Refer to PHY specification for correct value. Value After Reset: 0x2 Exists: Always 0 6 read-write ADDRMAP0 Description: Address Map Register 0 0x200 32 0x00000000 0x0000001F ADDRMAP_CS_BIT0 Description: Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0. Value After Reset: 0x0 Exists: MEMC_NUM_RANKS>1 0 5 read-write ADDRMAP1 Description: Address Map Register 1 0x204 32 0x00000000 0x001F1F1F ADDRMAP_BANK_B2 Description: Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0. Value After Reset: 0x0 Exists: Always 16 5 read-write ADDRMAP_BANK_B1 Description: Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. Value After Reset: 0x0 Exists: Always 8 5 read-write ADDRMAP_BANK_B0 Description: Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. Value After Reset: 0x0 Exists: Always 0 5 read-write ADDRMAP2 Description: Address Map Register 2 0x208 32 0x00000000 0x0F0F0F0F ADDRMAP_COL_B5 Description: Full bus width mode: Selects the HIF address bit used as column address bit 5 (if MEMC_BURST_LENGTH = 4) or 6 (if MEMC_BURST_LENGTH = 8). Half bus width mode: Selects the HIF address bit used as column address bit 6 (if MEMC_BURST_LENGTH = 4) or 7 (if MEMC_BURST_LENGTH = 8). Quarter bus width mode: Selects the HIF address bit used as column address bit 7 (if MEMC_BURST_LENGTH = 4) or 8 (if MEMC_BURST_LENGTH = 8). Valid Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Value After Reset: 0x0 Exists: Always 24 4 read-write ADDRMAP_COL_B4 Description: Full bus width mode: Selects the HIF address bit used as column address bit 4 (if MEMC_BURST_LENGTH = 4) or 5 (if MEMC_BURST_LENGTH = 8). Half bus width mode: Selects the HIF address bit used as column address bit 5 (if MEMC_BURST_LENGTH = 4) or 6 (if MEMC_BURST_LENGTH = 8). Quarter bus width mode: Selects the HIF address bit used as column address bit 6 (if MEMC_BURST_LENGTH = 4) or 7 (if MEMC_BURST_LENGTH = 8). Valid Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Value After Reset: 0x0 Exists: Always 16 4 read-write ADDRMAP_COL_B3 Description: Full bus width mode: Selects the HIF address bit used as column address bit 3 (if MEMC_BURST_LENGTH = 4) or 4 (if MEMC_BURST_LENGTH = 8). Half bus width mode: Selects the HIF address bit used as column address bit 4 (if MEMC_BURST_LENGTH = 4) or 5 (if MEMC_BURST_LENGTH = 8). Quarter bus width mode: Selects the HIF address bit used as column address bit 5 (if MEMC_BURST_LENGTH = 4) or 6 (if MEMC_BURST_LENGTH = 8). Valid Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this field. Value After Reset: 0x0 Exists: Always 8 4 read-write ADDRMAP_COL_B2 Description: Full bus width mode: Selects the HIF address bit used as column address bit 2 (if MEMC_BURST_LENGTH = 4) or 3 (if MEMC_BURST_LENGTH = 8). Half bus width mode: Selects the HIF address bit used as column address bit 3 (if MEMC_BURST_LENGTH = 4) or 4 (if MEMC_BURST_LENGTH = 8). Quarter bus width mode: Selects the HIF address bit used as column address bit 4 (if MEMC_BURST_LENGTH = 4) or 5 (if MEMC_BURST_LENGTH = 8). Valid Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this field. Value After Reset: 0x0 Exists: Always 0 4 read-write ADDRMAP3 Description: Address Map Register 3 0x20c 32 0x00000000 0x0F0F0F0F ADDRMAP_COL_B9 Description: Full bus width mode: Selects the HIF address bit used as column address bit 9 (if MEMC_BURST_LENGTH = 4) or 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8) Half bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). (Column address bit 11 in LPDDR2/LPDDR3 mode) Quarter bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or UNUSED (if MEMC_BURST_LENGTH = 8). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 Exists: Always 24 4 read-write ADDRMAP_COL_B8 Description: Full bus width mode: Selects the HIF address bit used as column address bit 8 (if MEMC_BURST_LENGTH = 4) or 9 (if MEMC_BURST_LENGTH = 8). Half bus width mode: Selects the HIF address bit used as column address bit 9 (if MEMC_BURST_LENGTH = 4) or 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 Exists: Always 16 4 read-write ADDRMAP_COL_B7 Description: Full bus width mode: Selects the HIF address bit used as column address bit 7 (if MEMC_BURST_LENGTH = 4) or 8 (if MEMC_BURST_LENGTH = 8). Half bus width mode: Selects the HIF address bit used as column address bit 8 (if MEMC_BURST_LENGTH = 4) or 9 (if MEMC_BURST_LENGTH = 8). Quarter bus width mode: Selects the HIF address bit used as column address bit 9 (if MEMC_BURST_LENGTH = 4) or 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). Valid Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge and hence no source address bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 Exists: Always 8 4 read-write ADDRMAP_COL_B6 Description: Full bus width mode: Selects the HIF address bit used as column address bit 6 (if MEMC_BURST_LENGTH = 4) or 7 (if MEMC_BURST_LENGTH = 8). Half bus width mode: Selects the HIF address bit used as column address bit 7 (if MEMC_BURST_LENGTH = 4) or 8 (if MEMC_BURST_LENGTH = 8). Quarter bus width mode: Selects the HIF address bit used as column address bit 8 (if MEMC_BURST_LENGTH = 4) or 9 (if MEMC_BURST_LENGTH = 8). Valid Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Value After Reset: 0x0 Exists: Always 0 4 read-write ADDRMAP4 Description: Address Map Register 4 0x210 32 0x00000000 0x00000F0F ADDRMAP_COL_B11 Description: Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or UNUSED (if MEMC_BURST_LENGTH = 8). Half bus width mode: Unused. To make it unused, this should be tied to 4'hF. Quarter bus width mode: Unused. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 Exists: Always 8 4 read-write ADDRMAP_COL_B10 Description: Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). Half bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or UNUSED (if MEMC_BURST_LENGTH = 8) Quarter bus width mode: UNUSED. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 Exists: Always 0 4 read-write ADDRMAP5 Description: Address Map Register 5 0x214 32 0x00000000 0x0F0F0F0F ADDRMAP_ROW_B11 Description: Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0. Value After Reset: 0x0 Exists: Always 24 4 read-write ADDRMAP_ROW_B2_10 Description: Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11 Internal Base: 8 (for row address bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. Value After Reset: 0x0 Exists: Always 16 4 read-write ADDRMAP_ROW_B1 Description: Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. Value After Reset: 0x0 Exists: Always 8 4 read-write ADDRMAP_ROW_B0 Description: Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. Value After Reset: 0x0 Exists: Always 0 4 read-write ADDRMAP6 Description: Address Map Register 6 0x218 32 0x00000000 0x0F0F0F0F ADDRMAP_ROW_B15 Description: Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0. Value After Reset: 0x0 Exists: Always 24 4 read-write ADDRMAP_ROW_B14 Description: Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0. Value After Reset: 0x0 Exists: Always 16 4 read-write ADDRMAP_ROW_B13 Description: Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0. Value After Reset: 0x0 Exists: Always 8 4 read-write ADDRMAP_ROW_B12 Description: Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0. Value After Reset: 0x0 Exists: Always 0 4 read-write ODTCFG Description: ODT Configuration Register 0x240 32 0x04000400 0x0F1F0F7C WR_ODT_HOLD Description: Cycles to hold ODT for a write command. The minimum supported value is 2. DDR2/DDR3/DDR4 BL8 - 0x6 BL4 - 0x4 LPDDR3 - RU(tDQSSmax/tCK) + 4 Value After Reset: 0x4 Exists: Always 24 4 read-write WR_ODT_DELAY Description: The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. ODT is used only in DDR2, DDR3, DDR4 and LPDDR3 designs. Recommended values: DDR2 If (CWL + AL < 3), then 0. If (CWL + AL >= 3), then (CWL + AL - 3) DDR3 - 0 DDR4 - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3 - (CWL - RU(tODToffmax/tCK)) Value After Reset: 0x0 Exists: Always 16 5 read-write RD_ODT_HOLD Description: Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2/DDR3 BL8 - 0x6 BL4 - 0x4 DDR4 - 0x6, but needs to be reduced to 0x5 in CAL mode to avoid overlap of read and write ODT LPDDR3 - RU(tDQSCKmax/tCK) + 4 + 1 Value After Reset: 0x4 Exists: Always 8 4 read-write RD_ODT_DELAY Description: The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. ODT is used only in DDR2, DDR3, DDR4 and LPDDR3 designs. Recommended values: DDR2 If (CL + AL < 4), then 0. If (CL + AL >= 4), then (CL + AL - 4) DDR3 (CL - CWL) DDR4 If CAL mode is enabled, CL - CWL + DFITMG1.dfi_t_cmd_lat If CAL mode is not enabled, CL - CWL -1, or 0 if CL - CWL < 1 LPDDR3, MEMC_FREQ_RATIO=2 CL - RU(tODToffmax/tCK)) Value After Reset: 0x0 Exists: Always 2 5 read-write ODTMAP Description: ODT/Rank Map Register 0x244 32 0x00002211 0x0000FFFF RANK1_RD_ODT Description: Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks Value After Reset: "(MEMC_NUM_RANKS>1) ? 0x2 : 0x0" Exists: MEMC_NUM_RANKS>1 12 4 read-write RANK1_WR_ODT Description: Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks Value After Reset: "(MEMC_NUM_RANKS>1) ? 0x2 : 0x0" Exists: MEMC_NUM_RANKS>1 8 4 read-write RANK0_RD_ODT Description: Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each rank, set its bit to 1 to enable its ODT. Value After Reset: 0x1 Exists: Always 4 4 read-write RANK0_WR_ODT Description: Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each rank, set its bit to 1 to enable its ODT. Value After Reset: 0x1 Exists: Always 0 4 read-write SCHED Description: Scheduler Control Register 0x250 32 0x00000805 0x7FFF3F07 RDWR_IDLE_GAP Description: When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this register. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. FOR PERFORMANCE ONLY Value After Reset: 0x0 Exists: Always 24 7 read-write GO2CRITICAL_HYSTERESIS Description: UNUSED Value After Reset: 0x0 Exists: Always 16 8 read-write LPR_NUM_ENTRIES Description: Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one less than in the non-ECC case. One entry each is reserved in the write and low- priority read CAMs for storing the RMW requests arising out of single bit error correction RMW operation. Value After Reset: "MEMC_NO_OF_ENTRY/2" Exists: Always 8 6 read-write PAGECLOSE Description: If true, bank is kept open only until there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a need to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open page policy can be overridden by setting the per-command-autopre bit on the HIF interface (co_ih_rxcmd_autopre). The pageclose feature provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY. Value After Reset: 0x1 Exists: Always 2 1 read-write PREFER_WRITE Description: If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. Value After Reset: 0x0 Exists: Always 1 1 read-write FORCE_LOW_PRI_N Description: Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Priority Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write side, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY. Value After Reset: 0x1 Exists: Always 0 1 read-write SCHED1 Description: Scheduler Control Register 1 0x254 32 0x00000000 0x000000FF PAGECLOSE_TIMER Description: This field works in conjunction with SCHED.pageclose. It only has meaning if SCHED.pageclose==1. If SCHED.pageclose==1 and pageclose_timer==0, then an auto-precharge may be scheduled for last read or write command in the CAM with a bank and page hit. Note, sometimes an explicit precharge is scheduled instead of the auto-precharge. See SCHED.pageclose for details of when this may happen. If SCHED.pageclose==1 and pageclose_timer>0, then an auto-precharge is not scheduled for last read or write command in the CAM with a bank and page hit. Instead, a timer is started, with pageclose_timer as the initial value. There is a timer on a per bank basis. The timer decrements unless the next read or write in the CAM to a bank is a page hit. It gets reset to pageclose_timer value if the next read or write in the CAM to a bank is a page hit. Once the timer has reached zero, an explcit precharge will be attempted to be scheduled. Value After Reset: 0x0 Exists: Always 0 8 read-write PERFHPR1 Description: High Priority Read CAM Register 1 0x25c 32 0x0F000001 0xFF00FFFF HPR_XACT_RUN_LENGTH Description: Number of transactions that are serviced once the HPR queue goes critical is the smaller of: This number Number of transactions available Unit: Transaction. FOR PERFORMANCE ONLY. Value After Reset: 0xf Exists: Always 24 8 read-write HPR_MAX_STARVE Description: Number of clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. Value After Reset: 0x1 Exists: Always 0 16 read-write PERFLPR1 Description: Low Priority Read CAM Register 1 0x264 32 0x0F00007F 0xFF00FFFF LPR_XACT_RUN_LENGTH Description: Number of transactions that are serviced once the LPR queue goes critical is the smaller of: This number Number of transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. Value After Reset: 0xf Exists: Always 24 8 read-write LPR_MAX_STARVE Description: Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. Value After Reset: 0x7f Exists: Always 0 16 read-write PERFWR1 Description: Write CAM Register 1 0x26c 32 0x0F00007F 0xFF00FFFF W_XACT_RUN_LENGTH Description: Number of transactions that are serviced once the WR queue goes critical is the smaller of: This number Number of transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. Value After Reset: 0xf Exists: Always 24 8 read-write W_MAX_STARVE Description: Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. Value After Reset: 0x7f Exists: Always 0 16 read-write PERFVPR1 Description: Variable Priority Read CAM Register 1 0x274 32 0x00000000 0x000007FF VPR_TIMEOUT_RANGE Description: Indicates the range of the timeout value that is used for grouping the expired VPR commands in the CAM in DDRC. For example, if the register value is set to 0xF, then the priorities of all the VPR commands whose timeout counters are 15 or below will be considered as expired-VPR commands when the timeout value of any of the VPR commands reach 0. The expired-VPR commands, when present, are given higher priority than HPR commands. The VPR commands are expected to consist of largely page hit traffic and by grouping them together the bus utilization is expected to increase. This register applies to transactions inside the DDRC only. The Max value for this register is 0x7FF and the Min value is 0x0. When programmed to the Max value of 0x7FF, all the VPR commands that come in to DDRC will time-out right-away and will be considered as expired-VPR. When programmed to the Min value of 0x0, the timer of each command would have to reach a value of 0 before it will be considered as expired-VPR. Unit: Clock cycles. FOR PERFORMANCE ONLY. Value After Reset: 0x0 Exists: UMCTL2_VPR_EN==1 0 11 read-write PERFVPW1 Description: Variable Priority Write CAM Register 1 0x278 32 0x00000000 0x000007FF VPW_TIMEOUT_RANGE Description: Indicates the range of the timeout value that is used for grouping the expired VPW commands in the CAM in DDRC. For example, if the register value is set to 0xF, then the priorities of all the VPW commands whose timeout counters are 15 or below will be considered as expired-VPW commands when the timeout value of any of the VPW commands reach 0. The expired-VPW commands, when present, are given higher priority than normal Write commands. The VPW commands are expected to consist of largely page hit traffic and by grouping them together the bus utilization is expected to increase. This register applies to transactions inside the DDRC only. The Max value for this register is 0x7FF and the Min value is 0x0. When programmed to the Max value of 0x7FF, all the VPW commands that come in to DDRC will time-out right-away and will be considered as expired-VPW. When programmed to the Min value of 0x0, the timer of each command would have to reach a value of 0 before it will be considered as expired-VPW. Unit: Clock cycles. FOR PERFORMANCE ONLY. Value After Reset: 0x0 Exists: UMCTL2_VPW_EN==1 0 11 read-write DBG0 Description: Debug Register 0 0x300 32 0x00000000 0x00000017 DIS_COLLISION_PAGE_OPT Description: When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY. Value After Reset: 0x0 Exists: Always 4 1 read-write DIS_ACT_BYPASS Description: Only present in designs supporting activate bypass. When 1, disable bypass path for high priority read activates FOR DEBUG ONLY. Value After Reset: 0x0 Exists: MEMC_BYPASS==1 2 1 read-write DIS_RD_BYPASS Description: Only present in designs supporting read bypass. When 1, disable bypass path for high priority read page hits FOR DEBUG ONLY. Value After Reset: 0x0 Exists: MEMC_BYPASS==1 1 1 read-write DIS_WC Description: When 1, disable write combine. FOR DEBUG ONLY Value After Reset: 0x0 Exists: Always 0 1 read-write DBG1 Description: Debug Register 1 0x304 32 0x00000000 0x00000003 DIS_HIF Description: When 1, uMCTL2 asserts the HIF command ih_co_stall. uMCTL2 will ignore the co_ih_rxcmd_valid and all other associated request signals. This bit is intended to be switched on-the-fly. Value After Reset: 0x0 Exists: Always 1 1 read-write DIS_DQ Description: When 1, uMCTL2 will not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. This bit may be used to prevent reads or writes being issued by the uMCTL2, which makes it safe to modify certain register fields associated with reads and writes (see User Guide for details). After setting this bit, it is strongly recommended to poll DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, before making changes to any registers which affect reads and writes. This will ensure that the relevant logic in the DDRC is idle. This bit is intended to be switched on-the-fly. Value After Reset: 0x0 Exists: Always 0 1 read-write DBGCAM Description: CAM Debug Register 0x308 32 0x00000000 0x377F7F7F WR_DATA_PIPELINE_EMPTY Description: This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. Value After Reset: 0x0 Exists: Always 29 1 read-only RD_DATA_PIPELINE_EMPTY Description: This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. Value After Reset: 0x0 Exists: Always 28 1 read-only DBG_WR_Q_EMPTY Description: When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. An example use-case scenario: When Controller enters Self- Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. FOR DEBUG ONLY Value After Reset: 0x0 Exists: Always 26 1 read-only DBG_RD_Q_EMPTY Description: When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. An example use-case scenario: When Controller enters Self- Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. FOR DEBUG ONLY Value After Reset: 0x0 Exists: Always 25 1 read-only DBG_STALL Description: Stall FOR DEBUG ONLY Value After Reset: 0x0 Exists: Always 24 1 read-only DBG_W_Q_DEPTH Description: Write queue depth Note: The width of this field is dependent on log(MEMC_NO_OF_ENTRY+1). For example, if CAM depth = 32, then register width is 6 bits and bit 22 is reserved. FOR DEBUG ONLY Value After Reset: 0x0 Exists: Always 16 7 read-only DBG_LPR_Q_DEPTH Description: Low priority read queue depth Note: The width of this field is dependent on log(MEMC_NO_OF_ENTRY+1). For example, if CAM depth = 32, then register width is 6 bits and bit 14 is reserved FOR DEBUG ONLY Value After Reset: 0x0 Exists: Always 8 7 read-only DBG_HPR_Q_DEPTH Description: High priority read queue depth Note: The width of this field is dependent on log(MEMC_NO_OF_ENTRY+1). For example, if CAM depth = 32, then register width is 6 bits and bit 6 is reserved FOR DEBUG ONLY Value After Reset: 0x0 Exists: Always 0 7 read-only DBGCMD Description: Command Debug Register 0x30c 32 0x00000000 0x00000033 CTRLUPD Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. Value After Reset: 0x0 Exists: Always 5 1 read-write ZQ_CALIB_SHORT Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short) command to the SDRAM. When this request is stored in uMCTL2, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignored when in Self-Refresh and Deep power-down operating modes. Value After Reset: 0x0 Exists: MEMC_DDR3_OR_4_OR_LPDDR2==1 4 1 read-write RANK1_REFRESH Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. When this request is stored in uMCTL2, the bit is automatically cleared. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. Value After Reset: 0x0 Exists: MEMC_NUM_RANKS>1 1 1 read-write RANK0_REFRESH Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. When this request is stored in uMCTL2, the bit is automatically cleared. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. Value After Reset: 0x0 Exists: Always 0 1 read-write DBGSTAT Description: Status Debug Register 0x310 32 0x00000000 0x00000033 CTRLUPD_BUSY Description: SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in uMCTL2. It is recommended not to perform ctrlupd operations when this signal is high. 0 - Indicates that the SoC core can initiate a ctrlupd operation 1 - Indicates that ctrlupd operation has not been initiated yet in uMCTL2 Value After Reset: 0x0 Exists: Always 5 1 read-only ZQ_CALIB_SHORT_BUSY Description: SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQCS request. It goes low when the ZQCS operation is initiated in uMCTL2. It is recommended not to perform ZQCS operations when this signal is high. 0 - Indicates that the SoC core can initiate a ZQCS operation 1 - Indicates that ZQCS operation has not been initiated yet in uMCTL2 Value After Reset: 0x0 Exists: MEMC_DDR3_OR_4_OR_LPDDR2==1 4 1 read-only RANK1_REFRESH_BUSY Description: SoC core may initiate a rank1_refresh operation (refresh operation to rank 1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh is set to one. It goes low when the rank1_refresh operation is stored in uMCTL2. It is recommended not to perform rank1_refresh operations when this signal is high. 0 - Indicates that the SoC core can initiate a rank1_refresh operation 1 - Indicates that rank1_refresh operation has not been stored yet in uMCTL2 Value After Reset: 0x0 Exists: MEMC_NUM_RANKS>1 1 1 read-only RANK0_REFRESH_BUSY Description: SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in uMCTL2. It is recommended not to perform rank0_refresh operations when this signal is high. 0 - Indicates that the SoC core can initiate a rank0_refresh operation 1 - Indicates that rank0_refresh operation has not been stored yet in uMCTL2 Value After Reset: 0x0 Exists: Always 0 1 read-only PSTAT Description: Port Status Register 0x3fc 32 0x00000000 0xFFFFFFFF WR_PORT_BUSY_15 Description: Indicates if there are outstanding writes for port 15. Value After Reset: 0x0 Exists: UMCTL2_PORT_15==1 31 1 read-only WR_PORT_BUSY_14 Description: Indicates if there are outstanding writes for port 14. Value After Reset: 0x0 Exists: UMCTL2_PORT_14==1 30 1 read-only WR_PORT_BUSY_13 Description: Indicates if there are outstanding writes for port 13. Value After Reset: 0x0 Exists: UMCTL2_PORT_13==1 29 1 read-only WR_PORT_BUSY_12 Description: Indicates if there are outstanding writes for port 12. Value After Reset: 0x0 Exists: UMCTL2_PORT_12==1 28 1 read-only WR_PORT_BUSY_11 Description: Indicates if there are outstanding writes for port 11. Value After Reset: 0x0 Exists: UMCTL2_PORT_11==1 27 1 read-only WR_PORT_BUSY_10 Description: Indicates if there are outstanding writes for port 10. Value After Reset: 0x0 Exists: UMCTL2_PORT_10==1 26 1 read-only WR_PORT_BUSY_9 Description: Indicates if there are outstanding writes for port 9. Value After Reset: 0x0 Exists: UMCTL2_PORT_9==1 25 1 read-only WR_PORT_BUSY_8 Description: Indicates if there are outstanding writes for port 8. Value After Reset: 0x0 Exists: UMCTL2_PORT_8==1 24 1 read-only WR_PORT_BUSY_7 Description: Indicates if there are outstanding writes for port 7. Value After Reset: 0x0 Exists: UMCTL2_PORT_7==1 23 1 read-only WR_PORT_BUSY_6 Description: Indicates if there are outstanding writes for port 6. Value After Reset: 0x0 Exists: UMCTL2_PORT_6==1 22 1 read-only WR_PORT_BUSY_5 Description: Indicates if there are outstanding writes for port 5. Value After Reset: 0x0 Exists: UMCTL2_PORT_5==1 21 1 read-only WR_PORT_BUSY_4 Description: Indicates if there are outstanding writes for port 4. Value After Reset: 0x0 Exists: UMCTL2_PORT_4==1 20 1 read-only WR_PORT_BUSY_3 Description: Indicates if there are outstanding writes for port 3. Value After Reset: 0x0 Exists: UMCTL2_PORT_3==1 19 1 read-only WR_PORT_BUSY_2 Description: Indicates if there are outstanding writes for port 2. Value After Reset: 0x0 Exists: UMCTL2_PORT_2==1 18 1 read-only WR_PORT_BUSY_1 Description: Indicates if there are outstanding writes for port 1. Value After Reset: 0x0 Exists: UMCTL2_PORT_1==1 17 1 read-only WR_PORT_BUSY_0 Description: Indicates if there are outstanding writes for port 0. Value After Reset: 0x0 Exists: UMCTL2_PORT_0==1 16 1 read-only RD_PORT_BUSY_15 Description: Indicates if there are outstanding reads for port 15. Value After Reset: 0x0 Exists: UMCTL2_PORT_15==1 15 1 read-only RD_PORT_BUSY_14 Description: Indicates if there are outstanding reads for port 14. Value After Reset: 0x0 Exists: UMCTL2_PORT_14==1 14 1 read-only RD_PORT_BUSY_13 Description: Indicates if there are outstanding reads for port 13. Value After Reset: 0x0 Exists: UMCTL2_PORT_13==1 13 1 read-only RD_PORT_BUSY_12 Description: Indicates if there are outstanding reads for port 12. Value After Reset: 0x0 Exists: UMCTL2_PORT_12==1 12 1 read-only RD_PORT_BUSY_11 Description: Indicates if there are outstanding reads for port 11. Value After Reset: 0x0 Exists: UMCTL2_PORT_11==1 11 1 read-only RD_PORT_BUSY_10 Description: Indicates if there are outstanding reads for port 10. Value After Reset: 0x0 Exists: UMCTL2_PORT_10==1 10 1 read-only RD_PORT_BUSY_9 Description: Indicates if there are outstanding reads for port 9. Value After Reset: 0x0 Exists: UMCTL2_PORT_9==1 9 1 read-only RD_PORT_BUSY_8 Description: Indicates if there are outstanding reads for port 8. Value After Reset: 0x0 Exists: UMCTL2_PORT_8==1 8 1 read-only RD_PORT_BUSY_7 Description: Indicates if there are outstanding reads for port 7. Value After Reset: 0x0 Exists: UMCTL2_PORT_7==1 7 1 read-only RD_PORT_BUSY_6 Description: Indicates if there are outstanding reads for port 6. Value After Reset: 0x0 Exists: UMCTL2_PORT_6==1 6 1 read-only RD_PORT_BUSY_5 Description: Indicates if there are outstanding reads for port 5. Value After Reset: 0x0 Exists: UMCTL2_PORT_5==1 5 1 read-only RD_PORT_BUSY_4 Description: Indicates if there are outstanding reads for port 4. Value After Reset: 0x0 Exists: UMCTL2_PORT_4==1 4 1 read-only RD_PORT_BUSY_3 Description: Indicates if there are outstanding reads for port 3. Value After Reset: 0x0 Exists: UMCTL2_PORT_3==1 3 1 read-only RD_PORT_BUSY_2 Description: Indicates if there are outstanding reads for port 2. Value After Reset: 0x0 Exists: UMCTL2_PORT_2==1 2 1 read-only RD_PORT_BUSY_1 Description: Indicates if there are outstanding reads for port 1. Value After Reset: 0x0 Exists: UMCTL2_PORT_1==1 1 1 read-only RD_PORT_BUSY_0 Description: Indicates if there are outstanding reads for port 0. Value After Reset: 0x0 Exists: UMCTL2_PORT_0==1 0 1 read-only PCCFG Description: Port Common Configuration Register 0x400 32 0x00000000 0x00000011 PAGEMATCH_LIMIT Description: Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. Value After Reset: 0x0 Exists: Always 4 1 read-write GO2CRITICAL_EN Description: If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_rd signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_rd signals at DDRC are driven to 1b'0. Value After Reset: 0x0 Exists: Always 0 1 read-write 16 0xb0 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 PCFG[%s] no description available 0x404 R Description: Port n Configuration Read Register 0x0 32 0x00004000 0x000073FF RD_PORT_PAGEMATCH_EN Description: If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (i.e. same bank and same row). See also related PCCFG.pagematch_limit register. Value After Reset: "(MEMC_DDR4_EN==1) ? 0x0 : 0x1" Exists: Always 14 1 read-write RD_PORT_URGENT_EN Description: If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_rd signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). Value After Reset: 0x0 Exists: Always 13 1 read-write RD_PORT_AGING_EN Description: If set to 1, enables aging function for the read channel of the port. Value After Reset: 0x0 Exists: Always 12 1 read-write RD_PORT_PRIORITY Description: Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: The two LSBs of this register field are tied internally to 2'b00. Value After Reset: 0x0 Exists: Always 0 10 read-write W Description: Port n Configuration Write Register 0x4 32 0x00004000 0x000073FF WR_PORT_PAGEMATCH_EN Description: If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (i.e. same bank and same row). See also related PCCFG.pagematch_limit register. Value After Reset: 0x1 Exists: Always 14 1 read-write WR_PORT_URGENT_EN Description: If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). Value After Reset: 0x0 Exists: Always 13 1 read-write WR_PORT_AGING_EN Description: If set to 1, enables aging function for the write channel of the port. Value After Reset: 0x0 Exists: Always 12 1 read-write WR_PORT_PRIORITY Description: Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port's priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. Note: The two LSBs of this register field are tied internally to 2'b00. Value After Reset: 0x0 Exists: Always 0 10 read-write C Description: Port n Common Configuration Register 0x8 32 0x00000000 0x00000003 AHB_ENDIANNESS Description: If set to 0, enables support for little endian on the AHB port. If set to 1, enables support for big endian (BE- 32) on the AHB port. If set to 2, enables support for big endian (BE-A) on the AHB port. Value After Reset: 0x0 Exists: UMCTL2_A_AHB_n==1 0 2 read-write 16 0x8 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 ID[%s] no description available 0xc MASKCH Description: Port n Channel m Configuration ID Mask Register 0x0 32 0x00000000 0xFFFFFFFF ID_MASK Description: Determines the mask used in the ID mapping function for virtual channel m. Value After Reset: 0x0 Exists: Always 0 32 read-write VALUECH Description: Port n Channel m Configuration ID Value Register 0x4 32 0x00000000 0xFFFFFFFF ID_VALUE Description: Determines the value used in the ID mapping function for virtual channel m. Value After Reset: 0x0 Exists: Always 0 32 read-write CTRL Description: Port n Control Register 0x8c 32 0x00000000 0x00000001 PORT_EN Description: Enables port n. Value After Reset: "UMCTL2_PORT_EN_RESET_VALUE" Exists: Always 0 1 read-write QOS0 Description: Port n Read QoS Configuration Register 0 0x90 32 0x00000000 0x0033000F RQOS_MAP_REGION1 Description: This bitfield indicates the traffic class of region 1. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR) then VPR traffic is aliased to LPR traffic. Value After Reset: 0x0 Exists: Always 20 2 read-write RQOS_MAP_REGION0 Description: This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR) then VPR traffic is aliased to LPR traffic. Value After Reset: 0x0 Exists: Always 16 2 read-write RQOS_MAP_LEVEL1 Description: Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13(for dual RAQ) or 0 to 14(for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinct values. Value After Reset: 0x0 Exists: Always 0 4 read-write QOS1 Description: Port n Read QoS Configuration Register 1 0x94 32 0x00000000 0x07FF07FF RQOS_MAP_TIMEOUTR Description: Specifies the timeout value for transactions mapped to the red address queue. Value After Reset: 0x0 Exists: Always 16 11 read-write RQOS_MAP_TIMEOUTB Description: Specifies the timeout value for transactions mapped to the blue address queue. Value After Reset: 0x0 Exists: Always 0 11 read-write WQOS0 Description: Port n Write QoS Configuration Register 0 0x98 32 0x00000000 0x0033000F WQOS_MAP_REGION1 Description: This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW 1: VPW When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW) then VPW traffic is aliased to NPW traffic. Value After Reset: 0x0 Exists: Always 20 2 read-write WQOS_MAP_REGION0 Description: This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW 1: VPW When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region0 is set to 1 (VPW) then VPW traffic is aliased to NPW traffic. Value After Reset: 0x0 Exists: Always 16 2 read-write WQOS_MAP_LEVEL Description: Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which corresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. Value After Reset: 0x0 Exists: Always 0 4 read-write WQOS1 Description: Port n Write QoS Configuration Register 1 0x9c 32 0x00000000 0x000007FF WQOS_MAP_TIMEOUT Description: Specifies the timeout value for write transactions. Value After Reset: 0x0 Exists: Always 0 11 read-write 4 0x8 0,1,2,3 SAR[%s] no description available 0xf04 BASE Description: SAR Base Address Register n 0x0 32 0x00000000 0xFFFFFFFF BASE_ADDR Description: Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). Value After Reset: 0x0 Exists: Always 0 32 read-write SIZE Description: SAR Size Register n 0x4 32 0x00000000 0x000000FF NBLOCKS Description: Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block size as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. Value After Reset: 0x0 Exists: Always 0 8 read-write SBRCTL Description: Scrubber Control Register 0xf24 32 0x0000FF10 0x001FFF77 SCRUB_INTERVAL Description: Scrub interval. (512 x scrub_interval) number of clock cycles between two scrub read commands. If set to 0, scrub commands are issued back-to-back. This mode of operation (scrub_interval=0) can typically be used for scrubbing the full range of memory at once before or after SW controlled low power operations. After completing the full range of scrub while scrub_interval=0, scrub_done register is set and sbr_done_intr interrupt signal is asserted. Value After Reset: 0xff Exists: UMCTL2_SBR_EN_1==1 8 13 read-write SCRUB_BURST Description: Scrub burst count. Determines the number of back-to-back scrub read commands that can be issued together when the controller is in one of the HW controlled low power modes. During low power, the period of the scrub burst becomes \"scrub_burst*scrub_interval\" cycles. During normal operation mode of the controller (ie. not in power-down or self refresh), scrub_burst is ignored and only one scrub command is generated. Valid values are: 1: 1 read, 2: 4 reads, 3: 16 reads, 4: 64 reads, 5: 256 reads, 6: 1024 reads. Value After Reset: 0x1 Exists: UMCTL2_SBR_EN_1==1 4 3 read-write SCRUB_MODE Description: scrub_mode:0 ECC scrubber will perform reads scrub_mode:1 ECC scrubber will perform writes Value After Reset: 0x0 Exists: UMCTL2_SBR_EN_1==1 2 1 read-write SCRUB_DURING_LOWPOWER Description: Continue scrubbing during low power. If set to 1, burst of scrubs will be issued in HW controlled low power modes. There are two such modes: automatically initiated by idleness or initiated by HW low-power (LP) interface. If set to 0, the scrubber will not attempt to send commands while the DDRC is in HW controlled low power modes. In this case, the scrubber will remember the last address issued and will automatically continue from there when the DDRC exits the LP mode. Value After Reset: 0x0 Exists: UMCTL2_SBR_EN_1==1 1 1 read-write SCRUB_EN Description: Enable ECC scrubber. If set to 1, enables the scrubber to generate background read commands after the memories are initialized. If set to 0, disables the scrubber, resets the address generator to 0 and clears the scrubber status. This bitfield must be accessed separately from the other bitfields in this register. Value After Reset: 0x0 Exists: UMCTL2_SBR_EN_1==1 0 1 read-write SBRSTAT Description: Scrubber Status Register 0xf28 32 0x00000000 0x00000003 SCRUB_DONE Description: Scrubber done. Controller sets this bit to 1, after full range of addresses are scrubbed once while scrub_interval is set to 0. Cleared if scrub_en is set to 0 (scrubber disabled) or scrub_interval is set to a non-zero value for normal scrub operation. The interrupt signal, sbr_done_intr, is equivalent to this status bitfield. Value After Reset: 0x0 Exists: UMCTL2_SBR_EN_1==1 1 1 read-only SCRUB_BUSY Description: Scrubber busy. Controller sets this bit to 1 when the scrubber logic has outstanding read commands being executed. Cleared when there are no active outstanding scrub reads in the system. Value After Reset: 0x0 Exists: UMCTL2_SBR_EN_1==1 0 1 read-only SBRWDATA0 Description: Scrubber Write Data Pattern0 0xf2c 32 0x00000000 0xFFFFFFFF SCRUB_PATTERN0 Description: ECC Scrubber write data pattern for data bus[31:0] Value After Reset: 0x0 Exists: UMCTL2_SBR_EN_1==1 0 32 read-write FFA FFA FFA 0xf3018000 0x0 0x48 registers CTRL No description available 0x0 32 0x00000000 0x80000001 SFTRST software reset the module if asserted to be 1. EN is only active after this bit is zero. 31 1 read-write EN Asserted to enable the module 0 1 read-write STATUS No description available 0x4 32 0x00000000 0x000000FF FIR_OV FIR Overflow err 7 1 write-only FFT_OV FFT Overflow Err 6 1 write-only WR_ERR AXI Data Write Error 5 1 write-only RD_NXT_ERR AXI Read Bus Error for NXT DATA 4 1 write-only RD_ERR AXI Data Read Error 3 1 write-only NXT_CMD_RD_DONE Indicate that next command sequence is already read into the module. 1 1 write-only OP_CMD_DONE Indicate that operation cmd is done, and data are available in system memory. 0 1 write-only INT_EN No description available 0x8 32 0x00000000 0xFFFFFFFF WRSV1 Reserved 8 24 read-write FIR_OV FIR Overflow err 7 1 read-write FFT_OV FFT Overflow Err 6 1 read-write WR_ERR Enable Data Write Error interrupt 5 1 read-write RD_NXT_ERR Enable Read Bus Error for NXT DATA interrupt 4 1 read-write RD_ERR Enable Data Read Error interrupt 3 1 read-write NXT_CMD_RD_DONE Indicate that next command sequence is already read into the module. 1 1 read-write OP_CMD_DONE Indicate that operation cmd is done, and data are available in system memory. 0 1 read-write OP_CTRL No description available 0x20 32 0x00000000 0xFFFFFFFF NXT_ADDR The address for the next command. It will be processed after CUR_CMD is executed and done.. 2 30 read-write NXT_EN Whether NXT_CMD is enabled. Asserted to enable the NXT_CMD when CUR_CMD is done, or CUR_CMD is not enabled.. 1 1 read-write EN Whether CUR_CMD is enabled. Asserted to enable the CUR_CMD 0 1 read-write OP_CMD No description available 0x24 32 0x00000000 0x01FFFEFF CONJ_C asserted to have conjuate value for coefs in computation 24 1 read-write CMD The Command Used: 0: FIR 2: FFT Others: Reserved 18 6 read-write OUTD_TYPE Output data type: 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 4:complex sp float 5: real sp float 15 3 read-write COEF_TYPE Coef data type (used for FIR): 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 4:complex sp float 5: real sp float 12 3 read-write IND_TYPE Input data type: 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 4:complex sp float 5: real sp float 9 3 read-write NXT_CMD_LEN The length of nxt commands in 32-bit words 0 8 read-write OP_REG0 No description available UNION_28 0x28 32 0x00000000 0xFFFFFFFF CT Contents 0 32 read-write OP_FIR_MISC No description available UNION_28 0x28 32 0x00000000 0x00003FFF FIR_COEF_TAPS Length of FIR coefs （max 256） 0 14 read-write OP_FFT_MISC No description available UNION_28 0x28 32 0x00000000 0x000007FF FFT_LEN FFT length 0:8, ..., n:2^(3+n) 7 4 read-write IFFT Asserted to indicate IFFT 6 1 read-write TMP_BLK Memory block for indata. Should be assigned as 1 2 2 read-write IND_BLK Memory block for indata. Should be assigned as 0 0 2 read-write OP_REG1 No description available UNION_2C 0x2c 32 0x00000000 0xFFFFFFFF CT Contents 0 32 read-write OP_FIR_MISC1 No description available UNION_2C 0x2c 32 0x00000000 0x003FFFFF OUTD_MEM_BLK Should be assigned as 0 20 2 read-write COEF_MEM_BLK Should be assigned as 1 18 2 read-write IND_MEM_BLK Should be assigned as 2 16 2 read-write FIR_DATA_TAPS The input data data length 0 16 read-write OP_REG2 No description available UNION_30 0x30 32 0x00000000 0xFFFFFFFF CT Contents 0 32 read-write OP_FFT_INRBUF No description available UNION_30 0x30 32 0x00000000 0xFFFFFFFF LOC The input (real) data buffer pointer 0 32 read-write OP_REG3 No description available UNION_34 0x34 32 0x00000000 0xFFFFFFFF CT Contents 0 32 read-write OP_FIR_INBUF No description available UNION_34 0x34 32 0x00000000 0xFFFFFFFF LOC The input data buffer pointer 0 32 read-write OP_REG4 No description available UNION_38 0x38 32 0x00000000 0xFFFFFFFF CT Contents 0 32 read-write OP_FIR_COEFBUF No description available UNION_38 0x38 32 0x00000000 0xFFFFFFFF LOC The coef buf pointer 0 32 read-write OP_FFT_OUTRBUF No description available UNION_38 0x38 32 0x00000000 0xFFFFFFFF LOC The output (real) data buffer pointer 0 32 read-write OP_REG5 No description available UNION_3C 0x3c 32 0x00000000 0xFFFFFFFF CT Contents 0 32 read-write OP_FIR_OUTBUF No description available UNION_3C 0x3c 32 0x00000000 0xFFFFFFFF LOC The output data buffer pointer. The length of the output buffer should be （FIR_DATA_TAPS - FIR_COEF_TAPS + 1） 0 32 read-write OP_REG6 No description available 0x40 32 0x00000000 0xFFFFFFFF CT Contents 0 32 read-write OP_REG7 No description available 0x44 32 0x00000000 0xFFFFFFFF CT Contents 0 32 read-write SDP SDP SDP 0xf3040000 0x0 0x60 registers SDPCR SDP control register 0x0 32 0x30000000 0xFFFE0101 SFTRST soft reset. Write 1 then 0, to reset the SDP block. 31 1 read-write CLKGAT Clock Gate for the SDP main logic. Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. 30 1 read-write CIPDIS Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. 1, Cipher is disabled in this chip. 0, Cipher is enabled in this chip. 29 1 read-only HASDIS HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. 1, HASH is disabled in this chip. 0, HASH is enabled in this chip. 28 1 read-only CIPHEN Cipher Enablement, controlled by SW. 1, Cipher is Enabled. 0, Cipher is Disabled. 23 1 read-write HASHEN HASH Enablement, controlled by SW. 1, HASH is Enabled. 0, HASH is Disabled. 22 1 read-write MCPEN Memory Copy Enablement, controlled by SW. 1, Memory copy is Enabled. 0, Memory copy is Disabled. 21 1 read-write CONFEN Constant Fill to memory, controlled by SW. 1, Constant fill is Enabled. 0, Constant fill is Disabled. 20 1 read-write DCRPDI Decryption Disable bit, Write to 1 to disable the decryption. 19 1 read-write TSTPKT0IRQ Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. 17 1 read-write RDSCEN when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) 8 1 read-write INTEN Interrupt Enablement, controlled by SW. 1, SDP interrupt is enabled. 0, SDP interrupt is disabled. 0 1 read-write MODCTRL Mod control register. 0x4 32 0x00000000 0xFFFFFFFF AESALG AES algorithem selection. 0x0 = AES 128; 0x1 = AES 256; 0x8 = SM4； Others, reserved. 28 4 read-write AESMOD AES mode selection. 0x0 = ECB; 0x1 = CBC; Others, reserved. 24 4 read-write AESKS AES Key Selection. These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: 0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. 0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. .... 0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. 0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. 0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. 0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. 0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. 0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. 0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. 0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. 0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. 0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. 0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. 0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. 0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. 0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. Other values, reserved. 18 6 read-write AESDIR AES direction 1x1, AES Decryption 1x0, AES Encryption. 16 1 read-write HASALG HASH Algorithem selection. 0x0 SHA1 — 0x1 CRC32 — 0x2 SHA256 — 12 4 read-write CRCEN CRC enable. 1x1, CRC is enabled. 1x0, CRC is disabled. 11 1 read-write HASCHK HASH Check Enable Bit. 1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; 1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. 10 1 read-write HASOUT When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. 0 INPUT HASH 1 OUTPUT HASH 9 1 read-write DINSWP Decide whether the SDP byteswaps the input data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format 4 2 read-write DOUTSWP Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format 2 2 read-write KEYSWP Decide whether the SDP byteswaps the Key (big-endian data). When all bits are set, the data is assumed to be in the big-endian format 0 2 read-write PKTCNT packet counter registers. 0x8 32 0x00000000 0xFFFFFFFF CNTVAL This read-only field shows the current (instantaneous) value of the packet counter 16 8 read-only CNTINCR The value written to this field is added to the spacket count. 0 8 read-write STA Status Registers 0xc 32 0x00000000 0xFFFFFFFF TAG packet tag. 24 8 read-only IRQ interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. 23 1 write-only CHN1PKT0 the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. 20 1 write-only AESBSY AES Busy 19 1 read-only HASBSY Hashing Busy 18 1 read-only PKTCNT0 Packet Counter registers reachs to ZERO now. 17 1 write-only PKTDON Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. 16 1 write-only ERRSET Working mode setup error. 5 1 write-only ERRPKT Packet head access error, or status update error. 4 1 write-only ERRSRC Source Buffer Access Error 3 1 write-only ERRDST Destination Buffer Error 2 1 write-only ERRHAS Hashing Check Error 1 1 write-only ERRCHAIN buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. 0 1 write-only KEYADDR Key Address 0x10 32 0x00000040 0xFFFFFFFF INDEX To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. Key index pointer. The valid indices are 0-[number_keys]. In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. 16 8 read-write SUBWRD Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field increments; To write a key, the software must first write the desired key index/subword to this register. 0 2 read-write KEYDAT Key Data 0x14 32 0x00000030 0xFFFFFFFF KEYDAT This register provides the write access to the key/key subword specified by the key index register. Writing this location updates the selected subword for the key located at the index specified by the key index register. The write also triggers the SUBWORD field of the KEY register to increment to the next higher word in the key 0 32 read-write 4 0x4 CIPHIV0,CIPHIV1,CIPHIV2,CIPHIV3 CIPHIV[%s] no description available 0x18 32 0x00000000 0xFFFFFFFF CIPHIV cipher initialization vector. 0 32 read-write 8 0x4 HASWRD0,HASWRD1,HASWRD2,HASWRD3,HASWRD4,HASWRD5,HASWRD6,HASWRD7 HASWRD[%s] no description available 0x28 32 0x00000030 0xFFFFFFFF HASWRD Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. 0 32 read-write CMDPTR Command Pointer 0x48 32 0x00000000 0xFFFFFFFF CMDPTR current command addresses the register points to the multiword descriptor that is to be executed (or is currently being executed) 0 32 read-write NPKTPTR Next Packet Address Pointer 0x4c 32 0x00000000 0xFFFFFFFF NPKTPTR Next Packet Address Pointer 0 32 read-write PKTCTL Packet Control Registers 0x50 32 0x00000000 0xFFFFFFFF PKTTAG packet tag 24 8 read-write CIPHIV Load Initial Vector for the AES in this packet. 6 1 read-write HASFNL Hash Termination packet 5 1 read-write HASINI Hash Initialization packat 4 1 read-write CHAIN whether the next command pointer register must be loaded into the channel's current descriptor pointer. 3 1 read-write DCRSEMA whether the channel's semaphore must be decremented at the end of the current operation. When the semaphore reaches a value of zero, no more operations are issued from the channel. 2 1 read-write PKTINT Reflects whether the channel must issue an interrupt upon the completion of the packet 1 1 read-write PKTSRC Packet Memory Source Address 0x54 32 0x00000000 0xFFFFFFFF PKTSRC Packet Memory Source Address 0 32 read-write PKTDST Packet Memory Destination Address 0x58 32 0x00000000 0xFFFFFFFF PKTDST Packet Memory Destination Address 0 32 read-write PKTBUF Packet buffer size. 0x5c 32 0x00000000 0xFFFFFFFF PKTBUF No description available 0 32 read-write SEC SEC SEC 0xf3044000 0x0 0x18 registers SECURE_STATE Secure state 0x0 32 0x00000000 0x000300F0 ALLOW_NSC Non-secure state allow 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state 1: system is healthy to enter non-secure state 17 1 read-only ALLOW_SEC Secure state allow 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state 1: system is healthy to enter secure state 16 1 read-only PMIC_FAIL PMIC secure state one hot indicator 0: secure state is not in fail state 1: secure state is in fail state 7 1 read-write PMIC_NSC PMIC secure state one hot indicator 0: secure state is not in non-secure state 1: secure state is in non-secure state 6 1 read-write PMIC_SEC PMIC secure state one hot indicator 0: secure state is not in secure state 1: secure state is in secure state 5 1 read-write PMIC_INS PMIC secure state one hot indicator 0: secure state is not in inspect state 1: secure state is in inspect state 4 1 read-write SECURE_STATE_CONFIG secure state configuration 0x4 32 0x00000000 0x00000009 LOCK Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset 0: not locked, register can be modified 1: register locked, write access to the register is ignored 3 1 read-write ALLOW_RESTART allow secure state restart from fail state 0: restart is not allowed, only hardware reset can recover secure state 1: software is allowed to switch to inspect state from fail state 0 1 read-write VIOLATION_CONFIG Security violation config 0x8 32 0x00000000 0xFFFFFFFF LOCK_NSC Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored 31 1 read-write NSC_VIO_CFG configuration of non-secure state violations, each bit represents one security event 0: event is not a security violation 1: event is a security violation 16 15 read-write LOCK_SEC Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored 15 1 read-write SEC_VIO_CFG configuration of secure state violations, each bit represents one security event 0: event is not a security violation 1: event is a security violation 0 15 read-write ESCALATE_CONFIG Escalate behavior on security event 0xc 32 0x00000000 0xFFFFFFFF LOCK_NSC Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored 31 1 read-write NSC_VIO_CFG configuration of non-secure state escalates, each bit represents one security event 0: event is not a security escalate 1: event is a security escalate 16 15 read-write LOCK_SEC Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored 15 1 read-write SEC_VIO_CFG configuration of secure state escalates, each bit represents one security event 0: event is not a security escalate 1: event is a security escalate 0 15 read-write EVENT Event and escalate status 0x10 32 0x00000000 0xFFFF000C EVENT local event statue, each bit represents one security event 16 16 read-only PMIC_ESC_NSC PMIC is escalating non-secure event 3 1 read-only PMIC_ESC_SEC PMIC is escalting secure event 2 1 read-only LIFECYCLE Lifecycle 0x14 32 0x00000000 0x000000FF LIFECYCLE lifecycle status, bit7: lifecycle_debate, bit6: lifecycle_scribe, bit5: lifecycle_no_ret, bit4: lifecycle_return, bit3: lifecycle_secure, bit2: lifecycle_nonsec, bit1: lifecycle_create, bit0: lifecycle_unknow 0 8 read-only MON MON MON 0xf3048000 0x0 0x48 registers 4 0x8 glitch0,glitch1,clock0,clock1 MONITOR[%s] no description available 0x0 CONTROL Glitch and clock monitor control 0x0 32 0x00000000 0x00000011 ACTIVE select glitch works in active mode or passve mode. 0: passive mode, depends on power glitch destroy DFF value 1: active mode, check glitch by DFF chain 4 1 read-write ENABLE enable glitch detector 0: detector disabled 1: detector enabled 0 1 read-write STATUS Glitch and clock monitor status 0x4 32 0x00000000 0x00000001 FLAG flag for glitch detected, write 1 to clear this flag 0: glitch not detected 1: glitch detected 0 1 read-write IRQ_FLAG No description available 0x40 32 0x00000000 0x0000000F FLAG interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag 0: no monitor interrupt 1: monitor interrupt happened 0 4 read-write IRQ_ENABLE No description available 0x44 32 0x00000000 0x0000000F ENABLE interrupt enable, each bit represents for one monitor 0: monitor interrupt disabled 1: monitor interrupt enabled 0 4 read-write RNG RNG RNG 0xf304c000 0x0 0x40 registers CMD Command Register 0x0 32 0x00000000 0xFFFFFFFF SFTRST Soft Reset, Perform a software reset of the RNG This bit is self-clearing. 0 Do not perform a software reset. 1 Software reset 6 1 read-write CLRERR Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. 0 Do not clear the errors and the interrupt. 1 Clear the errors and the interrupt. 5 1 read-write CLRINT Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. 0 Do not clear the interrupt. 1 Clear the interrupt 4 1 read-write GENSD Generate Seed, when both ST and GS triggered, ST first and GS next. 1 1 read-write SLFCHK Self Test, when both ST and GS triggered, ST first and GS next. 0 1 read-write CTRL Control Register 0x4 32 0x00000000 0xFFFFFFFF MIRQERR Mask Interrupt Request for Error 6 1 read-write MIRQDN Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: • Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). • Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. 5 1 read-write AUTRSD Auto Reseed 4 1 read-write FUFMOD FIFO underflow response mode 00 Return all zeros and set the ESR[FUFE]. 01 Return all zeros and set the ESR[FUFE]. 10 Generate the bus transfer error 11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). 0 2 read-write STA Status Register 0x8 32 0x00000000 0xFFFFFFFF SCPF Self Check Pass Fail 21 3 read-only FUNCERR Error was detected, check ESR register for details 16 1 read-only FSIZE Fifo Size, it is 5 in this design. 12 4 read-only FRNNU Fifo Level, Indicates the number of random words currently in the output FIFO 8 4 read-only NSDDN New seed done. 6 1 read-only FSDDN 1st Seed done When "1", Indicates that the RNG generated the first seed. 5 1 read-only SCDN Self Check Done Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is initiated by setting the CMD[ST]. 0 Self test not completed 1 Completed a self test since the last reset. 4 1 read-only RSDREQ Reseed needed Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or automatically if the CTRL[ARS] is set. 3 1 read-only IDLE Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. 2 1 read-only BUSY when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. 1 1 read-only ERR Error Registers 0xc 32 0x00000000 0xFFFFFF3F FUFE FIFO access error(underflow) 5 1 read-only SCKERR Self-test error Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a hardware reset or by writing 1 to the CMD[CE] 3 1 read-only FO2B FIFO out to bus/cpu 0x10 32 0x00000000 0xFFFFFFFF FO2B SW read the FIFO output. 0 32 read-only 8 0x4 FO2S0,FO2S1,FO2S2,FO2S3,FO2S4,FO2S5,FO2S6,FO2S7 R2SK[%s] no description available 0x20 32 0x00000000 0xFFFFFFFF FO2S0 FIFO out to KMAN, will be SDP engine key. 0 32 read-only OTP OTP OTP 0xf3050000 0x0 0xc08 registers 128 0x4 SHADOW000,SHADOW001,SHADOW002,SHADOW003,SHADOW004,SHADOW005,SHADOW006,SHADOW007,SHADOW008,SHADOW009,SHADOW010,SHADOW011,SHADOW012,SHADOW013,SHADOW014,SHADOW015,SHADOW016,SHADOW017,SHADOW018,SHADOW019,SHADOW020,SHADOW021,SHADOW022,SHADOW023,SHADOW024,SHADOW025,SHADOW026,SHADOW027,SHADOW028,SHADOW029,SHADOW030,SHADOW031,SHADOW032,SHADOW033,SHADOW034,SHADOW035,SHADOW036,SHADOW037,SHADOW038,SHADOW039,SHADOW040,SHADOW041,SHADOW042,SHADOW043,SHADOW044,SHADOW045,SHADOW046,SHADOW047,SHADOW048,SHADOW049,SHADOW050,SHADOW051,SHADOW052,SHADOW053,SHADOW054,SHADOW055,SHADOW056,SHADOW057,SHADOW058,SHADOW059,SHADOW060,SHADOW061,SHADOW062,SHADOW063,SHADOW064,SHADOW065,SHADOW066,SHADOW067,SHADOW068,SHADOW069,SHADOW070,SHADOW071,SHADOW072,SHADOW073,SHADOW074,SHADOW075,SHADOW076,SHADOW077,SHADOW078,SHADOW079,SHADOW080,SHADOW081,SHADOW082,SHADOW083,SHADOW084,SHADOW085,SHADOW086,SHADOW087,SHADOW088,SHADOW089,SHADOW090,SHADOW091,SHADOW092,SHADOW093,SHADOW094,SHADOW095,SHADOW096,SHADOW097,SHADOW098,SHADOW099,SHADOW100,SHADOW101,SHADOW102,SHADOW103,SHADOW104,SHADOW105,SHADOW106,SHADOW107,SHADOW108,SHADOW109,SHADOW110,SHADOW111,SHADOW112,SHADOW113,SHADOW114,SHADOW115,SHADOW116,SHADOW117,SHADOW118,SHADOW119,SHADOW120,SHADOW121,SHADOW122,SHADOW123,SHADOW124,SHADOW125,SHADOW126,SHADOW127 SHADOW[%s] no description available 0x0 32 0x00000000 0xFFFFFFFF SHADOW shadow register of fuse for pmic area for PMIC, index valid for 0-15, for SOC index valid for 16-128 0 32 read-write 8 0x4 LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 SHADOW_LOCK[%s] no description available 0x200 32 0x00000000 0xFFFFFFFF LOCK lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types 00: not locked 01: soft locked 10: not locked, and cannot lock in furture 11: double locked 0 32 read-write 128 0x4 FUSE000,FUSE001,FUSE002,FUSE003,FUSE004,FUSE005,FUSE006,FUSE007,FUSE008,FUSE009,FUSE010,FUSE011,FUSE012,FUSE013,FUSE014,FUSE015,FUSE016,FUSE017,FUSE018,FUSE019,FUSE020,FUSE021,FUSE022,FUSE023,FUSE024,FUSE025,FUSE026,FUSE027,FUSE028,FUSE029,FUSE030,FUSE031,FUSE032,FUSE033,FUSE034,FUSE035,FUSE036,FUSE037,FUSE038,FUSE039,FUSE040,FUSE041,FUSE042,FUSE043,FUSE044,FUSE045,FUSE046,FUSE047,FUSE048,FUSE049,FUSE050,FUSE051,FUSE052,FUSE053,FUSE054,FUSE055,FUSE056,FUSE057,FUSE058,FUSE059,FUSE060,FUSE061,FUSE062,FUSE063,FUSE064,FUSE065,FUSE066,FUSE067,FUSE068,FUSE069,FUSE070,FUSE071,FUSE072,FUSE073,FUSE074,FUSE075,FUSE076,FUSE077,FUSE078,FUSE079,FUSE080,FUSE081,FUSE082,FUSE083,FUSE084,FUSE085,FUSE086,FUSE087,FUSE088,FUSE089,FUSE090,FUSE091,FUSE092,FUSE093,FUSE094,FUSE095,FUSE096,FUSE097,FUSE098,FUSE099,FUSE100,FUSE101,FUSE102,FUSE103,FUSE104,FUSE105,FUSE106,FUSE107,FUSE108,FUSE109,FUSE110,FUSE111,FUSE112,FUSE113,FUSE114,FUSE115,FUSE116,FUSE117,FUSE118,FUSE119,FUSE120,FUSE121,FUSE122,FUSE123,FUSE124,FUSE125,FUSE126,FUSE127 FUSE[%s] no description available 0x400 32 0x00000000 0xFFFFFFFF FUSE fuse array, valid in PMIC part only read operation will read out value in fuse array write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) 0 32 read-write 8 0x4 LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 FUSE_LOCK[%s] no description available 0x600 32 0x00000000 0xFFFFFFFF LOCK lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types 00: not locked 01: soft locked 10: not locked, and cannot lock in furture 11: double locked 0 32 read-write UNLOCK UNLOCK 0x800 32 0x00000000 0xFFFFFFFF UNLOCK unlock word for fuse array operation write "OPEN" to unlock fuse array, write any other value will lock write to fuse. Please make sure 24M crystal is running and 2.5V LDO working properly 0 32 read-write DATA DATA 0x804 32 0x00000000 0xFFFFFFFF DATA data register for non-blocking access this register hold dat read from fuse array or data to by programmed to fuse array 0 32 read-write ADDR ADDR 0x808 32 0x00000000 0x0000007F ADDR word address to be read or write 0 7 read-write CMD CMD 0x80c 32 0x00000000 0xFFFFFFFF CMD command to access fure array "BLOW" will update fuse word at ADDR to value hold in DATA "READ" will fetch fuse value in at ADDR to DATA register 0 32 read-write LOAD_REQ LOAD Request 0xa00 32 0x00000007 0x0000000F REQUEST reload request for 4 regions bit0: region0 bit1: region1 bit2: region2 bit3: region3 0 4 read-write LOAD_COMP LOAD complete 0xa04 32 0x00000007 0x0000000F COMPLETE reload complete sign for 4 regions bit0: region 0 bit1: region1 bit2: region2 bit3: region3 0 4 read-write 4 0x4 LOAD_REGION0,LOAD_REGION1,LOAD_REGION2,LOAD_REGION3 REGION[%s] no description available 0xa20 32 0x00000800 0x00007F7F STOP stop address of load region, fuse word at end address will NOT be reloaded region0: fixed at 8 region1: fixed at 16 region2: fixed at 0, region3: usrer configurable 8 7 read-write START start address of load region, fuse word at start address will be reloaded region0: fixed at 0 region1: fixed at 8 region2: fixed at 16, region3: usrer configurable 0 7 read-write INT_FLAG interrupt flag 0xc00 32 0x00000000 0x00000007 WRITE fuse write flag, write 1 to clear 0: fuse is not written or writing 1: value in DATA register is programmed into fuse 2 1 read-write READ fuse read flag, write 1 to clear 0: fuse is not read or reading 1: fuse value is put in DATA register 1 1 read-write LOAD fuse load flag, write 1 to clear 0: fuse is not loaded or loading 1: fuse loaded 0 1 read-write INT_EN interrupt enable 0xc04 32 0x00000000 0x00000007 WRITE fuse write interrupt enable 0: fuse write interrupt is not enable 1: fuse write interrupt is enable 2 1 read-write READ fuse read interrupt enable 0: fuse read interrupt is not enable 1: fuse read interrupt is enable 1 1 read-write LOAD fuse load interrupt enable 0: fuse load interrupt is not enable 1: fuse load interrupt is enable 0 1 read-write KEYM KEYM KEYM 0xf3054000 0x0 0x50 registers 8 0x4 SFK0,SFK1,SFK2,SFK3,SFK4,SFK5,SFK6,SFK7 SOFTMKEY[%s] no description available 0x0 32 0x00000000 0xFFFFFFFF KEY software symmetric key key will be scambled to 4 variants for software to use, and replicable on same chip. scramble keys are chip different, and not replicable on different chip must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 0 32 read-write 8 0x4 SPK0,SPK1,SPK2,SPK3,SPK4,SPK5,SPK6,SPK7 SOFTPKEY[%s] no description available 0x20 32 0x00000000 0xFFFFFFFF KEY software asymmetric key key is derived from scrambles of fuse private key, software input key, SRK, and system security status. This key os read once, sencondary read will read out 0 0 32 read-write SEC_KEY_CTL secure key generation 0x40 32 0x00000000 0x80011117 LOCK_SEC_CTL block secure state key setting being changed 31 1 read-write SK_VAL session key valid 0: session key is all 0's and not usable 1: session key is valid 16 1 read-only SMK_SEL software symmetric key selection 0: use origin value in software symmetric key 1: use scramble version of software symmetric key 12 1 read-write ZMK_SEL batt symmetric key selection 0: use scramble version of software symmetric key 1: use origin value in software symmetric key 8 1 read-write FMK_SEL fuse symmetric key selection 0: use scramble version of fuse symmetric key 1: use alnertave scramble of fuse symmetric key 4 1 read-write KEY_SEL secure symmtric key synthesize setting, key is a XOR of following bit0: fuse mk, 0: not selected, 1:selected bit1: zmk from batt, 0: not selected, 1:selected bit2: software key 0: not selected, 1:selected 0 3 read-write NSC_KEY_CTL non-secure key generation 0x44 32 0x00000000 0x80011117 LOCK_NSC_CTL block non-secure state key setting being changed 31 1 read-write SK_VAL session key valid 0: session key is all 0's and not usable 1: session key is valid 16 1 read-only SMK_SEL software symmetric key selection 0: use scramble version of software symmetric key 1: use origin value in software symmetric key 12 1 read-write ZMK_SEL batt symmetric key selection 0: use scramble version of software symmetric key 1: use origin value in software symmetric key 8 1 read-write FMK_SEL fuse symmetric key selection 0: use scramble version of fuse symmetric key 1: use origin value in fuse symmetric key 4 1 read-write KEY_SEL non-secure symmtric key synthesize setting, key is a XOR of following bit0: fuse mk, 0: not selected, 1:selected bit1: zmk from batt, 0: not selected, 1:selected bit2: software key 0: not selected, 1:selected 0 3 read-write RNG Random number interface behavior 0x48 32 0x00000000 0x00010001 BLOCK_RNG_XOR block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset 0: RNG_XOR can be changed by software 1: RNG_XOR ignore software change from software 16 1 read-write RNG_XOR control how SFK is accepted from random number generator 0: SFK value replaced by random number input 1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG 0 1 read-write READ_CONTROL key read out control 0x4c 32 0x00000000 0x00010001 BLOCK_PK_READ asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset 0: key can be read out 1: key cannot be read out 16 1 read-write BLOCK_SMK_READ symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset 0: key can be read out 1: key cannot be read out 0 1 read-write SYSCTL SYSCTL SYSCTL 0xf4000000 0x0 0x2c00 registers 200 0x4 cpu0,cpx0,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,rsv14,rsv15,rsv16,rsv17,rsv18,rsv19,rsv20,pow_vis,pow_cpu0,pow_gpu,rsv24,rst_soc,rst_con,rst_vis,rst_cpu0,rst_gpu,rsv30,rsv31,clk_src_xtal,clk_src_pll0,clk_src_clk0_pll0,clk_src_pll1,clk_src_clk0_pll1,clk_src_clk1_pll1,clk_src_pll2,clk_src_clk0_pll2,clk_src_clk1_pll2,clk_src_pll3,clk_src_clk0_pll3,clk_src_pll4,clk_src_clk0_pll4,clk_src_pll0_ref,clk_src_pll1_ref,clk_src_pll2_ref,clk_src_pll3_ref,clk_src_pll4_ref,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,clk_top_cpu0,clk_top_mct0,clk_top_gpu0,clk_top_axif,clk_top_axis,clk_top_axic,clk_top_axiv,clk_top_axid,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_can4,clk_top_can5,clk_top_can6,clk_top_can7,clk_top_lin0,clk_top_lin1,clk_top_lin2,clk_top_lin3,clk_top_lin4,clk_top_lin5,clk_top_lin6,clk_top_lin7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_tmr4,clk_top_tmr5,clk_top_tmr6,clk_top_tmr7,clk_top_xpi0,clk_top_xram,clk_top_ana0,clk_top_ana1,clk_top_aud0,clk_top_aud1,clk_top_aud2,clk_top_aud3,clk_top_eth0,clk_top_ptp0,clk_top_sdc0,clk_top_sdc1,clk_top_ntm0,clk_top_ref0,clk_top_ref1,clk_top_cam0,clk_top_cam1,clk_top_lcd0,clk_top_lcd1,clk_top_csi0,clk_top_csi1,clk_top_adc0,clk_top_adc1,clk_top_i2s0,clk_top_i2s1,clk_top_i2s2,clk_top_i2s3,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,axis,axic,axiv,axig,lmm0,mct0,rom0,ddr0,xram,can0,can1,can2,can3,can4,can5,can6,can7,ptpc,crc0,oamp,lin0,lin1,lin2,lin3,lin4,lin5,lin6,lin7,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,urt0,urt1,urt2,urt3,urt4,urt5,urt6,urt7,wdg0,wdg1,mbx0,mbx1,tmr0,tmr1,tmr2,tmr3,tmr4,tmr5,tmr6,tmr7,i2s0,i2s1,i2s2,i2s3,pdm0,dao0,smix,rng0,sdp0,kman,gpio,adc0,adc1,sdm0,hdma,xdma,xpi0,ffa0,tsns,eth0,usb0,sdc0,sdc1,ntm0,ref0,ref1,cam0,cam1,pdma,jpeg,lcd0,lcd1,gwc0,gwc1,csi0,csi1,dsi0,dsi1,lvb0,lcb0,gpu0 RESOURCE[%s] no description available 0x0 32 0x00000000 0xC0000003 GLB_BUSY global busy 0: no changes pending to any nodes 1: any of nodes is changing status 31 1 read-only LOC_BUSY local busy 0: no change is pending for current node 1: current node is changing status 30 1 read-only MODE resource work mode 0:auto turn on and off as system required(recommended) 1:always on 2:always off 3:reserved 0 2 read-write 4 0x10 link0,link1,link2,link3 GROUP0[%s] no description available 0x800 VALUE Group setting 0x0 32 0x00000000 0xFFFFFFFF LINK denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: peripheral is not needed 1: periphera is needed 0 32 read-write SET Group setting 0x4 32 0x00000000 0xFFFFFFFF LINK denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: no effect 1: add periphera into this group，periphera is needed 0 32 read-write CLEAR Group setting 0x8 32 0x00000000 0xFFFFFFFF LINK denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: no effect 1: delete periphera in this group，periphera is not needed 0 32 read-write TOGGLE Group setting 0xc 32 0x00000000 0xFFFFFFFF LINK denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: no effect 1: toggle the result that whether periphera is needed before 0 32 read-write 1 0x10 cpu0 AFFILIATE[%s] no description available 0x900 VALUE Affiliate of Group 0x0 32 0x00000000 0x0000000F LINK Affiliate groups of cpu0, each bit represents a group bit0: cpu0 depends on group0 bit1: cpu0 depends on group1 bit2: cpu0 depends on group2 bit3: cpu0 depends on group3 0 4 read-write SET Affiliate of Group 0x4 32 0x00000000 0x0000000F LINK Affiliate groups of cpu0，each bit represents a group 0: no effect 1: the group is assigned to CPU0 0 4 read-write CLEAR Affiliate of Group 0x8 32 0x00000000 0x0000000F LINK Affiliate groups of cpu0, each bit represents a group 0: no effect 1: the group is not assigned to CPU0 0 4 read-write TOGGLE Affiliate of Group 0xc 32 0x00000000 0x0000000F LINK Affiliate groups of cpu0, each bit represents a group 0: no effect 1: toggle the result that whether the group is assigned to CPU0 before 0 4 read-write 1 0x10 cpu0 RETENTION[%s] no description available 0x920 VALUE Retention Control 0x0 32 0x00000000 0x00007FFF LINK retention setting while CPU0 enter stop mode, each bit represents a resource bit00: soc_mem is kept on while cpu0 stop bit01: soc_ctx is kept on while cpu0 stop bit02: cpu0_mem is kept on while cpu0 stop bit03: cpu0_ctx is kept on while cpu0 stop bit04: con_ctx is kept on while cpu0 stop bit05: vis_mem is kept on while cpu0 stop bit06: vis_ctx is kept on while cpu0 stop bit07: gpu_mem is kept on while cpu0 stop bit08: gpu_ctx is kept on while cpu0 stop bit09: xtal_hold is kept on while cpu0 stop bit10: pll0_hold is kept on while cpu0 stop bit11: pll1_hold is kept on while cpu0 stop bit12: pll2_hold is kept on while cpu0 stop bit13: pll3 is kept on while cpu0 stop bit14: pll4 is kept on while cpu0 stop 0 15 read-write SET Retention Control 0x4 32 0x00000000 0x00007FFF LINK retention setting while CPU0 enter stop mode, each bit represents a resource 0: no effect 1: keep 0 15 read-write CLEAR Retention Control 0x8 32 0x00000000 0x00007FFF LINK retention setting while CPU0 enter stop mode, each bit represents a resource 0: no effect 1: no keep 0 15 read-write TOGGLE Retention Control 0xc 32 0x00000000 0x00007FFF LINK retention setting while CPU0 enter stop mode, each bit represents a resource 0: no effect 1: toggle the result that whether the resource is kept on while CPU0 stop before 0 15 read-write 3 0x10 vis,cpu0,gpu POWER[%s] no description available 0x1000 status Power Setting 0x0 32 0x80000000 0xC0001100 FLAG flag represents power cycle happened from last clear of this bit 0: power domain did not edurance power cycle since last clear of this bit 1: power domain enduranced power cycle since last clear of this bit 31 1 read-write FLAG_WAKE flag represents wakeup power cycle happened from last clear of this bit 0: power domain did not edurance wakeup power cycle since last clear of this bit 1: power domain enduranced wakeup power cycle since last clear of this bit 30 1 read-write LF_DISABLE low fanout power switch disable 0: low fanout power switches are turned on 1: low fanout power switches are truned off 12 1 read-only LF_ACK low fanout power switch feedback 0: low fanout power switches are turned on 1: low fanout power switches are truned off 8 1 read-only lf_wait Power Setting 0x4 32 0x000000FF 0x000FFFFF WAIT wait time for low fan out power switch turn on, default value is 255 0: 0 clock cycle 1: 1 clock cycles . . . clock cycles count on 24MHz 0 20 read-write off_wait Power Setting 0xc 32 0x0000000F 0x000FFFFF WAIT wait time for power switch turn off, default value is 15 0: 0 clock cycle 1: 1 clock cycles . . . clock cycles count on 24MHz 0 20 read-write 5 0x10 soc,con,vis,cpu0,gpu RESET[%s] no description available 0x1400 control Reset Setting 0x0 32 0x80000000 0xC0000011 FLAG flag represents reset happened from last clear of this bit 0: domain did not edurance reset cycle since last clear of this bit 1: domain enduranced reset cycle since last clear of this bit 31 1 read-write FLAG_WAKE flag represents wakeup reset happened from last clear of this bit 0: domain did not edurance wakeup reset cycle since last clear of this bit 1: domain enduranced wakeup reset cycle since last clear of this bit 30 1 read-write HOLD perform reset and hold in reset, until ths bit cleared by software 0: reset is released for function 1: reset is assert and hold 4 1 read-write RESET perform reset and release imediately 0: reset is released 1 reset is asserted and will release automatically 0 1 read-write config Reset Setting 0x4 32 0x00402003 0x00FFFFFF PRE_WAIT wait cycle numbers before assert reset 0: wait 0 cycle 1: wait 1 cycles . . . Note, clock cycle is base on 24M 16 8 read-write RSTCLK_NUM reset clock number(must be even number) 0: 0 cycle 1: 0 cycles 2: 2 cycles 3: 2 cycles . . . Note, clock cycle is base on 24M 8 8 read-write POST_WAIT time guard band for reset release 0: wait 0 cycle 1: wait 1 cycles . . . Note, clock cycle is base on 24M 0 8 read-write counter Reset Setting 0xc 32 0x00000000 0x000FFFFF COUNTER self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset 0: wait 0 cycle 1: wait 1 cycles . . . Note, clock cycle is base on 24M 0 20 read-write 69 0x4 clk_top_cpu0,clk_top_mct0,clk_top_gpu0,clk_top_axif,clk_top_axis,clk_top_axic,clk_top_axiv,clk_top_axid,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_can4,clk_top_can5,clk_top_can6,clk_top_can7,clk_top_lin0,clk_top_lin1,clk_top_lin2,clk_top_lin3,clk_top_lin4,clk_top_lin5,clk_top_lin6,clk_top_lin7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_tmr4,clk_top_tmr5,clk_top_tmr6,clk_top_tmr7,clk_top_xpi0,clk_top_xram,clk_top_ana0,clk_top_ana1,clk_top_aud0,clk_top_aud1,clk_top_aud2,clk_top_aud3,clk_top_eth0,clk_top_ptp0,clk_top_sdc0,clk_top_sdc1,clk_top_ntm0,clk_top_ref0,clk_top_ref1,clk_top_cam0,clk_top_cam1,clk_top_lcd0,clk_top_lcd1,clk_top_csi0,clk_top_csi1 CLOCK[%s] no description available 0x1800 32 0x00000000 0xD00007FF GLB_BUSY global busy 0: no changes pending to any clock 1: any of nodes is changing status 31 1 read-only LOC_BUSY local busy 0: a change is pending for current node 1: current node is changing status 30 1 read-only PRESERVE preserve function against global select 0: select global clock setting 1: not select global clock setting 28 1 read-write MUX current mux in clock component 0:osc0_clk0 1:pll0_clk0 2:pll1_clk0 3:pll1_clk1 4:pll2_clk0 5:pll2_clk1 6:pll3_clk0 7:pll4_clk0 8 3 read-write DIV clock divider 0: divider by 1 1: divider by 2 2: divider by 3 . . . 255: divider by 256 0 8 read-write 2 0x4 clk_top_adc0,clk_top_adc1 ADCCLK[%s] no description available 0x1c00 32 0x00000000 0xD0000100 GLB_BUSY global busy 0: no changes pending to any clock 1: any of nodes is changing status 31 1 read-only LOC_BUSY local busy 0: a change is pending for current node 1: current node is changing status 30 1 read-only PRESERVE preserve function against global select 0: select global clock setting 1: not select global clock setting 28 1 read-write MUX current mux 0: ana clock N 1: axi clock 8 1 read-write 4 0x4 clk_top_i2s0,clk_top_i2s1,clk_top_i2s2,clk_top_i2s3 I2SCLK[%s] no description available 0x1c08 32 0x00000000 0xD0000100 GLB_BUSY global busy 0: no changes pending to any clock 1: any of nodes is changing status 31 1 read-only LOC_BUSY local busy 0: a change is pending for current node 1: current node is changing status 30 1 read-only PRESERVE preserve function against global select 0: select global clock setting 1: not select global clock setting 28 1 read-write MUX current mux 0: aud clock N 1: aud clock 0 8 1 read-write global00 Clock senario 0x2000 32 0x00000000 0x000000FF MUX global clock override request bit0: override to preset0 bit1: override to preset1 bit2: override to preset2 bit3: override to preset3 bit4: override to preset4 bit5: override to preset5 bit6: override to preset6 bit7: override to preset7 0 8 read-write 4 0x20 slice0,slice1,slice2,slice3 MONITOR[%s] no description available 0x2400 control Clock measure and monitor control 0x0 32 0x00000000 0x89FFD7FF VALID result is ready for read 0: not ready 1: result is ready 31 1 read-write DIV_BUSY divider is applying new setting 27 1 read-only OUTEN enable clock output 24 1 read-write DIV output divider 16 8 read-write HIGH clock frequency higher than upper limit 15 1 read-write LOW clock frequency lower than lower limit 14 1 read-write START start measurement 12 1 read-write MODE work mode, 0: register value will be compared to measurement 1: upper and lower value will be recordered in register 10 1 read-write ACCURACY measurement accuracy, 0: resolution is 1kHz 1: resolution is 1Hz 9 1 read-write REFERENCE reference clock selection, 0: 32k 1: 24M 8 1 read-write SELECTION clock measurement selection 0 8 read-write current Clock measure result 0x4 32 0x00000000 0xFFFFFFFF FREQUENCY self updating measure result 0 32 read-only low_limit Clock lower limit 0x8 32 0xFFFFFFFF 0xFFFFFFFF FREQUENCY lower frequency 0 32 read-write high_limit Clock upper limit 0xc 32 0x00000000 0xFFFFFFFF FREQUENCY upper frequency 0 32 read-write 1 0x400 cpu0 CPU[%s] no description available 0x2800 LP CPU0 LP control 0x0 32 0x00001000 0xFF013703 WAKE_CNT CPU0 wake up counter, counter satuated at 255, write 0x00 to clear 24 8 read-write HALT halt request for CPU0, 0: CPU0 will start to execute after reset or receive wakeup request 1: CPU0 will not start after reset, or wakeup after WFI 16 1 read-write WAKE CPU0 is waking up 0: CPU0 wake up not asserted 1: CPU0 wake up asserted 13 1 read-only EXEC CPU0 is executing 0: CPU0 is not executing 1: CPU0 is executing 12 1 read-only WAKE_FLAG CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit 0: CPU0 wakeup not happened 1: CPU0 wake up happened 10 1 read-write SLEEP_FLAG CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit 0: CPU0 sleep not happened 1: CPU0 sleep happened 9 1 read-write RESET_FLAG CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit 0: CPU0 reset not happened 1: CPU0 reset happened 8 1 read-write MODE Low power mode, system behavior after WFI 00: CPU clock stop after WFI 01: System enter low power mode after WFI 10: Keep running after WFI 11: reserved 0 2 read-write LOCK CPU0 Lock GPR 0x4 32 0x00000000 0x0000FFFE GPR Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset 2 14 read-write LOCK Lock bit for CPU_LOCK 1 1 read-write 14 0x4 GPR0,GPR1,GPR2,GPR3,GPR4,GPR5,GPR6,GPR7,GPR8,GPR9,GPR10,GPR11,GPR12,GPR13 GPR[%s] no description available 0x8 32 0x00000000 0xFFFFFFFF GPR register for software to handle resume, can save resume address or status 0 32 read-write 4 0x4 STATUS0,STATUS1,STATUS2,STATUS3 WAKEUP_STATUS[%s] no description available 0x40 32 0x00000000 0xFFFFFFFF STATUS IRQ values 0 32 read-only 4 0x4 ENABLE0,ENABLE1,ENABLE2,ENABLE3 WAKEUP_ENABLE[%s] no description available 0x80 32 0x00000000 0xFFFFFFFF ENABLE IRQ wakeup enable 0 32 read-write IOC IOC IOC 0xf4040000 0x0 0xf80 registers 496 0x8 pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,pb16,pb17,pb18,pb19,pb20,pb21,pb22,pb23,pb24,pb25,pb26,pb27,pb28,pb29,pb30,pb31,pc00,pc01,pc02,pc03,pc04,pc05,pc06,pc07,pc08,pc09,pc10,pc11,pc12,pc13,pc14,pc15,pc16,pc17,pc18,pc19,pc20,pc21,pc22,pc23,pc24,pc25,pc26,pc27,pc28,pc29,pc30,pc31,pd00,pd01,pd02,pd03,pd04,pd05,pd06,pd07,pd08,pd09,pd10,pd11,pd12,pd13,pd14,pd15,pd16,pd17,pd18,pd19,pd20,pd21,pd22,pd23,pd24,pd25,pd26,pd27,pd28,pd29,pd30,pd31,pe00,pe01,pe02,pe03,pe04,pe05,pe06,pe07,pe08,pe09,pe10,pe11,pe12,pe13,pe14,pe15,pe16,pe17,pe18,pe19,pe20,pe21,pe22,pe23,pe24,pe25,pe26,pe27,pe28,pe29,pe30,pe31,pf00,pf01,pf02,pf03,pf04,pf05,pf06,pf07,pf08,pf09,pf10,pf11,pf12,pf13,pf14,pf15,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,px00,px01,px02,px03,px04,px05,px06,px07,px08,px09,px10,px11,px12,px13,px14,px15,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,py00,py01,py02,py03,py04,py05,py06,py07,py08,py09,py10,py11,py12,py13,py14,py15,rsv464,rsv465,rsv466,rsv467,rsv468,rsv469,rsv470,rsv471,rsv472,rsv473,rsv474,rsv475,rsv476,rsv477,rsv478,rsv479,pz00,pz01,pz02,pz03,pz04,pz05,pz06,pz07,pz08,pz09,pz10,pz11,pz12,pz13,pz14,pz15 PAD[%s] no description available 0x0 FUNC_CTL ALT SELECT 0x0 32 0x00000000 0x0001011F LOOP_BACK force input on 0: disable 1: enable 16 1 read-write ANALOG select analog pin in pad 0: disable 1: enable 8 1 read-write ALT_SELECT alt select 0: ALT0 1: ALT1 ... 31:ALT31 0 5 read-write PAD_CTL PAD SETTINGS 0x4 32 0x01010056 0x01370177 HYS schmitt trigger enable 0: disable 1: enable 24 1 read-write PRS select pull up/down internal resistance strength: For pull down, only have 100 Kohm resistance For pull up: 00: 100 KOhm 01: 47 KOhm 10: 22 KOhm 11: 22 KOhm 20 2 read-write PS pull select 0: pull down 1: pull up 18 1 read-write PE pull enable 0: pull disable 1: pull enable 17 1 read-write KE keeper capability enable 0: keeper disable 1: keeper enable 16 1 read-write OD open drain 0: open drain disable 1: open drain enable 8 1 read-write SR slew rate 0: Slow slew rate 1: Fast slew rate 6 1 read-write SPD additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise 00: Slow frequency slew rate(50Mhz) 01: Medium frequency slew rate(100 Mhz) 10: Fast frequency slew rate(150 Mhz) 11: Max frequency slew rate(200Mhz) 4 2 read-write DS drive strength 1.8V Mode: 000: 260 Ohm 001: 260 Ohm 010: 130 Ohm 011: 88 Ohm 100: 65 Ohm 101: 52 Ohm 110: 43 Ohm 111: 37 Ohm 3.3V Mode: 000: 157 Ohm 001: 157 Ohm 010: 78 Ohm 011: 53 Ohm 100: 39 Ohm 101: 32 Ohm 110: 26 Ohm 111: 23 Ohm 0 3 read-write PIOC PIOC IOC 0xf4118000 BIOC BIOC IOC 0xf4210000 PLLCTLV2 PLLCTLV2 PLLCTLV2 0xf40c0000 0x0 0x300 registers XTAL OSC configuration 0x0 32 0x0001FFFF 0xB00FFFFF BUSY Busy flag 0: Oscillator is working or shutdown 1: Oscillator is changing status 31 1 read-only RESPONSE Crystal oscillator status 0: Oscillator is not stable 1: Oscillator is stable for use 29 1 read-only ENABLE Crystal oscillator enable status 0: Oscillator is off 1: Oscillator is on 28 1 read-only RAMP_TIME Rampup time of XTAL oscillator in cycles of RC24M clock 0: 0 cycle 1: 1 cycle 2: 2 cycle 1048575: 1048575 cycles 0 20 read-write 5 0x80 pll0,pll1,pll2,pll3,pll4 PLL[%s] no description available 0x80 MFI PLL0 multiple register 0x0 32 0x00000010 0xB000007F BUSY Busy flag 0: PLL is stable or shutdown 1: PLL is changing status 31 1 read-only RESPONSE PLL status 0: PLL is not stable 1: PLL is stable for use 29 1 read-only ENABLE PLL enable status 0: PLL is off 1: PLL is on 28 1 read-only MFI loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) 0-15: invalid 16: divide by 16 17: divide by17 . . . 42: divide by 42 43~:invalid 0 7 read-write MFN PLL0 fraction numerator register 0x4 32 0x09896800 0x3FFFFFFF MFN Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. 0 30 read-write MFD PLL0 fraction demoninator register 0x8 32 0x0E4E1C00 0x3FFFFFFF MFD Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. 0 30 read-write SS_STEP PLL0 spread spectrum step register 0xc 32 0x00000000 0x3FFFFFFF STEP Step of spread spectrum modulator. This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. 0 30 read-write SS_STOP PLL0 spread spectrum stop register 0x10 32 0x00000000 0x3FFFFFFF STOP Stop point of spread spectrum modulator This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. 0 30 read-write CONFIG PLL0 confguration register 0x14 32 0x00000000 0x00000101 SPREAD Enable spread spectrum function. This field supports changing during PLL running. 8 1 read-write REFSEL Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. 0: XTAL24M 1: IRC24M 0 1 read-write LOCKTIME PLL0 lock time register 0x18 32 0x000009C4 0x0000FFFF LOCKTIME Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. 0 16 read-write STEPTIME PLL0 step time register 0x1c 32 0x000009C4 0x0000FFFF STEPTIME Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. 0 16 read-write ADVANCED PLL0 advance configuration register 0x20 32 0x00000000 0x11000000 SLOW Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. 0: fast lock enabled, lock time is 100us 1: fast lock disabled, lock time is 400us 28 1 read-write DITHER Enable dither function 24 1 read-write 3 0x4 DIV0,DIV1,DIV2 DIV[%s] no description available 0x40 32 0x00000000 0xB000003F BUSY Busy flag 0: divider is working 1: divider is changing status 31 1 read-only RESPONSE Divider response status 0: Divider is not stable 1: Divider is stable for use 29 1 read-only ENABLE Divider enable status 0: Divider is off 1: Divider is on 28 1 read-only DIV Divider factor, divider factor is DIV/5 + 1 0: divide by 1 1: divide by 1.2 2: divide by 1.4 . . . 63: divide by 13.6 0 6 read-write PPOR PPOR PPOR 0xf4100000 0x0 0x20 registers RESET_FLAG flag indicate reset source 0x0 32 0x00000000 0xFFFFFFFF FLAG reset reason of last hard reset, write 1 to clear each bit 0: brownout 1: temperature(not available) 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software 0 32 write-only RESET_STATUS reset source status 0x4 32 0x00000000 0xFFFFFFFF STATUS current status of reset sources 0: brownout 1: temperature(not available) 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software 0 32 read-only RESET_HOLD reset hold attribute 0x8 32 0x00000000 0xFFFFFFFF HOLD hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status 0: brownout 1: temperature(not available) 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software 0 32 read-write RESET_ENABLE reset source enable 0xc 32 0xFFFFFFFF 0xFFFFFFFF ENABLE enable of reset sources 0: brownout 1: temperature(not available) 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software 0 32 read-write SOFTWARE_RESET Software reset counter 0x1c 32 0x00000000 0xFFFFFFFF COUNTER counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset 0 32 read-write PCFG PCFG PMU 0xf4104000 0x0 0xac registers BANDGAP BANGGAP control 0x0 32 0x00101010 0x831F1F1F VBG_TRIMMED Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: bandgap is not trimmed 1: bandgap is trimmed 31 1 read-write LOWPOWER_MODE Banggap work in low power mode, banggap function limited 0: banggap works in normal mode 1: banggap works in low power mode 25 1 read-write POWER_SAVE Banggap work in power save mode, banggap function normally 0: banggap works in high performance mode 1: banggap works in power saving mode 24 1 read-write VBG_1P0_TRIM Banggap 1.0V output trim value 16 5 read-write VBG_P65_TRIM Banggap 1.0V output trim value 8 5 read-write VBG_P50_TRIM Banggap 1.0V output trim value 0 5 read-write LDO1P1 1V LDO config 0x4 32 0x0000044C 0x00000FFF VOLT LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. 700: 700mV 720: 720mV . . . 1320:1320mV 0 12 read-write LDO2P5 2.5V LDO config 0x8 32 0x000009C4 0x10010FFF READY Ready flag, will set 1ms after enabled or voltage change 0: LDO is not ready for use 1: LDO is ready 28 1 read-only ENABLE LDO enable 0: turn off LDO 1: turn on LDO 16 1 read-write VOLT LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. 2125: 2125mV 2150: 2150mV . . . 2900:2900mV 0 12 read-write DCDC_MODE DCDC mode select 0x10 32 0x0003047E 0x10070FFF READY Ready flag 0: DCDC is applying new change 1: DCDC is ready 28 1 read-only MODE DCDC work mode XX0: turn off 001: basic mode 011: generic mode 101: automatic mode 111: expert mode 16 3 read-write VOLT DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. 600: 600mV 625: 625mV . . . 1375:1375mV 0 12 read-write DCDC_LPMODE DCDC low power mode 0x14 32 0x00000384 0x00000FFF STBY_VOLT DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. 600: 600mV 625: 625mV . . . 1375:1375mV 0 12 read-write DCDC_PROT DCDC protection 0x18 32 0x00000000 0x11818191 ILIMIT_LP over current setting for low power mode 0:250mA 1:200mA 28 1 read-write OVERLOAD_LP over current in low power mode 0: current is below setting 1: overcurrent happened in low power mode 24 1 read-only DISABLE_POWER_LOSS disable power loss protection 0: power loss protection enabled, DCDC shuts down when power loss 1: power loss protection disabled, DCDC try working after power voltage drop 23 1 read-write POWER_LOSS_FLAG power loss 0: input power is good 1: input power is too low 16 1 read-only DISABLE_OVERVOLTAGE output over voltage protection 0: protection enabled, DCDC will shut down is output voltage is unexpected high 1: protection disabled, DCDC continue to adjust output voltage 15 1 read-write OVERVOLT_FLAG output over voltage flag 0: output is normal 1: output is unexpected high 8 1 read-only DISABLE_SHORT disable output short circuit protection 0: short circuits protection enabled, DCDC shut down if short circuit on output detected 1: short circuit protection disabled 7 1 read-write SHORT_CURRENT short circuit current setting 0: 2.0A, 1: 1.3A 4 1 read-write SHORT_FLAG short circuit flag 0: current is within limit 1: short circuits detected 0 1 read-only DCDC_CURRENT DCDC current estimation 0x1c 32 0x00000000 0x0000811F ESTI_EN enable current measure 15 1 read-write VALID Current level valid 0: data is invalid 1: data is valid 8 1 read-only LEVEL DCDC current level, current level is num * 50mA 0 5 read-only DCDC_ADVMODE DCDC advance setting 0x20 32 0x05120067 0x073F006F EN_RCSCALE Enable RC scale 24 3 read-write DC_C Loop C number 20 2 read-write DC_R Loop R number 16 4 read-write EN_FF_DET enable feed forward detect 0: feed forward detect is disabled 1: feed forward detect is enabled 6 1 read-write EN_FF_LOOP enable feed forward loop 0: feed forward loop is disabled 1: feed forward loop is enabled 5 1 read-write EN_DCM_EXIT avoid over voltage 0: stay in DCM mode when voltage excess 1: change to CCM mode when voltage excess 3 1 read-write EN_SKIP enable skip on narrow pulse 0: do not skip narrow pulse 1: skip narrow pulse 2 1 read-write EN_IDLE enable skip when voltage is higher than threshold 0: do not skip 1: skip if voltage is excess 1 1 read-write EN_DCM DCM mode 0: CCM mode 1: DCM mode 0 1 read-write DCDC_ADVPARAM DCDC advance parameter 0x24 32 0x00006E1C 0x00007F7F MIN_DUT minimum duty cycle 8 7 read-write MAX_DUT maximum duty cycle 0 7 read-write DCDC_MISC DCDC misc parameter 0x28 32 0x00070100 0x13170317 EN_HYST hysteres enable 28 1 read-write HYST_SIGN hysteres sign 25 1 read-write HYST_THRS hysteres threshold 24 1 read-write RC_SCALE Loop RC scale threshold 20 1 read-write DC_FF Loop feed forward number 16 3 read-write OL_THRE overload for threshold for lod power mode 8 2 read-write OL_HYST current hysteres range 0: 12.5mV 1: 25mV 4 1 read-write DELAY enable delay 0: delay disabled, 1: delay enabled 2 1 read-write CLK_SEL clock selection 0: select DCDC internal oscillator 1: select RC24M oscillator 1 1 read-write EN_STEP enable stepping in voltage change 0: stepping disabled, 1: steping enabled 0 1 read-write DCDC_DEBUG DCDC Debug 0x2c 32 0x00005DBF 0x000FFFFF UPDATE_TIME DCDC voltage change time in 24M clock cycles, default value is 1mS 0 20 read-write DCDC_START_TIME DCDC ramp time 0x30 32 0x0001193F 0x000FFFFF START_TIME Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS 0 20 read-write DCDC_RESUME_TIME DCDC resume time 0x34 32 0x00008C9F 0x000FFFFF RESUME_TIME Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS 0 20 read-write POWER_TRAP power trap 0x40 32 0x00000000 0x80010001 TRIGGERED Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. 0: low power trap is not triggered 1: low power trap triggered 31 1 read-write RETENTION DCDC enter standby mode, which will reduce voltage for memory content retention 0: Shutdown DCDC 1: reduce DCDC voltage 16 1 read-write TRAP Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered 0: trap not enabled, pmic side low power function disabled 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. 0 1 read-write WAKE_CAUSE Wake up source 0x44 32 0x00000000 0xFFFFFFFF CAUSE wake up cause, each bit represents one wake up source, write 1 to clear the register bit 0: wake up source is not active during last wakeup 1: wake up source is active furing last wakeup bit 0: pmic_enable bit 5: VAD interrupt bit 6: VAD wake interrupt bit 7: UART interrupt bit 8: TMR interrupt bit 9: WDG interrupt bit10: GPIO in PMIC interrupt bit16: Security violation in BATT bit17: GPIO in BATT interrupt bit19: RTC alarm interrupt 0 32 read-write WAKE_MASK Wake up mask 0x48 32 0x00000000 0xFFFFFFFF MASK mask for wake up sources, each bit represents one wakeup source 0: allow source to wake up system 1: disallow source to wakeup system bit 0: pmic_enable bit 5: VAD interrupt bit 6: VAD wake interrupt bit 7: UART interrupt bit 8: TMR interrupt bit 9: WDG interrupt bit10: GPIO in PMIC interrupt bit16: Security violation in BATT bit17: GPIO in BATT interrupt bit19: RTC alarm interrupt 0 32 read-write SCG_CTRL Clock gate control in PMIC 0x4c 32 0xFFFFFFFF 0xFFFFFFFF SCG control whether clock being gated during PMIC low power flow, 2 bits for each peripheral 00,01: reserved 10: clock is always off 11: clock is always on bit6-7:gpio bit8-9:ioc bit10-11: timer bit12-13:wdog bit14-15:uart bit16-17:VAD bit18-19:SRAM 0 32 read-write RC24M RC 24M config 0x60 32 0x00000310 0x8000071F RC_TRIMMED RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: RC is not trimmed 1: RC is trimmed 31 1 read-write TRIM_C Coarse trim for RC24M, bigger value means faster 8 3 read-write TRIM_F Fine trim for RC24M, bigger value means faster 0 5 read-write RC24M_TRACK RC 24M track mode 0x64 32 0x00000000 0x00010011 SEL24M Select track reference 0: select 32K as reference 1: select 24M XTAL as reference 16 1 read-write RETURN Retrun default value when XTAL loss 0: remain last tracking value 1: switch to default value 4 1 read-write TRACK track mode 0: RC24M free running 1: track RC24M to external XTAL 0 1 read-write TRACK_TARGET RC 24M track target 0x68 32 0x00000000 0xFFFFFFFF PRE_DIV Divider for reference source 16 16 read-write TARGET Target frequency multiplier of divided source 0 16 read-write STATUS RC 24M track status 0x6c 32 0x00000000 0x0011871F SEL32K track is using XTAL32K 0: track is not using XTAL32K 1: track is using XTAL32K 20 1 read-only SEL24M track is using XTAL24M 0: track is not using XTAL24M 1: track is using XTAL24M 16 1 read-only EN_TRIM default value takes effect 0: default value is invalid 1: default value is valid 15 1 read-only TRIM_C default coarse trim value 8 3 read-only TRIM_F default fine trim value 0 5 read-only DCDCM_MODE DCDCM mode select 0x80 32 0x00030546 0x10070FFF READY Ready flag 0: DCDCM is applying new change 1: DCDCM is ready 28 1 read-only MODE DCDCM work mode XX0: turn off 001: basic mode 011: generic mode 101: automatic mode 111: expert mode 16 3 read-write VOLT DCDCM voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. 600: 600mV 625: 625mV . . . 1375:1375mV 0 12 read-write DCDCM_LPMODE DCDCM low power mode 0x84 32 0x00000546 0x00000FFF STBY_VOLT DCDCM voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. 600: 600mV 625: 625mV . . . 1375:1375mV 0 12 read-write DCDCM_PROT DCDCM protection 0x88 32 0x00000010 0x11818191 ILIMIT_LP over current setting for low power mode 0:250mA 1:200mA 28 1 read-write OVERLOAD_LP over current in low power mode 0: current is below setting 1: overcurrent happened in low power mode 24 1 read-only DISABLE_POWER_LOSS disable power loss protection 0: power loss protection enabled, DCDCM shuts down when power loss 1: power loss protection disabled, DCDCM try working after power voltage drop 23 1 read-write POWER_LOSS_FLAG power loss 0: input power is good 1: input power is too low 16 1 read-only DISABLE_OVERVOLTAGE output over voltage protection 0: protection enabled, DCDCM will shut down is output voltage is unexpected high 1: protection disabled, DCDCM continue to adjust output voltage 15 1 read-write OVERVOLT_FLAG output over voltage flag 0: output is normal 1: output is unexpected high 8 1 read-only DISABLE_SHORT disable output short circuit protection 0: short circuits protection enabled, DCDCM shut down if short circuit on output detected 1: short circuit protection disabled 7 1 read-write SHORT_CURRENT short circuit current setting 0: 2.0A 1: 1.3A 4 1 read-write SHORT_FLAG short circuit flag 0: current is within limit 1: short circuits detected 0 1 read-only DCDCM_CURRENT DCDCM current estimation 0x8c 32 0x00000000 0x0000811F ESTI_EN enable current measure 15 1 read-write VALID Current level valid 0: data is invalid 1: data is valid 8 1 read-only LEVEL DCDCM current level, current level is num * 50mA 0 5 read-only DCDCM_ADVMODE DCDCM advance setting 0x90 32 0x05120067 0x073F007F EN_RCSCALE Enable RC scale 24 3 read-write DC_C Loop C number 20 2 read-write DC_R Loop R number 16 4 read-write EN_FF_DET enable feed forward detect 0: feed forward detect is disabled 1: feed forward detect is enabled 6 1 read-write EN_FF_LOOP enable feed forward loop 0: feed forward loop is disabled 1: feed forward loop is enabled 5 1 read-write EN_AUTOLP enable auto enter low power mode 0: do not enter low power mode 1: enter low power mode if current is detected low 4 1 read-write EN_DCM_EXIT avoid over voltage 0: stay in DCM mode when voltage excess 1: change to CCM mode when voltage excess 3 1 read-write EN_SKIP enable skip on narrow pulse 0: do not skip narrow pulse 1: skip narrow pulse 2 1 read-write EN_IDLE enable skip when voltage is higher than threshold 0: do not skip 1: skip if voltage is excess 1 1 read-write EN_DCM DCM mode 0: CCM mode 1: DCM mode 0 1 read-write DCDCM_ADVPARAM DCDCM advance parameter 0x94 32 0x0000701C 0x00007F7F MIN_DUT minimum duty cycle 8 7 read-write MAX_DUT maximum duty cycle 0 7 read-write DCDCM_MISC DCDCM misc parameter 0x98 32 0x00070100 0x13170317 EN_HYST hysteres enable 28 1 read-write HYST_SIGN hysteres sign 25 1 read-write HYST_THRS hysteres threshold 24 1 read-write RC_SCALE Loop RC scale threshold 20 1 read-write DC_FF Loop feed forward number 16 3 read-write OL_THRE overload for threshold for lod power mode 8 2 read-write OL_HYST current hysteres range 0: 12.5mV 1: 25mV 4 1 read-write DELAY enable delay 0: delay disabled, 1: delay enabled 2 1 read-write CLK_SEL clock selection 0: select DCDCM internal oscillator 1: select RC24M oscillator 1 1 read-write EN_STEP enable stepping in voltage change 0: stepping disabled, 1: steping enabled 0 1 read-write DCDCM_DEBUG DCDCM Debug 0x9c 32 0x00005DBF 0x000FFFFF UPDATE_TIME DCDCM voltage change time in 24M clock cycles, default value is 1mS 0 20 read-write DCDCM_START_TIME DCDCM ramp time 0xa0 32 0x0001193F 0x000FFFFF START_TIME Start delay for DCDCM to turn on, in 24M clock cycles, default value is 3mS 0 20 read-write DCDCM_RESUME_TIME DCDCM resume time 0xa4 32 0x000000F0 0x000FFFFF RESUME_TIME Resume delay for DCDCM to recover from low power mode, in 24M clock cycles, default value is 10uS 0 20 read-write DCDCM_POWER_CONFIG DCDCM power config 0xa8 32 0x00000000 0x00010000 RETENTION DCDCM enter standby mode, which will reduce voltage for memory content retention 0: Shutdown DCDCM 1: reduce DCDC voltage 16 1 read-write PGPR0 PGPR0 PGPR 0xf4110000 0x0 0x40 registers PMIC_GPR00 Generic control 0x0 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR01 Generic control 0x4 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR02 Generic control 0x8 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR03 Generic control 0xc 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR04 Generic control 0x10 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR05 Generic control 0x14 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR06 Generic control 0x18 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR07 Generic control 0x1c 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR08 Generic control 0x20 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR09 Generic control 0x24 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR10 Generic control 0x28 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR11 Generic control 0x2c 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR12 Generic control 0x30 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR13 Generic control 0x34 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR14 Generic control 0x38 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PMIC_GPR15 Generic control 0x3c 32 0x00000000 0xFFFFFFFF GPR Generic control 0 32 read-write PGPR1 PGPR1 PGPR 0xf4114000 VAD VAD VAD 0xf412c000 0x0 0xa4 registers CTRL Control Register 0x0 32 0x00000000 0x0FF7FBFF CAPT_DLY Capture cycle delay>=0, should be less than PDM_CLK_HFDIV 24 4 read-write PDM_CLK_HFDIV The clock divider will work at least 4. 0: div-by-2, 1: div-by-4 . . . n: div-by-2*(n+1) 20 4 read-write VAD_IE VAD event interrupt enable 18 1 read-write OFIFO_AV_IE OFIFO data available interrupt enable 17 1 read-write MEMBUF_EMPTY_IE Buf empty interrupt enable 16 1 read-write OFIFO_OVFL_ERR_IE OFIFO overflow error interrupt enable 15 1 read-write IIR_OVLD_ERR_IE IIR overload error interrupt enable 14 1 read-write IIR_OVFL_ERR_IE IIR overflow error interrupt enable 13 1 read-write CIC_OVLD_ERR_IE CIC overload Interrupt Enable 12 1 read-write CIC_SAT_ERR_IE CIC saturation Interrupt Enable 11 1 read-write MEMBUF_DISABLE asserted to disable membuf 9 1 read-write FIFO_THRSH OFIFO threshold to generate ofifo_av (when fillings >= threshold) (fifo size: max 16 items, 16*32bits) 5 4 read-write PDM_CLK_DIV_BYPASS asserted to bypass the pdm clock divider 4 1 read-write PDM_CLK_OE pdm_clk_output_en 3 1 read-write CH_POL Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. 1 2 read-write CHNUM the number of channels to be stored in buffer. Asserted to enable 2 channels. 0 1 read-write FILTCTRL Filter Control Register 0x4 32 0x00000000 0x000007FF DECRATIO the decimation ratio of iir after CIC -1 2: means dec-by-3 8 3 read-write IIR_SLOT_EN IIR slot enable 0 8 read-write DEC_CTRL0 Decision Control Register 0 0x8 32 0x00000000 0xFFFF03FF NOISE_TOL the value of amplitude for noise determination when calculationg ZCR 16 16 read-write BLK_CFG asserted to have 3 sub-blocks, otherwise to have 2 sub-blocks 9 1 read-write SUBBLK_LEN length of sub-block 0 9 read-write DEC_CTRL1 Decision Control Register 1 0xc 32 0x00000000 0x003FFFFF ZCR_HIGH ZCR high limit 11 11 read-write ZCR_LOW ZCR low limit 0 11 read-write DEC_CTRL2 Decision Control Register 2 0x10 32 0x00000000 0xFFFFFFFF AMP_HIGH amplitude high limit 16 16 read-write AMP_LOW amplitude low limit 0 16 read-write ST Status 0x18 32 0x00000000 0x000000FF VAD VAD event found 7 1 write-only OFIFO_AV OFIFO data available 6 1 read-only MEMBUF_EMPTY Buf empty 5 1 write-only OFIFO_OVFL OFIFO overflow 4 1 write-only IIR_OVLD IIR overloading 3 1 write-only IIR_OVFL IIR oberflow 2 1 write-only CIC_OVLD_ERR CIC overload 1 1 write-only CIC_SAT_ERR CIC saturation 0 1 write-only OFIFO Out FIFO 0x1c 32 0x00000000 0xFFFFFFFF D The PCM data. When there is only one channel, the samples are from Ch0, and the 2 samples in the 32-bits are: bit [31:16]: the samples earlier in time ([T-1]). Bit [15:0]: the samples later in time ([T]). When there is two channels, the samples in the 32-bits are: bit [31:16]: the samples belong to Ch 1 (when ch_pol[1:0]==2, the data is captured at the positive part of the pdm clk). bit [15:0]: the samples belong to Ch 0 (when ch_pol[1:0]==2, the data is captured at the negtive part of the pdm clk). 0 32 read-write RUN Run Command Register 0x20 32 0x00000000 0x00000003 SFTRST software reset. Self-clear 1 1 read-write VAD_EN module enable 0 1 read-write OFIFO_CTRL Out FIFO Control Register 0x24 32 0x00000000 0x00000001 EN Asserted to enable OFIFO 0 1 read-write CIC_CFG CIC Configuration Register 0x28 32 0x00000000 0x0000FC00 POST_SCALE the shift value after CIC results. 10 6 read-write 1 0x4 STE_ACT COEF[%s] no description available 0xa0 32 0x00000000 0xFFFFFFFF VAL The current detected short time energy 0 32 read-only DDRPHY DDRPHY DDRPHY 0xf4150000 0x0 0x400 registers RIDR Revision Identification Register 0x0 32 0x00000000 0xFFFFFFFF UDRID User-Defined Revision ID: General purpose revision identification set by the user. 24 8 read-only PHYMJR PHY Major Revision: Indicates major revision of the PHY such addition of the features that make the new version not compatible with previous versions. 20 4 read-only PHYMDR PHY Moderate Revision: Indicates moderate revision of the PHY such as addition of new features. Normally the new version is still compatible with previous versions. 16 4 read-only PHYMNR PHY Minor Revision: Indicates minor update of the PHY such as bug fixes. Normally no new features are included. 12 4 read-only PUBMJR PUB Major Revision: Indicates major revision of the PUB such addition of the features that make the new version not compatible with previous versions. 8 4 read-only PUBMDR PUB Moderate Revision: Indicates moderate revision of the PUB such as addition of new features. Normally the new version is still compatible with previous versions. 4 4 read-only PUBMNR PUB Minor Revision: Indicates minor update of the PUB such as bug fixes. Normally no new features are included. 0 4 read-only PIR PHY Initialization Register (PIR) 0x4 32 0x00000000 0xFFFFFFFF INITBYP Initialization Bypass: Bypasses or stops, if set, all initialization routines currently running, including PHY initialization, DRAM initialization, and PHY training. Initialization may be triggered manually using INIT and the other relevant bits of the PIR register. This bit is self-clearing. 31 1 read-write ZCALBYP Impedance Calibration Bypass: Bypasses or stops, if set, impedance calibration of all ZQ control blocks that automatically triggers after reset. Impedance calibration may be triggered manually using INIT and ZCAL bits of the PIR register. This bit is self-clearing. 30 1 read-write DCALBYP Digital Delay Line (DDL) Calibration Bypass: Bypasses or stops, if set, DDL calibration that automatically triggers after reset. DDL calibration may be triggered manually using INIT and DCAL bits of the PIR register. This bit is self- clearing. 29 1 read-write LOCKBYP PLL Lock Bypass: Bypasses or stops, if set, the waiting of PLLs to lock. PLL lock wait is automatically triggered after reset. PLL lock wait may be triggered manually using INIT and PLLINIT bits of the PIR register. This bit is self-clearing. 28 1 read-write CLRSR Clear Status Registers: Writing 1 to this bit clears (reset to 0) select status bits in register PGSR0. This bit is primarily for debug purposes and is typically not needed during normal functional operation. It can be used when PGSR.IDONE=1, to manually clear a selection of the PGSR status bits, although starting a new initialization process (PIR[0].INIT = 1’b1) automatically clears the PGSR status bits associated with the initialization steps enabled. The following list describes which bits within the PGSR0 register are cleared when CLRSR is set to 1’b1 and which bits are not cleared: The following bits are not cleared by PIR[27] (CLRSR): PGSR0[31] (APLOCK) PGSR0[29:28] (PLDONE_CHN) PGSR0[23] (WLAERR) PGSR0[21] (WLERR) PGSR0[4] (DIDONE) PGSR0[2] (DCDONE) PGSR0[1] (PLDONE) PGSR0[0] (IDONE) The following bits are always zero: PGSR0[30] (reserved) PGSR0[19:12] (reserved) The following bits are cleared unconditionally by PIR[27] (CLRSR): PGSR0[27] (WEERR) PGSR0[26] (REERR) PGSR0[25] (WDERR) PGSR0[24] (RDERR) - PGSR0[22] (QSGERR) - PGSR0[20] (ZCERR) - PGSR0[11] (WEDONE) - PGSR0[10] (REDONE) - PGSR0[9] (WDDONE) - PGSR0[8] (RDDONE) - PGSR0[7] (WLADONE) - PGSR0[6] (QSGDONE) - PGSR0[5] (WLDONE) - PGSR0[3] (ZCDONE) 27 1 read-write RDIMMINIT RDIMM Initialization: Executes the RDIMM buffer chip initialization before executing DRAM initialization. The RDIMM buffer chip initialization is run after the DRAM is reset and CKE have been driven high by the DRAM initialization sequence. 19 1 read-write CTLDINIT Controller DRAM Initialization: Indicates, if set, that DRAM initialization will be performed by the controller. Otherwise if not set it indicates that DRAM initialization will be performed using the built-in initialization sequence or using software through the configuration port. 18 1 read-write PLLBYP PLL Bypass: A setting of 1 on this bit will put all PHY PLLs in bypass mode. 17 1 read-write ICPC Initialization Complete Pin Configuration: Specifies how the DFI initialization complete output pin (dfi_init_complete) should be used to indicate the status of initialization. Valid value are: 0 = Asserted after PHY initialization (DLL locking and impedance calibration) is complete. 1 = Asserted after PHY initialization is complete and the triggered the PUB initialization (DRAM initialization, data training, or initialization trigger with no selected initialization) is complete. 16 1 read-write WREYE Write Data Eye Training: Executes a PUB training routine to maximize the write data eye. 15 1 read-write RDEYE Read Data Eye Training: Executes a PUB training routine to maximize the read data eye. 14 1 read-write WRDSKW Write Data Bit Deskew: Executes a PUB training routine to deskew the DQ bits during write. 13 1 read-write RDDSKW Read Data Bit Deskew: Executes a PUB training routine to deskew the DQ bits during read. 12 1 read-write WLADJ Write Leveling Adjust (DDR3 Only): Executes a PUB training routine that re- adjusts the write latency used during write in case the write leveling routine changed the expected latency. Note: Ensure that the DCU command cache is cleared prior to running WLADJ. 11 1 read-write QSGATE Read DQS Gate Training: Executes a PUB training routine to determine the optimum position of the read data DQS strobe for maximum system timing margins. 10 1 read-write WL Write Leveling (DDR3 Only): Executes a PUB write leveling routine. 9 1 read-write DRAMINIT DRAM Initialization: Executes the DRAM initialization sequence. 8 1 read-write DRAMRST DRAM Reset (DDR3 Only): Issues a reset to the DRAM (by driving the DRAM reset pin low) and wait 200us. This can be triggered in isolation or with the full DRAM initialization (DRAMINIT). For the later case, the reset is issued and 200us is waited before starting the full initialization sequence. 7 1 read-write PHYRST PHY Reset: Resets the AC and DATX8 modules by asserting the AC/DATX8 reset pin. 6 1 read-write DCAL Digital Delay Line (DDL) Calibration: Performs PHY delay line calibration. 5 1 read-write PLLINIT PLL Initialization: Executes the PLL initialization sequence which includes correct driving of PLL power-down, reset and gear shift pins, and then waiting for the PHY PLLs to lock. 4 1 read-write ZCAL Impedance Calibration: Performs PHY impedance calibration. When set the impedance calibration will be performed in parallel with PHY initialization (PLL initialization + DDL calibration + PHY reset). 1 1 read-write INIT Initialization Trigger: A write of '1' to this bit triggers the DDR system initialization, including PHY initialization, DRAM initialization, and PHY training. The exact initialization steps to be executed are specified in bits 1 to 15 of this register. A bit setting of 1 means the step will be executed as part of the initialization sequence, while a setting of ‘0’ means the step will be bypassed. The initialization trigger bit is self-clearing. 0 1 read-write PGCR0 PHY General Configuration Registers 0-1 (PGCR0- 1) 0x8 32 0x00000000 0xFFFFFFFF CKEN CK Enable: Controls whether the CK going to the SDRAM is enabled (toggling) or disabled (static value) and whether the CK is inverted. Two bits for each of the up to three CK pairs. Valid values for the two bits are: 00 = CK disabled (Driven to constant 0) 01 = CK toggling with inverted polarity 10 = CK toggling with normal polarity (This should be the default setting) 11 = CK disabled (Driven to constant 1) 26 6 read-write PUBMODE Enables, if set, the PUB to control the interface to the PHY and SDRAM. In this mode the DFI commands from the controller are ignored. The bit must be set to 0 after the system determines it is convenient to pass control of the DFI bus to the controller. When set to 0 the DFI interface has control of the PHY and SDRAM interface except when triggering pub operations such as BIST, DCU or data training. 25 1 read-write DTOSEL Digital Test Output Select: Selects the PHY digital test output that is driven onto PHY digital test output (phy_dto) pin: Valid values are: 00000 = DATX8 0 PLL digital test output 00001 = DATX8 1 PLL digital test output 00010 = DATX8 2 PLL digital test output 00011 = DATX8 3 PLL digital test output 00100 = DATX8 4 PLL digital test output 00101 = DATX8 5 PLL digital test output 00110 = DATX8 6 PLL digital test output 00111 = DATX8 7 PLL digital test output 01000 = DATX8 8 PLL digital test output 01001 = AC PLL digital test output 01010 – 01111 = Reserved 10000 = DATX8 0 delay line digital test output 10001 = DATX8 1 delay line digital test output 10010 = DATX8 2 delay line digital test output 10011 = DATX8 3 delay line digital test output 10100 = DATX8 4 delay line digital test output 10101 = DATX8 5 delay line digital test output 10110 = DATX8 6 delay line digital test output 10111 = DATX8 7 delay line digital test output 11000 = DATX8 8 delay line digital test output 11001 = AC delay line digital test output 11010 – 11111 = Reserved 14 5 read-write OSCWDL Oscillator Mode Write-Leveling Delay Line Select: Selects which of the two write leveling LCDLs is active. The delay select value of the inactive LCDL is set to zero while the delay select value of the active LCDL can be varied by the input write leveling delay select pin. Valid values are: 00 = No WL LCDL is active 01 = DDR WL LCDL is active 10 = SDR WL LCDL is active 11 = Both LCDLs are active 12 2 read-write OSCDIV Oscillator Mode Division: Specifies the factor by which the delay line oscillator mode output is divided down before it is output on the delay line digital test output pin dl_dto. Valid values are: 000 = Divide by 1 001 = Divide by 256 010 = Divide by 512 011 = Divide by 1024 100 = Divide by 2048 101 = Divide by 4096 110 = Divide by 8192 111 = Divide by 65536 9 3 read-write OSCEN Oscillator Enable: Enables, if set, the delay line oscillation. 8 1 read-write DLTST Delay Line Test Start: A write of '1' to this bit will trigger delay line oscillator mode period measurement. This bit is not self clearing and needs to be reset to '0' before the measurement can be re-triggered. 7 1 read-write DLTMODE Delay Line Test Mode: Selects, if set, the delay line oscillator test mode. Setting this bit also clears all delay line register values. For DL oscillator testing, first set this bit, then apply desired non-zero LCDL and BDL register programmings. 6 1 read-write RDBVT Read Data BDL VT Compensation: Enables, if set, the VT drift compensation of the read data bit delay lines. 5 1 read-write WDBVT Write Data BDL VT Compensation: Enables, if set, the VT drift compensation of the write data bit delay lines. 4 1 read-write RGLVT Read DQS Gating LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the read DQS gating LCDL. 3 1 read-write RDLVT Read DQS LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the read DQS LCDL. 2 1 read-write WDLVT Write DQ LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the write DQ LCDL. 1 1 read-write WLLVT Write Leveling LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the write leveling LCDL. 0 1 read-write PGCR1 PHY General Configuration Registers 0-1 (PGCR0- 1) 0xc 32 0x00000000 0xFFFFFFFF LBMODE Loopback Mode: Indicates, if set, that the PHY/PUB is in loopback mode. 31 1 read-write LBGDQS Loopback DQS Gating: Selects the DQS gating mode that should be used when the PHY is in loopback mode, including BIST loopback mode. Valid values are: 00 = DQS gate is always on 01 = DQS gate training will be triggered on the PUB 10 = DQS gate is set manually using software 11 = Reserved 29 2 read-write LBDQSS Loopback DQS Shift: Selects how the read DQS is shifted during loopback to ensure that the read DQS is centered into the read data eye. Valid values are: 1b0 = PUB sets the read DQS LCDL to 0 (internally). DQS is already shifted 90 degrees by write path 1b1 = The read DQS shift is set manually through software 28 1 read-write IOLB I/O Loop-Back Select: Selects where inside the I/O the loop-back of signals happens. Valid values are: 0 = Loopback is after output buffer; output enable must be asserted 1 = Loopback is before output buffer; output enable is don’t care 27 1 read-write INHVT VT Calculation Inhibit: Inhibits calculation of the next VT compensated delay line values. A value of 1 will inhibit the VT calculation. This bit should be set to 1 during writes to the delay line registers. 26 1 read-write DXHRST DX PHY High-Speed Reset: a Write of '0' to this bit resets the DX macro without resetting the PUB RTL logic. This bit is not self-clearing and a '1' must be written to de-assert the reset. 25 1 read-write ZCKSEL Impedance Clock Divider Select: Selects the divide ratio for the clock used by the impedance control logic relative to the clock used by the memory controller and SDRAM. Valid values are: 00 = Divide by 2 01 = Divide by 8 10 = Divide by 32 11 = Divide by 64 For more information, refer to “Impedance Calibration” on page 174. 23 2 read-write DLDLMT Delay Line VT Drift Limit: Specifies the minimum change in the delay line VT drift in one direction which should result in the assertion of the delay line VT drift status signal (vt_drift). The limit is specified in terms of delay select values. A value of 0 disables the assertion of delay line VT drift status signal. 15 8 read-write FDEPTH Filter Depth: Specifies the number of measurements over which all AC and DATX8 initial period measurements, that happen after reset or when calibration is manually triggered, are averaged. Valid values are: 00 = 2 01 = 4 10 = 8 11 = 16 13 2 read-write LPFDEPTH Low-Pass Filter Depth: Specifies the number of measurements over which MDL period measurements are filtered. This determines the time constant of the low pass filter. Valid values are: 00 = 2 01 = 4 10 = 8 11 = 16 11 2 read-write LPFEN Low-Pass Filter Enable: Enables, if set, the low pass filtering of MDL period measurements. 10 1 read-write MDLEN Master Delay Line Enable: Enables, if set, the AC master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or on when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high. 9 1 read-write IODDRM I/O DDR Mode (D3F I/O Only): Selects the DDR mode for the I/Os. These bits connect to bits [2:1] of the IOM pin of the SSTL I/O. For more information, refer to the SSTL I/O chapter in the DWC DDR PHY Databook. 7 2 read-write WLSELT Write Leveling Select Type: Selects the encoding type for the write leveling select signal depending on the desired setup/hold margins for the internal pipelines. Refer to the DDR PHY Databook for details of how the select type is used. Valid values are: 0 = Type 1: Setup margin of 90 degrees and hold margin of 90 degrees 1 = Type 2: Setup margin of 135 degrees and hold margin of 45 degrees 6 1 read-write ACHRST AC PHY High-Speed Reset: a Write of '0' to this bit resets the AC macro without resetting the PUB RTL logic. This bit is not self-clearing and a '1' must be written to de-assert the reset. 5 1 read-write WSLOPT Write System Latency Optimization: controls the insertion of a pipeline stage on the AC signals from the DFI interface to the PHY to cater for a negative write system latency (WSL) value (only -1 possible). 0x0 = A pipeline stage is inserted only if WL2 training results in a WSL of -1 for any rank 0x1 = Inserts a pipeline stage 4 1 read-write WLSTEP Write Leveling Step: Specifies the number of delay step-size increments during each step of write leveling. Valid values are: 0 = computed to be 1/2 of the associated lane's DXnGSR0.WLPRD value 1 = 1 step size 2 1 read-write WLMODE Write Leveling (Software) Mode: Indicates, if set, that the PUB is in software write leveling mode in which software executes single steps of DQS pulsing by writing '1' to PIR.WL. The write leveling DQ status from the DRAM is captured in DXnGSR0.WLDQ. 1 1 read-write PDDISDX Power Down Disabled Byte: Indicates, if set, that the PLL and I/Os of a disabled byte should be powered down. 0 1 read-write PGSR0 “PHY General Status Registers 0-1 (PGSR0-1)” on page 89 0x10 32 0x00000000 0xFFFFFFFF APLOCK AC PLL Lock: Indicates, if set, that AC PLL has locked. This is a direct status of the AC PLL lock pin. 31 1 read-only PLDONE_CHN PLL Lock Done per Channel: Indicates PLL locking has completed for each underlying channel. Bit 28 represents channel 0 while bit 29 represents channel 1. 28 2 read-only WEERR Write Eye Training Error: Indicates, if set, that there is an error in write eye training. 27 1 read-only REERR Read Data Eye Training Error: Indicates, if set, that there is an error in read eye training. 26 1 read-only WDERR Write Data Bit Deskew Error: Indicates, if set, that there is an error in write bit deskew. 25 1 read-only RDERR Read Data Bit Deskew Error: Indicates, if set, that there is an error in read bit deskew. 24 1 read-only WLAERR Write Data Leveling Adjustment Error: Indicates, if set, that there is an error in write leveling adjustment. 23 1 read-only QSGERR Read DQS Gate Training Error: Indicates, if set, that there is an error in DQS gate training. 22 1 read-only WLERR Write Leveling Error: Indicates, if set, that there is an error in write leveling. 21 1 read-only ZCERR Impedance Calibration Error: Indicates, if set, that there is an error in impedance calibration. 20 1 read-only WEDONE Write Data Eye Training Done: Indicates, if set, that write eye training has completed. 11 1 read-only REDONE Read Data Eye Training Done: Indicates, if set, that read eye training has completed. 10 1 read-only WDDONE Write Data Bit Deskew Done: Indicates, if set, that write bit deskew has completed. 9 1 read-only RDDONE Read Data Bit Deskew Done: Indicates, if set, that read bit deskew has completed. 8 1 read-only WLADONE Write Leveling Adjustment Done: Indicates, if set, that write leveling adjustment has completed. 7 1 read-only QSGDONE Read DQS Gate Training Done: Indicates, if set, that DQS gate training has completed. 6 1 read-only WLDONE Write Leveling Done: Indicates, if set, that write leveling has completed. 5 1 read-only DIDONE DRAM Initialization Done: Indicates, if set, that DRAM initialization has completed. 4 1 read-only ZCDONE Impedance Calibration Done: Indicates, if set, that impedance calibration has completed. 3 1 read-only DCDONE Digital Delay Line (DDL) Calibration Done: Indicates, if set, that DDL calibration has completed. 2 1 read-only PLDONE PLL Lock Done: Indicates, if set, that PLL locking has completed. 1 1 read-only IDONE Initialization Done: Indicates, if set, that the DDR system initialization has completed. This bit is set after all the selected initialization routines in PIR register have completed. 0 1 read-only PGSR1 “PHY General Status Registers 0-1 (PGSR0-1)” on page 89 0x14 32 0x00000000 0xFFFFFFFF PARERR RDIMM Parity Error: Indicates, if set, that there was a parity error (i.e. err_out_n was sampled low) during one of the transactions to the RDIMM buffer chip. This bit remains asserted until cleared by the PIR.CLRSR. 31 1 read-only VTSTOP VT Stop: Indicates, if set, that the VT calculation logic has stopped computing the next values for the VT compensated delay line values. After assertion of the PGCR.INHVT, the VTSTOP bit should be read to ensure all VT compensation logic has stopped computations before writing to the delay line registers. 30 1 read-only DLTCODE Delay Line Test Code: Returns the code measured by the PHY control block that corresponds to the period of the AC delay line digital test output. 1 24 read-only DLTDONE Delay Line Test Done: Indicates, if set, that the PHY control block has finished doing period measurement of the AC delay line digital test output. 0 1 read-only PLLCR “PLL Control Register (PLLCR)” on page 91 0x18 32 0x00000000 0xFFFFFFFF BYP PLL Bypass: Bypasses the PLL, if set, to 1. 31 1 read-write PLLRST PLL Rest: Resets the PLLs by driving the PLL reset pin. This bit is not self-clearing and a ‘0’ must be written to de-assert the reset. 30 1 read-write PLLPD PLL Power Down: Puts the PLLs in power down mode by driving the PLL power down pin. This bit is not self-clearing and a ‘0’ must be written to de-assert the power-down. 29 1 read-write FRQSEL PLL Frequency Select: Selects the operating range of the PLL. Valid values for PHYs that go up to 2133 Mbps are: 00 = PLL reference clock (ctl_clk/REF_CLK) ranges from 335MHz to 533MHz 01 = PLL reference clock (ctl_clk/REF_CLK) ranges from 225MHz to 385MHz 10 = Reserved 11 = PLL reference clock (ctl_clk/REF_CLK) ranges from 166MHz to 275MHz Valid values for PHYs that don’t go up to 2133 Mbps are: 00 = PLL reference clock (ctl_clk/REF_CLK) ranges from 250MHz to 400MHz 01 = PLL reference clock (ctl_clk/REF_CLK) ranges from 166MHz to 300MHz 10 = Reserved 11 = Reserved 18 2 read-write QPMODE PLL Quadrature Phase Mode: Enables, if set, the quadrature phase clock outputs. This mode is not used in this version of the PHY. 17 1 read-write CPPC Charge Pump Proportional Current Control 13 4 read-write CPIC Charge Pump Integrating Current Control 11 2 read-write GSHIFT Gear Shift: Enables, if set, rapid locking mode. 10 1 read-write ATOEN Analog Test Enable (ATOEN): Selects the analog test signal that is driven on the analog test output pin. Otherwise the analog test output is tri-stated. This allows analog test output pins from multiple PLLs to be connected together. Valid values are: 0000 = All PLL analog test signals are tri-stated 0001 = AC PLL analog test signal is driven out 0010 = DATX8 0 PLL analog test signal is driven out 0011 = DATX8 1 PLL analog test signal is driven out 0100 = DATX8 2 PLL analog test signal is driven out 0101 = DATX8 3 PLL analog test signal is driven out 0110 = DATX8 4 PLL analog test signal is driven out 0111 = DATX8 5 PLL analog test signal is driven out 1000 = DATX8 6 PLL analog test signal is driven out 1001 = DATX8 7 PLL analog test signal is driven out 1010 = DATX8 8 PLL analog test signal is driven out 1011 – 1111 = Reserved 6 4 read-write ATC Analog Test Control: Selects various PLL analog test signals to be brought out via PLL analog test output pin (pll_ato). Valid values are: 0000 = Reserved 0001 = vdd_ckin 0010 = vrfbf 0011 = vdd_cko 0100 = vp_cp 0101 = vpfil(vp) 0110 = Reserved 0111 = gd 1000 = vcntrl_atb 1001 = vref_atb 1010 = vpsf_atb 1011 – 1111 = Reserved 2 4 read-write DTC Digital Test Control: Selects various PLL digital test signals and other test mode signals to be brought out via bit [1] of the PLL digital test output (pll_dto[1]). Valid values are: 00 = ‘0’ (Test output is disabled) 01 = PLL x1 clock (X1) 10 = PLL reference (input) clock (REF_CLK) 11 = PLL feedback clock (FB_X1) 0 2 read-write PTR0 PHY Timing Registers 0-4 (PTR0-4) 0x1c 32 0x00000000 0xFFFFFFFF TPLLPD PLL Power-Down Time: Number of configuration or APB clock cycles that the PLL must remain in power-down mode, i.e. number of clock cycles from when PLL power-down pin is asserted to when PLL power-down pin is de-asserted. This must correspond to a value that is equal to or more than 1us. Default value corresponds to 1us. 21 11 read-write TPLLGS PLL Gear Shift Time: Number of configuration or APB clock cycles from when the PLL reset pin is de-asserted to when the PLL gear shift pin is de-asserted. This must correspond to a value that is equal to or more than 4us. Default value corresponds to 4us. 6 15 read-write TPHYRST PHY Reset Time: Number of configuration or APB clock cycles that the PHY reset must remain asserted after PHY calibration is done before the reset to the PHY is de-asserted. This is used to extend the reset to the PHY so that the reset is asserted for some clock cycles after the clocks are stable. Valid values are from 1 to 63 (the value must be non-zero). 0 6 read-write PTR1 PHY Timing Registers 0-4 (PTR0-4) 0x20 32 0x00000000 0xFFFFFFFF TPLLLOCK PLL Lock Time: Number of configuration or APB clock cycles for the PLL to stabilize and lock, i.e. number of clock cycles from when the PLL reset pin is de-asserted to when the PLL has lock and is ready for use. This must correspond to a value that is equal to or more than 100us. Default value corresponds to 100us. 16 16 read-write TPLLRST PLL Reset Time: Number of configuration or APB clock cycles that the PLL must remain in reset mode, i.e. number of clock cycles from when PLL power-down pin is de-asserted and PLL reset pin is asserted to when PLL reset pin is de-asserted. The setting must correspond to a value that is equal to, or greater than, 3us. 0 13 read-write PTR2 PHY Timing Registers 0-4 (PTR0-4) 0x24 32 0x00000000 0xFFFFFFFF TWLDLYS Write Leveling Delay Settling Time: Number of controller clock cycles from when a new value of the write leveling delay is applies to the LCDL to when to DQS high is driven high. This allows the delay to settle. 15 5 read-write TCALH Calibration Hold Time: Number of controller clock cycles from when the clock was disabled (cal_clk_en deasserted) to when calibration is enable (cal_en asserted). 10 5 read-write TCALS Calibration Setup Time: Number of controller clock cycles from when calibration is enabled (cal_en asserted) to when the calibration clock is asserted again (cal_clk_en asserted). 5 5 read-write TCALON Calibration On Time: Number of clock cycles that the calibration clock is enabled (cal_clk_en asserted). 0 5 read-write PTR3 PHY Timing Registers 0-4 (PTR0-4) 0x28 32 0x00000000 0xFFFFFFFF TDINIT1 DRAM Initialization Time 1: DRAM initialization time in DRAM clock cycles corresponding to the following: DDR3 = CKE high time to first command (tRFC + 10 ns or 5 tCK, whichever is bigger) DDR2 = CKE high time to first command (400 ns) Default value corresponds to DDR3 tRFC of 360ns at 1066 MHz. 20 9 read-write TDINIT0 DRAM Initialization Time 0: DRAM initialization time in DRAM clock cycles corresponding to the following: DDR3 = CKE low time with power and clock stable (500 us) DDR2 = CKE low time with power and clock stable (200 us) Default value corresponds to DDR3 500 us at 1066 MHz. During Verilog simulations, it is recommended that this value is changed to a much smaller value in order to avoid long simulation times. However, this may cause a memory model error, due to a violation of the CKE setup sequence. This violation is expected if this value is not programmed to the required SDRAM CKE low time, but memory models should be able to tolerate this violation without malfunction of the model. 0 20 read-write PTR4 PHY Timing Registers 0-4 (PTR0-4) 0x2c 32 0x00000000 0xFFFFFFFF TDINIT3 DRAM Initialization Time 3: DRAM initialization time in DRAM clock cycles corresponding to the following: DDR3 = Time from ZQ initialization command to first command (1 us) Default value corresponds to the DDR3 640ns at 1066 MHz. 18 10 read-write TDINIT2 DRAM Initialization Time 2: DRAM initialization time in DRAM clock cycles corresponding to the following: DDR3 = Reset low time (200 us on power-up or 100 ns after power-up) Default value corresponds to DDR3 200 us at 1066 MHz. 0 18 read-write ACMDLR “AC Master Delay Line Register (ACMDLR)” on page 96 0x30 32 0x00000000 0xFFFFFFFF MDLD MDL Delay: Delay select for the LCDL for the Master Delay Line. 16 8 read-write TPRD Target Period: Target period measured by the master delay line calibration for VT drift compensation. This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. 8 8 read-write IPRD Initial Period: Initial period measured by the master delay line calibration for VT drift compensation. This value is used as the denominator when calculating the ratios of updates during VT compensation. 0 8 read-write ACBDLR “AC Bit Delay Line Register (ACBDLR)” on page 96 0x34 32 0x00000000 0xFFFFFFFF ACBD Address/Command Bit Delay: Delay select for the BDLs on address and command signals. 18 6 read-write CK2BD CK2 Bit Delay: Delay select for the BDL on CK2. 12 6 read-write CK1BD CK1 Bit Delay: Delay select for the BDL on CK1. 6 6 read-write CK0BD CK0 Bit Delay: Delay select for the BDL on CK0. 0 6 read-write ACIOCR “AC I/O Configuration Register (ACIOCR)” on page 97 0x38 32 0x00000000 0xFFFFFFFF ACSR Address/Command Slew Rate (D3F I/O Only): Selects slew rate of the I/O for all address and command pins. 30 2 read-write RSTIOM SDRAM Reset I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for SDRAM Reset. 29 1 read-write RSTPDR SDRAM Reset Power Down Receiver: Powers down, when set, the input receiver on the I/O for SDRAM RST# pin. 28 1 read-write RSTPDD1 SDRAM Reset Power Down Driver: Powers down, when set, the output driver on the I/O for SDRAM RST# pin. 27 1 read-write RSTODT SDRAM Reset On-Die Termination: Enables, when set, the on-die termination on the I/O for SDRAM RST# pin. 26 1 read-write RANKPDR Rank Power Down Receiver: Powers down, when set, the input receiver on the I/O CKE[3:0], ODT[3:0], and CS#[3:0] pins. RANKPDR[0] controls the power down for CKE[0], ODT[0], and CS#[0], RANKPDR[1] controls the power down for CKE[1], ODT[1], and CS#[1], and so on. 22 4 read-write CSPDD1 CS# Power Down Driver: Powers down, when set, the output driver on the I/O for CS#[3:0] pins. CSPDD[0] controls the power down for CS#[0], CSPDD[1] controls the power down for CS#[1], and so on. CKE and ODT driver power down is controlled by DSGCR register. 18 4 read-write RANKODT Rank On-Die Termination: Enables, when set, the on-die termination on the I/O for CKE[3:0], ODT[3:0], and CS#[3:0] pins. RANKODT[0] controls the on-die termination for CKE[0], ODT[0], and CS#[0], RANKODT[1] controls the on-die termination for CKE[1], ODT[1], and CS#[1], and so on. 14 4 read-write CKPDR CK Power Down Receiver: Powers down, when set, the input receiver on the I/O for CK[0], CK[1], and CK[2] pins, respectively. 11 3 read-write CKPDD1 CK Power Down Driver: Powers down, when set, the output driver on the I/O for CK[0], CK[1], and CK[2] pins, respectively. 8 3 read-write CKODT CK On-Die Termination: Enables, when set, the on-die termination on the I/O for CK[0], CK[1], and CK[2] pins, respectively. 5 3 read-write ACPDR AC Power Down Receiver: Powers down, when set, the input receiver on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. 4 1 read-write ACPDD1 AC Power Down Driver: Powers down, when set, the output driver on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. 3 1 read-write ACODT Address/Command On-Die Termination: Enables, when set, the on-die termination on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. 2 1 read-write ACOE Address/Command Output Enable: Enables, when set, the output driver on the I/O for all address and command pins. 1 1 read-write ACIOM Address/Command I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for all address and command pins. This bit connects to bit [0] of the IOM pin on the D3F I/Os, and for other I/O libraries, it connects to the IOM pin of the I/O. 0 1 read-write DXCCR “DATX8 Common Configuration Register (DXCCR)” on page 99 0x3c 32 0x00000000 0xFFFFFFFF DDPDRCDO Dynamic Data Power Down Receiver Count Down Offset: Offset applied in calculating window of time where receiver is powered up 28 4 read-write DDPDDCDO Dynamic Data Power Down Driver Count Down Offset: Offset applied in calculating window of time where driver is powered up 24 4 read-write DYNDXPDR Data Power Down Receiver: Dynamically powers down, when set, the input receiver on I/O for the DQ pins of the active DATX8 macros. Applies only when DXPDR and DXnGCR.DXPDR are not set to 1. Receiver is powered-up on a DFI READ command and powered-down (trddata_en + fixed_read_latency + n) HDR cycles after the last DFI READ command. Note that n is defined by the register bit field DXCCR[31:28] (DDPDRCDO). 23 1 read-write DYNDXPDD1 Dynamic Data Power Down Driver: Dynamically powers down, when set, the output driver on I/O for the DQ pins of the active DATX8 macros. Applies only when DXPDD and DXnGCR.DXPDD are not set to 1. Driver is powered-up on a DFI WRITE command and powered-down (twrlat + WL/2 + n) HDR cycles after the last DFI WRITE command. Note that n is defined by the register bit field DXCCR[27:24] (DDPDDCDO). 22 1 read-write UDQIOM Unused DQ I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for unused DQ pins. 21 1 read-write UDQPDR Unused DQ Power Down Receiver: Powers down, when set, the input receiver on the I/O for unused DQ pins. 20 1 read-write UDQPDD1 Unused DQ Power Down Driver: Powers down, when set, the output driver on the I/O for unused DQ pins. 19 1 read-write UDQODT Unused DQ On-Die Termination: Enables, when set, the on-die termination on the I/O for unused DQ pins. 18 1 read-write MSBUDQ Most Significant Byte Unused DQs: Specifies the number of DQ bits that are not used in the most significant byte. The used (valid) bits for this byte are [8-MSBDQ- 1:0]. To disable the whole byte, use the DXnGCR.DXEN register. 15 3 read-write DXSR Data Slew Rate (D3F I/O Only): Selects slew rate of the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. 13 2 read-write DQSNRES DQS# Resistor: Selects the on-die pull-up/pull-down resistor for DQS# pins. Same encoding as DQSRES. Refer PHY databook for pull-down/pull-up resistor values (RA_SEL/RB_SEL) for DQS/DQS_b. 9 4 read-write DQSRES DQS Resistor: Selects the on-die pull-down/pull-up resistor for DQS pins. DQSRES[3] selects pull-down (when set to 0) or pull-up (when set to 1). DQSRES[2:0] selects the resistor value. Refer PHY databook for pull-down/pull-up resistor values (RA_SEL/RB_SEL) for DQS/DQS_b. 5 4 read-write DXPDR Data Power Down Receiver: Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the PDR configuration bit of the individual DATX8. 4 1 read-write DXPDD1 Data Power Down Driver: Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the PDD configuration bit of the individual DATX8. 3 1 read-write MDLEN Master Delay Line Enable: Enables, if set, all DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or on when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high. This bit is ANDed with the MDLEN bit in the individual DATX8. 2 1 read-write DXIOM Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the IOM configuration bit of the individual DATX8. 1 1 read-write DXODT Data On-Die Termination: Enables, when set, the on-die termination on the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the ODT configuration bit of the individual DATX8 (“DATX8 General Configuration Register (DXnGCR)” on page 148) 0 1 read-write DSGCR “DDR System General Configuration Register (DSGCR)” on page 101 0x40 32 0x00000000 0xFFFFFFFF CKEOE SDRAM CKE Output Enable: Enables, when set, the output driver on the I/O for SDRAM CKE pins. 31 1 read-write RSTOE SDRAM Reset Output Enable: Enables, when set, the output driver on the I/O for SDRAM RST# pin. 30 1 read-write ODTOE SDRAM ODT Output Enable: Enables, when set, the output driver on the I/O for SDRAM ODT pins. 29 1 read-write CKOE SDRAM CK Output Enable: Enables, when set, the output driver on the I/O for SDRAM CK/CK# pins. 28 1 read-write ODTPDD1 ODT Power Down Driver: Powers down, when set, the output driver on the I/O for ODT[3:0] pins. ODTPDD[0] controls the power down for ODT[0], ODTPDD[1] controls the power down for ODT[1], and so on. 24 4 read-write CKEPDD1 CKE Power Down Driver: Powers down, when set, the output driver on the I/O for CKE[3:0] pins. CKEPDD[0] controls the power down for CKE[0], CKEPDD[1] controls the power down for CKE[1], and so on. 20 4 read-write SDRMODE Single Data Rate Mode: Indicates, if set, that the external controller is configured to run in single data rate (SDR) mode. Otherwise if not set the controller is running in half data rate (HDR) mode. This bit not supported in the current version of the PUB. 19 1 read-write RRMODE Rise-to-Rise Mode: Indicates, if set, that the PHY mission mode is configured to run in rise-to-rise mode. Otherwise if not set the PHY mission mode is running in rise-to- fall mode. 18 1 read-write ATOAE ATO Analog Test Enable: Enables, if set, the analog test output (ATO) I/O. 17 1 read-write DTOOE DTO Output Enable: Enables, when set, the output driver on the I/O for DTO pins. 16 1 read-write DTOIOM DTO I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DTO pins. 15 1 read-write DTOPDR DTO Power Down Receiver: Powers down, when set, the input receiver on the I/O for DTO pins. 14 1 read-write DTOPDD1 DTO Power Down Driver: Powers down, when set, the output driver on the I/O for DTO pins. 13 1 read-write DTOODT DTO On-Die Termination: Enables, when set, the on-die termination on the I/O for DTO pins. 12 1 read-write PUAD PHY Update Acknowledge Delay: Specifies the number of clock cycles that the indication for the completion of PHY update from the PHY to the controller should be delayed. This essentially delays, by this many clock cycles, the de-assertion of dfi_ctrlup_ack and dfi_phyupd_req signals relative to the time when the delay lines or I/Os are updated. 8 4 read-write BRRMODE Bypass Rise-to-Rise Mode: Indicates, if set, that the PHY bypass mode is configured to run in rise-to-rise mode. Otherwise if not set the PHY bypass mode is running in rise-to-fall mode. 7 1 read-write DQSGX DQS Gate Extension: Specifies, if set, that the DQS gating must be extended by two DRAM clock cycles and then re-centered, i.e. one clock cycle extension on either side. 6 1 read-write CUAEN Controller Update Acknowledge Enable: Specifies, if set, that the PHY should issue controller update acknowledge when the DFI controller update request is asserted. By default the PHY does not acknowledge controller initiated update requests but simply does an update whenever there is a controller update request. This speeds up the update. 5 1 read-write LPPLLPD Low Power PLL Power Down: Specifies, if set, that the PHY should respond to the DFI low power opportunity request and power down the PLL of the byte if the wakeup time request satisfies the PLL lock time. 4 1 read-write LPIOPD Low Power I/O Power Down: Specifies, if set, that the PHY should respond to the DFI low power opportunity request and power down the I/Os of the byte. 3 1 read-write ZUEN Impedance Update Enable: Specifies, if set, that in addition to DDL VT update, the PHY could also perform impedance calibration (update). Refer to the “Impedance Control Register 0-1 (ZQnCR0-1)” on page 145 bit fields DFICU0, DFICU1 and DFICCU bits to control if an impedance calibration is performed (update) with a DFI controller update request. Refer to the “Impedance Control Register 0-1 (ZQnCR0-1)” on page 145 bit fields DFIPU0 and DFIPU1 bits to control if an impedance calibration is performed (update) with a DFI PHY update request. 2 1 read-write BDISEN Byte Disable Enable: Specifies, if set, that the PHY should respond to DFI byte disable request. Otherwise the byte disable from the DFI is ignored in which case bytes can only be disabled using the DXnGCR register. 1 1 read-write PUREN PHY Update Request Enable: Specifies if set, that the PHY should issue PHY- initiated update request when there is DDL VT drift. 0 1 read-write DCR “DRAM Configuration Register (DCR)” on page 103 0x44 32 0x00000000 0xFFFFFFFF UDIMM Un-buffered DIMM Address Mirroring: Indicates, if set, that there is address mirroring on the second rank of an un-buffered DIMM (the rank connected to CS#[1]). In this case, the PUB re-scrambles the bank and address when sending mode register commands to the second rank. This only applies to PUB internal SDRAM transactions. Transactions generated by the controller must make its own adjustments when using an un-buffered DIMM. DCR[NOSRA] must be set if address mirroring is enabled. 29 1 read-write DDR2T DDR 2T Timing: Indicates, if set, that 2T timing should be used by PUB internally generated SDRAM transactions. 28 1 read-write NOSRA No Simultaneous Rank Access: Specifies, if set, that simultaneous rank access on the same clock cycle is not allowed. This means that multiple chip select signals should not be asserted at the same time. This may be required on some DIMM systems. 27 1 read-write BYTEMASK Byte Mask: Mask applied to all beats of read data on all bytes lanes during read DQS gate training. This allows training to be conducted based on selected bit(s) from the byte lanes. Valid values for each bit are: 0 = Disable compare for that bit 1 = Enable compare for that bit Note that this mask applies in DDR3 MPR operation mode as well and must be in keeping with the PDQ field setting. 10 8 read-write MPRDQ Multi-Purpose Register (MPR) DQ (DDR3 Only): Specifies the value that is driven on non-primary DQ pins during MPR reads. Valid values are: 0 = Primary DQ drives out the data from MPR (0-1-0-1); non-primary DQs drive ‘0’ 1 = Primary DQ and non-primary DQs all drive the same data from MPR (0-1-0-1) 7 1 read-write PDQ Primary DQ (DDR3 Only): Specifies the DQ pin in a byte that is designated as a primary pin for Multi-Purpose Register (MPR) reads. Valid values are 0 to 7 for DQ[0] to DQ[7], respectively. 4 3 read-write DDR8BNK DDR 8-Bank: Indicates, if set, that the SDRAM used has 8 banks. tRPA = tRP+1 and tFAW are used for 8-bank DRAMs, otherwise tRPA = tRP and no tFAW is used. Note that a setting of 1 for DRAMs that have fewer than 8 banks results in correct functionality, but less tight DRAM command spacing for the parameters. 3 1 read-write DDRMD DDR Mode: SDRAM DDR mode. Valid values are: 000 = Reserved 001 = Reserved 010 = DDR2 011 = DDR3 100 – 111 = Reserved 0 3 read-write DTPR0 DRAM Timing Parameters Register 0-2 (DTPR0-2) 0x48 32 0x00000000 0xFFFFFFFF TRC Activate to activate command delay (same bank). Valid values are 2 to 63. 26 6 read-write TRRD Activate to activate command delay (different banks). Valid values are 1 to 15. 22 4 read-write TRAS Activate to precharge command delay. Valid values are 2 to 63. 16 6 read-write TRCD Activate to read or write delay. Minimum time from when an activate command is issued to when a read or write to the activated row can be issued. Valid values are 2 to 15. 12 4 read-write TRP Precharge command period: The minimum time between a precharge command and any other command. Note that the Controller automatically derives tRPA for 8- bank DDR2 devices by adding 1 to tRP. Valid values are 2 to 15. 8 4 read-write TWTR Internal write to read command delay. Valid values are 1 to 15. 4 4 read-write TRTP Internal read to precharge command delay. Valid values are 2 to 15. 0 4 read-write DTPR1 DRAM Timing Parameters Register 0-2 (DTPR0-2) 0x4c 32 0x00000000 0xFFFFFFFF TAOND_TAOFD ODT turn-on/turn-off delays (DDR2 only). Valid values are: 00 = 2/2.5 01 = 3/3.5 10 = 4/4.5 11 = 5/5.5 Most DDR2 devices utilize a fixed value of 2/2.5. For non-standard SDRAMs, the user must ensure that the operational Write Latency is always greater than or equal to the ODT turn-on delay. For example, a DDR2 SDRAM with CAS latency set to 3 and CAS additive latency set to 0 has a Write Latency of 2. Thus 2/2.5 can be used, but not 3/3.5 or higher. 30 2 read-write TWLO Write leveling output delay: Number of clock cycles from when write leveling DQS is driven high by the control block to when the results from the SDRAM on DQ is sampled by the control block. This must include the SDRAM tWLO timing parameter plus the round trip delay from control block to SDRAM back to control block. 26 4 read-write TWLMRD Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge. 20 6 read-write TRFC Refresh-to-Refresh: Indicates the minimum time between two refresh commands or between a refresh and an active command. This is derived from the minimum refresh interval from the datasheet, tRFC(min), divided by the clock cycle time. The default number of clock cycles is for the largest JEDEC tRFC(min parameter value supported. 11 9 read-write TFAW 4-bank activate period. No more than 4-bank activate commands may be issued in a given tFAW period. Only applies to 8-bank devices. Valid values are 2 to 63. 5 6 read-write TMOD Load mode update delay (DDR3 only). The minimum time between a load mode register command and a non-load mode register command. Valid values are: 000 = 12 001 = 13 010 = 14 011 = 15 100 = 16 101 = 17 110 – 111 = Reserved 2 3 read-write TMRD Load mode cycle time: The minimum time between a load mode register command and any other command. For DDR3 this is the minimum time between two load mode register commands. Valid values for DDR2 are 2 to 3. For DDR3, the value used for tMRD is 4 plus the value programmed in these bits, i.e. tMRD value for DDR3 ranges from 4 to 7. 0 2 read-write DTPR2 DRAM Timing Parameters Register 0-2 (DTPR0-2) 0x50 32 0x00000000 0xFFFFFFFF TCCD Read to read and write to write command delay. Valid values are: 0 = BL/2 for DDR2 and 4 for DDR3 1 = BL/2 + 1 for DDR2 and 5 for DDR3 31 1 read-write TRTW Read to Write command delay. Valid values are: 0 = standard bus turn around delay 1 = add 1 clock to standard bus turn around delay This parameter allows the user to increase the delay between issuing Write commands to the SDRAM when preceded by Read commands. This provides an option to increase bus turn-around margin for high frequency systems. 30 1 read-write TRTODT Read to ODT delay (DDR3 only). Specifies whether ODT can be enabled immediately after the read post-amble or one clock delay has to be added. Valid values are: 0 = ODT may be turned on immediately after read post-amble 1 = ODT may not be turned on until one clock after the read post-amble If tRTODT is set to 1, then the read-to-write latency is increased by 1 if ODT is enabled. 29 1 read-write TDLLK DLL locking time. Valid values are 2 to 1023. 19 10 read-write TCKE CKE minimum pulse width. Also specifies the minimum time that the SDRAM must remain in power down or self refresh mode. For DDR3 this parameter must be set to the value of tCKESR which is usually bigger than the value of tCKE. Valid values are 2 to 15. 15 4 read-write TXP Power down exit delay. The minimum time between a power down exit command and any other command. This parameter must be set to the maximum of the various minimum power down exit delay parameters specified in the SDRAM datasheet, i.e. max(tXP, tXARD, tXARDS) for DDR2 and max(tXP, tXPDLL) for DDR3. Valid values are 2 to 31. 10 5 read-write TXS Self refresh exit delay. The minimum time between a self refresh exit command and any other command. This parameter must be set to the maximum of the various minimum self refresh exit delay parameters specified in the SDRAM datasheet, i.e. max(tXSNR, tXSRD) for DDR2 and max(tXS, tXSDLL) for DDR3. Valid values are 2 to 1023. 0 10 read-write MR0 “Mode Register 0 (MR0)” on page 108 UNION_MR0 0x54 32 0x00000000 0xFFFFFFFF PD Power-Down Control: Controls the exit time for power-down modes. Refer to the SDRAM datasheet for details on power-down modes. Valid values are: 0 = Slow exit (DLL off) 1 = Fast exit (DLL on) 12 1 read-write WR Write Recovery: This is the value of the write recovery. It is calculated by dividing the datasheet write recovery time, tWR (ns) by the datasheet clock cycle time, tCK (ns) and rounding up a non-integer value to the next integer. Valid values are: 000 = 16 001 = 5 010 = 6 011 = 7 100 = 8 101 = 10 110 = 12 111 = 14 All other settings are reserved and should not be used. NOTE: tWR (ns) is the time from the first SDRAM positive clock edge after the last data-in pair of a write command, to when a precharge of the same bank can be issued. 9 3 read-write DR DLL Reset: Writing a ‘1’ to this bit will reset the SDRAM DLL. This bit is self- clearing, i.e. it returns back to ‘0’ after the DLL reset has been issued. 8 1 read-write TM Operating Mode: Selects either normal operating mode (0) or test mode (1). Test mode is reserved for the manufacturer and should not be used. 7 1 read-write CLH CAS Latency: The delay between when the SDRAM registers a read command to when data is available. Valid values are: 0010 = 5 0100 = 6 0110 = 7 1000 = 8 1010 = 9 1100 = 10 1110 = 11 0001 = 12 0011 = 13 0101 = 14 All other settings are reserved and should not be used. 4 3 read-write BT Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). 3 1 read-write CLL CAS Latency low bit 2 1 read-write BL Burst Length: Determines the maximum number of column locations that can be accessed during a given read or write command. Valid values are: Valid values for DDR3 are: 00 = 8 (Fixed) 01 = 4 or 8 (On the fly) 10 = 4 (Fixed) 11 = Reserved 0 2 read-write MR No description available UNION_MR0 0x54 32 0x00000000 0xFFFFFFFF PD Power-Down Control: Controls the exit time for power-down modes. Refer to the SDRAM datasheet for details on power-down modes. Valid values are: 0 = Fast exit 1 = Slow exit 12 1 read-write WR Write Recovery: This is the value of the write recovery. It is calculated by dividing the datasheet write recovery time, tWR (ns) by the datasheet clock cycle time, tCK (ns) and rounding up a non-integer value to the next integer. Valid values are: 001 = 2 010 = 3 011 = 4 100 = 5 101 = 6 All other settings are reserved and should not be used. NOTE: tWR (ns) is the time from the first SDRAM positive clock edge after the last data-in pair of a write command, to when a precharge of the same bank can be issued. 9 3 read-write DR DLL Reset: Writing a ‘1’ to this bit will reset the SDRAM DLL. This bit is self- clearing, i.e. it returns back to ‘0’ after the DLL reset has been issued. 8 1 read-write TM Operating Mode: Selects either normal operating mode (0) or test mode (1). Test mode is reserved for the manufacturer and should not be used. 7 1 read-write CL CAS Latency: The delay between when the SDRAM registers a read command to when data is available. Valid values are: 010 = 2 011 = 3 100 = 4 101 = 5 110 = 6 111 = 7 All other settings are reserved and should not be used. 4 3 read-write BT Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). 3 1 read-write BL Burst Length: Determines the maximum number of column locations that can be accessed during a given read or write command. Valid values are: 010 = 4 011 = 8 All other settings are reserved and should not be used. 0 3 read-write MR1 “Mode Register 1 (MR1)” on page 111 UNION_MR1 0x58 32 0x00000000 0xFFFFFFFF QOFF Output Enable/Disable: When ‘0’, all outputs function normal; when ‘1’ all SDRAM outputs are disabled removing output buffer current. This feature is intended to be used for IDD characterization of read current and should not be used in normal operation. 12 1 read-write TDQS Termination Data Strobe: When enabled (‘1’) TDQS provides additional termination resistance outputs that may be useful in some system configurations. Refer to the SDRAM datasheet for details. 11 1 read-write RTTH On Die Termination high bit 9 1 read-write LEVEL Write Leveling Enable: Enables write-leveling when set. 7 1 read-write RTTM On Die Termination mid bit: Selects the effective resistance for SDRAM on die termination. Valid values are: 000 = ODT disabled 001 = RZQ/4 010 = RZQ/2 011 = RZQ/6 100 = RZQ/12 101 = RZQ/8 All other settings are reserved and should not be used. Bit on [9, 6,2] 6 1 read-write DICH Output Driver Impedance Control high bit: Controls the output drive strength. Valid values are: 00 = RZQ/6 01 = RZQ7 10 = Reserved 11 = Reserved 5 1 read-write AL Posted CAS Additive Latency: Setting additive latency that allows read and write commands to be issued to the SDRAM earlier than normal (refer to the SDRAM datasheet for details). Valid values are: 00 = 0 (AL disabled) 01 = CL - 1 10 = CL - 2 11 = Reserved 3 2 read-write RTTL On Die Termination low bit 2 1 read-write DICL Output Driver Impedance Control low bit 1 1 read-write DE DLL Enable/Disable: Enable (0) or disable (1) the DLL. DLL must be enabled for normal operation. Note: SDRAM DLL off mode is not supported 0 1 read-write EMR No description available UNION_MR1 0x58 32 0x00000000 0xFFFFFFFF QOFF Output Enable/Disable: When ‘0’, all outputs function normal; when ‘1’ all SDRAM outputs are disabled removing output buffer current. This feature is intended to be used for IDD characterization of read current and should not be used in normal operation. 12 1 read-write RDQS RDQS Enable/Disable: When enabled (‘1’), RDQS is identical in function and timing to data strobe DQS during a read, and ignored during a write. A ‘0’ disables the SDRAM from driving RDQS. The Controller does not allow the user to change this bit. 11 1 read-write DQS DQS_b Enable/Disable: When ‘0’, DQS_b is the complement of the differential data strobe pair DQS/DQS_b. When ‘1’, DQS is used in a single-ended mode and the DQS_b pin is disabled. Also used to similarly enable/disable RDQS_b if RDQS is enabled. The Controller does not allow the user to change this bit. 10 1 read-write OCD Off-Chip Driver (OCD) Impedance Calibration: Used to calibrate and match pull-up to pull- down impedance to 18  nominal (refer to the SDRAM datasheet for details). Valid values are: 000 = OCD calibration mode exit 001 = Drive (1) pull-up 010 = Drive (0) pull-down 100 = OCD enter adjust mode 111 = OCD calibration default All other settings are reserved and should not be used. Note that OCD is not supported by all vendors. Refer to the SDRAM datasheet for details on the recommended OCD settings. 7 3 read-write RTTH On Die Termination high bit: Selects the effective resistance for SDRAM on die termination. Valid values are: 00 = ODT disabled 01 = 75 10 = 150 11 = 50 (some vendors) 6 1 read-write AL Posted CAS Additive Latency: Setting additive latency that allows read and write commands to be issued to the SDRAM earlier than normal (refer to the SDRAM datasheet for details). Valid values are: 000 = 0 001 = 1 010 = 2 011 = 3 100 = 4 101 = 5 All other settings are reserved and should not be used. The maximum allowed value of AL is tRCD-1. 3 3 read-write RTTL On Die Termination low bit: 2 1 read-write DIC Output Driver Impedance Control: Controls the output drive strength. Valid values are: 0 = Full strength 1 = Reduced strength 1 1 read-write DE DLL Enable/Disable: Enable (0) or disable (1) the DLL. DLL must be enabled for normal operation. 0 1 read-write MR2 “Mode Register 2/Extended Mode Register 2 (MR2/EMR2)” on page 114 UNION_MR2 0x5c 32 0x00000000 0xFFFFFFFF RTTWR Dynamic ODT: Selects RTT for dynamic ODT. Valid values are: 00 = Dynamic ODT off 01 = RZQ/4 10 = RZQ/2 11 = Reserved 9 2 read-write SRT Self-Refresh Temperature Range: Selects either normal (‘0’) or extended (‘1’) operating temperature range during self-refresh. 7 1 read-write ASR Auto Self-Refresh: When enabled (‘1’), SDRAM automatically provides self-refresh power management functions for all supported operating temperature values. Otherwise the SRT bit must be programmed to indicate the temperature range. 6 1 read-write CWL CAS Write Latency: The delay between when the SDRAM registers a write command to when write data is available. Valid values are: 000 = 5 (tCK > 2.5ns) 001 = 6 (2.5ns > tCK > 1.875ns) 010 = 7 (1.875ns > tCK> 1.5ns) 011 = 8 (1.5ns > tCK > 1.25ns) 100 = 9 (1.25ns > tCK > 1.07ns) 101 = 10 (1.07ns > tCK > 0.935ns) 110 = 11 (0.935ns > tCK > 0.833ns) 111 = 12 (0.833ns > tCK > 0.75ns) All other settings are reserved and should not be used. 3 3 read-write PASR Partial Array Self Refresh: Specifies that data located in areas of the array beyond the specified location will be lost if self refresh is entered. Valid settings for 4 banks are: 000 = Full Array 001 = Half Array (BA[1:0] = 00 & 01) 010 = Quarter Array (BA[1:0] = 00) 011 = Not defined 100 = 3/4 Array (BA[1:0] = 01, 10, & 11) 101 = Half Array (BA[1:0] = 10 & 11) 110 = Quarter Array (BA[1:0] = 11) 111 = Not defined Valid settings for 8 banks are: 000 = Full Array 001 = Half Array (BA[2:0] = 000, 001, 010 & 011) 010 = Quarter Array (BA[2:0] = 000, 001) 011 = 1/8 Array (BA[2:0] = 000) 100 = 3/4 Array (BA[2:0] = 010, 011, 100, 101, 110 & 111) 101 = Half Array (BA[2:0] = 100, 101, 110 & 111) 110 = Quarter Array (BA[2:0] = 110 & 111) 111 = 1/8 Array (BA[2:0] 111) 0 3 read-write EMR2 No description available UNION_MR2 0x5c 32 0x00000000 0xFFFFFFFF SRF Self Refresh Rate: Enables, if set, high temperature self refresh rate. 7 1 read-write DCC Duty Cycle Corrector: Enables, if set, duty cycle correction within SDRAM. 3 1 read-write PASR Partial Array Self Refresh: Specifies that data located in areas of the array beyond the specified location will be lost if self refresh is entered. Valid settings for 4 banks are: 000 = Full Array 001 = Half Array (BA[1:0] = 00 & 01) 010 = Quarter Array (BA[1:0] = 00) 011 = Not defined 100 = 3/4 Array (BA[1:0] = 01, 10, & 11) 101 = Half Array (BA[1:0] = 10 & 11) 110 = Quarter Array (BA[1:0] = 11) 111 = Not defined Valid settings for 8 banks are: 000 = Full Array 001 = Half Array (BA[2:0] = 000, 001, 010 & 011) 010 = Quarter Array (BA[2:0] = 000, 001) 011 = 1/8 Array (BA[2:0] = 000) 100 = 3/4 Array (BA[2:0] = 010, 011, 100, 101, 110 & 111) 101 = Half Array (BA[2:0] = 100, 101, 110 & 111) 110 = Quarter Array (BA[2:0] = 110 & 111) 111 = 1/8 Array (BA[2:0] 111) 0 3 read-write MR3 “Mode Register 3 (MR3)” on page 116 UNION_MR3 0x60 32 0x00000000 0xFFFFFFFF MPR Multi-Purpose Register Enable: Enables, if set, that read data should come from the Multi-Purpose Register. Otherwise read data come from the DRAM array. 2 1 read-write MPRLOC Multi-Purpose Register (MPR) Location: Selects MPR data location: Valid value are: 00 = Predefined pattern for system calibration All other settings are reserved and should not be used. 0 2 read-write EMR3 No description available UNION_MR3 0x60 32 0x00000000 0xFFFFFFFF ODTCR “ODT Configuration Register (ODTCR)” on page 117 0x64 32 0x00000000 0xFFFFFFFF WRODT3 No description available 28 4 read-write WRODT2 No description available 24 4 read-write WRODT1 No description available 20 4 read-write WRODT0 Write ODT: Specifies whether ODT should be enabled (‘1’) or disabled (‘0’) on each of the up to four ranks when a write command is sent to rank n. WRODT0, WRODT1, WRODT2, and WRODT3 specify ODT settings when a write is to rank 0, rank 1, rank 2, and rank 3, respectively. The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3. Default is to enable ODT only on rank being written to. 16 4 read-write RDODT3 No description available 12 4 read-write RDODT2 No description available 8 4 read-write RDODT1 No description available 4 4 read-write RDODT0 Read ODT: Specifies whether ODT should be enabled (‘1’) or disabled (‘0’) on each of the up to four ranks when a read command is sent to rank n. RDODT0, RDODT1, RDODT2, and RDODT3 specify ODT settings when a read is to rank 0, rank 1, rank 2, and rank 3, respectively. The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3. Default is to disable ODT during reads. 0 4 read-write DTCR “Data Training Configuration Register (DTCR)” on page 118 0x68 32 0x00000000 0xFF7FFFFF RFSHDT Refresh During Training: A non-zero value specifies that a burst of refreshes equal to the number specified in this field should be sent to the SDRAM after training each rank except the last rank. 28 4 read-write RANKEN Rank Enable: Specifies the ranks that are enabled for data-training. Bit 0 controls rank 0, bit 1 controls rank 1, bit 2 controls rank 2, and bit 3 controls rank 3. Setting the bit to ‘1’ enables the rank, and setting it to ‘0’ disables the rank. 24 4 read-write DTEXD Data Training Extended Write DQS: Enables, if set, an extended write DQS whereby two additional pulses of DQS are added as post-amble to a burst of writes. Generally this should only be enabled when running read bit deskew with the intention of performing read eye deskew prior to running write leveling adjustment. 22 1 read-write DTDSTP Data Training Debug Step: A write of 1 to this bit steps the data training algorithm through a single step. This bit is used to initiate one step of the data training algorithm in question. This bit is self-clearing. To trigger the next step, this bit must be written to again. Note: The training steps must be repeated in order to get new data in the “Data Training Eye Data Register 0-1 (DTEDR0-1)” on page 122. For example, to see the training results for a different lane, select that lane and repeat the training steps to populate DTEDR0 and DTEDR1 with the correct data. 21 1 read-write DTDEN Data Training Debug Enable: Enables, if set, the data training single step debug mode. 20 1 read-write DTDBS Data Training Debug Byte Select: Selects the byte during data training single step debug mode. Note: DTDEN is not used to enable this feature. 16 4 read-write DTWDQMO Data Training WDQ Margin Override: If set, the Training WDQ Margin value specified in DTCR[11:8] (DTWDQM) is used during data training. Otherwise the value is computed as ¼ of the ddr_clk period measurement found during calibration of the WDQ LCDL. 14 1 read-write DTBDC Data Training Bit Deskew Centering: Enables, if set, eye centering capability during write and read bit deskew training. 13 1 read-write DTWBDDM Data Training Write Bit Deskew Data Mask, if set, it enables write bit deskew of the data mask 12 1 read-write DTWDQM Training WDQ Margin: Defines how close to 0 or how close to 2*(wdq calibration_value) the WDQ LCDL can be moved during training. Basically defines how much timing margin. 8 4 read-write DTCMPD Read Data Training Compare Data: Specifies, if set, that DQS gate training should also check if the returning read data is correct. Otherwise data-training only checks if the correct number of DQS edges were returned. 7 1 read-write DTMPR Read Data Training Using MPR (DDR3 Only): Specifies, if set, that DQS gate training should use the SDRAM Multi-Purpose Register (MPR) register. Otherwise data-training is performed by first writing to some locations in the SDRAM and then reading them back. 6 1 read-write DTRANK Data Training Rank: Select the SDRAM rank to be used during Read DQS gate training, Read/Write Data Bit Deskew, Read/Write Eye Training. 4 2 read-write DTRPTN Data Training Repeat Number: Repeat number used to confirm stability of DDR write or read. Note: The minimum value should be 0x4 and the maximum value should be 0x14. 0 4 read-write DTAR0 Data Training Address Register 0-3 (DTAR0-3) 0x6c 32 0x00000000 0xFFFFFFFF DTBANK Data Training Bank Address: Selects the SDRAM bank address to be used during data training. 28 3 read-write DTROW Data Training Row Address: Selects the SDRAM row address to be used during data training. 12 16 read-write DTCOL Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. 0 12 read-write DTAR1 Data Training Address Register 0-3 (DTAR0-3) 0x70 32 0x00000000 0xFFFFFFFF DTBANK Data Training Bank Address: Selects the SDRAM bank address to be used during data training. 28 3 read-write DTROW Data Training Row Address: Selects the SDRAM row address to be used during data training. 12 16 read-write DTCOL Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. 0 12 read-write DTAR2 Data Training Address Register 0-3 (DTAR0-3) 0x74 32 0x00000000 0xFFFFFFFF DTBANK Data Training Bank Address: Selects the SDRAM bank address to be used during data training. 28 3 read-write DTROW Data Training Row Address: Selects the SDRAM row address to be used during data training. 12 16 read-write DTCOL Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. 0 12 read-write DTAR3 Data Training Address Register 0-3 (DTAR0-3) 0x78 32 0x00000000 0xFFFFFFFF DTBANK Data Training Bank Address: Selects the SDRAM bank address to be used during data training. 28 3 read-write DTROW Data Training Row Address: Selects the SDRAM row address to be used during data training. 12 16 read-write DTCOL Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. 0 12 read-write DTDR0 Data Training Eye Data Register 0-1 (DTEDR0-1) 0x7c 32 0x00000000 0xFFFFFFFF DTBYTE3 No description available 24 8 read-write DTBYTE2 No description available 16 8 read-write DTBYTE1 No description available 8 8 read-write DTBYTE0 Data Training Data: The first 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle. 0 8 read-write DTDR1 Data Training Eye Data Register 0-1 (DTEDR0-1) 0x80 32 0x00000000 0xFFFFFFFF DTBYTE7 No description available 24 8 read-write DTBYTE6 No description available 16 8 read-write DTBYTE5 No description available 8 8 read-write DTBYTE4 Data Training Data: The second 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle. 0 8 read-write DTEDR0 Data Training Eye Data Register 0-1 (DTEDR0-1) 0x84 32 0x00000000 0xFFFFFFFF DTWBMX Data Training Write BDL Shift Maximum. 24 8 read-only DTWBMN Data Training Write BDL Shift Minimum. 16 8 read-only DTWLMX Data Training WDQ LCDL Maximum. 8 8 read-only DTWLMN Data Training WDQ LCDL Minimum. 0 8 read-only DTEDR1 Data Training Eye Data Register 0-1 (DTEDR0-1) 0x88 32 0x00000000 0xFFFFFFFF DTRBMX Data Training Read BDL Shift Maximum. 24 8 read-only DTRBMN Data Training Read BDL Shift Minimum. 16 8 read-only DTRLMX Data Training RDQS LCDL Maximum. 8 8 read-only DTRLMN Data Training RDQS LCDL Minimum. 0 8 read-only PGCR2 “PHY General Configuration Register 2 (PGCR2)” on page 87 0x8c 32 0x00000000 0xFFFFFFFF DYNACPDD1 Dynamic AC Power Down Driver: Powers down, when set, the output driver on I/O for ADDR and BA. This bit is ORed with bit ACIOCR[3] (ACPDD). 31 1 read-write LPMSTRC0 Low-Power Master Channel 0: set to 1 to have channel 0 act as master to drive channel 1 low-power functions simultaneously. Only valid in shared-AC mode. 30 1 read-write ACPDDC AC Power-Down with Dual Channels: Set to 1 to power-down address/command lane when both data channels are powered-down. Only valid in shared-AC mode. 29 1 read-write SHRAC Shared-AC mode: set to 1 to enable shared address/command mode with two independent data channels – available only if shared address/command mode support is compiled in. 28 1 read-write DTPMXTMR Data Training PUB Mode Timer Exit: Specifies the number of controller clocks to wait when entering and exiting pub mode data training. The default value ensures controller refreshes do not cause memory model errors when entering and exiting data training. The value should be increased if controller initiated SDRAM ZQ short or long operation may occur just before or just after the execution of data training. 20 8 read-write FXDLAT Fixed Latency: Specified whether all reads should be returned to the controller with a fixed read latency. Enabling fixed read latency increases the read latency. Valid values are: 0 = Disable fixed read latency 1 = Enable fixed read latency Fixed read latency is calculated as (12 + (maximum DXnGTR.RxDGSL)/2) HDR clock cycles 19 1 read-write NOBUB No Bubbles: Specified whether reads should be returned to the controller with no bubbles. Enabling no-bubble reads increases the read latency. Valid values are: 0 = Bubbles are allowed during reads 1 = Bubbles are not allowed during reads 18 1 read-write TREFPRD Refresh Period: Indicates the period, after which the PUB has to issue a refresh command to the SDRAM. This is derived from the maximum refresh interval from the datasheet, tRFC(max) or REFI, divided by the clock cycle time. A further 400 clocks must be subtracted from the derived number to account for command flow and missed slots of refreshes in the internal PUB blocks. The default corresponds to DDR3 9*7.8us at 1066MHz when a burst of 9 refreshes are issued at every refresh interval. 0 18 read-write RDIMMGCR0 RDIMM General Configuration Register 0-1 (RDIMMGCR0-1) 0xb0 32 0x00000000 0xFFFFFFFF MIRROR RDIMM Mirror: Selects between two different ballouts of the RDIMM buffer chip for front or back operation. This register bit controls the buffer chip MIRROR signal. 31 1 read-only QCSEN RDMIMM Quad CS Enable: Enables, if set, the Quad CS mode for the RDIMM registering buffer chip. This register bit controls the buffer chip QCSEN# signal. 30 1 read-only MIRROROE MIRROR Output Enable: Enables, when set, the output driver on the I/O for MIRROR pin. 29 1 read-only QCSENOE QCSEN# Output Enable: Enables, when set, the output driver on the I/O for QCSEN# pin. 28 1 read-only RDIMMIOM RDIMM Outputs I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for QCSEN# and MIRROR pins. 27 1 read-only RDIMMPDR RDIMM Outputs Power Down Receiver: Powers down, when set, the input receiver on the I/O for QCSEN# and MIRROR pins. 26 1 read-only RDIMMPDD RDIMM Outputs Power Down Driver: Powers down, when set, the output driver on the I/O for QCSEN# and MIRROR pins. 25 1 read-only RDIMMODT RDIMM Outputs On-Die Termination: Enables, when set, the on-die termination on the I/O for QCSEN# and MIRROR pins. 24 1 read-only ERROUTOE ERROUT# Output Enable: Enables, when set, the output driver on the I/O for ERROUT# pin. 23 1 read-only ERROUTIOM ERROUT# I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for ERROUT# pin. 22 1 read-only ERROUTPDR ERROUT# Power Down Receiver: Powers down, when set, the input receiver on the I/O for ERROUT# pin. 21 1 read-only ERROUTPDD ERROUT# Power Down Driver: Powers down, when set, the output driver on the I/O for ERROUT# pin. 20 1 read-only ERROUTODT ERROUT# On-Die Termination: Enables, when set, the on-die termination on the I/O for ERROUT# pin. 19 1 read-only PARINOE PAR_IN Output Enable: Enables, when set, the output driver on the I/O for PAR_IN pin. 18 1 read-only PARINIOM PAR_IN I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for PAR_IN pin. 17 1 read-only PARINPDR PAR_IN Power Down Receiver: Powers down, when set, the input receiver on the I/O for PAR_IN pin. 16 1 read-only PARINPDD PAR_IN Power Down Driver: Powers down, when set, the output driver on the I/O for PAR_IN pin. 15 1 read-only PARINODT PAR_IN On-Die Termination: Enables, when set, the on-die termination on the I/O for PAR_IN pin. 14 1 read-only SOPERR Stop On Parity Error: Indicates, if set, that the PUB is to stop driving commands to the DRAM upon encountering a parity error. Transactions can resume only after status is cleared via PIR.CLRSR. 2 1 read-only ERRNOREG Parity Error No Registering: Indicates, if set, that parity error signal from the RDIMM should be passed to the DFI controller without any synchronization or registering. Otherwise, the error signal is synchronized as shown in Figure 4-30 on page 262. 1 1 read-only RDIMM Registered DIMM: Indicates, if set, that a registered DIMM is used. In this case, the PUB increases the SDRAM write and read latencies (WL/RL) by 1 and also enforces that accesses adhere to RDIMM buffer chip. This only applies to PUB internal SDRAM transactions. Transactions generated by the controller must make its own adjustments to WL/RL when using a registered DIMM. The DCR.NOSRA register bit must be set to ‘1’ if using the standard RDIMM buffer chip so that normal DRAM accesses do not assert multiple chip select bits at the same time. 0 1 read-only RDIMMGCR1 RDIMM General Configuration Register 0-1 (RDIMMGCR0-1) 0xb4 32 0x00000000 0xFFFFFFFF CRINIT Control Registers Initialization Enable: Indicates which RDIMM buffer chip control registers (RC0 to RC15) should be initialized (written) when the PUB is triggered to initialize the buffer chip. A setting of ‘1’ on CRINIT[n] bit means that CRn should be written during initialization. 16 16 read-only TBCMRD Command word to command word programming delay: Number of DRAM clock cycles between two RDIMM buffer chip command programming accesses. The value used for tBCMRD is 8 plus the value programmed in these bits, i.e. tBCMRD value ranges from 8 to 15. This parameter corresponds to the buffer chip tMRD parameter. 12 3 read-only TBCSTAB Stabilization time: Number of DRAM clock cycles for the RDIMM buffer chip to stabilize. This parameter corresponds to the buffer chip tSTAB parameter. Default value is in decimal format and corresponds to 6us at 533MHz. 0 12 read-only RDIMMCR0 RDIMM Control Register 0-1 (RDIMMCR0-1) 0xb8 32 0x00000000 0xFFFFFFFF RC7 Control Word 7: Reserved, free to use by vendor. 28 4 read-only RC6 Control Word 6: Reserved, free to use by vendor. 24 4 read-only RC5 Control Word 5 (CK Driver Characteristics Control Word): RC5[1:0] is driver settings for clock Y1, Y1#, Y3, and Y3# outputs, and RC5[3:2] is driver settings for clock Y0, Y0#, Y2, and Y2# outputs. Bit definitions are: 00 = Light drive (4 or 5 DRAM loads) 01 = Moderate drive (8 or 10 DRAM loads) 10 = Strong drive (16 or 20 DRAM loads) 11 = Reserved 20 4 read-only RC4 Control Word 4 (Control Signals Driver Characteristics Control Word): RC4[1:0] is driver settings for control A outputs, and RC4[3:2] is driver settings for control B outputs. Bit definitions are: 00 = Light drive (4 or 5 DRAM loads) 01 = Moderate drive (8 or 10 DRAM loads) 10 = Reserved 11 = Reserved 16 4 read-only RC3 Control Word 3 (Command/Address Signals Driver Characteristics Control Word): RC3[1:0] is driver settings for command/address A outputs, and RC3[3:2] is driver settings for command/address B outputs. Bit definitions are: 00 = Light drive (4 or 5 DRAM loads) 01 = Moderate drive (8 or 10 DRAM loads) 10 = Strong drive (16 or 20 DRAM loads) 11 = Reserved 12 4 read-only RC2 Control Word 2 (Timing Control Word): Bit definitions are: RC2[0]: 0 = Standard (1/2 clock) pre-launch, 1 = Prelaunch controlled by RC12. RC2[1]: 0 = Reserved. RC2[2]: 0 = 100 Ohm input bus termination, 1 = 150 Ohm input bus termination. RC2[3]: 0 = Operation frequency band 1, 1 = Test mode frequency band 2. 8 4 read-only RC1 Control Word 1 (Clock Driver Enable Control Word): Bit definitions are: RC1[0]: 0 = Y0/Y0# clock enabled, 1 = Y0/Y0# clock disabled. RC1[1]: 0 = Y1/Y1# clock enabled, 1 = Y1/Y1# clock disabled. RC1[2]: 0 = Y2/Y2# clock enabled, 1 = Y2/Y2# clock disabled. RC1[3]: 0 = Y3/Y3# clock enabled, 1 = Y3/Y3# clock disabled. 4 4 read-only RC0 Control Word 0 (Global Features Control Word): Bit definitions are: RC0[0]: 0 = Output inversion enabled, 1 = Output inversion disabled. RC0[1]: 0 = Floating outputs disabled, 1 = Floating outputs enabled. RC0[2]: 0 = A outputs enabled, 1 = A outputs disabled. RC0[3]: 0 = B outputs enabled, 1 = B outputs disabled. 0 4 read-only RDIMMCR1 RDIMM Control Register 0-1 (RDIMMCR0-1) 0xbc 32 0x00000000 0xFFFFFFFF RC15 Control Word 15: Reserved for future use. 28 4 read-only RC14 Control Word 14: Reserved for future use. 24 4 read-only RC13 Control Word 13: Reserved for future use. 20 4 read-only RC12 Control Word 12: Reserved for future use. 16 4 read-only RC11 Control Word 11 (Operating Voltage VDD Control Word): RC10[1:0] is VDD operating voltage setting as follows: 00 = DDR3 1.5V mode 01 = DDR3L 1.35V mode 10 = Reserved 11 = Reserved RC10[3:2]: Reserved. 12 4 read-only RC10 Control Word 10 (RDIMM Operating Speed Control Word): RC10[2:0] is RDIMM operating speed setting as follows: 000 = DDR3/DDR3L-800 001 = DDR3/DDR3L-1066 010 = DDR3/DDR3L-1333 011 = DDR3/DDR3L-1600 100 = Reserved 101 = Reserved 110 = Reserved 111 = Reserved RC10[3]: Don’t care. 8 4 read-only RC9 Control Word 9 (Power Saving Settings Control Word): Bit definitions are: RC9[0]: 0 = Floating outputs as defined in RC0, 1 = Weak drive enabled. RC9[1]: 0 = Reserved. RC9[2]: 0 = CKE power down with IBT ON, QxODT is a function of DxODT, 1 = CKE power down with IBT off, QxODT held LOW. RC9[2] is valid only when RC9[3] is 1. RC9[3]: 0 = CKE power down mode disabled, 1 = CKE power down mode enabled. 4 4 read-only RC8 Control Word 8 (Additional Input Bus Termination Setting Control Word): RC8[2:0] is Input Bus Termination (IBT) setting as follows: 000 = IBT as defined in RC2. 001 = Reserved 010 = 200 Ohm 011 = Reserved 100 = 300 Ohm 101 = Reserved 110 = Reserved 111 = Off RC8[3]: 0 = IBT off when MIRROR is HIGH, 1 = IBT on when MIRROR is high 0 4 read-only DCUAR “DCU Address Register (DCUAR)” on page 129 0xc0 32 0x00000000 0xFFFFFFFF ATYPE Access Type: Specifies the type of access to be performed using this address. Valid values are: 0 = Write access 1 = Read access 11 1 read-write INCA Increment Address: Specifies, if set, that the cache address specified in WADDR and SADDR should be automatically incremented after each access of the cache. The increment happens in such a way that all the slices of a selected word are first accessed before going to the next word. 10 1 read-write CSEL Cache Select: Selects the cache to be accessed. Valid values are: 00 = Command cache 01 = Expected data cache 10 = Read data cache 11 = Reserved 8 2 read-write CSADDR Cache Slice Address: Address of the cache slice to be accessed. 4 4 read-write CWADDR Cache Word Address: Address of the cache word to be accessed. 0 4 read-write DCUDR “DCU Data Register (DCUDR)” on page 130 0xc4 32 0x00000000 0xFFFFFFFF CDATA Cache Data: Data to be written to or read from a cache. This data corresponds to the cache word slice specified by the DCU Address Register. 0 32 read-write DCURR “DCU Run Register (DCURR)” on page 130 0xc8 32 0x00000000 0xFFFFFFFF XCEN Expected Compare Enable: Indicates, if set, that read data coming back from the SDRAM should be should be compared with the expected data. 23 1 read-write RCEN Read Capture Enable: Indicates, if set, that read data coming back from the SDRAM should be captured into the read data cache. 22 1 read-write SCOF Stop Capture On Full: Specifies, if set, that the capture of read data should stop when the capture cache is full. 21 1 read-write SONF Stop On Nth Fail: Specifies, if set, that the execution of commands and the capture of read data should stop when there are N read data failures. The number of failures is specified by NFAIL. Otherwise commands execute until the end of the program or until manually stopped using a STOP command. 20 1 read-write NFAIL Number of Failures: Specifies the number of failures after which the execution of commands and the capture of read data should stop if SONF bit of this register is set. Execution of commands and the capture of read data will stop after (NFAIL+1) failures if SONF is set. Valid values are from 0 to 254. 12 8 read-write EADDR End Address: Cache word address where the execution of command should end. 8 4 read-write SADDR Start Address: Cache word address where the execution of commands should begin. 4 4 read-write DINST DCU Instruction: Selects the DCU command to be executed: Valid values are: 0000 = NOP: No operation 0001 = Run: Triggers the execution of commands in the command cache. 0010 = Stop: Stops the execution of commands in the command cache. 0011 = Stop Loop: Stops the execution of an infinite loop in the command cache. 0100 = Reset: Resets all DCU run time registers. See “DCU Status” on page 255 for details. 0101 – 1111 Reserved 0 4 read-write DCULR “DCU Loop Register (DCULR)” on page 131 0xcc 32 0x00000000 0xFFFFFFFF XLEADDR Expected Data Loop End Address: The last expected data cache word address that contains valid expected data. Expected data should looped between 0 and this address. XLEADDR field uses only the following bits based on the cache depth: DCU expected data cache = 4, XLEADDR[1:0] DCU expected data cache = 8, XLEADDR[2:0] DCU expected data cache = 16, XLEADDR[3:0] 28 4 read-write IDA Increment DRAM Address: Indicates, if set, that DRAM addresses should be incremented every time a DRAM read/write command inside the loop is executed. 17 1 read-write LINF Loop Infinite: Indicates, if set, that the loop should be executed indefinitely until stopped by the STOP command. Otherwise the loop is execute LCNT times. 16 1 read-write LCNT Loop Count: The number of times that the loop should be executed if LINF is not set. 8 8 read-write LEADDR Loop End Address: Command cache word address where the loop should end. 4 4 read-write LSADDR Loop Start Address: Command cache word address where the loop should start. 0 4 read-write DCUGCR “DCU General Configuration Register (DCUGCR)” on page 132 0xd0 32 0x00000000 0xFFFFFFFF RCSW Read Capture Start Word: The capture and compare of read data should start after Nth word. For example setting this value to 12 will skip the first 12 read data. 0 16 read-write DCUTPR “DCU Timing Parameter Register (DCUTPR)” on page 132 0xd4 32 0x00000000 0xFFFFFFFF TDCUT3 DCU Generic Timing Parameter 3 24 8 read-write TDCUT2 DCU Generic Timing Parameter 2 16 8 read-write TDCUT1 DCU Generic Timing Parameter 1 8 8 read-write TDCUT0 DCU Generic Timing Parameter 0 0 8 read-write DCUSR0 DCU Status Register 0-1 (DCUSR0-1) 0xd8 32 0x00000000 0xFFFFFFFF CFULL Capture Full: Indicates, if set, that the capture cache is full. 2 1 read-only CFAIL Capture Fail: Indicates, if set, that at least one read data word has failed. 1 1 read-only RDONE Run Done: Indicates, if set, that the DCU has finished executing the commands in the command cache. This bit is also set to indicate that a STOP command has successfully been executed and command execution has stopped. 0 1 read-only DCUSR1 DCU Status Register 0-1 (DCUSR0-1) 0xdc 32 0x00000000 0xFFFFFFFF LPCNT Loop Count: Indicates the value of the loop count. This is useful when the program has stopped because of failures to assess how many reads were executed before first fail. 24 8 read-only FLCNT Fail Count: Number of read words that have failed. 16 8 read-only RDCNT Read Count: Number of read words returned from the SDRAM. 0 16 read-only BISTRR “BIST Run Register (BISTRR)” on page 133 0x100 32 0x00000000 0xFFFFFFFF BCCSEL BIST Clock Cycle Select: Selects the clock numbers on which the AC loopback data is written into the FIFO. Data is written into the loopback FIFO once every four clock cycles. Valid values are: 00 = Clock cycle 0, 4, 8, 12, etc. 01 = Clock cycle 1, 5, 9, 13, etc. 10 = Clock cycle 2, 6, 10, 14, etc. 11 = Clock cycle 3, 7, 11, 15, etc. 25 2 read-write BCKSEL BIST CK Select: Selects the CK that should be used to register the AC loopback signals from the I/Os. Valid values are: 00 = CK[0] 01 = CK[1] 10 = CK[2] 11 = Reserved 23 2 read-write BDXSEL BIST DATX8 Select: Select the byte lane for comparison of loopback/read data. Valid values are 0 to 8. 19 4 read-write BDPAT BIST Data Pattern: Selects the data pattern used during BIST. Valid values are: 00 = Walking 0 01 = Walking 1 10 = LFSR-based pseudo-random 11 = User programmable (Not valid for AC loopback). 17 2 read-write BDMEN BIST Data Mask Enable: Enables, if set, that the data mask BIST should be included in the BIST run, i.e. data pattern generated and loopback data compared. This is valid only for loopback mode. 16 1 read-write BACEN BIST AC Enable: Enables the running of BIST on the address/command lane PHY. This bit is exclusive with BDXEN, i.e. both cannot be set to ‘1’ at the same time. 15 1 read-write BDXEN BIST DATX8 Enable: Enables the running of BIST on the data byte lane PHYs. This bit is exclusive with BACEN, i.e. both cannot be set to ‘1’ at the same time. 14 1 read-write BSONF BIST Stop On Nth Fail: Specifies, if set, that the BIST should stop when an nth data word or address/command comparison error has been encountered. 13 1 read-write NFAIL Number of Failures: Specifies the number of failures after which the execution of commands and the capture of read data should stop if BSONF bit of this register is set. Execution of commands and the capture of read data will stop after (NFAIL+1) failures if BSONF is set. 5 8 read-write BINF BIST Infinite Run: Specifies, if set, that the BIST should be run indefinitely until when it is either stopped or a failure has been encountered. Otherwise BIST is run until number of BIST words specified in the BISTWCR register has been generated. 4 1 read-write BMODE BIST Mode: Selects the mode in which BIST is run. Valid values are: 0 = Loopback mode: Address, commands and data loop back at the PHY I/Os. 1 = DRAM mode: Address, commands and data go to DRAM for normal memory accesses. 3 1 read-write BINST BIST Instruction: Selects the BIST instruction to be executed: Valid values are: 000 = NOP: No operation 001 = Run: Triggers the running of the BIST. 010 = Stop: Stops the running of the BIST. 011 = Reset: Resets all BIST run-time registers, such as error counters. 100 – 111 Reserved 0 3 read-write BISTWCR “BIST Word Count Register (BISTWCR)” on page 136 0x104 32 0x00000000 0xFFFFFFFF BWCNT BIST Word Count: Indicates the number of words to generate during BIST. This must be a multiple of DRAM burst length (BL) divided by 2, e.g. for BL=8, valid values are 4, 8, 12, 16, and so on. 0 16 read-write BISTMSKR0 BIST Mask Register 0-2 (BISTMSKR0-2) 0x108 32 0x00000000 0xFFFFFFFF ODTMSK Mask bit for each of the up to 4 ODT bits. 28 4 read-write CSMSK Mask bit for each of the up to 4 CS# bits. 24 4 read-write CKEMSK Mask bit for each of the up to 4 CKE bits. 20 4 read-write WEMSK Mask bit for the WE#. 19 1 read-write BAMSK Mask bit for each of the up to 3 bank address bits. 16 3 read-write AMSK Mask bit for each of the up to 16 address bits. 0 16 read-write BISTMSKR1 BIST Mask Register 0-2 (BISTMSKR0-2) 0x10c 32 0x00000000 0xFFFFFFFF DMMSK Mask bit for the data mask (DM) bit. 28 4 read-write PARMSK Mask bit for the PAR_IN. Only for DIMM parity support and only if the design is compiled for less than 3 ranks. 27 1 read-write CASMSK Mask bit for the CAS. 1 1 read-write RASMSK Mask bit for the RAS. 0 1 read-write BISTMSKR2 BIST Mask Register 0-2 (BISTMSKR0-2) 0x110 32 0x00000000 0xFFFFFFFF DQMSK Mask bit for each of the 8 data (DQ) bits. 0 32 read-write BISTLSR “BIST LFSR Seed Register (BISTLSR)” on page 137 0x114 32 0x00000000 0xFFFFFFFF SEED LFSR seed for pseudo-random BIST patterns. 0 32 read-write BISTAR0 BIST Address Register 0-2 (BISTAR0-2) 0x118 32 0x00000000 0xFFFFFFFF BBANK BIST Bank Address: Selects the SDRAM bank address to be used during BIST. 28 3 read-write BROW BIST Row Address: Selects the SDRAM row address to be used during BIST. 12 16 read-write BCOL BIST Column Address: Selects the SDRAM column address to be used during BIST. The lower bits of this address must be “0000” for BL16, “000” for BL8, “00” for BL4 and “0” for BL2. 0 12 read-write BISTAR1 BIST Address Register 0-2 (BISTAR0-2) 0x11c 32 0x00000000 0xFFFFFFFF BAINC BIST Address Increment: Selects the value by which the SDRAM address is incremented for each write/read access. This value must be at the beginning of a burst boundary, i.e. the lower bits must be “0000” for BL16, “000” for BL8, “00” for BL4 and “0” for BL2. 4 12 read-write BMRANK BIST Maximum Rank: Specifies the maximum SDRAM rank to be used during BIST. The default value is set to maximum ranks minus 1. Example default shown here is for a 4-rank system 2 2 read-write BRANK BIST Rank: Selects the SDRAM rank to be used during BIST. Valid values range from 0 to maximum ranks minus 1. 0 2 read-write BISTAR2 BIST Address Register 0-2 (BISTAR0-2) 0x120 32 0x00000000 0xFFFFFFFF BMBANK BIST Maximum Bank Address: Specifies the maximum SDRAM bank address to be used during BIST before the address increments to the next rank. 28 3 read-write BMROW BIST Maximum Row Address: Specifies the maximum SDRAM row address to be used during BIST before the address increments to the next bank. 12 16 read-write BMCOL BIST Maximum Column Address: Specifies the maximum SDRAM column address to be used during BIST before the address increments to the next row. 0 12 read-write BISTUDPR “BIST User Data Pattern Register (BISTUDPR)” on page 138 0x124 32 0x00000000 0xFFFFFFFF BUDP1 BIST User Data Pattern 1: Data to be applied on odd DQ pins during BIST. 16 16 read-write BUDP0 BIST User Data Pattern 0: Data to be applied on even DQ pins during BIST. 0 16 read-write BISTGSR “BIST General Status Register (BISTGSR)” on page 139 0x128 32 0x00000000 0xFFFFFFFF CASBER CAS Bit Error: Indicates the number of bit errors on CAS. 30 2 read-only RASBER RAS Bit Error: Indicates the number of bit errors on RAS. 28 2 read-only DMBER DM Bit Error: Indicates the number of bit errors on data mask (DM) bit. DMBER[1:0] are for even DQS cycles first DM beat, and DMBER[3:2] are for even DQS cycles second DM beat. Similarly, DMBER[5:4] are for odd DQS cycles first DM beat, and DMBER[7:6] are for odd DQS cycles second DM beat. 20 8 read-only PARBER PAR_IN Bit Error (DIMM Only): Indicates the number of bit errors on PAR_IN 16 2 read-only BDXERR BIST Data Error: indicates, if set, that there is a data comparison error in the byte lane. 2 1 read-only BACERR BIST Address/Command Error: indicates, if set, that there is a data comparison error in the address/command lane. 1 1 read-only BDONE BIST Done: Indicates, if set, that the BIST has finished executing. This bit is reset to zero when BIST is triggered. 0 1 read-only BISTWER “BIST Word Error Register (BISTWER)” on page 139 0x12c 32 0x00000000 0xFFFFFFFF DXWER Byte Word Error: Indicates the number of word errors on the byte lane. An error on any bit of the data bus including the data mask bit increments the error count. 16 16 read-only ACWER Address/Command Word Error: Indicates the number of word errors on the address/command lane. An error on any bit of the address/command bus increments the error count. 0 16 read-only BISTBER0 BIST Bit Error Register 0-3 (BISTBER0-3) 0x130 32 0x00000000 0xFFFFFFFF ABER Address Bit Error: Each group of two bits indicate the bit error count on each of the 0 32 read-only BISTBER1 BIST Bit Error Register 0-3 (BISTBER0-3) 0x134 32 0x00000000 0xFFFFFFFF ODTBER ODT Bit Error: Each group of two bits indicates the bit error count on each of the up to 4 ODT bits. [1:0] is the error count for ODT[0], [3:2] for ODT[1], and so on. 24 8 read-only CSBER CS# Bit Error: Each group of two bits indicate the bit error count on each of the up to 4 CS# bits. [1:0] is the error count for CS#[0], [3:2] for CS#[1], and so on. 16 8 read-only CKEBER CKE Bit Error: Each group of two bits indicate the bit error count on each of the up to 4 CKE bits. [1:0] is the error count for CKE[0], [3:2] for CKE[1], and so on. 8 8 read-only WEBER WE# Bit Error: Indicates the number of bit errors on WE#. 6 2 read-only BABER Bank Address Bit Error: Each group of two bits indicate the bit error count on each of the up to 3 bank address bits. [1:0] is the error count for BA[0], [3:2] for BA[1], and so on. 0 6 read-only BISTBER2 BIST Bit Error Register 0-3 (BISTBER0-3) 0x138 32 0x00000000 0xFFFFFFFF DQBER0 Data Bit Error: The error count for even DQS cycles. The first 16 bits indicate the error count for the first data beat (i.e. the data driven out on DQ[7:0] on the rising edge of DQS). The second 16 bits indicate the error on the second data beat (i.e. the error count of the data driven out on DQ[7:0] on the falling edge of DQS). For each of the 16-bit group, the first 2 bits are for DQ[0], the second for DQ[1], and so on. 0 32 read-only BISTBER3 BIST Bit Error Register 0-3 (BISTBER0-3) 0x13c 32 0x00000000 0xFFFFFFFF DQBER1 Data Bit Error: The error count for odd DQS cycles. The first 16 bits indicate the error count for the first data beat (i.e. the data driven out on DQ[7:0] on the rising edge of DQS). The second 16 bits indicate the error on the second data beat (i.e. the error count of the data driven out on DQ[7:0] on the falling edge of DQS). For each of the 16-bit group, the first 2 bits are for DQ[0], the second for DQ[1], and so on. 0 32 read-only BISTWCSR “BIST Word Count Status Register (BISTWCSR)” on page 141 0x140 32 0x00000000 0xFFFFFFFF DXWCNT Byte Word Count: Indicates the number of words received from the byte lane. 16 16 read-only ACWCNT Address/Command Word Count: Indicates the number of words received from the address/command lane. 0 16 read-only BISTFWR0 BIST Fail Word Register 0-2 (BISTFWR0-2) 0x144 32 0x00000000 0xFFFFFFFF ODTWEBS Bit status during a word error for each of the up to 4 ODT bits. 28 4 read-only CSWEBS Bit status during a word error for each of the up to 4 CS# bits. 24 4 read-only CKEWEBS Bit status during a word error for each of the up to 4 CKE bits. 20 4 read-only WEWEBS Bit status during a word error for the WE#. 19 1 read-only BAWEBS Bit status during a word error for each of the up to 3 bank address bits. 16 3 read-only AWEBS Bit status during a word error for each of the up to 16 address bits. 0 16 read-only BISTFWR1 BIST Fail Word Register 0-2 (BISTFWR0-2) 0x148 32 0x00000000 0xFFFFFFFF DMWEBS Bit status during a word error for the data mask (DM) bit. DMWEBS [0] is for the first DM beat, DMWEBS [1] is for the second DM beat, and so on. 28 4 read-only PARWEBS Bit status during a word error for the PAR_IN. Only for DIMM parity support 26 1 read-only CASWEBS Bit status during a word error for the CAS. 1 1 read-only RASWEBS Bit status during a word error for the RAS. 0 1 read-only BISTFWR2 BIST Fail Word Register 0-2 (BISTFWR0-2) 0x14c 32 0x00000000 0xFFFFFFFF DQWEBS Bit status during a word error for each of the 8 data (DQ) bits. The first 8 bits indicate the status of the first data beat (i.e. the status of the data driven out on DQ[7:0] on the rising edge of DQS). The second 8 bits indicate the status of the second data beat (i.e. the status of the data driven out on DQ[7:0] on the falling edge of DQS), and so on. For each of the 8-bit group, the first bit is for DQ[0], the second bit is for DQ[1], and so on. 0 32 read-only AACR “Anti-Aging Control Register (AACR)” on page 143 0x174 32 0x00000000 0xFFFFFFFF AAOENC Anti-Aging PAD Output Enable Control: Enables, if set, anti-aging toggling on the pad output enable signal “ctl_oe_n” going into the DATX8s. This will increase power consumption for the anti-aging feature. 31 1 read-write AAENC Anti-Aging Enable Control: Enables, if set, the automatic toggling of the data going to the DATX8 when the data channel from the controller/PUB to DATX8 is idle for programmable number of clock cycles. 30 1 read-write AATR Anti-Aging Toggle Rate: Defines the number of controller clock (ctl_clk) cycles after which the PUB will toggle the data going to DATX8 if the data channel between the controller/PUB and DATX8 has been idle for this long. The default value correspond to a toggling count of 4096 ctl_clk cycles. For a ctl_clk running at 533MHz the toggle rate will be approximately 7.68us. The default value may also be overridden by the macro DWC_AACR_AATR_DFLT. 0 30 read-write GPR0 General Purpose Register 0-1 (GPR0-1) 0x178 32 0x00000000 0xFFFFFFFF GPR0 General Purpose Register 0: General purpose register bits. 0 32 read-write GPR1 General Purpose Register 0-1 (GPR0-1) 0x17c 32 0x00000000 0xFFFFFFFF GPR1 General Purpose Register 1: General purpose register bits. 0 32 read-write 4 0x10 0,1,2,3 ZQ[%s] no description available 0x180 CR0 Impedance Control Register 0-1 (ZQnCR0-1) 0x0 32 0x00000000 0xFFFFFFFF ZQPD ZQ Power Down: Powers down, if set, the PZQ cell. 31 1 read-write ZCALEN Impedance Calibration Enable: Enables, if set, the impedance calibration of this ZQ control block when impedance calibration is triggered using either the ZCAL bit of PIR register or the DFI update interface. 30 1 read-write ZCALBYP Impedance Calibration Bypass: Bypasses, if set, impedance calibration of this ZQ control block when impedance calibration is already in progress. Impedance calibration can be disabled prior to trigger by using the ZCALEN bit. 29 1 read-write ZDEN Impedance Over-ride Enable: When this bit is set, it allows users to directly drive the impedance control using the data programmed in the ZDATA field. Otherwise, the control is generated automatically by the impedance control logic. 28 1 read-write ZDATA Impedance Over-Ride Data: Data used to directly drive the impedance control. ZDATA field mapping for D3F I/Os is as follows: ZDATA[27:21] is used to select the pull-up on-die termination impedance ZDATA[20:14] is used to select the pull-down on-die termination impedance ZDATA[13:7] is used to select the pull-up output impedance ZDATA[6:0] is used to select the pull-down output impedance ZDATA field mapping for D3A/B/R I/Os is as follows: ZDATA[27:20] is reserved and returns zeros on reads ZDATA[19:15] is used to select the pull-up on-die termination impedance ZDATA[14:10] is used to select the pull-down on-die termination impedance ZDATA[9:5] is used to select the pull-up output impedance ZDATA[4:0] is used to select the pull-down output impedance The default value is 0x000014A for I/O type D3C/R and 0x0001830 for I/O type D3F. 0 28 read-write CR1 Impedance Control Register 0-1 (ZQnCR0-1) 0x4 32 0x00000000 0xFFFFFFFF DFIPU1 DFI Update Interface 1: Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 1 (channel 1) requests an update. Only valid in shared-AC mode. 17 1 read-write DFIPU0 DFI Update Interface 0: Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 0 (channel 0) requests an update. 16 1 read-write DFICCU DFI Concurrent Controller Update Interface: Sets this impedance controller to be enabled for calibration when both of the DFI controller update interfaces request an update on the same clock. This provides the ability to enable impedance calibration updates for the Address/Command lane. Only valid in shared-AC mode. 14 1 read-write DFICU1 DFI Controller Update Interface 1: Sets this impedance controller to be enabled for calibration when the DFI controller update interface 1 (channel 1) requests an update. Only valid in shared-AC mode. 13 1 read-write DFICU0 DFI Controller Update Interface 0: Sets this impedance controller to be enabled for calibration when the DFI controller update interface 0 (channel 0) requests an update. 12 1 read-write ZPROG Impedance Divide Ratio: Selects the external resistor divide ratio to be used to set the output impedance and the on-die termination as follows: ZPROG[7:4] = On-die termination divide select ZPROG[3:0] = Output impedance divide select 0 8 read-write SR0 Impedance Status Register 0-1 (ZQnSR0-1) 0x8 32 0x00000000 0xFFFFFFFF ZDONE Impedance Calibration Done: Indicates that impedance calibration has completed. 31 1 read-only ZERR Impedance Calibration Error: If set, indicates that there was an error during impedance calibration. 30 1 read-only ZCTRL Impedance Control: Current value of impedance control. ZCTRL field mapping for D3F I/Os is as follows: ZCTRL[27:21] is used to select the pull-up on-die termination impedance ZCTRL[20:14] is used to select the pull-down on-die termination impedance ZCTRL[13:7] is used to select the pull-up output impedance ZCTRL[6:0] is used to select the pull-down output impedance ZCTRL field mapping for D3A/B/R I/Os is as follows: ZCTRL[27:20] is reserved and returns zeros on reads ZCTRL[19:15] is used to select the pull-up on-die termination impedance ZCTRL[14:10] is used to select the pull-down on-die termination impedance ZCTRL[9:5] is used to select the pull-up output impedance ZCTRL[4:0] is used to select the pull-down output impedance Note: The default value is 0x000014A for I/O type D3C/D3R and 0x0001839 for I/O type D3F. 0 28 read-only SR1 Impedance Status Register 0-1 (ZQnSR0-1) 0xc 32 0x00000000 0xFFFFFFFF OPU On-die termination (ODT) pull-up calibration status. Similar status encodings as ZPD. 6 2 read-only OPD On-die termination (ODT) pull-down calibration status. Similar status encodings as ZPD. 4 2 read-only ZPU Output impedance pull-up calibration status. Similar status encodings as ZPD. 2 2 read-only ZPD Output impedance pull-down calibration status. Valid status encodings are: 00 = Completed with no errors 01 = Overflow error 10 = Underflow error 11 = Calibration in progress 0 2 read-only 9 0x40 0,1,2,3,4,5,6,7,8 DX[%s] no description available 0x1c0 GCR “DATX8 General Configuration Register (DXnGCR)” on page 148 0x0 32 0x00000000 0xFFFFFFFF CALBYP Calibration Bypass: Prevents, if set, period measurement calibration from automatically triggering after PHY initialization. 31 1 read-write MDLEN Master Delay Line Enable: Enables, if set, the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high. This bit is ANDed with the common DATX8 MDL enable bit. 30 1 read-write WLRKEN Write Level Rank Enable: Specifies the ranks that should be write leveled for this byte. Write leveling responses from ranks that are not enabled for write leveling for a particular byte are ignored and write leveling is flagged as done for these ranks. WLRKEN[0] enables rank 0, [1] enables rank 1, [2] enables rank 2, and [3] enables rank 3. 26 4 read-write PLLBYP PLL Bypass: Puts the byte PLL in bypass mode by driving the PLL bypass pin. This bit is not self-clearing and a '0' must be written to de-assert the bypass. This bit is ORed with the global BYP configuration bit (see Table 3-10 on page 91). 19 1 read-write GSHIFT Gear Shift: Enables, if set, rapid locking mode on the byte PLL. This bit is ORed with the global GSHIFT configuration bit (see Table 3-10 on page 91). 18 1 read-write PLLPD PLL Power Down: Puts the byte PLL in power down mode by driving the PLL power down pin. This bit is not self-clearing and a '0' must be written to de-assert the power-down. This bit is ORed with the global PLLPD configuration bit (see Table 3-10 on page 91). 17 1 read-write PLLRST PLL Rest: Resets the byte PLL by driving the PLL reset pin. This bit is not self- clearing and a '0' must be written to de-assert the reset. This bit is ORed with the global PLLRST configuration bit (see Table 3-10 on page 91). 16 1 read-write DXOEO Data Byte Output Enable Override: Specifies whether the output I/O output enable for the byte lane should be set to a fixed value. Valid values are: 00 = No override. Output enable is controlled by DFI transactions 01 = output enable is asserted (I/O is forced to output mode). 10 = Output enable is de-asserted (I/O is forced to input mode) 11 = Reserved 14 2 read-write RTTOAL RTT On Additive Latency: Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles. Valid values are: 0 = ODT control is set to DQSODT/DQODT almost two cycles before read data preamble 1 = ODT control is set to DQSODT/DQODT almost one cycle before read data preamble 13 1 read-write RTTOH RTT Output Hold: Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to ‘0’) when using dynamic ODT control. ODT is disabled almost RTTOH clock cycles after the read postamble. 11 2 read-write DQRTT DQ Dynamic RTT Control: If set, the on die termination (ODT) control of the DQ/DM SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise. By setting this bit to '0' the dynamic ODT feature is disabled. To control ODT statically this bit must be set to '0' and DXnGCR0[2] (DQODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). 10 1 read-write DQSRTT DQS Dynamic RTT Control: If set, the on die termination (ODT) control of the DQS/DQS# SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise. By setting this bit to '0' the dynamic ODT feature is disabled. To control ODT statically this bit must be set to '0' and DXnGCR0[1] (DQSODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). 9 1 read-write DSEN Write DQS Enable: Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted. DQS# is always the inversion of DQS. These values are valid only when DQS/DQS# output enable is on, otherwise the DQS/DQS# is tristated. Valid settings are: 00 = Reserved 01 = DQS toggling with normal polarity (This should be the default setting) 10 = Reserved 11 = Reserved 7 2 read-write DQSRPD DQSR Power Down: Powers down, if set, the PDQSR cell. This bit is ORed with the common PDR configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99) 6 1 read-write DXPDR Data Power Down Receiver: Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the common PDR configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). 5 1 read-write DXPDD1 Data Power Down Driver: Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the common PDD configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). 4 1 read-write DXIOM Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the IOM configuration bit of the individual DATX8(see “DATX8 Common Configuration Register (DXCCR)” on page 99). 3 1 read-write DQODT Data On-Die Termination: Enables, when set, the on-die termination on the I/O for DQ and DM pins of the byte. This bit is ORed with the common DATX8 ODT configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). Note: This bit is only valid when DXnGCR0[10] is '0'. 2 1 read-write DQSODT DQS On-Die Termination: Enables, when set, the on-die termination on the I/O for DQS/DQS# pin of the byte. This bit is ORed with the common DATX8 ODT configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). Note: This bit is only valid when DXnGCR0[9] is '0'. 1 1 read-write DXEN Data Byte Enable: Enables, if set, the data byte. Setting this bit to '0' disables the byte, i.e. the byte is not used in PHY initialization or training and is ignored during SDRAM read/write operations. 0 1 read-write GSR0 DATX8 General Status Registers 0-2 (DXnGSR0-2) 0x4 32 0x00000000 0xFFFFFFFF WLDQ Write Leveling DQ Status: Captures the write leveling DQ status from the DRAM during software write leveling. 28 1 read-only QSGERR DQS Gate Training Error: Indicates, if set, that there is an error in DQS gate training. One bit for each of the up to 4 ranks. 24 4 read-only GDQSPRD Read DQS gating Period: Returns the DDR clock period measured by the read DQS gating LCDL during calibration. This value is PVT compensated. 16 8 read-only DPLOCK DATX8 PLL Lock: Indicates, if set, that the DATX8 PLL has locked. This is a direct status of the DATX8 PLL lock pin. 15 1 read-only WLPRD Write Leveling Period: Returns the DDR clock period measured by the write leveling LCDL during calibration. The measured period is used to generate the control of the write leveling pipeline which is a function of the write-leveling delay and the clock period. This value is PVT compensated. 7 8 read-only WLERR Write Leveling Error: Indicates, if set, that there is a write leveling error in the DATX8. 6 1 read-only WLDONE Write Leveling Done: Indicates, if set, that the DATX8 has completed write leveling. 5 1 read-only WLCAL Write Leveling Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line. 4 1 read-only GDQSCAL Read DQS gating Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL. 3 1 read-only RDQSNCAL Read DQS# Calibration (Type B/B1 PHY Only): Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL. 2 1 read-only RDQSCAL Read DQS Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS LCDL. 1 1 read-only WDQCAL Write DQ Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write DQ LCDL. 0 1 read-only GSR1 DATX8 General Status Registers 0-2 (DXnGSR0-2) 0x8 32 0x00000000 0xFFFFFFFF DLTCODE Delay Line Test Code: Returns the code measured by the PHY control block that corresponds to the period of the DATX8 delay line digital test output. 1 24 read-only DLTDONE Delay Line Test Done: Indicates, if set, that the PHY control block has finished doing period measurement of the DATX8 delay line digital test output. 0 1 read-only BDLR0 DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) 0xc 32 0x00000000 0xFFFFFFFF DQ4WBD DQ4 Write Bit Delay: Delay select for the BDL on DQ4 write path. 24 6 read-write DQ3WBD DQ3 Write Bit Delay: Delay select for the BDL on DQ3 write path 18 6 read-write DQ2WBD DQ2 Write Bit Delay: Delay select for the BDL on DQ2 write path. 12 6 read-write DQ1WBD DQ1 Write Bit Delay: Delay select for the BDL on DQ1 write path. 6 6 read-write DQ0WBD DQ0 Write Bit Delay: Delay select for the BDL on DQ0 write path. 0 6 read-write BDLR1 DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) 0x10 32 0x00000000 0xFFFFFFFF DSWBD DQS Write Bit Delay: Delay select for the BDL on DQS write path 24 6 read-write DMWBD DM Write Bit Delay: Delay select for the BDL on DM write path. 18 6 read-write DQ7WBD DQ7 Write Bit Delay: Delay select for the BDL on DQ7 write path. 12 6 read-write DQ6WBD DQ6 Write Bit Delay: Delay select for the BDL on DQ6 write path. 6 6 read-write DQ5WBD DQ5 Write Bit Delay: Delay select for the BDL on DQ5 write path. 0 6 read-write BDLR2 DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) 0x14 32 0x00000000 0xFFFFFFFF DSNRBD DQSN Read Bit Delay (Type B/B1 PHY Only): Delay select for the BDL on DQSN read path 18 6 read-write DSRBD DQS Read Bit Delay: Delay select for the BDL on DQS read path 12 6 read-write DQOEBD DQ Output Enable Bit Delay: Delay select for the BDL on DQ/DM output enable path. 6 6 read-write DSOEBD DQS Output Enable Bit Delay: Delay select for the BDL on DQS output enable path 0 6 read-write BDLR3 DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) 0x18 32 0x00000000 0xFFFFFFFF DQ4RBD DQ4 Read Bit Delay: Delay select for the BDL on DQ4 read path. 24 6 read-write DQ3RBD DQ3 Read Bit Delay: Delay select for the BDL on DQ3 read path 18 6 read-write DQ2RBD DQ2 Read Bit Delay: Delay select for the BDL on DQ2 read path. 12 6 read-write DQ1RBD DQ1 Read Bit Delay: Delay select for the BDL on DQ1 read path. 6 6 read-write DQ0RBD DQ0 Read Bit Delay: Delay select for the BDL on DQ0 read path. 0 6 read-write BDLR4 DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) 0x1c 32 0x00000000 0xFFFFFFFF DMRBD DM Read Bit Delay: Delay select for the BDL on DM read path. 18 6 read-write DQ7RBD DQ7 Read Bit Delay: Delay select for the BDL on DQ7 read path. 12 6 read-write DQ6RBD DQ6 Read Bit Delay: Delay select for the BDL on DQ6 read path. 6 6 read-write DQ5RBD DQ5 Read Bit Delay: Delay select for the BDL on DQ5 read path. 0 6 read-write LCDLR0 DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) 0x20 32 0x00000000 0xFFFFFFFF R3WLD Rank 3 Write Leveling Delay: Rank 3 delay select for the write leveling (WL) LCDL 24 8 read-write R2WLD Rank 2 Write Leveling Delay: Rank 2 delay select for the write leveling (WL) LCDL 16 8 read-write R1WLD Rank 1 Write Leveling Delay: Rank 1 delay select for the write leveling (WL) LCDL 8 8 read-write R0WLD Rank 0 Write Leveling Delay: Rank 0 delay select for the write leveling (WL) LCDL 0 8 read-write LCDLR1 DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) 0x24 32 0x00000000 0xFFFFFFFF RDQSND Read DQSN Delay (Type B/B1 PHY Only): Delay select for the read DQSN (RDQS) LCDL 16 8 read-write RDQSD Read DQS Delay: Delay select for the read DQS (RDQS) LCDL 8 8 read-write WDQD Write Data Delay: Delay select for the write data (WDQ) LCDL 0 8 read-write LCDLR2 DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) 0x28 32 0x00000000 0xFFFFFFFF R3DQSGD Rank 3 Read DQS Gating Delay: Rank 3 delay select for the read DQS gating (DQSG) LCDL 24 8 read-write R2DQSGD Rank 2 Read DQS Gating Delay: Rank 2 delay select for the read DQS gating (DQSG) LCDL 16 8 read-write R1DQSGD Rank 1 Read DQS Gating Delay: Rank 1 delay select for the read DQS gating (DQSG) LCDL 8 8 read-write R0DQSGD Rank 0 Read DQS Gating Delay: Rank 0 delay select for the read DQS gating (DQSG) LCDL 0 8 read-write MDLR “DATX8 Master Delay Line Register (DXnMDLR)” on page 157 0x2c 32 0x00000000 0xFFFFFFFF MDLD MDL Delay: Delay select for the LCDL for the Master Delay Line. 16 8 read-write TPRD Target Period: Target period measured by the master delay line calibration for VT drift compensation. This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. 8 8 read-write IPRD Initial Period: Initial period measured by the master delay line calibration for VT drift compensation. This value is used as the denominator when calculating the ratios of updates during VT compensation. 0 8 read-write GTR “DATX8 General Timing Register (DXnGTR)” on page 159 0x30 32 0x00000000 0x000FFFFF R3WLSL No description available 18 2 read-write R2WLSL No description available 16 2 read-write R1WLSL No description available 14 2 read-write R0WLSL Rank n Write Leveling System Latency: This is used to adjust the write latency after write leveling. Power-up default is 01 (i.e. no extra clock cycles required). The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register. Every two bits of this register control the latency of each of the (up to) four ranks. R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on. Valid values: 00 = Write latency = WL - 1 01 = Write latency = WL 10 = Write latency = WL + 1 11 = Reserved 12 2 read-write R3DGSL No description available 9 3 read-write R2DGSL No description available 6 3 read-write R1DGSL No description available 3 3 read-write R0DGSL Rank n DQS Gating System Latency: This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles. This is used to compensate for board delays and other system delays. Power-up default is 000 (i.e. no extra clock cycles required). The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register. Every three bits of this register control the latency of each of the (up to) four ranks. R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on. Valid values are 0 to 7: 0 3 read-write GSR2 “DATX8 General Status Register 2 (DXnGSR2)” on page 152 0x34 32 0x00000000 0xFFFFFFFF ESTAT Error Status: If an error occurred for this lane as indicated by RDERR, WDERR, REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution. 8 4 read-write WEWN Write Data Eye Training Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the write data eye training. 7 1 read-write WEERR Write Data Eye Training Error: Indicates, if set, that the DATX8 has encountered an error during execution of the write data eye training. 6 1 read-write REWN Read Data Eye Training Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the read data eye training. 5 1 read-write REERR Read Data Eye Training Error: Indicates, if set, that the DATX8 has encountered an error during execution of the read data eye training. 4 1 read-write WDWN Write Bit Deskew Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the write bit deskew training. 3 1 read-write WDERR Write Bit Deskew Error: Indicates, if set, that the DATX8 has encountered an error during execution of the write bit deskew training. 2 1 read-write RDWN Read Bit Deskew Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the read bit deskew training. 1 1 read-write RDERR Read Bit Deskew Error: Indicates, if set, that the DATX8 has encountered an error during execution of the read bit deskew training. 0 1 read-write TSNS TSNS TSNS 0xf4154000 0x0 0x3c registers T Temperature 0x0 32 0x00000000 0xFFFFFFFF T Signed number of temperature in 256 x celsius degree 0 32 read-only TMAX Maximum Temperature 0x4 32 0xFF800000 0xFFFFFFFF T maximum temperature ever found 0 32 read-only TMIN Minimum Temperature 0x8 32 0x007FFFFF 0xFFFFFFFF T minimum temperature ever found 0 32 read-only AGE Sample age 0xc 32 0x00000000 0xFFFFFFFF AGE age of T register in 24MHz clock cycles 0 32 read-only STATUS Status 0x10 32 0x00000000 0x80000001 VALID indicate value in T is valid or not 0: not valid 1:valid 31 1 read-only TRIGGER Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode 0 1 write-only CONFIG Configuration 0x14 32 0x00600300 0xC3FF0713 IRQ_EN Enable interrupt 31 1 read-write RST_EN Enable reset 30 1 read-write COMPARE_MIN_EN Enable compare for minimum temperature 25 1 read-write COMPARE_MAX_EN Enable compare for maximum temperature 24 1 read-write SPEED cycles of a progressive step in 24M clock, valid from 24-255, default 96 24: 24 cycle for a step 25: 25 cycle for a step 26: 26 cycle for a step ... 255: 255 cycle for a step 16 8 read-write AVERAGE Average time, default in 3 0: measure and return 1: twice and average 2: 4 times and average . . . 7: 128 times and average 8 3 read-write CONTINUOUS continuous mode that keep sampling temperature peridically 0: trigger mode 1: continuous mode 4 1 read-write ASYNC Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value 0: active mode 1: Async mode 1 1 read-write ENABLE Enable temperature 0: disable, temperature sensor is shut down 1: enable. Temperature sensor enabled 0 1 read-write VALIDITY Sample validity 0x18 32 0x016E3600 0xFFFFFFFF VALIDITY time for temperature values to expire in 24M clock cycles 0 32 read-write FLAG Temperature flag 0x1c 32 0x00000000 0x00330001 RECORD_MIN_CLR Clear minimum recorder of temerature, write 1 to clear 21 1 read-write RECORD_MAX_CLR Clear maximum recorder of temerature, write 1 to clear 20 1 read-write UNDER_TEMP Clear under temperature status, write 1 to clear 17 1 read-write OVER_TEMP Clear over temperature status, write 1 to clear 16 1 read-write IRQ IRQ flag, write 1 to clear 0 1 read-write UPPER_LIM_IRQ Maximum temperature to interrupt 0x20 32 0x00000000 0xFFFFFFFF T Maximum temperature for compare 0 32 read-write LOWER_LIM_IRQ Minimum temperature to interrupt 0x24 32 0x00000000 0xFFFFFFFF T Minimum temperature for compare 0 32 read-write UPPER_LIM_RST Maximum temperature to reset 0x28 32 0x00000000 0xFFFFFFFF T Maximum temperature for compare 0 32 read-write LOWER_LIM_RST Minimum temperature to reset 0x2c 32 0x00000000 0xFFFFFFFF T Minimum temperature for compare 0 32 read-write ASYNC Configuration in asynchronous mode 0x30 32 0x00000000 0x010107FF ASYNC_TYPE Compare hotter than or colder than in asynchoronous mode 0: hotter than 1: colder than 24 1 read-write POLARITY Polarity of internal comparator 16 1 read-write VALUE Value of async mode to compare 0 11 read-write ADVAN Advance configuration 0x38 32 0x00000000 0x03010003 ASYNC_IRQ interrupt status of asynchronous mode 25 1 read-only ACTIVE_IRQ interrupt status of active mode 24 1 read-only SAMPLING temperature sampling is working 16 1 read-only NEG_ONLY use negative compare polarity only 1 1 read-write POS_ONLY use positive compare polarity only 0 1 read-write BACC BACC BACC 0xf4200000 0x0 0x10 registers CONFIG Access timing for access 0x0 32 0x00000000 0x3000FFFF FAST_WRITE Use fast write 0: Write normally 1: boost write 29 1 read-write FAST_READ Use fast read 0: Read normally 1: boost read 28 1 read-write TIMING Time in APB clock cycles, for battery timing penerate 0 16 read-write PRE_TIME Timing gap before rising edge 0x8 32 0x00000000 0x000FFFFF PRE_RATIO Ratio of guard band before rising edge 0: 0 1: 1/32768 of low level width 2: 1/16384 of low level width 14: 1/4 of low level width 15: 1/2 of low level width 16 4 read-write PRE_OFFSET guard band before rising edge this value will be added to ratio number 0 16 read-write POST_TIME Timing gap after rising edge 0xc 32 0x00000000 0x000FFFFF POST_RATIO Ratio of guard band after rising edge 0: 0 1: 1/32768 of high level width 2: 1/16384 of high level width 14: 1/4 of high level width 15: 1/2 of high level width 16 4 read-write POST_OFFSET guard band after rising edge this value will be added to ratio number 0 16 read-write BPOR BPOR BPOR 0xf4204000 0x0 0x4 registers POR_CONFIG Power on reset config 0x0 32 0x00000000 0x00000001 RETENTION retention battery domain setting 0: battery reset on reset pin reset happen 1: battery domain retention when reset pin reset happen 0 1 read-write BCFG BCFG TRIM 0xf4208000 0x0 0x14 registers VBG_CFG Bandgap config 0x0 32 0x00000000 0x811F1F1F VBG_TRIMMED Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: bandgap is not trimmed 1: bandgap is trimmed 31 1 read-write POWER_SAVE Bandgap works in power save mode 0: not in power save mode 1: bandgap work in power save mode 24 1 read-write VBG_1P0 Bandgap 1.0V output trim 16 5 read-write VBG_P65 Bandgap 0.65V output trim 8 5 read-write VBG_P50 Bandgap 0.50V output trim 0 5 read-write IRC32K_CFG On-chip 32k oscillator config 0x8 32 0x00000000 0x80C001FF IRC_TRIMMED IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: irc is not trimmed 1: irc is trimmed 31 1 read-write CAPEX7_TRIM IRC32K bit 7 23 1 read-write CAPEX6_TRIM IRC32K bit 6 22 1 read-write CAP_TRIM capacitor trim bits 0 9 read-write XTAL32K_CFG XTAL 32K config 0xc 32 0x00000000 0x00001313 HYST_EN crystal 32k hysteres enable 12 1 read-write GMSEL crystal 32k gm selection 8 2 read-write CFG crystal 32k config 4 1 read-write AMP crystal 32k amplifier 0 2 read-write CLK_CFG Clock config 0x10 32 0x00000000 0x10010010 XTAL_SEL crystal selected 28 1 read-only KEEP_IRC force irc32k run 16 1 read-write FORCE_XTAL force switch to crystal 4 1 read-write BUTN BUTN BUTN 0xf420c000 0x0 0xc registers BTN_STATUS Button status 0x0 32 0x00000000 0x77770FFF XWCLICK wake button click status when power button held, write 1 to clear flag bit0: clicked bit1: double clicked bit2: tripple clicked 28 3 read-write WCLICK wake button click status, write 1 to clear flag bit0: clicked bit1: double clicked bit2: tripple clicked 24 3 read-write XPCLICK power button click status when wake button held, write 1 to clear flag bit0: clicked bit1: double clicked bit2: tripple clicked 20 3 read-write PCLICK power button click status, write 1 to clear flag bit0: clicked bit1: double clicked bit2: tripple clicked 16 3 read-write DBTN Dual button press status, write 1 to clear flag bit0: button pressed bit1: button confirmd bit2: button long pressed bit3: button long long pressed 8 4 read-write WBTN Wake button press status, write 1 to clear flag bit0: button pressed bit1: button confirmd bit2: button long pressed bit3: button long long pressed 4 4 read-write PBTN Power button press status, write 1 to clear flag bit0: button pressed bit1: button confirmd bit2: button long pressed bit3: button long long pressed 0 4 read-write BTN_IRQ_MASK Button interrupt mask 0x4 32 0x00000000 0x77770FFF XWCLICK wake button click status when power button held interrupt enable bit0: clicked bit1: double clicked bit2: tripple clicked 28 3 read-write WCLICK wake button click interrupt enable bit0: clicked bit1: double clicked bit2: tripple clicked 24 3 read-write XPCLICK power button click status when wake button held interrupt enable bit0: clicked bit1: double clicked bit2: tripple clicked 20 3 read-write PCLICK power button click interrupt enable bit0: clicked bit1: double clicked bit2: tripple clicked 16 3 read-write DBTN Dual button press interrupt enable bit0: button pressed bit1: button confirmd bit2: button long pressed bit3: button long long pressed 8 4 read-write WBTN Wake button press interrupt enable bit0: button pressed bit1: button confirmd bit2: button long pressed bit3: button long long pressed 4 4 read-write PBTN Power button press interrupt enable bit0: button pressed bit1: button confirmd bit2: button long pressed bit3: button long long pressed 0 4 read-write LED_INTENSE Debounce setting 0x8 32 0x00000000 0x000F000F RLED Rbutton brightness 0 16 4 read-write PLED Pbutton brightness 0 0 4 read-write BGPR BGPR BGPR 0xf4218000 0x0 0x20 registers 8 0x4 0,1,2,3,4,5,6,7 GPR[%s] no description available 0x0 32 0x00000000 0xFFFFFFFF DATA Generic control 0 32 read-write RTCSHW RTCSHW RTC 0xf421c000 0x0 0x28 registers SECOND Second counter 0x0 32 0x00000000 0xFFFFFFFF SECOND second counter 0 32 read-write SUBSEC Sub-second counter 0x4 32 0x00000000 0xFFFFFFFF SUBSEC sub second counter 0 32 read-only SEC_SNAP Second counter snap shot 0x8 32 0x00000000 0xFFFFFFFF SEC_SNAP second snap shot, write to take snap shot 0 32 read-write SUB_SNAP Sub-second counter snap shot 0xc 32 0x00000000 0xFFFFFFFF SUB_SNAP sub second snap shot, write to take snap shot 0 32 read-write ALARM0 RTC alarm0 0x10 32 0x00000000 0xFFFFFFFF ALARM Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC 0 32 read-write ALARM0_INC Alarm0 incremental 0x14 32 0x00000000 0xFFFFFFFF INCREASE adder when ARLAM0 happen, helps to create periodical alarm 0 32 read-write ALARM1 RTC alarm1 0x18 32 0x00000000 0xFFFFFFFF ALARM Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC 0 32 read-write ALARM1_INC Alarm1 incremental 0x1c 32 0x00000000 0xFFFFFFFF INCREASE adder when ARLAM0 happen, helps to create periodical alarm 0 32 read-write ALARM_FLAG RTC alarm flag 0x20 32 0x00000000 0x00000003 ALARM1 alarm1 happen 1 1 read-write ALARM0 alarm0 happen 0 1 read-write ALARM_EN RTC alarm enable 0x24 32 0x00000000 0x00000003 ENABLE1 alarm1 mask 0: alarm1 disabled 1: alarm1 enabled 1 1 read-write ENABLE0 alarm0 mask 0: alarm0 disabled 1: alarm0 enabled 0 1 read-write RTC RTC RTC 0xf4244000 BSEC BSEC BSEC 0xf4240000 0x0 0x14 registers SECURE_STATE Secure state 0x0 32 0x00000000 0x0003000F ALLOW_NSC Non-secure state allow 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state 1: system is healthy to enter non-secure state 17 1 read-only ALLOW_SEC Secure state allow 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state 1: system is healthy to enter secure state 16 1 read-only BATT_FAIL BATT secure state one hot indicator 0: secure state is not in fail state 1: secure state is in fail state 3 1 read-write BATT_NSC BATT secure state one hot indicator 0: secure state is not in non-secure state 1: secure state is in non-secure state 2 1 read-write BATT_SEC BATT secure state one hot indicator 0: secure state is not in secure state 1: secure state is in secure state 1 1 read-write BATT_INS BATT secure state one hot indicator 0: secure state is not in inspect state 1: secure state is in inspect state 0 1 read-write SECURE_STATE_CONFIG secure state configuration 0x4 32 0x00000000 0x00000009 LOCK Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset 0: not locked, register can be modified 1: register locked, write access to the register is ignored 3 1 read-write ALLOW_RESTART allow secure state restart from fail state 0: restart is not allowed, only hardware reset can recover secure state 1: software is allowed to switch to inspect state from fail state 0 1 read-write VIOLATION_CONFIG Security violation config 0x8 32 0x00000000 0xFFFFFFFF LOCK_NSC Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored 31 1 read-write NSC_VIO_CFG configuration of non-secure state violations, each bit represents one security event 0: event is not a security violation 1: event is a security violation 16 15 read-write LOCK_SEC Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored 15 1 read-write SEC_VIO_CFG configuration of secure state violations, each bit represents one security event 0: event is not a security violation 1: event is a security violation 0 15 read-write ESCALATE_CONFIG Escalate behavior on security event 0xc 32 0x00000000 0xFFFFFFFF LOCK_NSC Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored 31 1 read-write NSC_VIO_CFG configuration of non-secure state escalates, each bit represents one security event 0: event is not a security escalate 1: event is a security escalate 16 15 read-write LOCK_SEC Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored 15 1 read-write SEC_VIO_CFG configuration of secure state escalates, each bit represents one security event 0: event is not a security escalate 1: event is a security escalate 0 15 read-write EVENT Event and escalate status 0x10 32 0x00000000 0xFFFF0003 EVENT local event statue, each bit represents one security event 16 16 read-only BATT_ESC_NSC BATT is escalating non-secure event 1 1 read-only BATT_ESC_SEC BATT is escalting ssecure event 0 1 read-only BKEY BKEY BKEY 0xf4248000 0x0 0x4c registers 2 0x20 0,1 KEY[%s] no description available 0x0 8 0x4 0,1,2,3,4,5,6,7 DATA[%s] no description available 0x0 32 0x00000000 0xFFFFFFFF DATA security key data 0 32 read-write 2 0x4 KEY0,KEY1 ECC[%s] no description available 0x40 32 0x00000000 0xC000FFFF WLOCK write lock to key0 0: write enable 1: write ignored 31 1 read-write RLOCK read lock to key0 0: key read enable 1: key always read as 0 30 1 read-write ECC Parity check bits for key0 0 16 read-write SELECT Key selection 0x48 32 0x00000000 0x00000001 SELECT select key, key0 treated as secure key, in non-scure mode, only key1 can be selected 0: select key0 in secure mode, key1 in non-secure mode 1: select key1 in secure or nonsecure mode 0 1 read-write BMON BMON BMON 0xf424c000 0x0 0x20 registers 2 0x10 glitch0,clock0 MONITOR[%s] no description available 0x0 CONTROL Glitch and clock monitor control 0x0 32 0x00000000 0x00000011 ACTIVE select glitch works in active mode or passve mode. 0: passive mode, depends on power glitch destroy DFF value 1: active mode, check glitch by DFF chain 4 1 read-write ENABLE enable glitch detector 0: detector disabled 1: detector enabled 0 1 read-write STATUS Glitch and clock monitor status 0x4 32 0x00000000 0x00000001 FLAG flag for glitch detected, write 1 to clear this flag 0: glitch not detected 1: glitch detected 0 1 read-write TAMP TAMP TAMP 0xf4250000 0x0 0x88 registers 4 0x10 tamp0,tamp1,tamp2,tamp3 TAMP[%s] no description available 0x0 CONTROL Tamper n control 0x0 32 0x00000000 0x801F03F7 LOCK lock tamper setting 0: tamper setting can be changed 1: tamper setting will last to next battery domain power cycle 31 1 read-write BYPASS bypass tamper violation filter 0: filter applied 1: filter not used 20 1 read-write FILTER filter length 0: 1 cycle 1: 2 cycle 15: 65526 cycle 16 4 read-write VALUE pin value for passive tamper 8 2 read-write SPEED tamper speed selection, (2^SPEED) changes per second 0: 1 shift per second 1: 2 shifts per second . . . 15: 32768 shifts per second 4 4 read-write RECOVER tamper will recover itself if tamper LFSR goes wrong 0: tamper will not recover 1: tamper will recover 2 1 read-write ACTIVE select active or passive tamper 0: passive tamper 1: active tamper 1 1 read-write ENABLE enable tamper 0: tamper disableed 1: tamper enabled 0 1 read-write POLY Tamper n Polynomial of LFSR 0x4 32 0x00000000 0xFFFFFFFF POLY tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" 0 32 read-write LFSR Tamper n LFSR shift register 0x8 32 0x00000000 0xFFFFFFFF LFSR LFSR for active tamper, write only register, always read 0 0 32 write-only TAMP_FLAG Tamper flag 0x80 32 0x00000000 0x00000FFF FLAG tamper flag, each bit represents one tamper pin, write 1 to clear the flag Note, clear can only be cleared when tamper disappeared 0 12 read-write IRQ_EN Tamper interrupt enable 0x84 32 0x00000000 0x80000FFF LOCK lock bit for IRQ enable 0: enable bits can be changed 1: enable bits hold until next battery domain power cycle 31 1 read-write IRQ_EN interrupt enable, each bit represents one tamper pin 0: interrupt disabled 1: interrupt enabled 0 12 read-write MONO MONO MONO 0xf4254000 0x0 0x8 registers MONOL Low part of monotonic counter 0x0 32 0x00000000 0xFFFFFFFF COUNTER low part of monotonica counter, write to this counter will cause counter increase by 1 0 32 read-write MONOH High part of monotonic counter 0x4 32 0x00000000 0xFFFFFFFF EPOCH Fuse value for high part of monotonica 16 16 read-write COUNTER high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow 0 16 read-write