Project file "D:\1.Project\git\highib\Src\Src_ThirdParty\Src_GLIWA\T1\T1_project.t1p" auto-generated from "..\..\Src\Src_ThirdParty\Src_KPIT-HighiB\ApplicationStack\Configuration\Generated_Files\1_Os\" on 28.04.2025 at 01:06:15 Core0 ..\..\..\..\Build\Bin\F02Hq001_App_default\F02Hq001_App_default.elf 89 89 500 > 1); \ * temp = temp + (temp >> 7); \ * temp & 0xFFu; \ * }) } */ /* Uncomment to use T1_WAIT and T1_RESUME with T1.cont enabled. */ /* #define T1_WAIT_RESUME (1) */ #include "T1_config.h" #include "T1_baseInterface.h" #include "T1_scopeInterface.h" #include "T1_delayInterface.h" #define T1_CONT_NOF_VRTL_STPWS 8 #include "T1_contInterface.h" #include "T1_flexInterface.h" #include "T1_modInterface.h" /*----------------------------------------------------------------------------------*/ /*--- macros and inline functions --------------------------------------------------*/ /*----------------------------------------------------------------------------------*/ /* Backwards compatibility. */ #define T1_AppRxCallback( _pData ) T1_AppReceiveFrame( (_pData), 8u ) #if defined T1_ENABLE # if ! defined T1_GET_RAW_TIME # error T1_GET_RAW_TIME is not generated in T1_config.h and must be defined in T1_AppInterface.h, see +++ # endif /* ! defined T1_GET_RAW_TIME */ # if defined T1_DEFN_CONT_UNMAP_CORE_ID T1_DEFN_CONT_UNMAP_CORE_ID # endif /* defined T1_DEFN_CONT_UNMAP_CORE_ID */ /*! * Default configuration for all stopwatches. Possible values are * #T1_CONT_CET_STOPWATCH, #T1_CONT_GET_STOPWATCH and #T1_CONT_DATA_AGE_STOPWATCH. * See \ref USER_STOPWATCHES. */ # define T1_CONT_DEFAULT_CONFIG_STOPWATCH( idx_ ) T1_CONT_CET_STOPWATCH( idx_ ) /*! * Default configuration allocating constraints to be used by the T1-HOST-SW. * This macro needs to be commented to manually configure constraints, see * \ref CONSTRAINTS. */ # define T1_CONT_DEFAULT_CONFIG_CONSTRAINT T1_CONT_INVALID_CONSTRAINT # if 1 == T1_NOF_CORES # define INC_T1_ERROR_COUNT( coreId_ ) \ ( T1_errorCount[0] < 255u ? ++T1_errorCount[0] : 255u ) # else /* 1 < T1_NOF_CORES */ # define INC_T1_ERROR_COUNT( coreId_ ) \ ( T1_errorCount[(coreId_)] < 255u ? ++T1_errorCount[(coreId_)] : 255u ) # endif /* 1 == T1_NOF_CORES */ /* @T1@ */ #define T1_AF_TRACE_STARTUP 0x00000001uL /* capture start-up of the ECU */ /* @T1@ */ /* @T1@ */ #define T1_AF_ALLOW_TRIGGER 0x00000002uL /* permit triggering (trace capture) */ /* @T1@ */ /* @T1@ */ #define T1_AF_ALLOW_TRACEDATA 0x00000004uL /* permit T1_TraceData */ /* @T1@ */ /* @T1@ */ #define T1_AF_CHECK_INTEGRATION 0x00000008uL /* trace the stopwatch T1_SW_CHECK_INTEGRATION_COREx */ /* @T1@ */ /*----------------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------------*/ /* @T1@ */ #define T1_UE_T1_CONT_ERR_CORE0 0x20 /* @T1@ */ /* @T1@ */ #define T1_UE_T1_CONT_ERR_CORE1 0x21 /* @T1@ */ /* @T1@ */ #define T1_UE_T1_CONT_ERR_CORE2 0x22 /* @T1@ */ /* @T1@ */ #define T1_UE_T1_CONT_ERR_CORE3 0x23 /* @T1@ */ /* @T1@ */ #define T1_UE_T1_CONT_ERR_CORE4 0x24 /* @T1@ */ /* @T1@ */ #define T1_UE_T1_CONT_ERR_CORE5 0x25 /* @T1@ */ /* @T1@ */ #define T1_UE_CPU_LOAD_CALLBACK_CORE0 0x26 /* @T1@ */ /* @T1@ */ #define T1_UE_CPU_LOAD_CALLBACK_CORE1 0x27 /* @T1@ */ /* @T1@ */ #define T1_UE_CPU_LOAD_CALLBACK_CORE2 0x28 /* @T1@ */ /* @T1@ */ #define T1_UE_CPU_LOAD_CALLBACK_CORE3 0x29 /* @T1@ */ /* @T1@ */ #define T1_UE_CPU_LOAD_CALLBACK_CORE4 0x2A /* @T1@ */ /* @T1@ */ #define T1_UE_CPU_LOAD_CALLBACK_CORE5 0x2B /* @T1@ */ /*----------------------------------------------------------------------------------*/ /* @T1@ */ #define T1_SW_NvM_ReadAll 0u /* @T1@ */ #define T1_rrCan1VedCmdMsg 1u #define T1_rpCddSwi10ms 2u /*----------------------------------------------------------------------------------*/ #define T1_NOF_USER_STPWS_CORE0 3u /* @T1@ */ #define T1_SW_CHECK_INTEGRATION_CORE1 0u /* @T1@ */ #define T1_NOF_USER_STPWS_CORE1 1u /*----------------------------------------------------------------------------------*/ /* @T1@ */ #define T1_SW_CHECK_INTEGRATION_CORE2 0u /* @T1@ */ #define T1_NOF_USER_STPWS_CORE2 1u /*----------------------------------------------------------------------------------*/ /* @T1@ */ #define T1_SW_CHECK_INTEGRATION_CORE3 0u /* @T1@ */ #define T1_NOF_USER_STPWS_CORE3 1u /*----------------------------------------------------------------------------------*/ /* @T1@ */ #define T1_SW_CHECK_INTEGRATION_CORE4 0u /* @T1@ */ #define T1_NOF_USER_STPWS_CORE4 1u /*----------------------------------------------------------------------------------*/ /* @T1@ */ #define T1_SW_CHECK_INTEGRATION_CORE5 0u /* @T1@ */ #define T1_NOF_USER_STPWS_CORE5 1u /*----------------------------------------------------------------------------------*/ /* Event Chain IDs: */ #define T1_EVTCHN_0_ID 0u /*----------------------------------------------------------------------------------*/ /* T1.delay: Core0 */ enum { /* @T1@ */ T1_DL_CHECK_INTEGRATION_CORE0_ID = 0, /* @T1@ */ T1_NOF_DELAYS_CORE0 = 1 }; /* T1.delay: Core1 */ enum { /* @T1@ */ T1_DL_CHECK_INTEGRATION_CORE1_ID = 0, /* @T1@ */ T1_NOF_DELAYS_CORE1 = 1 }; /* T1.delay: Core2 */ enum { /* @T1@ */ T1_DL_CHECK_INTEGRATION_CORE2_ID = 0, /* @T1@ */ T1_NOF_DELAYS_CORE2 = 1 }; /* T1.delay: Core3 */ enum { /* @T1@ */ T1_DL_CHECK_INTEGRATION_CORE3_ID = 0, /* @T1@ */ T1_NOF_DELAYS_CORE3 = 1 }; /* T1.delay: Core4 */ enum { /* @T1@ */ T1_DL_CHECK_INTEGRATION_CORE4_ID = 0, /* @T1@ */ T1_NOF_DELAYS_CORE4 = 1 }; /* T1.delay: Core5 */ enum { /* @T1@ */ T1_DL_CHECK_INTEGRATION_CORE5_ID = 0, /* @T1@ */ T1_NOF_DELAYS_CORE5 = 1 }; /*----------------------------------------------------------------------------------*/ /*--- external declarations for global variables -----------------------------------*/ /*----------------------------------------------------------------------------------*/ # define T1_START_SEC_CONST_32 # include "T1_MemMap.h" T1_DeclarePluginTable(T1_pluginTable); # define T1_STOP_SEC_CONST_32 # include "T1_MemMap.h" # define T1_START_SEC_VAR_POWER_ON_CLEARED_8 # include "T1_MemMap.h" T1_EXTERN T1_uint8_t T1_SEC_VAR_POWER_ON_CLEARED_8 T1_errorCount[T1_NOF_CORES]; # define T1_STOP_SEC_VAR_POWER_ON_CLEARED_8 # include "T1_MemMap.h" #if ! defined T1_DISABLE_T1_CONT && defined T1_CONT_REMOTE # define T1_START_SEC_VAR_CLEARED_32 # include "T1_MemMap.h" /*! \brief Shared data for remote core T1.cont pairs of cores. */ T1_EXTERN T1_bakery_t T1_SEC_VAR_CLEARED_32 T1_contRemoteSemPC[T1_NOF_CORES][2]; # define T1_STOP_SEC_VAR_CLEARED_32 # include "T1_MemMap.h" #endif /* ! defined T1_DISABLE_T1_CONT && defined T1_CONT_REMOTE */ # if 1 < T1_NOF_CORES # define T1_START_SEC_VAR_POWER_ON_CLEARED_8 # include "T1_MemMap.h" T1_EXTERN T1_uint8_t T1_SEC_VAR_POWER_ON_CLEARED_8 T1_coreTriggerCounter[T1_NOF_CORES]; # define T1_STOP_SEC_VAR_POWER_ON_CLEARED_8 # include "T1_MemMap.h" # define T1_START_SEC_VAR_POWER_ON_CLEARED_16 # include "T1_MemMap.h" T1_EXTERN T1_uint16_t T1_SEC_VAR_POWER_ON_CLEARED_16 T1_afterXevents; # define T1_STOP_SEC_VAR_POWER_ON_CLEARED_16 # include "T1_MemMap.h" # endif /* 1 < T1_NOF_CORES */ # if defined T1_COMMS_SHARED_MEM # define T1_CORE_COMMS_START_SEC_VAR_POWER_ON_CLEARED_8 # include "T1_MemMap.h" /* Read and written by T1-TARGET-SW */ T1_EXTERN T1_uint8_t T1_CORE_COMMS_SEC_VAR_POWER_ON_CLEARED_8 T1_targetToHostArray[T1_GCP_MAX_TX_FRAME_SIZE]; T1_EXTERN T1_uint8_t T1_CORE_COMMS_SEC_VAR_POWER_ON_CLEARED_8 T1_targetToHostHandshakeAnnounce; T1_EXTERN T1_uint8_t T1_CORE_COMMS_SEC_VAR_POWER_ON_CLEARED_8 T1_hostToTargetHandshakeAcknowledge; /* Only read by T1-TARGET-SW (except for in T1_AppInit) */ T1_EXTERN T1_uint8_t T1_CORE_COMMS_SEC_VAR_POWER_ON_CLEARED_8 T1_hostToTargetArray[T1_GCP_MAX_RX_FRAME_SIZE]; T1_EXTERN T1_uint8_t T1_CORE_COMMS_SEC_VAR_POWER_ON_CLEARED_8 T1_hostToTargetHandshakeAnnounce; T1_EXTERN T1_uint8_t T1_CORE_COMMS_SEC_VAR_POWER_ON_CLEARED_8 T1_targetToHostHandshakeAcknowledge; # define T1_CORE_COMMS_STOP_SEC_VAR_POWER_ON_CLEARED_8 # include "T1_MemMap.h" # define T1_CORE_COMMS_START_SEC_VAR_POWER_ON_CLEARED_16 # include "T1_MemMap.h" /* Read and written by T1-TARGET-SW */ T1_EXTERN T1_uint16_t T1_CORE_COMMS_SEC_VAR_POWER_ON_CLEARED_16 T1_targetToHostFrameLength; /* Only read by T1-TARGET-SW (except for in T1_AppInit) */ T1_EXTERN T1_uint16_t T1_CORE_COMMS_SEC_VAR_POWER_ON_CLEARED_16 T1_hostToTargetFrameLength; # define T1_CORE_COMMS_STOP_SEC_VAR_POWER_ON_CLEARED_16 # include "T1_MemMap.h" # endif /* defined T1_COMMS_SHARED_MEM */ # if defined T1_CHECK_INTEGRATION # define T1_START_SEC_CONST_32 # include "T1_MemMap.h" T1_EXTERN T1_uint32_t * const T1_SEC_CONST_32 T1_checkIntegrationPC[]; # define T1_STOP_SEC_CONST_32 # include "T1_MemMap.h" # endif /* defined T1_CHECK_INTEGRATION */ #endif /* defined T1_ENABLE */ /*----------------------------------------------------------------------------------*/ /*--- forward declarations for global functions ------------------------------------*/ /*----------------------------------------------------------------------------------*/ /* wrapper functions defined in T1_AppInterface.c */ #define T1_START_SEC_CODE #include "T1_MemMap.h" T1_EXTERN void T1_CODE T1_AppSetStopTriggerAllCores(T1_uint8Least_t coreId, T1_nofEntries_t afterXevents); T1_EXTERN void T1_CODE T1_AppInit(void); T1_EXTERN void T1_CODE T1_AppBackgroundHandler(void); T1_EXTERN void T1_CODE T1_AppHandler(void); T1_EXTERN void T1_CODE T1_AppReceiveFrame(T1_uint8_t const T1_FARPTR pData, T1_frameSize_t nOfBytes); #if defined T1_ENABLE && defined T1_CHECK_INTEGRATION # if ! defined T1_CHECK_INTEGRATION_INV_PARAM # error Please use the invocation file parameter -checkIntegration to enable the check integration feature! # endif /* ! defined T1_CHECK_INTEGRATION_INV_PARAM */ T1_EXTERN void T1_CODE T1_CheckIntegrationInitPC(T1_uint8Least_t coreId); T1_EXTERN void T1_CODE T1_CheckIntegrationHandlerPC(T1_uint8Least_t coreId); # define T1_CheckIntegrationInit( ) T1_CheckIntegrationInitPC( T1_GetCoreIdOffset( ) ) # define T1_CheckIntegrationHandler( ) T1_CheckIntegrationHandlerPC( T1_GetCoreIdOffset( ) ) #else /* ! defined T1_ENABLE || ! defined T1_CHECK_INTEGRATION */ # define T1_CheckIntegrationInitPC( coreId_ ) ((void)0) # define T1_CheckIntegrationHandlerPC( coreId_ ) ((void)0) # define T1_CheckIntegrationInit( ) ((void)0) # define T1_CheckIntegrationHandler( ) ((void)0) #endif /* defined T1_ENABLE && defined T1_CHECK_INTEGRATION */ #define T1_STOP_SEC_CODE #include "T1_MemMap.h" /*----------------------------------------------------------------------------------*/ #endif /* T1_APPINTERFACE_H_ */ ]]> pure T1 0 2 1925 false CAN1 CAN RX pure T1 0 2 1924 false CAN1 CAN TX CAN1 CAN VN1630A Channel 3 VECTOR 10 500000 1 0 10 5 4 1