//***************************************************************************** // (C) Automotive Lighting Reutlingen GmbH // Tuebinger Strasse 123, 72762 Reutlingen, Germany // // Automotive Lighting Reutlingen GmbH owns all the rights to this work. // This work shall not be copied, reproduced, used, modified, transferred // or its information shall not be disclosed without the prior written // authorization of Automotive Lighting Reutlingen GmbH. //***************************************************************************** //----------------------------------------------------------------------------- /// \file CddTps92520_Sched.h /// /// \brief Schedule table for TPS92520 /// /// \author OTT, Peter ALDE-RT/EES6 //----------------------------------------------------------------------------- #ifndef CDD_TPS92520_SCHED_2021_01_21_H_ #define CDD_TPS92520_SCHED_2021_01_21_H_ //----------------------------------------------------------------------------- // Includes //----------------------------------------------------------------------------- #include #include <../Gen/CddTps92520_Types.h> #include <../Cfg/CddTps92520_Cfg.h> //----------------------------------------------------------------------------- // Defines //----------------------------------------------------------------------------- // Actions executed synchrone with SPI schedule Table before a SPI Tx #define CDDTPS92520_NO_ACT 0u #define CDDTPS92520_ST_CHECK_START 1u //SYSCFG1 register coonfiguration #define CDDTPS92520_Cfg_CH1INTPWM CDDTPS92520_INTPWM_NotUsed //Internal PWM generator not used #define CDDTPS92520_Cfg_CH2INTPWM CDDTPS92520_INTPWM_NotUsed //Internal PWM generator not used #define CDDTPS92520_Cfg_PWMPH CDDTPS92520_INTPWM_PhaseShift_0 //SYSCFG2 register coonfiguration #define CDDTPS92520_Cfg_IFT CDDTPS92520_IFT_FaultTimer_32ms #define CDDTPS92520_Cfg_CH1TSFL CDDTPS92520_TSFL_ThermalShutdown_AutoRestart #define CDDTPS92520_Cfg_CH2TSFL CDDTPS92520_TSFL_ThermalShutdown_AutoRestart //Communication watchdog timer (CMWTAP) register configuration #define CDDTPS92520_Cfg_CMWTAP CDDTPS92520_CMWTAP_ComWatchdogPerdiod_1670ms //Thermal warning limit (TWLMT) register configuration #define CDDTPS92520_Cfg_TWLMT 147u // Thermal warning limit : Tj = 0,7168°C * 147d * 4 - 271,51°C = 150°C //Internal PWM clock divider (PWMDIV) register configuration #define CDDTPS92520_Cfg_PWMDIV CDDTPS92520_PWMDIV_InternalPWMFreq_610Hz //Buck ON-time and freqauency for channel 1 (CH1TON) register configuration #define CDDTPS92520_Cfg_CH1TON CDDTPS92520_CHxTON_BuckFreq_400kHz //Buck ON-time and frequency for channel 2 (CH2TON) register configuration #define CDDTPS92520_Cfg_CH2TON CDDTPS92520_CHxTON_BuckFreq_400kHz //Limp home internal or external current reference set point. #define CDDTPS92520_Cfg_LHEXTIADJ CDDTPS92520_LHEXTIADJ_OFF //Limp home internal or external PWM for LED current duty cycle #define CDDTPS92520_Cfg_LH1INTPM CDDTPS92520_LHxINTPWM_ON #define CDDTPS92520_Cfg_LH2INTPM CDDTPS92520_LHxINTPWM_ON #define CDDTPS92520_Cfg_LHPWMPH CDDTPS92520_LHPWMPH_PhaseShift_0 //Limp home Buck ON-time and frequency register configuration #define CDDTPS92520_Cfg_LH1TON CDDTPS92520_LHxTON_BuckFreq_400kHz #define CDDTPS92520_Cfg_LH2TON CDDTPS92520_LHxTON_BuckFreq_400kHz // Limp home counter limit for the ILIM fault timer #define CDDTPS92520_Cfg_LHIFT CDDTPS92520_LHIFT_32ms //----------------------------------------------------------------------------- // SPI scheduling configuration //----------------------------------------------------------------------------- #define CDDTPS92520_Cfg_SpiSchedTableLen 129u #define CDDTPS92520_Cfg_SpiSchedTable_Init \ { \ /* next Optional Read/Write Register Data Data */ \ /* index state action command address to transmit to receive */ \ /*--------------------------------- Init sequence -----------------------------------------------------------------------------------------------------------*/ \ /* 0 */ { 1u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrRESET_Tx, CDDTPS92520_RESET_Tx, CDDTPS92520_Dummy_Rx }, \ /* 1 */ { 2u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrSYSCFG1_Tx, CDDTPS92520_SYSCFG1_Tx, CDDTPS92520_Dummy_Rx }, \ /* 2 */ { 3u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrSTATUS3_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_SYSCFG1_Rx }, \ /* 3 */ { 4u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrSYSCFG2_Tx, CDDTPS92520_SYSCFG2_Tx, CDDTPS92520_STATUS3_Rx }, \ /* 4 */ { 5u, CDDTPS92520_ST_CHECK_START, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCMWTAP_Tx, CDDTPS92520_CMWTAP_Tx, CDDTPS92520_SYSCFG2_Rx }, \ /* 5 */ { 6u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrTWLMT_Tx, CDDTPS92520_TWLMT_Tx, CDDTPS92520_CMWTAP_Rx }, \ /* 6 */ { 7u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrSLEEP_Tx, CDDTPS92520_SLEEP_Tx, CDDTPS92520_TWLMT_Rx }, \ /* 7 */ { 8u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH1IADJH_Tx, CDDTPS92520_CH1IADJH_Tx, CDDTPS92520_SLEEP_Rx }, \ /* 8 */ { 9u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH1IADJL_Tx, CDDTPS92520_CH1IADJL_Tx, CDDTPS92520_CH1IADJH_Rx }, \ /* 9 */ { 10u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH2IADJH_Tx, CDDTPS92520_CH2IADJH_Tx, CDDTPS92520_CH1IADJL_Rx }, \ /* 10 */ { 11u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH2IADJL_Tx, CDDTPS92520_CH2IADJL_Tx, CDDTPS92520_CH2IADJH_Rx }, \ /* 11 */ { 12u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrPWMDIV_Tx, CDDTPS92520_PMWDIV_Tx, CDDTPS92520_CH2IADJL_Rx }, \ /* 12 */ { 13u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH1PWMH_Tx, CDDTPS92520_CH1PWMH_Tx, CDDTPS92520_PMWDIV_Rx }, \ /* 13 */ { 14u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH1PWML_Tx, CDDTPS92520_CH1PWML_Tx, CDDTPS92520_CH1PWMH_Rx }, \ /* 14 */ { 15u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH2PWMH_Tx, CDDTPS92520_CH2PWMH_Tx, CDDTPS92520_CH1PWML_Rx }, \ /* 15 */ { 16u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH2PWML_Tx, CDDTPS92520_CH2PWML_Tx, CDDTPS92520_CH2PWMH_Rx }, \ /* 16 */ { 17u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH1TON_Tx, CDDTPS92520_CH1TON_Tx, CDDTPS92520_CH2PWML_Rx }, \ /* 17 */ { 18u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH2TON_Tx, CDDTPS92520_CH2TON_Tx, CDDTPS92520_CH1TON_Rx }, \ /* 18 */ { 19u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VIN_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2TON_Rx }, \ /* 19 */ { 20u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VIN_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VIN_Rx }, \ /* 20 */ { 21u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VLED_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2VIN_Rx }, \ /* 21 */ { 22u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VLED_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VLED_Rx }, \ /* 22 */ { 23u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VLEDON_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2VLED_Rx }, \ /* 23 */ { 24u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VLEDON_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VLEDON_Rx }, \ /* 24 */ { 25u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VLEDOFF_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2VLEDON_Rx }, \ /* 25 */ { 26u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VLEDOFF_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VLEDOFF_Rx }, \ /* 26 */ { 27u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrTEMPL_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2VLEDOFF_Rx }, \ /* 27 */ { 28u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrTEMPH_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_TEMPL_Rx }, \ /* 28 */ { 29u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrV5D_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_TEMPH_Rx }, \ /* 29 */ { 30u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrLHCFG1_Tx, CDDTPS92520_LHCFG1_Tx, CDDTPS92520_V5D_Rx }, \ /* 30 */ { 31u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrLHCFG2_Tx, CDDTPS92520_LHCFG2_Tx, CDDTPS92520_LHCFG1_Rx }, \ /* 31 */ { 32u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrLHIL_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_LHCFG2_Rx }, \ /* 32 */ { 33u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrLHIH_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_LHIL_Rx }, \ /* 33 */ { 34u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrLHIFILTL_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_LHIH_Rx }, \ /* 34 */ { 35u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrLHIFILTH_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_LHIFILTL_Rx }, \ /* 35 */ { 36u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrLH1IADJH_Tx, CDDTPS92520_LH1IADJH_Tx, CDDTPS92520_LHIFILTH_Rx }, \ /* 36 */ { 37u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrLH1IADJL_Tx, CDDTPS92520_LH1IADJL_Tx, CDDTPS92520_LH1IADJH_Rx }, \ /* 37 */ { 38u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrLH2IADJH_Tx, CDDTPS92520_LH2IADJH_Tx, CDDTPS92520_LH1IADJL_Rx }, \ /* 38 */ { 39u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrLH2IADJL_Tx, CDDTPS92520_LH2IADJL_Tx, CDDTPS92520_LH2IADJH_Rx }, \ /* 39 */ { 40u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrLHCH1PWMH_Tx, CDDTPS92520_LHCH1PWMH_Tx, CDDTPS92520_LH2IADJL_Rx }, \ /* 40 */ { 41u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrLHCH1PWML_Tx, CDDTPS92520_LHCH1PWML_Tx, CDDTPS92520_LHCH1PWMH_Rx }, \ /* 41 */ { 42u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrLHCH2PWMH_Tx, CDDTPS92520_LHCH2PWMH_Tx, CDDTPS92520_LHCH1PWML_Rx }, \ /* 42 */ { 43u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrLHCH2PWML_Tx, CDDTPS92520_LHCH2PWML_Tx, CDDTPS92520_LHCH2PWMH_Rx }, \ /* 43 */ { 44u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrLH1TON_Tx, CDDTPS92520_LH1TON_Tx, CDDTPS92520_LHCH2PWML_Rx }, \ /* 44 */ { 45u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrLH2TON_Tx, CDDTPS92520_LH2TON_Tx, CDDTPS92520_LH1TON_Rx }, \ /* 45 */ { 46u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrSTATUS1_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_LH2TON_Rx }, \ /* 46 */ { 47u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrSTATUS2_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_STATUS1_Rx }, \ /* 47 */ { 48u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrSTATUS3_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_STATUS2_Rx }, \ /* 48 */ { 49u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VLEDOFF_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_STATUS3_Rx }, \ /*---------------------------- Cyclic 0ms -------------------------------------------------------------------------------------------------------------------*/ \ /* 49 */ { 50u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrSYSCFG1_Tx, CDDTPS92520_SYSCFG1_Tx, CDDTPS92520_CH2VLEDOFF_Rx }, \ /* 50 */ { 51u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH1IADJH_Tx, CDDTPS92520_CH1IADJH_Tx, CDDTPS92520_SYSCFG1_Rx }, \ /* 51 */ { 52u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH1IADJL_Tx, CDDTPS92520_CH1IADJL_Tx, CDDTPS92520_CH1IADJH_Rx }, \ /* 52 */ { 53u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH2IADJH_Tx, CDDTPS92520_CH2IADJH_Tx, CDDTPS92520_CH1IADJL_Rx }, \ /* 53 */ { 54u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH2IADJL_Tx, CDDTPS92520_CH2IADJL_Tx, CDDTPS92520_CH2IADJH_Rx }, \ /* 54 */ { 55u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrSTATUS1_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2IADJL_Rx }, \ /* 55 */ { 56u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrSTATUS2_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_STATUS1_Rx }, \ /* 56 */ { 57u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrTEMPL_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_STATUS2_Rx }, \ /* 57 */ { 58u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrTEMPH_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_TEMPL_Rx }, \ /* 58 */ { 59u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrSLEEP_Tx, CDDTPS92520_SLEEP_Tx, CDDTPS92520_TEMPH_Rx }, \ /*---------------------------- Cyclic 10ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 59 */ { 60u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrSYSCFG1_Tx, CDDTPS92520_SYSCFG1_Tx, CDDTPS92520_SLEEP_Rx }, \ /* 60 */ { 61u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrSTATUS3_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_SYSCFG1_Rx }, \ /* 61 */ { 62u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VIN_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_STATUS3_Rx }, \ /* 62 */ { 63u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VLED_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VIN_Rx }, \ /* 63 */ { 64u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VLEDON_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VLED_Rx }, \ /* 64 */ { 65u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VLEDOFF_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VLEDON_Rx }, \ /* 65 */ { 66u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VIN_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VLEDOFF_Rx }, \ /* 66 */ { 67u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VLED_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2VIN_Rx }, \ /* 67 */ { 68u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VLEDON_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2VLED_Rx }, \ /* 68 */ { 69u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VLEDOFF_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2VLEDON_Rx }, \ /*---------------------------- Cyclic 20ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 69 */ { 70u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrSYSCFG1_Tx, CDDTPS92520_SYSCFG1_Tx, CDDTPS92520_CH2VLEDOFF_Rx }, \ /* 70 */ { 71u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH1IADJH_Tx, CDDTPS92520_CH1IADJH_Tx, CDDTPS92520_SYSCFG1_Rx }, \ /* 71 */ { 72u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH1IADJL_Tx, CDDTPS92520_CH1IADJL_Tx, CDDTPS92520_CH1IADJH_Rx }, \ /* 72 */ { 73u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH2IADJH_Tx, CDDTPS92520_CH2IADJH_Tx, CDDTPS92520_CH1IADJL_Rx }, \ /* 73 */ { 74u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH2IADJL_Tx, CDDTPS92520_CH2IADJL_Tx, CDDTPS92520_CH2IADJH_Rx }, \ /* 74 */ { 75u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrSTATUS1_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2IADJL_Rx }, \ /* 75 */ { 76u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrSTATUS2_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_STATUS1_Rx }, \ /* 76 */ { 77u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrSYSCFG2_Tx, CDDTPS92520_SYSCFG2_Tx, CDDTPS92520_STATUS2_Rx }, \ /* 77 */ { 78u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCMWTAP_Tx, CDDTPS92520_CMWTAP_Tx, CDDTPS92520_SYSCFG2_Rx }, \ /* 78 */ { 79u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrSLEEP_Tx, CDDTPS92520_SLEEP_Tx, CDDTPS92520_CMWTAP_Rx }, \ /*---------------------------- Cyclic 30ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 79 */ { 80u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrSYSCFG1_Tx, CDDTPS92520_SYSCFG1_Tx, CDDTPS92520_SLEEP_Rx }, \ /* 80 */ { 81u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrSTATUS3_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_SYSCFG1_Rx }, \ /* 81 */ { 82u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VIN_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_STATUS3_Rx }, \ /* 82 */ { 83u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VLED_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VIN_Rx }, \ /* 83 */ { 84u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VLEDON_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VLED_Rx }, \ /* 84 */ { 85u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VLEDOFF_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VLEDON_Rx }, \ /* 85 */ { 86u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VIN_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VLEDOFF_Rx }, \ /* 86 */ { 87u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VLED_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2VIN_Rx }, \ /* 87 */ { 88u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VLEDON_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2VLED_Rx }, \ /* 88 */ { 89u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VLEDOFF_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2VLEDON_Rx }, \ /*---------------------------- Cyclic 40ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 89 */ { 90u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrSYSCFG1_Tx, CDDTPS92520_SYSCFG1_Tx, CDDTPS92520_CH2VLEDOFF_Rx }, \ /* 90 */ { 91u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH1IADJH_Tx, CDDTPS92520_CH1IADJH_Tx, CDDTPS92520_SYSCFG1_Rx }, \ /* 91 */ { 92u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH1IADJL_Tx, CDDTPS92520_CH1IADJL_Tx, CDDTPS92520_CH1IADJH_Rx }, \ /* 92 */ { 93u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH2IADJH_Tx, CDDTPS92520_CH2IADJH_Tx, CDDTPS92520_CH1IADJL_Rx }, \ /* 93 */ { 94u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH2IADJL_Tx, CDDTPS92520_CH2IADJL_Tx, CDDTPS92520_CH2IADJH_Rx }, \ /* 94 */ { 95u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrSTATUS1_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2IADJL_Rx }, \ /* 95 */ { 96u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrSTATUS2_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_STATUS1_Rx }, \ /* 96 */ { 97u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrTWLMT_Tx, CDDTPS92520_TWLMT_Tx, CDDTPS92520_STATUS2_Rx }, \ /* 97 */ { 98u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrLHCFG1_Tx, CDDTPS92520_LHCFG1_Tx, CDDTPS92520_TWLMT_Rx }, \ /* 98 */ { 99u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrSLEEP_Tx, CDDTPS92520_SLEEP_Tx, CDDTPS92520_LHCFG1_Rx }, \ /*---------------------------- Cyclic 50ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 199 */ { 100u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrSYSCFG1_Tx, CDDTPS92520_SYSCFG1_Tx, CDDTPS92520_SLEEP_Rx }, \ /* 100 */ { 101u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrSTATUS3_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_SYSCFG1_Rx }, \ /* 101 */ { 102u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VIN_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_STATUS3_Rx }, \ /* 102 */ { 103u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VLED_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VIN_Rx }, \ /* 103 */ { 104u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VLEDON_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VLED_Rx }, \ /* 104 */ { 105u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VLEDOFF_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VLEDON_Rx }, \ /* 105 */ { 106u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VIN_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VLEDOFF_Rx }, \ /* 106 */ { 107u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VLED_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2VIN_Rx }, \ /* 107 */ { 108u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VLEDON_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2VLED_Rx }, \ /* 108 */ { 109u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VLEDOFF_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2VLEDON_Rx }, \ /*---------------------------- Cyclic 60ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 109 */ { 110u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrSYSCFG1_Tx, CDDTPS92520_SYSCFG1_Tx, CDDTPS92520_CH2VLEDOFF_Rx }, \ /* 110 */ { 111u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH1IADJH_Tx, CDDTPS92520_CH1IADJH_Tx, CDDTPS92520_SYSCFG1_Rx }, \ /* 111 */ { 112u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH1IADJL_Tx, CDDTPS92520_CH1IADJL_Tx, CDDTPS92520_CH1IADJH_Rx }, \ /* 112 */ { 113u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH2IADJH_Tx, CDDTPS92520_CH2IADJH_Tx, CDDTPS92520_CH1IADJL_Rx }, \ /* 113 */ { 114u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH2IADJL_Tx, CDDTPS92520_CH2IADJL_Tx, CDDTPS92520_CH2IADJH_Rx }, \ /* 114 */ { 115u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrSTATUS1_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2IADJL_Rx }, \ /* 115 */ { 116u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrSTATUS2_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_STATUS1_Rx }, \ /* 116 */ { 117u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH1TON_Tx, CDDTPS92520_CH1TON_Tx, CDDTPS92520_STATUS2_Rx }, \ /* 117 */ { 118u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrCH2TON_Tx, CDDTPS92520_CH2TON_Tx, CDDTPS92520_CH1TON_Rx }, \ /* 118 */ { 119u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrSLEEP_Tx, CDDTPS92520_SLEEP_Tx, CDDTPS92520_CH2TON_Rx }, \ /*---------------------------- Cyclic 70ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 119 */ { 120u, CDDTPS92520_NO_ACT, CDDTPS92520_WriteCmdBit_Tx, CDDTPS92520_AddrSYSCFG1_Tx, CDDTPS92520_SYSCFG1_Tx, CDDTPS92520_SLEEP_Rx }, \ /* 120 */ { 121u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrSTATUS3_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_SYSCFG1_Rx }, \ /* 121 */ { 122u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VIN_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_STATUS3_Rx }, \ /* 122 */ { 123u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VLED_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VIN_Rx }, \ /* 123 */ { 124u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VLEDON_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VLED_Rx }, \ /* 124 */ { 125u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH1VLEDOFF_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VLEDON_Rx }, \ /* 125 */ { 126u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VIN_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH1VLEDOFF_Rx }, \ /* 126 */ { 127u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VLED_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2VIN_Rx }, \ /* 127 */ { 128u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VLEDON_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2VLED_Rx }, \ /* 128 */ { 49u, CDDTPS92520_NO_ACT, CDDTPS92520_ReadCmdBit_Tx, CDDTPS92520_AddrCH2VLEDOFF_Tx, CDDTPS92520_Zero_Tx, CDDTPS92520_CH2VLEDON_Rx } \ /*---------------------------- Cyclic 80ms ------------------------------------------------------------------------------------------------------------------*/ \ } #endif // CDD_TPS92520_SCHED_2021_01_21_H_