#ifndef DEVICE_2020_06_08_H_ #define DEVICE_2020_06_08_H_ //============================================================================= // Target Device File (CYPRESS TRAVEO II) //============================================================================= //============================================================================= // includes //============================================================================= #include "Std_Types.h" //============================================================================= // SCB //============================================================================= /** * \brief Generic control (SCB_CTRL) */ typedef struct stc_SCB_CTRL_field { uint32 u4OVS:4; uint32 :4; uint32 u1EC_AM_MODE:1; uint32 u1EC_OP_MODE:1; uint32 u1EZ_MODE:1; uint32 :1; uint32 u1CMD_RESP_MODE:1; uint32 :1; uint32 u2MEM_WIDTH:2; uint32 u1ADDR_ACCEPT:1; uint32 u1BLOCK:1; uint32 :6; uint32 u2MODE:2; uint32 :2; uint32 u1EC_ACCESS:1; uint32 :2; uint32 u1ENABLED:1; } stc_SCB_CTRL_field_t; typedef union un_SCB_CTRL { uint32 u32Register; stc_SCB_CTRL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_CTRL_t; /** * \brief Generic status (SCB_STATUS) */ typedef struct stc_SCB_STATUS_field { uint32 u1EC_BUSY:1; uint32 :31; } stc_SCB_STATUS_field_t; typedef union un_SCB_STATUS { uint32 u32Register; stc_SCB_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_STATUS_t; /** * \brief Command/response control (SCB_CMD_RESP_CTRL) */ typedef struct stc_SCB_CMD_RESP_CTRL_field { uint32 u9BASE_RD_ADDR:9; uint32 :7; uint32 u9BASE_WR_ADDR:9; uint32 :7; } stc_SCB_CMD_RESP_CTRL_field_t; typedef union un_SCB_CMD_RESP_CTRL { uint32 u32Register; stc_SCB_CMD_RESP_CTRL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_CMD_RESP_CTRL_t; /** * \brief Command/response status (SCB_CMD_RESP_STATUS) */ typedef struct stc_SCB_CMD_RESP_STATUS_field { uint32 u9CURR_RD_ADDR:9; uint32 :7; uint32 u9CURR_WR_ADDR:9; uint32 :5; uint32 u1CMD_RESP_EC_BUS_BUSY:1; uint32 u1CMD_RESP_EC_BUSY:1; } stc_SCB_CMD_RESP_STATUS_field_t; typedef union un_SCB_CMD_RESP_STATUS { uint32 u32Register; stc_SCB_CMD_RESP_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_CMD_RESP_STATUS_t; /** * \brief SPI control (SCB_SPI_CTRL) */ typedef struct stc_SCB_SPI_CTRL_field { uint32 u1SSEL_CONTINUOUS:1; uint32 u1SELECT_PRECEDE:1; uint32 u1CPHA:1; uint32 u1CPOL:1; uint32 u1LATE_MISO_SAMPLE:1; uint32 u1SCLK_CONTINUOUS:1; uint32 :2; uint32 u1SSEL_POLARITY0:1; uint32 u1SSEL_POLARITY1:1; uint32 u1SSEL_POLARITY2:1; uint32 u1SSEL_POLARITY3:1; uint32 u1SSEL_SETUP_DEL:1; uint32 u1SSEL_HOLD_DEL:1; uint32 u1SSEL_INTER_FRAME_DEL:1; uint32 :1; uint32 u1LOOPBACK:1; uint32 :7; uint32 u2MODE:2; uint32 u2SSEL:2; uint32 :3; uint32 u1MASTER_MODE:1; } stc_SCB_SPI_CTRL_field_t; typedef union un_SCB_SPI_CTRL { uint32 u32Register; stc_SCB_SPI_CTRL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_SPI_CTRL_t; /** * \brief SPI status (SCB_SPI_STATUS) */ typedef struct stc_SCB_SPI_STATUS_field { uint32 u1BUS_BUSY:1; uint32 u1SPI_EC_BUSY:1; uint32 :6; uint32 u8CURR_EZ_ADDR:8; uint32 u8BASE_EZ_ADDR:8; uint32 :8; } stc_SCB_SPI_STATUS_field_t; typedef union un_SCB_SPI_STATUS { uint32 u32Register; stc_SCB_SPI_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_SPI_STATUS_t; /** * \brief SPI transmitter control (SCB_SPI_TX_CTRL) */ typedef struct stc_SCB_SPI_TX_CTRL_field { uint32 :4; uint32 u1PARITY:1; uint32 u1PARITY_ENABLED:1; uint32 :26; } stc_SCB_SPI_TX_CTRL_field_t; typedef union un_SCB_SPI_TX_CTRL { uint32 u32Register; stc_SCB_SPI_TX_CTRL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_SPI_TX_CTRL_t; /** * \brief SPI receiver control (SCB_SPI_RX_CTRL) */ typedef struct stc_SCB_SPI_RX_CTRL_field { uint32 :4; uint32 u1PARITY:1; uint32 u1PARITY_ENABLED:1; uint32 :2; uint32 u1DROP_ON_PARITY_ERROR:1; uint32 :23; } stc_SCB_SPI_RX_CTRL_field_t; typedef union un_SCB_SPI_RX_CTRL { uint32 u32Register; stc_SCB_SPI_RX_CTRL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_SPI_RX_CTRL_t; /** * \brief UART control (SCB_UART_CTRL) */ typedef struct stc_SCB_UART_CTRL_field { uint32 :16; uint32 u1LOOPBACK:1; uint32 :7; uint32 u2MODE:2; uint32 :6; } stc_SCB_UART_CTRL_field_t; typedef union un_SCB_UART_CTRL { uint32 u32Register; stc_SCB_UART_CTRL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_UART_CTRL_t; /** * \brief UART transmitter control (SCB_UART_TX_CTRL) */ typedef struct stc_SCB_UART_TX_CTRL_field { uint32 u3STOP_BITS:3; uint32 :1; uint32 u1PARITY:1; uint32 u1PARITY_ENABLED:1; uint32 :2; uint32 u1RETRY_ON_NACK:1; uint32 :23; } stc_SCB_UART_TX_CTRL_field_t; typedef union un_SCB_UART_TX_CTRL { uint32 u32Register; stc_SCB_UART_TX_CTRL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_UART_TX_CTRL_t; /** * \brief UART receiver control (SCB_UART_RX_CTRL) */ typedef struct stc_SCB_UART_RX_CTRL_field { uint32 u3STOP_BITS:3; uint32 :1; uint32 u1PARITY:1; uint32 u1PARITY_ENABLED:1; uint32 u1POLARITY:1; uint32 :1; uint32 u1DROP_ON_PARITY_ERROR:1; uint32 u1DROP_ON_FRAME_ERROR:1; uint32 u1MP_MODE:1; uint32 :1; uint32 u1LIN_MODE:1; uint32 u1SKIP_START:1; uint32 :2; uint32 u4BREAK_WIDTH:4; uint32 :4; uint32 u1BREAK_LEVEL:1; uint32 :7; } stc_SCB_UART_RX_CTRL_field_t; typedef union un_SCB_UART_RX_CTRL { uint32 u32Register; stc_SCB_UART_RX_CTRL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_UART_RX_CTRL_t; /** * \brief UART receiver status (SCB_UART_RX_STATUS) */ typedef struct stc_SCB_UART_RX_STATUS_field { uint32 u12BR_COUNTER:12; uint32 :20; } stc_SCB_UART_RX_STATUS_field_t; typedef union un_SCB_UART_RX_STATUS { uint32 u32Register; stc_SCB_UART_RX_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_UART_RX_STATUS_t; /** * \brief UART flow control (SCB_UART_FLOW_CTRL) */ typedef struct stc_SCB_UART_FLOW_CTRL_field { uint32 u8TRIGGER_LEVEL:8; uint32 :8; uint32 u1RTS_POLARITY:1; uint32 :7; uint32 u1CTS_POLARITY:1; uint32 u1CTS_ENABLED:1; uint32 :6; } stc_SCB_UART_FLOW_CTRL_field_t; typedef union un_SCB_UART_FLOW_CTRL { uint32 u32Register; stc_SCB_UART_FLOW_CTRL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_UART_FLOW_CTRL_t; /** * \brief I2C control (SCB_I2C_CTRL) */ typedef struct stc_SCB_I2C_CTRL_field { uint32 u4HIGH_PHASE_OVS:4; uint32 u4LOW_PHASE_OVS:4; uint32 u1M_READY_DATA_ACK:1; uint32 u1M_NOT_READY_DATA_NACK:1; uint32 :1; uint32 u1S_GENERAL_IGNORE:1; uint32 u1S_READY_ADDR_ACK:1; uint32 u1S_READY_DATA_ACK:1; uint32 u1S_NOT_READY_ADDR_NACK:1; uint32 u1S_NOT_READY_DATA_NACK:1; uint32 u1LOOPBACK:1; uint32 :13; uint32 u1SLAVE_MODE:1; uint32 u1MASTER_MODE:1; } stc_SCB_I2C_CTRL_field_t; typedef union un_SCB_I2C_CTRL { uint32 u32Register; stc_SCB_I2C_CTRL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_I2C_CTRL_t; /** * \brief I2C status (SCB_I2C_STATUS) */ typedef struct stc_SCB_I2C_STATUS_field { uint32 u1BUS_BUSY:1; uint32 u1I2C_EC_BUSY:1; uint32 u1I2CS_IC_BUSY:1; uint32 :1; uint32 u1S_READ:1; uint32 u1M_READ:1; uint32 :2; uint32 u8CURR_EZ_ADDR:8; uint32 u8BASE_EZ_ADDR:8; uint32 :8; } stc_SCB_I2C_STATUS_field_t; typedef union un_SCB_I2C_STATUS { uint32 u32Register; stc_SCB_I2C_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_I2C_STATUS_t; /** * \brief I2C master command (SCB_I2C_M_CMD) */ typedef struct stc_SCB_I2C_M_CMD_field { uint32 u1M_START:1; uint32 u1M_START_ON_IDLE:1; uint32 u1M_ACK:1; uint32 u1M_NACK:1; uint32 u1M_STOP:1; uint32 :27; } stc_SCB_I2C_M_CMD_field_t; typedef union un_SCB_I2C_M_CMD { uint32 u32Register; stc_SCB_I2C_M_CMD_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_I2C_M_CMD_t; /** * \brief I2C slave command (SCB_I2C_S_CMD) */ typedef struct stc_SCB_I2C_S_CMD_field { uint32 u1S_ACK:1; uint32 u1S_NACK:1; uint32 :30; } stc_SCB_I2C_S_CMD_field_t; typedef union un_SCB_I2C_S_CMD { uint32 u32Register; stc_SCB_I2C_S_CMD_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_I2C_S_CMD_t; /** * \brief I2C configuration (SCB_I2C_CFG) */ typedef struct stc_SCB_I2C_CFG_field { uint32 u2SDA_IN_FILT_TRIM:2; uint32 :2; uint32 u1SDA_IN_FILT_SEL:1; uint32 :3; uint32 u2SCL_IN_FILT_TRIM:2; uint32 :2; uint32 u1SCL_IN_FILT_SEL:1; uint32 :3; uint32 u2SDA_OUT_FILT0_TRIM:2; uint32 u2SDA_OUT_FILT1_TRIM:2; uint32 u2SDA_OUT_FILT2_TRIM:2; uint32 :6; uint32 u2SDA_OUT_FILT_SEL:2; uint32 :2; } stc_SCB_I2C_CFG_field_t; typedef union un_SCB_I2C_CFG { uint32 u32Register; stc_SCB_I2C_CFG_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_I2C_CFG_t; /** * \brief Digital DfT control (SCB_DDFT_CTRL) */ typedef struct stc_SCB_DDFT_CTRL_field { uint32 u1DDFT_IN0_SEL:1; uint32 :3; uint32 u1DDFT_IN1_SEL:1; uint32 :11; uint32 u3DDFT_OUT0_SEL:3; uint32 :1; uint32 u3DDFT_OUT1_SEL:3; uint32 :9; } stc_SCB_DDFT_CTRL_field_t; typedef union un_SCB_DDFT_CTRL { uint32 u32Register; stc_SCB_DDFT_CTRL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_DDFT_CTRL_t; /** * \brief Transmitter control (SCB_TX_CTRL) */ typedef struct stc_SCB_TX_CTRL_field { uint32 u5DATA_WIDTH:5; uint32 :3; uint32 u1MSB_FIRST:1; uint32 :7; uint32 u1OPEN_DRAIN:1; uint32 :15; } stc_SCB_TX_CTRL_field_t; typedef union un_SCB_TX_CTRL { uint32 u32Register; stc_SCB_TX_CTRL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_TX_CTRL_t; /** * \brief Transmitter FIFO control (SCB_TX_FIFO_CTRL) */ typedef struct stc_SCB_TX_FIFO_CTRL_field { uint32 u8TRIGGER_LEVEL:8; uint32 :8; uint32 u1CLEAR:1; uint32 u1FREEZE:1; uint32 :14; } stc_SCB_TX_FIFO_CTRL_field_t; typedef union un_SCB_TX_FIFO_CTRL { uint32 u32Register; stc_SCB_TX_FIFO_CTRL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_TX_FIFO_CTRL_t; /** * \brief Transmitter FIFO status (SCB_TX_FIFO_STATUS) */ typedef struct stc_SCB_TX_FIFO_STATUS_field { uint32 u9USED:9; uint32 :6; uint32 u1SR_VALID:1; uint32 u8RD_PTR:8; uint32 u8WR_PTR:8; } stc_SCB_TX_FIFO_STATUS_field_t; typedef union un_SCB_TX_FIFO_STATUS { uint32 u32Register; stc_SCB_TX_FIFO_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_TX_FIFO_STATUS_t; /** * \brief Transmitter FIFO write (SCB_TX_FIFO_WR) */ typedef struct stc_SCB_TX_FIFO_WR_field { uint32 u32DATA:32; } stc_SCB_TX_FIFO_WR_field_t; typedef union un_SCB_TX_FIFO_WR { uint32 u32Register; stc_SCB_TX_FIFO_WR_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_TX_FIFO_WR_t; /** * \brief Receiver control (SCB_RX_CTRL) */ typedef struct stc_SCB_RX_CTRL_field { uint32 u5DATA_WIDTH:5; uint32 :3; uint32 u1MSB_FIRST:1; uint32 u1MEDIAN:1; uint32 :22; } stc_SCB_RX_CTRL_field_t; typedef union un_SCB_RX_CTRL { uint32 u32Register; stc_SCB_RX_CTRL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_RX_CTRL_t; /** * \brief Receiver FIFO control (SCB_RX_FIFO_CTRL) */ typedef struct stc_SCB_RX_FIFO_CTRL_field { uint32 u8TRIGGER_LEVEL:8; uint32 :8; uint32 u1CLEAR:1; uint32 u1FREEZE:1; uint32 :14; } stc_SCB_RX_FIFO_CTRL_field_t; typedef union un_SCB_RX_FIFO_CTRL { uint32 u32Register; stc_SCB_RX_FIFO_CTRL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_RX_FIFO_CTRL_t; /** * \brief Receiver FIFO status (SCB_RX_FIFO_STATUS) */ typedef struct stc_SCB_RX_FIFO_STATUS_field { uint32 u9USED:9; uint32 :6; uint32 u1SR_VALID:1; uint32 u8RD_PTR:8; uint32 u8WR_PTR:8; } stc_SCB_RX_FIFO_STATUS_field_t; typedef union un_SCB_RX_FIFO_STATUS { uint32 u32Register; stc_SCB_RX_FIFO_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_RX_FIFO_STATUS_t; /** * \brief Slave address and mask (SCB_RX_MATCH) */ typedef struct stc_SCB_RX_MATCH_field { uint32 u8ADDR:8; uint32 :8; uint32 u8MASK:8; uint32 :8; } stc_SCB_RX_MATCH_field_t; typedef union un_SCB_RX_MATCH { uint32 u32Register; stc_SCB_RX_MATCH_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_RX_MATCH_t; /** * \brief Receiver FIFO read (SCB_RX_FIFO_RD) */ typedef struct stc_SCB_RX_FIFO_RD_field { uint32 u32DATA:32; } stc_SCB_RX_FIFO_RD_field_t; typedef union un_SCB_RX_FIFO_RD { uint32 u32Register; stc_SCB_RX_FIFO_RD_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_RX_FIFO_RD_t; /** * \brief Receiver FIFO read silent (SCB_RX_FIFO_RD_SILENT) */ typedef struct stc_SCB_RX_FIFO_RD_SILENT_field { uint32 u32DATA:32; } stc_SCB_RX_FIFO_RD_SILENT_field_t; typedef union un_SCB_RX_FIFO_RD_SILENT { uint32 u32Register; stc_SCB_RX_FIFO_RD_SILENT_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_RX_FIFO_RD_SILENT_t; /** * \brief Memory buffer (SCB_EZ_DATA) */ typedef struct stc_SCB_EZ_DATA_field { uint32 u8EZ_DATA:8; uint32 :24; } stc_SCB_EZ_DATA_field_t; typedef union un_SCB_EZ_DATA { uint32 u32Register; stc_SCB_EZ_DATA_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_EZ_DATA_t; /** * \brief Active clocked interrupt signal (SCB_INTR_CAUSE) */ typedef struct stc_SCB_INTR_CAUSE_field { uint32 u1M:1; uint32 u1S:1; uint32 u1TX:1; uint32 u1RX:1; uint32 u1I2C_EC:1; uint32 u1SPI_EC:1; uint32 :26; } stc_SCB_INTR_CAUSE_field_t; typedef union un_SCB_INTR_CAUSE { uint32 u32Register; stc_SCB_INTR_CAUSE_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_CAUSE_t; /** * \brief Externally clocked I2C interrupt request (SCB_INTR_I2C_EC) */ typedef struct stc_SCB_INTR_I2C_EC_field { uint32 u1WAKE_UP:1; uint32 u1EZ_STOP:1; uint32 u1EZ_WRITE_STOP:1; uint32 u1EZ_READ_STOP:1; uint32 :28; } stc_SCB_INTR_I2C_EC_field_t; typedef union un_SCB_INTR_I2C_EC { uint32 u32Register; stc_SCB_INTR_I2C_EC_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_I2C_EC_t; /** * \brief Externally clocked I2C interrupt mask (SCB_INTR_I2C_EC_MASK) */ typedef struct stc_SCB_INTR_I2C_EC_MASK_field { uint32 u1WAKE_UP:1; uint32 u1EZ_STOP:1; uint32 u1EZ_WRITE_STOP:1; uint32 u1EZ_READ_STOP:1; uint32 :28; } stc_SCB_INTR_I2C_EC_MASK_field_t; typedef union un_SCB_INTR_I2C_EC_MASK { uint32 u32Register; stc_SCB_INTR_I2C_EC_MASK_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_I2C_EC_MASK_t; /** * \brief Externally clocked I2C interrupt masked (SCB_INTR_I2C_EC_MASKED) */ typedef struct stc_SCB_INTR_I2C_EC_MASKED_field { uint32 u1WAKE_UP:1; uint32 u1EZ_STOP:1; uint32 u1EZ_WRITE_STOP:1; uint32 u1EZ_READ_STOP:1; uint32 :28; } stc_SCB_INTR_I2C_EC_MASKED_field_t; typedef union un_SCB_INTR_I2C_EC_MASKED { uint32 u32Register; stc_SCB_INTR_I2C_EC_MASKED_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_I2C_EC_MASKED_t; /** * \brief Externally clocked SPI interrupt request (SCB_INTR_SPI_EC) */ typedef struct stc_SCB_INTR_SPI_EC_field { uint32 u1WAKE_UP:1; uint32 u1EZ_STOP:1; uint32 u1EZ_WRITE_STOP:1; uint32 u1EZ_READ_STOP:1; uint32 :28; } stc_SCB_INTR_SPI_EC_field_t; typedef union un_SCB_INTR_SPI_EC { uint32 u32Register; stc_SCB_INTR_SPI_EC_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_SPI_EC_t; /** * \brief Externally clocked SPI interrupt mask (SCB_INTR_SPI_EC_MASK) */ typedef struct stc_SCB_INTR_SPI_EC_MASK_field { uint32 u1WAKE_UP:1; uint32 u1EZ_STOP:1; uint32 u1EZ_WRITE_STOP:1; uint32 u1EZ_READ_STOP:1; uint32 :28; } stc_SCB_INTR_SPI_EC_MASK_field_t; typedef union un_SCB_INTR_SPI_EC_MASK { uint32 u32Register; stc_SCB_INTR_SPI_EC_MASK_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_SPI_EC_MASK_t; /** * \brief Externally clocked SPI interrupt masked (SCB_INTR_SPI_EC_MASKED) */ typedef struct stc_SCB_INTR_SPI_EC_MASKED_field { uint32 u1WAKE_UP:1; uint32 u1EZ_STOP:1; uint32 u1EZ_WRITE_STOP:1; uint32 u1EZ_READ_STOP:1; uint32 :28; } stc_SCB_INTR_SPI_EC_MASKED_field_t; typedef union un_SCB_INTR_SPI_EC_MASKED { uint32 u32Register; stc_SCB_INTR_SPI_EC_MASKED_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_SPI_EC_MASKED_t; /** * \brief Master interrupt request (SCB_INTR_M) */ typedef struct stc_SCB_INTR_M_field { uint32 u1I2C_ARB_LOST:1; uint32 u1I2C_NACK:1; uint32 u1I2C_ACK:1; uint32 :1; uint32 u1I2C_STOP:1; uint32 :3; uint32 u1I2C_BUS_ERROR:1; uint32 u1SPI_DONE:1; uint32 :22; } stc_SCB_INTR_M_field_t; typedef union un_SCB_INTR_M { uint32 u32Register; stc_SCB_INTR_M_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_M_t; /** * \brief Master interrupt set request (SCB_INTR_M_SET) */ typedef struct stc_SCB_INTR_M_SET_field { uint32 u1I2C_ARB_LOST:1; uint32 u1I2C_NACK:1; uint32 u1I2C_ACK:1; uint32 :1; uint32 u1I2C_STOP:1; uint32 :3; uint32 u1I2C_BUS_ERROR:1; uint32 u1SPI_DONE:1; uint32 :22; } stc_SCB_INTR_M_SET_field_t; typedef union un_SCB_INTR_M_SET { uint32 u32Register; stc_SCB_INTR_M_SET_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_M_SET_t; /** * \brief Master interrupt mask (SCB_INTR_M_MASK) */ typedef struct stc_SCB_INTR_M_MASK_field { uint32 u1I2C_ARB_LOST:1; uint32 u1I2C_NACK:1; uint32 u1I2C_ACK:1; uint32 :1; uint32 u1I2C_STOP:1; uint32 :3; uint32 u1I2C_BUS_ERROR:1; uint32 u1SPI_DONE:1; uint32 :22; } stc_SCB_INTR_M_MASK_field_t; typedef union un_SCB_INTR_M_MASK { uint32 u32Register; stc_SCB_INTR_M_MASK_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_M_MASK_t; /** * \brief Master interrupt masked request (SCB_INTR_M_MASKED) */ typedef struct stc_SCB_INTR_M_MASKED_field { uint32 u1I2C_ARB_LOST:1; uint32 u1I2C_NACK:1; uint32 u1I2C_ACK:1; uint32 :1; uint32 u1I2C_STOP:1; uint32 :3; uint32 u1I2C_BUS_ERROR:1; uint32 u1SPI_DONE:1; uint32 :22; } stc_SCB_INTR_M_MASKED_field_t; typedef union un_SCB_INTR_M_MASKED { uint32 u32Register; stc_SCB_INTR_M_MASKED_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_M_MASKED_t; /** * \brief Slave interrupt request (SCB_INTR_S) */ typedef struct stc_SCB_INTR_S_field { uint32 u1I2C_ARB_LOST:1; uint32 u1I2C_NACK:1; uint32 u1I2C_ACK:1; uint32 u1I2C_WRITE_STOP:1; uint32 u1I2C_STOP:1; uint32 u1I2C_START:1; uint32 u1I2C_ADDR_MATCH:1; uint32 u1I2C_GENERAL:1; uint32 u1I2C_BUS_ERROR:1; uint32 u1SPI_EZ_WRITE_STOP:1; uint32 u1SPI_EZ_STOP:1; uint32 u1SPI_BUS_ERROR:1; uint32 :20; } stc_SCB_INTR_S_field_t; typedef union un_SCB_INTR_S { uint32 u32Register; stc_SCB_INTR_S_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_S_t; /** * \brief Slave interrupt set request (SCB_INTR_S_SET) */ typedef struct stc_SCB_INTR_S_SET_field { uint32 u1I2C_ARB_LOST:1; uint32 u1I2C_NACK:1; uint32 u1I2C_ACK:1; uint32 u1I2C_WRITE_STOP:1; uint32 u1I2C_STOP:1; uint32 u1I2C_START:1; uint32 u1I2C_ADDR_MATCH:1; uint32 u1I2C_GENERAL:1; uint32 u1I2C_BUS_ERROR:1; uint32 u1SPI_EZ_WRITE_STOP:1; uint32 u1SPI_EZ_STOP:1; uint32 u1SPI_BUS_ERROR:1; uint32 :20; } stc_SCB_INTR_S_SET_field_t; typedef union un_SCB_INTR_S_SET { uint32 u32Register; stc_SCB_INTR_S_SET_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_S_SET_t; /** * \brief Slave interrupt mask (SCB_INTR_S_MASK) */ typedef struct stc_SCB_INTR_S_MASK_field { uint32 u1I2C_ARB_LOST:1; uint32 u1I2C_NACK:1; uint32 u1I2C_ACK:1; uint32 u1I2C_WRITE_STOP:1; uint32 u1I2C_STOP:1; uint32 u1I2C_START:1; uint32 u1I2C_ADDR_MATCH:1; uint32 u1I2C_GENERAL:1; uint32 u1I2C_BUS_ERROR:1; uint32 u1SPI_EZ_WRITE_STOP:1; uint32 u1SPI_EZ_STOP:1; uint32 u1SPI_BUS_ERROR:1; uint32 :20; } stc_SCB_INTR_S_MASK_field_t; typedef union un_SCB_INTR_S_MASK { uint32 u32Register; stc_SCB_INTR_S_MASK_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_S_MASK_t; /** * \brief Slave interrupt masked request (SCB_INTR_S_MASKED) */ typedef struct stc_SCB_INTR_S_MASKED_field { uint32 u1I2C_ARB_LOST:1; uint32 u1I2C_NACK:1; uint32 u1I2C_ACK:1; uint32 u1I2C_WRITE_STOP:1; uint32 u1I2C_STOP:1; uint32 u1I2C_START:1; uint32 u1I2C_ADDR_MATCH:1; uint32 u1I2C_GENERAL:1; uint32 u1I2C_BUS_ERROR:1; uint32 u1SPI_EZ_WRITE_STOP:1; uint32 u1SPI_EZ_STOP:1; uint32 u1SPI_BUS_ERROR:1; uint32 :20; } stc_SCB_INTR_S_MASKED_field_t; typedef union un_SCB_INTR_S_MASKED { uint32 u32Register; stc_SCB_INTR_S_MASKED_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_S_MASKED_t; /** * \brief Transmitter interrupt request (SCB_INTR_TX) */ typedef struct stc_SCB_INTR_TX_field { uint32 u1TRIGGER:1; uint32 u1NOT_FULL:1; uint32 :2; uint32 u1EMPTY:1; uint32 u1OVERFLOW:1; uint32 u1UNDERFLOW:1; uint32 u1BLOCKED:1; uint32 u1UART_NACK:1; uint32 u1UART_DONE:1; uint32 u1UART_ARB_LOST:1; uint32 :21; } stc_SCB_INTR_TX_field_t; typedef union un_SCB_INTR_TX { uint32 u32Register; stc_SCB_INTR_TX_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_TX_t; /** * \brief Transmitter interrupt set request (SCB_INTR_TX_SET) */ typedef struct stc_SCB_INTR_TX_SET_field { uint32 u1TRIGGER:1; uint32 u1NOT_FULL:1; uint32 :2; uint32 u1EMPTY:1; uint32 u1OVERFLOW:1; uint32 u1UNDERFLOW:1; uint32 u1BLOCKED:1; uint32 u1UART_NACK:1; uint32 u1UART_DONE:1; uint32 u1UART_ARB_LOST:1; uint32 :21; } stc_SCB_INTR_TX_SET_field_t; typedef union un_SCB_INTR_TX_SET { uint32 u32Register; stc_SCB_INTR_TX_SET_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_TX_SET_t; /** * \brief Transmitter interrupt mask (SCB_INTR_TX_MASK) */ typedef struct stc_SCB_INTR_TX_MASK_field { uint32 u1TRIGGER:1; uint32 u1NOT_FULL:1; uint32 :2; uint32 u1EMPTY:1; uint32 u1OVERFLOW:1; uint32 u1UNDERFLOW:1; uint32 u1BLOCKED:1; uint32 u1UART_NACK:1; uint32 u1UART_DONE:1; uint32 u1UART_ARB_LOST:1; uint32 :21; } stc_SCB_INTR_TX_MASK_field_t; typedef union un_SCB_INTR_TX_MASK { uint32 u32Register; stc_SCB_INTR_TX_MASK_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_TX_MASK_t; /** * \brief Transmitter interrupt masked request (SCB_INTR_TX_MASKED) */ typedef struct stc_SCB_INTR_TX_MASKED_field { uint32 u1TRIGGER:1; uint32 u1NOT_FULL:1; uint32 :2; uint32 u1EMPTY:1; uint32 u1OVERFLOW:1; uint32 u1UNDERFLOW:1; uint32 u1BLOCKED:1; uint32 u1UART_NACK:1; uint32 u1UART_DONE:1; uint32 u1UART_ARB_LOST:1; uint32 :21; } stc_SCB_INTR_TX_MASKED_field_t; typedef union un_SCB_INTR_TX_MASKED { uint32 u32Register; stc_SCB_INTR_TX_MASKED_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_TX_MASKED_t; /** * \brief Receiver interrupt request (SCB_INTR_RX) */ typedef struct stc_SCB_INTR_RX_field { uint32 u1TRIGGER:1; uint32 :1; uint32 u1NOT_EMPTY:1; uint32 u1FULL:1; uint32 :1; uint32 u1OVERFLOW:1; uint32 u1UNDERFLOW:1; uint32 u1BLOCKED:1; uint32 u1FRAME_ERROR:1; uint32 u1PARITY_ERROR:1; uint32 u1BAUD_DETECT:1; uint32 u1BREAK_DETECT:1; uint32 :20; } stc_SCB_INTR_RX_field_t; typedef union un_SCB_INTR_RX { uint32 u32Register; stc_SCB_INTR_RX_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_RX_t; /** * \brief Receiver interrupt set request (SCB_INTR_RX_SET) */ typedef struct stc_SCB_INTR_RX_SET_field { uint32 u1TRIGGER:1; uint32 :1; uint32 u1NOT_EMPTY:1; uint32 u1FULL:1; uint32 :1; uint32 u1OVERFLOW:1; uint32 u1UNDERFLOW:1; uint32 u1BLOCKED:1; uint32 u1FRAME_ERROR:1; uint32 u1PARITY_ERROR:1; uint32 u1BAUD_DETECT:1; uint32 u1BREAK_DETECT:1; uint32 :20; } stc_SCB_INTR_RX_SET_field_t; typedef union un_SCB_INTR_RX_SET { uint32 u32Register; stc_SCB_INTR_RX_SET_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_RX_SET_t; /** * \brief Receiver interrupt mask (SCB_INTR_RX_MASK) */ typedef struct stc_SCB_INTR_RX_MASK_field { uint32 u1TRIGGER:1; uint32 :1; uint32 u1NOT_EMPTY:1; uint32 u1FULL:1; uint32 :1; uint32 u1OVERFLOW:1; uint32 u1UNDERFLOW:1; uint32 u1BLOCKED:1; uint32 u1FRAME_ERROR:1; uint32 u1PARITY_ERROR:1; uint32 u1BAUD_DETECT:1; uint32 u1BREAK_DETECT:1; uint32 :20; } stc_SCB_INTR_RX_MASK_field_t; typedef union un_SCB_INTR_RX_MASK { uint32 u32Register; stc_SCB_INTR_RX_MASK_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_RX_MASK_t; /** * \brief Receiver interrupt masked request (SCB_INTR_RX_MASKED) */ typedef struct stc_SCB_INTR_RX_MASKED_field { uint32 u1TRIGGER:1; uint32 :1; uint32 u1NOT_EMPTY:1; uint32 u1FULL:1; uint32 :1; uint32 u1OVERFLOW:1; uint32 u1UNDERFLOW:1; uint32 u1BLOCKED:1; uint32 u1FRAME_ERROR:1; uint32 u1PARITY_ERROR:1; uint32 u1BAUD_DETECT:1; uint32 u1BREAK_DETECT:1; uint32 :20; } stc_SCB_INTR_RX_MASKED_field_t; typedef union un_SCB_INTR_RX_MASKED { uint32 u32Register; stc_SCB_INTR_RX_MASKED_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_SCB_INTR_RX_MASKED_t; /** * \brief Serial Communications Block (SPI/UART/I2C) (SCB) */ typedef struct stc_SCB { un_SCB_CTRL_t unCTRL; /*!< 0x00000000 Generic control */ un_SCB_STATUS_t unSTATUS; /*!< 0x00000004 Generic status */ un_SCB_CMD_RESP_CTRL_t unCMD_RESP_CTRL; /*!< 0x00000008 Command/response control */ un_SCB_CMD_RESP_STATUS_t unCMD_RESP_STATUS; /*!< 0x0000000C Command/response status */ uint32 au32Reserved[4]; un_SCB_SPI_CTRL_t unSPI_CTRL; /*!< 0x00000020 SPI control */ un_SCB_SPI_STATUS_t unSPI_STATUS; /*!< 0x00000024 SPI status */ un_SCB_SPI_TX_CTRL_t unSPI_TX_CTRL; /*!< 0x00000028 SPI transmitter control */ un_SCB_SPI_RX_CTRL_t unSPI_RX_CTRL; /*!< 0x0000002C SPI receiver control */ uint32 au32Reserved1[4]; un_SCB_UART_CTRL_t unUART_CTRL; /*!< 0x00000040 UART control */ un_SCB_UART_TX_CTRL_t unUART_TX_CTRL; /*!< 0x00000044 UART transmitter control */ un_SCB_UART_RX_CTRL_t unUART_RX_CTRL; /*!< 0x00000048 UART receiver control */ un_SCB_UART_RX_STATUS_t unUART_RX_STATUS; /*!< 0x0000004C UART receiver status */ un_SCB_UART_FLOW_CTRL_t unUART_FLOW_CTRL; /*!< 0x00000050 UART flow control */ uint32 au32Reserved2[3]; un_SCB_I2C_CTRL_t unI2C_CTRL; /*!< 0x00000060 I2C control */ un_SCB_I2C_STATUS_t unI2C_STATUS; /*!< 0x00000064 I2C status */ un_SCB_I2C_M_CMD_t unI2C_M_CMD; /*!< 0x00000068 I2C master command */ un_SCB_I2C_S_CMD_t unI2C_S_CMD; /*!< 0x0000006C I2C slave command */ un_SCB_I2C_CFG_t unI2C_CFG; /*!< 0x00000070 I2C configuration */ uint32 au32Reserved3[35]; un_SCB_DDFT_CTRL_t unDDFT_CTRL; /*!< 0x00000100 Digital DfT control */ uint32 au32Reserved4[63]; un_SCB_TX_CTRL_t unTX_CTRL; /*!< 0x00000200 Transmitter control */ un_SCB_TX_FIFO_CTRL_t unTX_FIFO_CTRL; /*!< 0x00000204 Transmitter FIFO control */ un_SCB_TX_FIFO_STATUS_t unTX_FIFO_STATUS; /*!< 0x00000208 Transmitter FIFO status */ uint32 au32Reserved5[13]; un_SCB_TX_FIFO_WR_t unTX_FIFO_WR; /*!< 0x00000240 Transmitter FIFO write */ uint32 au32Reserved6[47]; un_SCB_RX_CTRL_t unRX_CTRL; /*!< 0x00000300 Receiver control */ un_SCB_RX_FIFO_CTRL_t unRX_FIFO_CTRL; /*!< 0x00000304 Receiver FIFO control */ un_SCB_RX_FIFO_STATUS_t unRX_FIFO_STATUS; /*!< 0x00000308 Receiver FIFO status */ uint32 u32Reserved7; un_SCB_RX_MATCH_t unRX_MATCH; /*!< 0x00000310 Slave address and mask */ uint32 au32Reserved8[11]; un_SCB_RX_FIFO_RD_t unRX_FIFO_RD; /*!< 0x00000340 Receiver FIFO read */ un_SCB_RX_FIFO_RD_SILENT_t unRX_FIFO_RD_SILENT; /*!< 0x00000344 Receiver FIFO read silent */ uint32 au32Reserved9[46]; un_SCB_EZ_DATA_t unEZ_DATA[512]; /*!< 0x00000400 Memory buffer */ uint32 au32Reserved10[128]; un_SCB_INTR_CAUSE_t unINTR_CAUSE; /*!< 0x00000E00 Active clocked interrupt signal */ uint32 au32Reserved11[31]; un_SCB_INTR_I2C_EC_t unINTR_I2C_EC; /*!< 0x00000E80 Externally clocked I2C interrupt request */ uint32 u32Reserved12; un_SCB_INTR_I2C_EC_MASK_t unINTR_I2C_EC_MASK; /*!< 0x00000E88 Externally clocked I2C interrupt mask */ un_SCB_INTR_I2C_EC_MASKED_t unINTR_I2C_EC_MASKED; /*!< 0x00000E8C Externally clocked I2C interrupt masked */ uint32 au32Reserved13[12]; un_SCB_INTR_SPI_EC_t unINTR_SPI_EC; /*!< 0x00000EC0 Externally clocked SPI interrupt request */ uint32 u32Reserved14; un_SCB_INTR_SPI_EC_MASK_t unINTR_SPI_EC_MASK; /*!< 0x00000EC8 Externally clocked SPI interrupt mask */ un_SCB_INTR_SPI_EC_MASKED_t unINTR_SPI_EC_MASKED; /*!< 0x00000ECC Externally clocked SPI interrupt masked */ uint32 au32Reserved15[12]; un_SCB_INTR_M_t unINTR_M; /*!< 0x00000F00 Master interrupt request */ un_SCB_INTR_M_SET_t unINTR_M_SET; /*!< 0x00000F04 Master interrupt set request */ un_SCB_INTR_M_MASK_t unINTR_M_MASK; /*!< 0x00000F08 Master interrupt mask */ un_SCB_INTR_M_MASKED_t unINTR_M_MASKED; /*!< 0x00000F0C Master interrupt masked request */ uint32 au32Reserved16[12]; un_SCB_INTR_S_t unINTR_S; /*!< 0x00000F40 Slave interrupt request */ un_SCB_INTR_S_SET_t unINTR_S_SET; /*!< 0x00000F44 Slave interrupt set request */ un_SCB_INTR_S_MASK_t unINTR_S_MASK; /*!< 0x00000F48 Slave interrupt mask */ un_SCB_INTR_S_MASKED_t unINTR_S_MASKED; /*!< 0x00000F4C Slave interrupt masked request */ uint32 au32Reserved17[12]; un_SCB_INTR_TX_t unINTR_TX; /*!< 0x00000F80 Transmitter interrupt request */ un_SCB_INTR_TX_SET_t unINTR_TX_SET; /*!< 0x00000F84 Transmitter interrupt set request */ un_SCB_INTR_TX_MASK_t unINTR_TX_MASK; /*!< 0x00000F88 Transmitter interrupt mask */ un_SCB_INTR_TX_MASKED_t unINTR_TX_MASKED; /*!< 0x00000F8C Transmitter interrupt masked request */ uint32 au32Reserved18[12]; un_SCB_INTR_RX_t unINTR_RX; /*!< 0x00000FC0 Receiver interrupt request */ un_SCB_INTR_RX_SET_t unINTR_RX_SET; /*!< 0x00000FC4 Receiver interrupt set request */ un_SCB_INTR_RX_MASK_t unINTR_RX_MASK; /*!< 0x00000FC8 Receiver interrupt mask */ un_SCB_INTR_RX_MASKED_t unINTR_RX_MASKED; /*!< 0x00000FCC Receiver interrupt masked request */ } stc_SCB_t; /*!< Size = 4048 (0xFD0) */ #define SCB0_BASE 0x40600000UL #define SCB1_BASE 0x40610000UL #define SCB2_BASE 0x40620000UL #define SCB3_BASE 0x40630000UL #define SCB4_BASE 0x40640000UL #define SCB5_BASE 0x40650000UL #define SCB6_BASE 0x40660000UL #define SCB7_BASE 0x40670000UL #define SCB0 ((volatile stc_SCB_t* const) SCB0_BASE) /* 0x40600000 */ #define SCB1 ((volatile stc_SCB_t* const) SCB1_BASE) /* 0x40610000 */ #define SCB2 ((volatile stc_SCB_t* const) SCB2_BASE) /* 0x40620000 */ #define SCB3 ((volatile stc_SCB_t* const) SCB3_BASE) /* 0x40630000 */ #define SCB4 ((volatile stc_SCB_t* const) SCB4_BASE) /* 0x40640000 */ #define SCB5 ((volatile stc_SCB_t* const) SCB5_BASE) /* 0x40650000 */ #define SCB6 ((volatile stc_SCB_t* const) SCB6_BASE) /* 0x40660000 */ #define SCB7 ((volatile stc_SCB_t* const) SCB7_BASE) /* 0x40670000 */ /******************************************************************************* * GPIO *******************************************************************************/ /** * \brief Port output data register (GPIO_PRT_OUT) */ typedef struct stc_GPIO_PRT_OUT_field { uint32 u1OUT0:1; uint32 u1OUT1:1; uint32 u1OUT2:1; uint32 u1OUT3:1; uint32 u1OUT4:1; uint32 u1OUT5:1; uint32 u1OUT6:1; uint32 u1OUT7:1; uint32 :24; } stc_GPIO_PRT_OUT_field_t; typedef union un_GPIO_PRT_OUT { uint32 u32Register; stc_GPIO_PRT_OUT_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_PRT_OUT_t; /** * \brief Port output data clear register (GPIO_PRT_OUT_CLR) */ typedef struct stc_GPIO_PRT_OUT_CLR_field { uint32 u1OUT0:1; uint32 u1OUT1:1; uint32 u1OUT2:1; uint32 u1OUT3:1; uint32 u1OUT4:1; uint32 u1OUT5:1; uint32 u1OUT6:1; uint32 u1OUT7:1; uint32 :24; } stc_GPIO_PRT_OUT_CLR_field_t; typedef union un_GPIO_PRT_OUT_CLR { uint32 u32Register; stc_GPIO_PRT_OUT_CLR_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_PRT_OUT_CLR_t; /** * \brief Port output data set register (GPIO_PRT_OUT_SET) */ typedef struct stc_GPIO_PRT_OUT_SET_field { uint32 u1OUT0:1; uint32 u1OUT1:1; uint32 u1OUT2:1; uint32 u1OUT3:1; uint32 u1OUT4:1; uint32 u1OUT5:1; uint32 u1OUT6:1; uint32 u1OUT7:1; uint32 :24; } stc_GPIO_PRT_OUT_SET_field_t; typedef union un_GPIO_PRT_OUT_SET { uint32 u32Register; stc_GPIO_PRT_OUT_SET_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_PRT_OUT_SET_t; /** * \brief Port output data invert register (GPIO_PRT_OUT_INV) */ typedef struct stc_GPIO_PRT_OUT_INV_field { uint32 u1OUT0:1; uint32 u1OUT1:1; uint32 u1OUT2:1; uint32 u1OUT3:1; uint32 u1OUT4:1; uint32 u1OUT5:1; uint32 u1OUT6:1; uint32 u1OUT7:1; uint32 :24; } stc_GPIO_PRT_OUT_INV_field_t; typedef union un_GPIO_PRT_OUT_INV { uint32 u32Register; stc_GPIO_PRT_OUT_INV_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_PRT_OUT_INV_t; /** * \brief Port input state register (GPIO_PRT_IN) */ typedef struct stc_GPIO_PRT_IN_field { uint32 u1IN0:1; uint32 u1IN1:1; uint32 u1IN2:1; uint32 u1IN3:1; uint32 u1IN4:1; uint32 u1IN5:1; uint32 u1IN6:1; uint32 u1IN7:1; uint32 u1FLT_IN:1; uint32 :23; } stc_GPIO_PRT_IN_field_t; typedef union un_GPIO_PRT_IN { uint32 u32Register; stc_GPIO_PRT_IN_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_PRT_IN_t; /** * \brief Port interrupt status register (GPIO_PRT_INTR) */ typedef struct stc_GPIO_PRT_INTR_field { uint32 u1EDGE0:1; uint32 u1EDGE1:1; uint32 u1EDGE2:1; uint32 u1EDGE3:1; uint32 u1EDGE4:1; uint32 u1EDGE5:1; uint32 u1EDGE6:1; uint32 u1EDGE7:1; uint32 u1FLT_EDGE:1; uint32 :7; uint32 u1IN_IN0:1; uint32 u1IN_IN1:1; uint32 u1IN_IN2:1; uint32 u1IN_IN3:1; uint32 u1IN_IN4:1; uint32 u1IN_IN5:1; uint32 u1IN_IN6:1; uint32 u1IN_IN7:1; uint32 u1FLT_IN_IN:1; uint32 :7; } stc_GPIO_PRT_INTR_field_t; typedef union un_GPIO_PRT_INTR { uint32 u32Register; stc_GPIO_PRT_INTR_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_PRT_INTR_t; /** * \brief Port interrupt mask register (GPIO_PRT_INTR_MASK) */ typedef struct stc_GPIO_PRT_INTR_MASK_field { uint32 u1EDGE0:1; uint32 u1EDGE1:1; uint32 u1EDGE2:1; uint32 u1EDGE3:1; uint32 u1EDGE4:1; uint32 u1EDGE5:1; uint32 u1EDGE6:1; uint32 u1EDGE7:1; uint32 u1FLT_EDGE:1; uint32 :23; } stc_GPIO_PRT_INTR_MASK_field_t; typedef union un_GPIO_PRT_INTR_MASK { uint32 u32Register; stc_GPIO_PRT_INTR_MASK_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_PRT_INTR_MASK_t; /** * \brief Port interrupt masked status register (GPIO_PRT_INTR_MASKED) */ typedef struct stc_GPIO_PRT_INTR_MASKED_field { uint32 u1EDGE0:1; uint32 u1EDGE1:1; uint32 u1EDGE2:1; uint32 u1EDGE3:1; uint32 u1EDGE4:1; uint32 u1EDGE5:1; uint32 u1EDGE6:1; uint32 u1EDGE7:1; uint32 u1FLT_EDGE:1; uint32 :23; } stc_GPIO_PRT_INTR_MASKED_field_t; typedef union un_GPIO_PRT_INTR_MASKED { uint32 u32Register; stc_GPIO_PRT_INTR_MASKED_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_PRT_INTR_MASKED_t; /** * \brief Port interrupt set register (GPIO_PRT_INTR_SET) */ typedef struct stc_GPIO_PRT_INTR_SET_field { uint32 u1EDGE0:1; uint32 u1EDGE1:1; uint32 u1EDGE2:1; uint32 u1EDGE3:1; uint32 u1EDGE4:1; uint32 u1EDGE5:1; uint32 u1EDGE6:1; uint32 u1EDGE7:1; uint32 u1FLT_EDGE:1; uint32 :23; } stc_GPIO_PRT_INTR_SET_field_t; typedef union un_GPIO_PRT_INTR_SET { uint32 u32Register; stc_GPIO_PRT_INTR_SET_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_PRT_INTR_SET_t; /** * \brief Port interrupt configuration register (GPIO_PRT_INTR_CFG) */ typedef struct stc_GPIO_PRT_INTR_CFG_field { uint32 u2EDGE0_SEL:2; uint32 u2EDGE1_SEL:2; uint32 u2EDGE2_SEL:2; uint32 u2EDGE3_SEL:2; uint32 u2EDGE4_SEL:2; uint32 u2EDGE5_SEL:2; uint32 u2EDGE6_SEL:2; uint32 u2EDGE7_SEL:2; uint32 u2FLT_EDGE_SEL:2; uint32 u3FLT_SEL:3; uint32 :11; } stc_GPIO_PRT_INTR_CFG_field_t; typedef union un_GPIO_PRT_INTR_CFG { uint32 u32Register; stc_GPIO_PRT_INTR_CFG_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_PRT_INTR_CFG_t; /** * \brief Port configuration register (GPIO_PRT_CFG) */ typedef struct stc_GPIO_PRT_CFG_field { uint32 u3DRIVE_MODE0:3; uint32 u1IN_EN0:1; uint32 u3DRIVE_MODE1:3; uint32 u1IN_EN1:1; uint32 u3DRIVE_MODE2:3; uint32 u1IN_EN2:1; uint32 u3DRIVE_MODE3:3; uint32 u1IN_EN3:1; uint32 u3DRIVE_MODE4:3; uint32 u1IN_EN4:1; uint32 u3DRIVE_MODE5:3; uint32 u1IN_EN5:1; uint32 u3DRIVE_MODE6:3; uint32 u1IN_EN6:1; uint32 u3DRIVE_MODE7:3; uint32 u1IN_EN7:1; } stc_GPIO_PRT_CFG_field_t; typedef union un_GPIO_PRT_CFG { uint32 u32Register; stc_GPIO_PRT_CFG_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_PRT_CFG_t; /** * \brief Port input buffer configuration register (GPIO_PRT_CFG_IN) */ typedef struct stc_GPIO_PRT_CFG_IN_field { uint32 u1VTRIP_SEL0_0:1; uint32 u1VTRIP_SEL1_0:1; uint32 u1VTRIP_SEL2_0:1; uint32 u1VTRIP_SEL3_0:1; uint32 u1VTRIP_SEL4_0:1; uint32 u1VTRIP_SEL5_0:1; uint32 u1VTRIP_SEL6_0:1; uint32 u1VTRIP_SEL7_0:1; uint32 :24; } stc_GPIO_PRT_CFG_IN_field_t; typedef union un_GPIO_PRT_CFG_IN { uint32 u32Register; stc_GPIO_PRT_CFG_IN_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_PRT_CFG_IN_t; /** * \brief Port output buffer configuration register (GPIO_PRT_CFG_OUT) */ typedef struct stc_GPIO_PRT_CFG_OUT_field { uint32 u1SLOW0:1; uint32 u1SLOW1:1; uint32 u1SLOW2:1; uint32 u1SLOW3:1; uint32 u1SLOW4:1; uint32 u1SLOW5:1; uint32 u1SLOW6:1; uint32 u1SLOW7:1; uint32 :8; uint32 u2DRIVE_SEL0:2; uint32 u2DRIVE_SEL1:2; uint32 u2DRIVE_SEL2:2; uint32 u2DRIVE_SEL3:2; uint32 u2DRIVE_SEL4:2; uint32 u2DRIVE_SEL5:2; uint32 u2DRIVE_SEL6:2; uint32 u2DRIVE_SEL7:2; } stc_GPIO_PRT_CFG_OUT_field_t; typedef union un_GPIO_PRT_CFG_OUT { uint32 u32Register; stc_GPIO_PRT_CFG_OUT_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_PRT_CFG_OUT_t; /** * \brief Port SIO configuration register (GPIO_PRT_CFG_SIO) */ typedef struct stc_GPIO_PRT_CFG_SIO_field { uint32 u1VREG_EN01:1; uint32 u1IBUF_SEL01:1; uint32 u1VTRIP_SEL01:1; uint32 u2VREF_SEL01:2; uint32 u3VOH_SEL01:3; uint32 u1VREG_EN23:1; uint32 u1IBUF_SEL23:1; uint32 u1VTRIP_SEL23:1; uint32 u2VREF_SEL23:2; uint32 u3VOH_SEL23:3; uint32 u1VREG_EN45:1; uint32 u1IBUF_SEL45:1; uint32 u1VTRIP_SEL45:1; uint32 u2VREF_SEL45:2; uint32 u3VOH_SEL45:3; uint32 u1VREG_EN67:1; uint32 u1IBUF_SEL67:1; uint32 u1VTRIP_SEL67:1; uint32 u2VREF_SEL67:2; uint32 u3VOH_SEL67:3; } stc_GPIO_PRT_CFG_SIO_field_t; typedef union un_GPIO_PRT_CFG_SIO { uint32 u32Register; stc_GPIO_PRT_CFG_SIO_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_PRT_CFG_SIO_t; /** * \brief Port GPIO5V input buffer configuration register (GPIO_PRT_CFG_IN_GPIO5V) */ typedef struct stc_GPIO_PRT_CFG_IN_GPIO5V_field { uint32 u1VTRIP_SEL0_1:1; uint32 u1VTRIP_SEL1_1:1; uint32 u1VTRIP_SEL2_1:1; uint32 u1VTRIP_SEL3_1:1; uint32 u1VTRIP_SEL4_1:1; uint32 u1VTRIP_SEL5_1:1; uint32 u1VTRIP_SEL6_1:1; uint32 u1VTRIP_SEL7_1:1; uint32 :24; } stc_GPIO_PRT_CFG_IN_GPIO5V_field_t; typedef union un_GPIO_PRT_CFG_IN_GPIO5V { uint32 u32Register; stc_GPIO_PRT_CFG_IN_GPIO5V_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_PRT_CFG_IN_GPIO5V_t; /** * \brief Interrupt port cause register 0 (GPIO_INTR_CAUSE0) */ typedef struct stc_GPIO_INTR_CAUSE0_field { uint32 u32PORT_INT:32; } stc_GPIO_INTR_CAUSE0_field_t; typedef union un_GPIO_INTR_CAUSE0 { uint32 u32Register; stc_GPIO_INTR_CAUSE0_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_INTR_CAUSE0_t; /** * \brief Interrupt port cause register 1 (GPIO_INTR_CAUSE1) */ typedef struct stc_GPIO_INTR_CAUSE1_field { uint32 u32PORT_INT:32; } stc_GPIO_INTR_CAUSE1_field_t; typedef union un_GPIO_INTR_CAUSE1 { uint32 u32Register; stc_GPIO_INTR_CAUSE1_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_INTR_CAUSE1_t; /** * \brief Interrupt port cause register 2 (GPIO_INTR_CAUSE2) */ typedef struct stc_GPIO_INTR_CAUSE2_field { uint32 u32PORT_INT:32; } stc_GPIO_INTR_CAUSE2_field_t; typedef union un_GPIO_INTR_CAUSE2 { uint32 u32Register; stc_GPIO_INTR_CAUSE2_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_INTR_CAUSE2_t; /** * \brief Interrupt port cause register 3 (GPIO_INTR_CAUSE3) */ typedef struct stc_GPIO_INTR_CAUSE3_field { uint32 u32PORT_INT:32; } stc_GPIO_INTR_CAUSE3_field_t; typedef union un_GPIO_INTR_CAUSE3 { uint32 u32Register; stc_GPIO_INTR_CAUSE3_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_INTR_CAUSE3_t; /** * \brief Extern power supply detection register (GPIO_VDD_ACTIVE) */ typedef struct stc_GPIO_VDD_ACTIVE_field { uint32 u16VDDIO_ACTIVE:16; uint32 :14; uint32 u1VDDA_ACTIVE:1; uint32 u1VDDD_ACTIVE:1; } stc_GPIO_VDD_ACTIVE_field_t; typedef union un_GPIO_VDD_ACTIVE { uint32 u32Register; stc_GPIO_VDD_ACTIVE_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_VDD_ACTIVE_t; /** * \brief Supply detection interrupt register (GPIO_VDD_INTR) */ typedef struct stc_GPIO_VDD_INTR_field { uint32 u16VDDIO_ACTIVE:16; uint32 :14; uint32 u1VDDA_ACTIVE:1; uint32 u1VDDD_ACTIVE:1; } stc_GPIO_VDD_INTR_field_t; typedef union un_GPIO_VDD_INTR { uint32 u32Register; stc_GPIO_VDD_INTR_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_VDD_INTR_t; /** * \brief Supply detection interrupt mask register (GPIO_VDD_INTR_MASK) */ typedef struct stc_GPIO_VDD_INTR_MASK_field { uint32 u16VDDIO_ACTIVE:16; uint32 :14; uint32 u1VDDA_ACTIVE:1; uint32 u1VDDD_ACTIVE:1; } stc_GPIO_VDD_INTR_MASK_field_t; typedef union un_GPIO_VDD_INTR_MASK { uint32 u32Register; stc_GPIO_VDD_INTR_MASK_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_VDD_INTR_MASK_t; /** * \brief Supply detection interrupt masked register (GPIO_VDD_INTR_MASKED) */ typedef struct stc_GPIO_VDD_INTR_MASKED_field { uint32 u16VDDIO_ACTIVE:16; uint32 :14; uint32 u1VDDA_ACTIVE:1; uint32 u1VDDD_ACTIVE:1; } stc_GPIO_VDD_INTR_MASKED_field_t; typedef union un_GPIO_VDD_INTR_MASKED { uint32 u32Register; stc_GPIO_VDD_INTR_MASKED_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_VDD_INTR_MASKED_t; /** * \brief Supply detection interrupt set register (GPIO_VDD_INTR_SET) */ typedef struct stc_GPIO_VDD_INTR_SET_field { uint32 u16VDDIO_ACTIVE:16; uint32 :14; uint32 u1VDDA_ACTIVE:1; uint32 u1VDDD_ACTIVE:1; } stc_GPIO_VDD_INTR_SET_field_t; typedef union un_GPIO_VDD_INTR_SET { uint32 u32Register; stc_GPIO_VDD_INTR_SET_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_GPIO_VDD_INTR_SET_t; /** * \brief GPIO port registers (GPIO_PRT) */ typedef struct stc_GPIO_PRT { un_GPIO_PRT_OUT_t unOUT; /*!< 0x00000000 Port output data register */ un_GPIO_PRT_OUT_CLR_t unOUT_CLR; /*!< 0x00000004 Port output data clear register */ un_GPIO_PRT_OUT_SET_t unOUT_SET; /*!< 0x00000008 Port output data set register */ un_GPIO_PRT_OUT_INV_t unOUT_INV; /*!< 0x0000000C Port output data invert register */ un_GPIO_PRT_IN_t unIN; /*!< 0x00000010 Port input state register */ un_GPIO_PRT_INTR_t unINTR; /*!< 0x00000014 Port interrupt status register */ un_GPIO_PRT_INTR_MASK_t unINTR_MASK; /*!< 0x00000018 Port interrupt mask register */ un_GPIO_PRT_INTR_MASKED_t unINTR_MASKED; /*!< 0x0000001C Port interrupt masked status register */ un_GPIO_PRT_INTR_SET_t unINTR_SET; /*!< 0x00000020 Port interrupt set register */ uint32 au32Reserved[7]; un_GPIO_PRT_INTR_CFG_t unINTR_CFG; /*!< 0x00000040 Port interrupt configuration register */ un_GPIO_PRT_CFG_t unCFG; /*!< 0x00000044 Port configuration register */ un_GPIO_PRT_CFG_IN_t unCFG_IN; /*!< 0x00000048 Port input buffer configuration register */ un_GPIO_PRT_CFG_OUT_t unCFG_OUT; /*!< 0x0000004C Port output buffer configuration register */ un_GPIO_PRT_CFG_SIO_t unCFG_SIO; /*!< 0x00000050 Port SIO configuration register */ uint32 u32Reserved1; un_GPIO_PRT_CFG_IN_GPIO5V_t unCFG_IN_GPIO5V; /*!< 0x00000058 Port GPIO5V input buffer configuration register */ uint32 au32Reserved2[9]; } stc_GPIO_PRT_t; /*!< Size = 128 (0x80) */ /** * \brief GPIO port control/configuration (GPIO) */ typedef struct stc_GPIO { stc_GPIO_PRT_t PRT[128]; /*!< 0x00000000 GPIO port registers */ un_GPIO_INTR_CAUSE0_t unINTR_CAUSE0; /*!< 0x00004000 Interrupt port cause register 0 */ un_GPIO_INTR_CAUSE1_t unINTR_CAUSE1; /*!< 0x00004004 Interrupt port cause register 1 */ un_GPIO_INTR_CAUSE2_t unINTR_CAUSE2; /*!< 0x00004008 Interrupt port cause register 2 */ un_GPIO_INTR_CAUSE3_t unINTR_CAUSE3; /*!< 0x0000400C Interrupt port cause register 3 */ un_GPIO_VDD_ACTIVE_t unVDD_ACTIVE; /*!< 0x00004010 Extern power supply detection register */ un_GPIO_VDD_INTR_t unVDD_INTR; /*!< 0x00004014 Supply detection interrupt register */ un_GPIO_VDD_INTR_MASK_t unVDD_INTR_MASK; /*!< 0x00004018 Supply detection interrupt mask register */ un_GPIO_VDD_INTR_MASKED_t unVDD_INTR_MASKED; /*!< 0x0000401C Supply detection interrupt masked register */ un_GPIO_VDD_INTR_SET_t unVDD_INTR_SET; /*!< 0x00004020 Supply detection interrupt set register */ } stc_GPIO_t; /*!< Size = 16420 (0x4024) */ #define GPIO_BASE 0x40310000UL #define GPIO ((volatile stc_GPIO_t* /*const*/) GPIO_BASE) /* 0x40310000 */ #define GPIO_PRT0 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[0]) /* 0x40310000 */ #define GPIO_PRT1 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[1]) /* 0x40310080 */ #define GPIO_PRT2 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[2]) /* 0x40310100 */ #define GPIO_PRT3 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[3]) /* 0x40310180 */ #define GPIO_PRT4 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[4]) /* 0x40310200 */ #define GPIO_PRT5 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[5]) /* 0x40310280 */ #define GPIO_PRT6 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[6]) /* 0x40310300 */ #define GPIO_PRT7 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[7]) /* 0x40310380 */ #define GPIO_PRT8 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[8]) /* 0x40310400 */ #define GPIO_PRT9 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[9]) /* 0x40310480 */ #define GPIO_PRT10 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[10]) /* 0x40310500 */ #define GPIO_PRT11 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[11]) /* 0x40310580 */ #define GPIO_PRT12 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[12]) /* 0x40310600 */ #define GPIO_PRT13 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[13]) /* 0x40310680 */ #define GPIO_PRT14 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[14]) /* 0x40310700 */ #define GPIO_PRT15 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[15]) /* 0x40310780 */ #define GPIO_PRT16 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[16]) /* 0x40310800 */ #define GPIO_PRT17 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[17]) /* 0x40310880 */ #define GPIO_PRT18 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[18]) /* 0x40310900 */ #define GPIO_PRT19 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[19]) /* 0x40310980 */ #define GPIO_PRT20 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[20]) /* 0x40310A00 */ #define GPIO_PRT21 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[21]) /* 0x40310A80 */ #define GPIO_PRT22 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[22]) /* 0x40310B00 */ #define GPIO_PRT23 ((volatile stc_GPIO_PRT_t* /*const*/) &GPIO->PRT[23]) /* 0x40310B80 */ /******************************************************************************* * HSIOM *******************************************************************************/ #define HSIOM_PRT_SECTION_SIZE 0x00000010UL #define HSIOM_SECTION_SIZE 0x00004000UL /** * \brief Port selection 0 (HSIOM_PRT_PORT_SEL0) */ typedef struct stc_HSIOM_PRT_PORT_SEL0_field { uint32 u5IO0_SEL:5; uint32 :3; uint32 u5IO1_SEL:5; uint32 :3; uint32 u5IO2_SEL:5; uint32 :3; uint32 u5IO3_SEL:5; uint32 :3; } stc_HSIOM_PRT_PORT_SEL0_field_t; typedef union un_HSIOM_PRT_PORT_SEL0 { uint32 u32Register; stc_HSIOM_PRT_PORT_SEL0_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_HSIOM_PRT_PORT_SEL0_t; /** * \brief Port selection 1 (HSIOM_PRT_PORT_SEL1) */ typedef struct stc_HSIOM_PRT_PORT_SEL1_field { uint32 u5IO4_SEL:5; uint32 :3; uint32 u5IO5_SEL:5; uint32 :3; uint32 u5IO6_SEL:5; uint32 :3; uint32 u5IO7_SEL:5; uint32 :3; } stc_HSIOM_PRT_PORT_SEL1_field_t; typedef union un_HSIOM_PRT_PORT_SEL1 { uint32 u32Register; stc_HSIOM_PRT_PORT_SEL1_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_HSIOM_PRT_PORT_SEL1_t; /** * \brief AMUX splitter cell control (HSIOM_AMUX_SPLIT_CTL) */ typedef struct stc_HSIOM_AMUX_SPLIT_CTL_field { uint32 u1SWITCH_AA_SL:1; uint32 u1SWITCH_AA_SR:1; uint32 u1SWITCH_AA_S0:1; uint32 :1; uint32 u1SWITCH_BB_SL:1; uint32 u1SWITCH_BB_SR:1; uint32 u1SWITCH_BB_S0:1; uint32 :25; } stc_HSIOM_AMUX_SPLIT_CTL_field_t; typedef union un_HSIOM_AMUX_SPLIT_CTL { uint32 u32Register; stc_HSIOM_AMUX_SPLIT_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_HSIOM_AMUX_SPLIT_CTL_t; /** * \brief Power/Ground Monitor cell control 0 (HSIOM_MONITOR_CTL_0) */ typedef struct stc_HSIOM_MONITOR_CTL_0_field { uint32 u32MONITOR_EN:32; } stc_HSIOM_MONITOR_CTL_0_field_t; typedef union un_HSIOM_MONITOR_CTL_0 { uint32 u32Register; stc_HSIOM_MONITOR_CTL_0_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_HSIOM_MONITOR_CTL_0_t; /** * \brief Power/Ground Monitor cell control 1 (HSIOM_MONITOR_CTL_1) */ typedef struct stc_HSIOM_MONITOR_CTL_1_field { uint32 u32MONITOR_EN:32; } stc_HSIOM_MONITOR_CTL_1_field_t; typedef union un_HSIOM_MONITOR_CTL_1 { uint32 u32Register; stc_HSIOM_MONITOR_CTL_1_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_HSIOM_MONITOR_CTL_1_t; /** * \brief Power/Ground Monitor cell control 2 (HSIOM_MONITOR_CTL_2) */ typedef struct stc_HSIOM_MONITOR_CTL_2_field { uint32 u32MONITOR_EN:32; } stc_HSIOM_MONITOR_CTL_2_field_t; typedef union un_HSIOM_MONITOR_CTL_2 { uint32 u32Register; stc_HSIOM_MONITOR_CTL_2_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_HSIOM_MONITOR_CTL_2_t; /** * \brief Power/Ground Monitor cell control 3 (HSIOM_MONITOR_CTL_3) */ typedef struct stc_HSIOM_MONITOR_CTL_3_field { uint32 u32MONITOR_EN:32; } stc_HSIOM_MONITOR_CTL_3_field_t; typedef union un_HSIOM_MONITOR_CTL_3 { uint32 u32Register; stc_HSIOM_MONITOR_CTL_3_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_HSIOM_MONITOR_CTL_3_t; /** * \brief Alternate JTAG IF selection register (HSIOM_ALT_JTAG_EN) */ typedef struct stc_HSIOM_ALT_JTAG_EN_field { uint32 :31; uint32 u1ENABLE:1; } stc_HSIOM_ALT_JTAG_EN_field_t; typedef union un_HSIOM_ALT_JTAG_EN { uint32 u32Register; stc_HSIOM_ALT_JTAG_EN_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_HSIOM_ALT_JTAG_EN_t; /** * \brief HSIOM port registers (HSIOM_PRT) */ typedef struct stc_HSIOM_PRT { un_HSIOM_PRT_PORT_SEL0_t unPORT_SEL0; /*!< 0x00000000 Port selection 0 */ un_HSIOM_PRT_PORT_SEL1_t unPORT_SEL1; /*!< 0x00000004 Port selection 1 */ uint32 au32Reserved[2]; } stc_HSIOM_PRT_t; /*!< Size = 16 (0x10) */ /** * \brief High Speed IO Matrix (HSIOM) (HSIOM) */ typedef struct stc_HSIOM { stc_HSIOM_PRT_t PRT[128]; /*!< 0x00000000 HSIOM port registers */ uint32 au32Reserved[1536]; un_HSIOM_AMUX_SPLIT_CTL_t unAMUX_SPLIT_CTL[64]; /*!< 0x00002000 AMUX splitter cell control */ uint32 au32Reserved1[64]; un_HSIOM_MONITOR_CTL_0_t unMONITOR_CTL_0; /*!< 0x00002200 Power/Ground Monitor cell control 0 */ un_HSIOM_MONITOR_CTL_1_t unMONITOR_CTL_1; /*!< 0x00002204 Power/Ground Monitor cell control 1 */ un_HSIOM_MONITOR_CTL_2_t unMONITOR_CTL_2; /*!< 0x00002208 Power/Ground Monitor cell control 2 */ un_HSIOM_MONITOR_CTL_3_t unMONITOR_CTL_3; /*!< 0x0000220C Power/Ground Monitor cell control 3 */ uint32 au32Reserved2[12]; un_HSIOM_ALT_JTAG_EN_t unALT_JTAG_EN; /*!< 0x00002240 Alternate JTAG IF selection register */ } stc_HSIOM_t; /*!< Size = 8772 (0x2244) */ #define HSIOM_BASE 0x40300000UL #define HSIOM ((volatile stc_HSIOM_t* /*const*/) HSIOM_BASE) /* 0x40300000 */ #define HSIOM_PRT0 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[0]) /* 0x40300000 */ #define HSIOM_PRT1 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[1]) /* 0x40300010 */ #define HSIOM_PRT2 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[2]) /* 0x40300020 */ #define HSIOM_PRT3 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[3]) /* 0x40300030 */ #define HSIOM_PRT4 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[4]) /* 0x40300040 */ #define HSIOM_PRT5 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[5]) /* 0x40300050 */ #define HSIOM_PRT6 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[6]) /* 0x40300060 */ #define HSIOM_PRT7 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[7]) /* 0x40300070 */ #define HSIOM_PRT8 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[8]) /* 0x40300080 */ #define HSIOM_PRT9 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[9]) /* 0x40300090 */ #define HSIOM_PRT10 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[10]) /* 0x403000A0 */ #define HSIOM_PRT11 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[11]) /* 0x403000B0 */ #define HSIOM_PRT12 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[12]) /* 0x403000C0 */ #define HSIOM_PRT13 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[13]) /* 0x403000D0 */ #define HSIOM_PRT14 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[14]) /* 0x403000E0 */ #define HSIOM_PRT15 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[15]) /* 0x403000F0 */ #define HSIOM_PRT16 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[16]) /* 0x40300100 */ #define HSIOM_PRT17 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[17]) /* 0x40300110 */ #define HSIOM_PRT18 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[18]) /* 0x40300120 */ #define HSIOM_PRT19 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[19]) /* 0x40300130 */ #define HSIOM_PRT20 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[20]) /* 0x40300140 */ #define HSIOM_PRT21 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[21]) /* 0x40300150 */ #define HSIOM_PRT22 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[22]) /* 0x40300160 */ #define HSIOM_PRT23 ((volatile stc_HSIOM_PRT_t* /*const*/) &HSIOM->PRT[23]) /* 0x40300170 */ /******************************************************************************* * DMAC *******************************************************************************/ /** * \brief Channel control (DMAC_CH_CTL) */ typedef struct stc_DMAC_CH_CTL_field { uint32 u1P:1; uint32 u1NS:1; uint32 u1B:1; uint32 :1; uint32 u4PC:4; uint32 u2PRIO:2; uint32 :21; uint32 u1ENABLED:1; } stc_DMAC_CH_CTL_field_t; typedef union un_DMAC_CH_CTL { uint32 u32Register; stc_DMAC_CH_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_CTL_t; /** * \brief Channel current indices (DMAC_CH_IDX) */ typedef struct stc_DMAC_CH_IDX_field { uint32 u16X:16; uint32 u16Y:16; } stc_DMAC_CH_IDX_field_t; typedef union un_DMAC_CH_IDX { uint32 u32Register; stc_DMAC_CH_IDX_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_IDX_t; /** * \brief Channel current source address (DMAC_CH_SRC) */ typedef struct stc_DMAC_CH_SRC_field { uint32 u32ADDR:32; } stc_DMAC_CH_SRC_field_t; typedef union un_DMAC_CH_SRC { uint32 u32Register; stc_DMAC_CH_SRC_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_SRC_t; /** * \brief Channel current destination address (DMAC_CH_DST) */ typedef struct stc_DMAC_CH_DST_field { uint32 u32ADDR:32; } stc_DMAC_CH_DST_field_t; typedef union un_DMAC_CH_DST { uint32 u32Register; stc_DMAC_CH_DST_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_DST_t; /** * \brief Channel current descriptor pointer (DMAC_CH_CURR) */ typedef struct stc_DMAC_CH_CURR_field { uint32 :2; uint32 u30PTR:30; } stc_DMAC_CH_CURR_field_t; typedef union un_DMAC_CH_CURR { uint32 u32Register; stc_DMAC_CH_CURR_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_CURR_t; /** * \brief Channle software trigger (DMAC_CH_TR_CMD) */ typedef struct stc_DMAC_CH_TR_CMD_field { uint32 u1ACTIVATE:1; uint32 :31; } stc_DMAC_CH_TR_CMD_field_t; typedef union un_DMAC_CH_TR_CMD { uint32 u32Register; stc_DMAC_CH_TR_CMD_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_TR_CMD_t; /** * \brief Channel descriptor status (DMAC_CH_DESCR_STATUS) */ typedef struct stc_DMAC_CH_DESCR_STATUS_field { uint32 :31; uint32 u1VALID:1; } stc_DMAC_CH_DESCR_STATUS_field_t; typedef union un_DMAC_CH_DESCR_STATUS { uint32 u32Register; stc_DMAC_CH_DESCR_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_DESCR_STATUS_t; /** * \brief Channel descriptor control (DMAC_CH_DESCR_CTL) */ typedef struct stc_DMAC_CH_DESCR_CTL_field { uint32 u2WAIT_FOR_DEACT:2; uint32 u2INTR_TYPE:2; uint32 u2TR_OUT_TYPE:2; uint32 u2TR_IN_TYPE:2; uint32 u1DATA_PREFETCH:1; uint32 :7; uint32 u2DATA_SIZE:2; uint32 :6; uint32 u1CH_DISABLE:1; uint32 :1; uint32 u1SRC_TRANSFER_SIZE:1; uint32 u1DST_TRANSFER_SIZE:1; uint32 u3DESCR_TYPE:3; } stc_DMAC_CH_DESCR_CTL_field_t; typedef union un_DMAC_CH_DESCR_CTL { uint32 u32Register; stc_DMAC_CH_DESCR_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_DESCR_CTL_t; /** * \brief Channel descriptor source (DMAC_CH_DESCR_SRC) */ typedef struct stc_DMAC_CH_DESCR_SRC_field { uint32 u32ADDR:32; } stc_DMAC_CH_DESCR_SRC_field_t; typedef union un_DMAC_CH_DESCR_SRC { uint32 u32Register; stc_DMAC_CH_DESCR_SRC_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_DESCR_SRC_t; /** * \brief Channel descriptor destination (DMAC_CH_DESCR_DST) */ typedef struct stc_DMAC_CH_DESCR_DST_field { uint32 u32ADDR:32; } stc_DMAC_CH_DESCR_DST_field_t; typedef union un_DMAC_CH_DESCR_DST { uint32 u32Register; stc_DMAC_CH_DESCR_DST_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_DESCR_DST_t; /** * \brief Channel descriptor X size (DMAC_CH_DESCR_X_SIZE) */ typedef struct stc_DMAC_CH_DESCR_X_SIZE_field { uint32 u16X_COUNT:16; uint32 :16; } stc_DMAC_CH_DESCR_X_SIZE_field_t; typedef union un_DMAC_CH_DESCR_X_SIZE { uint32 u32Register; stc_DMAC_CH_DESCR_X_SIZE_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_DESCR_X_SIZE_t; /** * \brief Channel descriptor X increment (DMAC_CH_DESCR_X_INCR) */ typedef struct stc_DMAC_CH_DESCR_X_INCR_field { uint32 u16SRC_X:16; uint32 u16DST_X:16; } stc_DMAC_CH_DESCR_X_INCR_field_t; typedef union un_DMAC_CH_DESCR_X_INCR { uint32 u32Register; stc_DMAC_CH_DESCR_X_INCR_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_DESCR_X_INCR_t; /** * \brief Channel descriptor Y size (DMAC_CH_DESCR_Y_SIZE) */ typedef struct stc_DMAC_CH_DESCR_Y_SIZE_field { uint32 u16Y_COUNT:16; uint32 :16; } stc_DMAC_CH_DESCR_Y_SIZE_field_t; typedef union un_DMAC_CH_DESCR_Y_SIZE { uint32 u32Register; stc_DMAC_CH_DESCR_Y_SIZE_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_DESCR_Y_SIZE_t; /** * \brief Channel descriptor Y increment (DMAC_CH_DESCR_Y_INCR) */ typedef struct stc_DMAC_CH_DESCR_Y_INCR_field { uint32 u16SRC_Y:16; uint32 u16DST_Y:16; } stc_DMAC_CH_DESCR_Y_INCR_field_t; typedef union un_DMAC_CH_DESCR_Y_INCR { uint32 u32Register; stc_DMAC_CH_DESCR_Y_INCR_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_DESCR_Y_INCR_t; /** * \brief Channel descriptor next pointer (DMAC_CH_DESCR_NEXT) */ typedef struct stc_DMAC_CH_DESCR_NEXT_field { uint32 :2; uint32 u30PTR:30; } stc_DMAC_CH_DESCR_NEXT_field_t; typedef union un_DMAC_CH_DESCR_NEXT { uint32 u32Register; stc_DMAC_CH_DESCR_NEXT_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_DESCR_NEXT_t; /** * \brief Interrupt (DMAC_CH_INTR) */ typedef struct stc_DMAC_CH_INTR_field { uint32 u1COMPLETION:1; uint32 u1SRC_BUS_ERROR:1; uint32 u1DST_BUS_ERROR:1; uint32 u1SRC_MISAL:1; uint32 u1DST_MISAL:1; uint32 u1CURR_PTR_NULL:1; uint32 u1ACTIVE_CH_DISABLED:1; uint32 u1DESCR_BUS_ERROR:1; uint32 :24; } stc_DMAC_CH_INTR_field_t; typedef union un_DMAC_CH_INTR { uint32 u32Register; stc_DMAC_CH_INTR_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_INTR_t; /** * \brief Interrupt set (DMAC_CH_INTR_SET) */ typedef struct stc_DMAC_CH_INTR_SET_field { uint32 u1COMPLETION:1; uint32 u1SRC_BUS_ERROR:1; uint32 u1DST_BUS_ERROR:1; uint32 u1SRC_MISAL:1; uint32 u1DST_MISAL:1; uint32 u1CURR_PTR_NULL:1; uint32 u1ACTIVE_CH_DISABLED:1; uint32 u1DESCR_BUS_ERROR:1; uint32 :24; } stc_DMAC_CH_INTR_SET_field_t; typedef union un_DMAC_CH_INTR_SET { uint32 u32Register; stc_DMAC_CH_INTR_SET_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_INTR_SET_t; /** * \brief Interrupt mask (DMAC_CH_INTR_MASK) */ typedef struct stc_DMAC_CH_INTR_MASK_field { uint32 u1COMPLETION:1; uint32 u1SRC_BUS_ERROR:1; uint32 u1DST_BUS_ERROR:1; uint32 u1SRC_MISAL:1; uint32 u1DST_MISAL:1; uint32 u1CURR_PTR_NULL:1; uint32 u1ACTIVE_CH_DISABLED:1; uint32 u1DESCR_BUS_ERROR:1; uint32 :24; } stc_DMAC_CH_INTR_MASK_field_t; typedef union un_DMAC_CH_INTR_MASK { uint32 u32Register; stc_DMAC_CH_INTR_MASK_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_INTR_MASK_t; /** * \brief Interrupt masked (DMAC_CH_INTR_MASKED) */ typedef struct stc_DMAC_CH_INTR_MASKED_field { uint32 u1COMPLETION:1; uint32 u1SRC_BUS_ERROR:1; uint32 u1DST_BUS_ERROR:1; uint32 u1SRC_MISAL:1; uint32 u1DST_MISAL:1; uint32 u1CURR_PTR_NULL:1; uint32 u1ACTIVE_CH_DISABLED:1; uint32 u1DESCR_BUS_ERROR:1; uint32 :24; } stc_DMAC_CH_INTR_MASKED_field_t; typedef union un_DMAC_CH_INTR_MASKED { uint32 u32Register; stc_DMAC_CH_INTR_MASKED_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CH_INTR_MASKED_t; /** * \brief Control (DMAC_CTL) */ typedef struct stc_DMAC_CTL_field { uint32 :31; uint32 u1ENABLED:1; } stc_DMAC_CTL_field_t; typedef union un_DMAC_CTL { uint32 u32Register; stc_DMAC_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_CTL_t; /** * \brief Active channels (DMAC_ACTIVE) */ typedef struct stc_DMAC_ACTIVE_field { uint32 u8ACTIVE:8; uint32 :24; } stc_DMAC_ACTIVE_field_t; typedef union un_DMAC_ACTIVE { uint32 u32Register; stc_DMAC_ACTIVE_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_DMAC_ACTIVE_t; /** * \brief DMA controller channel (DMAC_CH) */ typedef struct stc_DMAC_CH { un_DMAC_CH_CTL_t unCTL; /*!< 0x00000000 Channel control */ uint32 au32Reserved[3]; un_DMAC_CH_IDX_t unIDX; /*!< 0x00000010 Channel current indices */ un_DMAC_CH_SRC_t unSRC; /*!< 0x00000014 Channel current source address */ un_DMAC_CH_DST_t unDST; /*!< 0x00000018 Channel current destination address */ uint32 u32Reserved1; un_DMAC_CH_CURR_t unCURR; /*!< 0x00000020 Channel current descriptor pointer */ uint32 u32Reserved2; un_DMAC_CH_TR_CMD_t unTR_CMD; /*!< 0x00000028 Channle software trigger */ uint32 au32Reserved3[5]; un_DMAC_CH_DESCR_STATUS_t unDESCR_STATUS; /*!< 0x00000040 Channel descriptor status */ uint32 au32Reserved4[7]; un_DMAC_CH_DESCR_CTL_t unDESCR_CTL; /*!< 0x00000060 Channel descriptor control */ un_DMAC_CH_DESCR_SRC_t unDESCR_SRC; /*!< 0x00000064 Channel descriptor source */ un_DMAC_CH_DESCR_DST_t unDESCR_DST; /*!< 0x00000068 Channel descriptor destination */ un_DMAC_CH_DESCR_X_SIZE_t unDESCR_X_SIZE; /*!< 0x0000006C Channel descriptor X size */ un_DMAC_CH_DESCR_X_INCR_t unDESCR_X_INCR; /*!< 0x00000070 Channel descriptor X increment */ un_DMAC_CH_DESCR_Y_SIZE_t unDESCR_Y_SIZE; /*!< 0x00000074 Channel descriptor Y size */ un_DMAC_CH_DESCR_Y_INCR_t unDESCR_Y_INCR; /*!< 0x00000078 Channel descriptor Y increment */ un_DMAC_CH_DESCR_NEXT_t unDESCR_NEXT; /*!< 0x0000007C Channel descriptor next pointer */ un_DMAC_CH_INTR_t unINTR; /*!< 0x00000080 Interrupt */ un_DMAC_CH_INTR_SET_t unINTR_SET; /*!< 0x00000084 Interrupt set */ un_DMAC_CH_INTR_MASK_t unINTR_MASK; /*!< 0x00000088 Interrupt mask */ un_DMAC_CH_INTR_MASKED_t unINTR_MASKED; /*!< 0x0000008C Interrupt masked */ uint32 au32Reserved5[28]; } stc_DMAC_CH_t; /*!< Size = 256 (0x100) */ /** * \brief DMAC (DMAC) */ typedef struct stc_DMAC { un_DMAC_CTL_t unCTL; /*!< 0x00000000 Control */ uint32 u32Reserved; un_DMAC_ACTIVE_t unACTIVE; /*!< 0x00000008 Active channels */ uint32 au32Reserved1[1021]; stc_DMAC_CH_t CH[8]; /*!< 0x00001000 DMA controller channel */ } stc_DMAC_t; /*!< Size = 6144 (0x1800) */ #define DMAC_BASE 0x402A0000UL #define DMAC ((volatile stc_DMAC_t* const) DMAC_BASE) /* 0x402A0000 */ #define DMAC_CH0 ((volatile stc_DMAC_CH_t* const) &DMAC->CH[0]) /* 0x402A1000 */ #define DMAC_CH1 ((volatile stc_DMAC_CH_t* const) &DMAC->CH[1]) /* 0x402A1100 */ #define DMAC_CH2 ((volatile stc_DMAC_CH_t* const) &DMAC->CH[2]) /* 0x402A1200 */ #define DMAC_CH3 ((volatile stc_DMAC_CH_t* const) &DMAC->CH[3]) /* 0x402A1300 */ /******************************************************************************* * PERI *******************************************************************************/ /** * \brief Clock control (PERI_GR_CLOCK_CTL) */ typedef struct stc_PERI_GR_CLOCK_CTL_field { uint32 :8; uint32 u8INT8_DIV:8; uint32 :16; } stc_PERI_GR_CLOCK_CTL_field_t; typedef union un_PERI_GR_CLOCK_CTL { uint32 u32Register; stc_PERI_GR_CLOCK_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_PERI_GR_CLOCK_CTL_t; /** * \brief Slave control (PERI_GR_SL_CTL) */ typedef struct stc_PERI_GR_SL_CTL_field { uint32 u1ENABLED_0:1; uint32 u1ENABLED_1:1; uint32 u1ENABLED_2:1; uint32 u1ENABLED_3:1; uint32 u1ENABLED_4:1; uint32 u1ENABLED_5:1; uint32 u1ENABLED_6:1; uint32 u1ENABLED_7:1; uint32 u1ENABLED_8:1; uint32 u1ENABLED_9:1; uint32 u1ENABLED_10:1; uint32 u1ENABLED_11:1; uint32 u1ENABLED_12:1; uint32 u1ENABLED_13:1; uint32 u1ENABLED_14:1; uint32 u1ENABLED_15:1; uint32 u1DISABLED_0:1; uint32 u1DISABLED_1:1; uint32 u1DISABLED_2:1; uint32 u1DISABLED_3:1; uint32 u1DISABLED_4:1; uint32 u1DISABLED_5:1; uint32 u1DISABLED_6:1; uint32 u1DISABLED_7:1; uint32 u1DISABLED_8:1; uint32 u1DISABLED_9:1; uint32 u1DISABLED_10:1; uint32 u1DISABLED_11:1; uint32 u1DISABLED_12:1; uint32 u1DISABLED_13:1; uint32 u1DISABLED_14:1; uint32 u1DISABLED_15:1; } stc_PERI_GR_SL_CTL_field_t; typedef union un_PERI_GR_SL_CTL { uint32 u32Register; stc_PERI_GR_SL_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_PERI_GR_SL_CTL_t; /** * \brief Trigger control register (PERI_TR_GR_TR_CTL) */ typedef struct stc_PERI_TR_GR_TR_CTL_field { uint32 u8TR_SEL:8; uint32 u1TR_INV:1; uint32 u1TR_EDGE:1; uint32 :2; uint32 u1DBG_FREEZE_EN:1; uint32 :19; } stc_PERI_TR_GR_TR_CTL_field_t; typedef union un_PERI_TR_GR_TR_CTL { uint32 u32Register; stc_PERI_TR_GR_TR_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_PERI_TR_GR_TR_CTL_t; /** * \brief Trigger control register (PERI_TR_1TO1_GR_TR_CTL) */ typedef struct stc_PERI_TR_1TO1_GR_TR_CTL_field { uint32 u1TR_SEL:1; uint32 :7; uint32 u1TR_INV:1; uint32 u1TR_EDGE:1; uint32 :2; uint32 u1DBG_FREEZE_EN:1; uint32 :19; } stc_PERI_TR_1TO1_GR_TR_CTL_field_t; typedef union un_PERI_TR_1TO1_GR_TR_CTL { uint32 u32Register; stc_PERI_TR_1TO1_GR_TR_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_PERI_TR_1TO1_GR_TR_CTL_t; /** * \brief Timeout control (PERI_TIMEOUT_CTL) */ typedef struct stc_PERI_TIMEOUT_CTL_field { uint32 u16TIMEOUT:16; uint32 :16; } stc_PERI_TIMEOUT_CTL_field_t; typedef union un_PERI_TIMEOUT_CTL { uint32 u32Register; stc_PERI_TIMEOUT_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_PERI_TIMEOUT_CTL_t; /** * \brief Trigger command (PERI_TR_CMD) */ typedef struct stc_PERI_TR_CMD_field { uint32 u8TR_SEL:8; uint32 u5GROUP_SEL:5; uint32 :16; uint32 u1TR_EDGE:1; uint32 u1OUT_SEL:1; uint32 u1ACTIVATE:1; } stc_PERI_TR_CMD_field_t; typedef union un_PERI_TR_CMD { uint32 u32Register; stc_PERI_TR_CMD_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_PERI_TR_CMD_t; /** * \brief Divider command (PERI_DIV_CMD) */ typedef struct stc_PERI_DIV_CMD_field { uint32 u8DIV_SEL:8; uint32 u2TYPE_SEL:2; uint32 :6; uint32 u8PA_DIV_SEL:8; uint32 u2PA_TYPE_SEL:2; uint32 :4; uint32 u1DISABLE:1; uint32 u1ENABLE:1; } stc_PERI_DIV_CMD_field_t; typedef union un_PERI_DIV_CMD { uint32 u32Register; stc_PERI_DIV_CMD_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_PERI_DIV_CMD_t; /** * \brief Clock control (PERI_CLOCK_CTL) */ typedef struct stc_PERI_CLOCK_CTL_field { uint32 u8DIV_SEL:8; uint32 u2TYPE_SEL:2; uint32 :22; } stc_PERI_CLOCK_CTL_field_t; typedef union un_PERI_CLOCK_CTL { uint32 u32Register; stc_PERI_CLOCK_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_PERI_CLOCK_CTL_t; /** * \brief Divider control (for 8.0 divider) (PERI_DIV_8_CTL) */ typedef struct stc_PERI_DIV_8_CTL_field { uint32 u1EN:1; uint32 :7; uint32 u8INT8_DIV:8; uint32 :16; } stc_PERI_DIV_8_CTL_field_t; typedef union un_PERI_DIV_8_CTL { uint32 u32Register; stc_PERI_DIV_8_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_PERI_DIV_8_CTL_t; /** * \brief Divider control (for 16.0 divider) (PERI_DIV_16_CTL) */ typedef struct stc_PERI_DIV_16_CTL_field { uint32 u1EN:1; uint32 :7; uint32 u16INT16_DIV:16; uint32 :8; } stc_PERI_DIV_16_CTL_field_t; typedef union un_PERI_DIV_16_CTL { uint32 u32Register; stc_PERI_DIV_16_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_PERI_DIV_16_CTL_t; /** * \brief Divider control (for 16.5 divider) (PERI_DIV_16_5_CTL) */ typedef struct stc_PERI_DIV_16_5_CTL_field { uint32 u1EN:1; uint32 :2; uint32 u5FRAC5_DIV:5; uint32 u16INT16_DIV:16; uint32 :8; } stc_PERI_DIV_16_5_CTL_field_t; typedef union un_PERI_DIV_16_5_CTL { uint32 u32Register; stc_PERI_DIV_16_5_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_PERI_DIV_16_5_CTL_t; /** * \brief Divider control (for 24.5 divider) (PERI_DIV_24_5_CTL) */ typedef struct stc_PERI_DIV_24_5_CTL_field { uint32 u1EN:1; uint32 :2; uint32 u5FRAC5_DIV:5; uint32 u24INT24_DIV:24; } stc_PERI_DIV_24_5_CTL_field_t; typedef union un_PERI_DIV_24_5_CTL { uint32 u32Register; stc_PERI_DIV_24_5_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_PERI_DIV_24_5_CTL_t; /** * \brief ECC control (PERI_ECC_CTL) */ typedef struct stc_PERI_ECC_CTL_field { uint32 u11WORD_ADDR:11; uint32 :5; uint32 u1ECC_EN:1; uint32 :1; uint32 u1ECC_INJ_EN:1; uint32 :5; uint32 u8PARITY:8; } stc_PERI_ECC_CTL_field_t; typedef union un_PERI_ECC_CTL { uint32 u32Register; stc_PERI_ECC_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_PERI_ECC_CTL_t; /** * \brief Peripheral group structure (PERI_GR) */ typedef struct stc_PERI_GR { un_PERI_GR_CLOCK_CTL_t unCLOCK_CTL; /*!< 0x00000000 Clock control */ uint32 au32Reserved[3]; un_PERI_GR_SL_CTL_t unSL_CTL; /*!< 0x00000010 Slave control */ uint32 au32Reserved1[3]; } stc_PERI_GR_t; /*!< Size = 32 (0x20) */ /** * \brief Trigger group (PERI_TR_GR) */ typedef struct stc_PERI_TR_GR { un_PERI_TR_GR_TR_CTL_t unTR_CTL[256]; /*!< 0x00000000 Trigger control register */ } stc_PERI_TR_GR_t; /*!< Size = 1024 (0x400) */ /** * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR) */ typedef struct stc_PERI_TR_1TO1_GR { un_PERI_TR_1TO1_GR_TR_CTL_t unTR_CTL[256]; /*!< 0x00000000 Trigger control register */ } stc_PERI_TR_1TO1_GR_t; /*!< Size = 1024 (0x400) */ /** * \brief Peripheral interconnect (PERI) */ typedef struct stc_PERI { uint32 au32Reserved[128]; un_PERI_TIMEOUT_CTL_t unTIMEOUT_CTL; /*!< 0x00000200 Timeout control */ uint32 au32Reserved1[7]; un_PERI_TR_CMD_t unTR_CMD; /*!< 0x00000220 Trigger command */ uint32 au32Reserved2[119]; un_PERI_DIV_CMD_t unDIV_CMD; /*!< 0x00000400 Divider command */ uint32 au32Reserved3[511]; un_PERI_CLOCK_CTL_t unCLOCK_CTL[256]; /*!< 0x00000C00 Clock control */ un_PERI_DIV_8_CTL_t unDIV_8_CTL[256]; /*!< 0x00001000 Divider control (for 8.0 divider) */ un_PERI_DIV_16_CTL_t unDIV_16_CTL[256]; /*!< 0x00001400 Divider control (for 16.0 divider) */ un_PERI_DIV_16_5_CTL_t unDIV_16_5_CTL[256]; /*!< 0x00001800 Divider control (for 16.5 divider) */ un_PERI_DIV_24_5_CTL_t unDIV_24_5_CTL[255]; /*!< 0x00001C00 Divider control (for 24.5 divider) */ uint32 u32Reserved4; un_PERI_ECC_CTL_t unECC_CTL; /*!< 0x00002000 ECC control */ uint32 au32Reserved5[2047]; stc_PERI_GR_t GR[16]; /*!< 0x00004000 Peripheral group structure */ uint32 au32Reserved6[3968]; stc_PERI_TR_GR_t TR_GR[16]; /*!< 0x00008000 Trigger group */ stc_PERI_TR_1TO1_GR_t TR_1TO1_GR[16]; /*!< 0x0000C000 Trigger 1-to-1 group */ } stc_PERI_t; /*!< Size = 65536 (0x10000) */ #define PERI_BASE 0x40000000UL #define PERI ((volatile stc_PERI_t* /*const*/) PERI_BASE) /* 0x40000000 */ #define PERI_GR0 ((volatile stc_PERI_GR_t* /*const*/) &PERI->GR[0]) /* 0x40004000 */ #define PERI_GR1 ((volatile stc_PERI_GR_t* const) &PERI->GR[1]) /* 0x40004020 */ #define PERI_GR2 ((volatile stc_PERI_GR_t* const) &PERI->GR[2]) /* 0x40004040 */ #define PERI_GR3 ((volatile stc_PERI_GR_t* const) &PERI->GR[3]) /* 0x40004060 */ #define PERI_GR5 ((volatile stc_PERI_GR_t* const) &PERI->GR[5]) /* 0x400040A0 */ #define PERI_GR6 ((volatile stc_PERI_GR_t* const) &PERI->GR[6]) /* 0x400040C0 */ #define PERI_GR9 ((volatile stc_PERI_GR_t* const) &PERI->GR[9]) /* 0x40004120 */ #define PERI_TR_GR0 ((volatile stc_PERI_TR_GR_t* const) &PERI->TR_GR[0]) /* 0x40008000 */ #define PERI_TR_GR1 ((volatile stc_PERI_TR_GR_t* const) &PERI->TR_GR[1]) /* 0x40008400 */ #define PERI_TR_GR2 ((volatile stc_PERI_TR_GR_t* const) &PERI->TR_GR[2]) /* 0x40008800 */ #define PERI_TR_GR3 ((volatile stc_PERI_TR_GR_t* const) &PERI->TR_GR[3]) /* 0x40008C00 */ #define PERI_TR_GR4 ((volatile stc_PERI_TR_GR_t* const) &PERI->TR_GR[4]) /* 0x40009000 */ #define PERI_TR_GR5 ((volatile stc_PERI_TR_GR_t* const) &PERI->TR_GR[5]) /* 0x40009400 */ #define PERI_TR_GR6 ((volatile stc_PERI_TR_GR_t* const) &PERI->TR_GR[6]) /* 0x40009800 */ #define PERI_TR_GR7 ((volatile stc_PERI_TR_GR_t* const) &PERI->TR_GR[7]) /* 0x40009C00 */ #define PERI_TR_GR8 ((volatile stc_PERI_TR_GR_t* const) &PERI->TR_GR[8]) /* 0x4000A000 */ #define PERI_TR_GR9 ((volatile stc_PERI_TR_GR_t* const) &PERI->TR_GR[9]) /* 0x4000A400 */ #define PERI_TR_GR10 ((volatile stc_PERI_TR_GR_t* const) &PERI->TR_GR[10]) /* 0x4000A800 */ #define PERI_TR_1TO1_GR0 ((volatile stc_PERI_TR_1TO1_GR_t* const) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ #define PERI_TR_1TO1_GR1 ((volatile stc_PERI_TR_1TO1_GR_t* const) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ #define PERI_TR_1TO1_GR2 ((volatile stc_PERI_TR_1TO1_GR_t* const) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ #define PERI_TR_1TO1_GR3 ((volatile stc_PERI_TR_1TO1_GR_t* const) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ #define PERI_TR_1TO1_GR4 ((volatile stc_PERI_TR_1TO1_GR_t* const) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ #define PERI_TR_1TO1_GR5 ((volatile stc_PERI_TR_1TO1_GR_t* const) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ #define PERI_TR_1TO1_GR6 ((volatile stc_PERI_TR_1TO1_GR_t* const) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ #define PERI_TR_1TO1_GR7 ((volatile stc_PERI_TR_1TO1_GR_t* const) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ #define PERI_TR_1TO1_GR8 ((volatile stc_PERI_TR_1TO1_GR_t* const) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ #define PERI_TR_1TO1_GR9 ((volatile stc_PERI_TR_1TO1_GR_t* const) &PERI->TR_1TO1_GR[9]) /* 0x4000E400 */ #define PERI_TR_1TO1_GR10 ((volatile stc_PERI_TR_1TO1_GR_t* const) &PERI->TR_1TO1_GR[10]) /* 0x4000E800 */ /******************************************************************************* * CPUSS *******************************************************************************/ /** * \brief Identity (CPUSS_IDENTITY) */ typedef struct stc_CPUSS_IDENTITY_field { uint32 u1P:1; uint32 u1NS:1; uint32 :2; uint32 u4PC:4; uint32 u4MS:4; uint32 :20; } stc_CPUSS_IDENTITY_field_t; typedef union un_CPUSS_IDENTITY { uint32 u32Register; stc_CPUSS_IDENTITY_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_IDENTITY_t; /** * \brief CM4 status (CPUSS_CM4_STATUS) */ typedef struct stc_CPUSS_CM4_STATUS_field { uint32 u1SLEEPING:1; uint32 u1SLEEPDEEP:1; uint32 :2; uint32 u1PWR_DONE:1; uint32 :27; } stc_CPUSS_CM4_STATUS_field_t; typedef union un_CPUSS_CM4_STATUS { uint32 u32Register; stc_CPUSS_CM4_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM4_STATUS_t; /** * \brief CM4 clock control (CPUSS_CM4_CLOCK_CTL) */ typedef struct stc_CPUSS_CM4_CLOCK_CTL_field { uint32 :8; uint32 u8FAST_INT_DIV:8; uint32 :16; } stc_CPUSS_CM4_CLOCK_CTL_field_t; typedef union un_CPUSS_CM4_CLOCK_CTL { uint32 u32Register; stc_CPUSS_CM4_CLOCK_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM4_CLOCK_CTL_t; /** * \brief CM4 control (CPUSS_CM4_CTL) */ typedef struct stc_CPUSS_CM4_CTL_field { uint32 :24; uint32 u1IOC_MASK:1; uint32 u1DZC_MASK:1; uint32 u1OFC_MASK:1; uint32 u1UFC_MASK:1; uint32 u1IXC_MASK:1; uint32 :2; uint32 u1IDC_MASK:1; } stc_CPUSS_CM4_CTL_field_t; typedef union un_CPUSS_CM4_CTL { uint32 u32Register; stc_CPUSS_CM4_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM4_CTL_t; /** * \brief CM4 interrupt 0 status (CPUSS_CM4_INT0_STATUS) */ typedef struct stc_CPUSS_CM4_INT0_STATUS_field { uint32 u10SYSTEM_INT_IDX:10; uint32 :21; uint32 u1SYSTEM_INT_VALID:1; } stc_CPUSS_CM4_INT0_STATUS_field_t; typedef union un_CPUSS_CM4_INT0_STATUS { uint32 u32Register; stc_CPUSS_CM4_INT0_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM4_INT0_STATUS_t; /** * \brief CM4 interrupt 1 status (CPUSS_CM4_INT1_STATUS) */ typedef struct stc_CPUSS_CM4_INT1_STATUS_field { uint32 u10SYSTEM_INT_IDX:10; uint32 :21; uint32 u1SYSTEM_INT_VALID:1; } stc_CPUSS_CM4_INT1_STATUS_field_t; typedef union un_CPUSS_CM4_INT1_STATUS { uint32 u32Register; stc_CPUSS_CM4_INT1_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM4_INT1_STATUS_t; /** * \brief CM4 interrupt 2 status (CPUSS_CM4_INT2_STATUS) */ typedef struct stc_CPUSS_CM4_INT2_STATUS_field { uint32 u10SYSTEM_INT_IDX:10; uint32 :21; uint32 u1SYSTEM_INT_VALID:1; } stc_CPUSS_CM4_INT2_STATUS_field_t; typedef union un_CPUSS_CM4_INT2_STATUS { uint32 u32Register; stc_CPUSS_CM4_INT2_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM4_INT2_STATUS_t; /** * \brief CM4 interrupt 3 status (CPUSS_CM4_INT3_STATUS) */ typedef struct stc_CPUSS_CM4_INT3_STATUS_field { uint32 u10SYSTEM_INT_IDX:10; uint32 :21; uint32 u1SYSTEM_INT_VALID:1; } stc_CPUSS_CM4_INT3_STATUS_field_t; typedef union un_CPUSS_CM4_INT3_STATUS { uint32 u32Register; stc_CPUSS_CM4_INT3_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM4_INT3_STATUS_t; /** * \brief CM4 interrupt 4 status (CPUSS_CM4_INT4_STATUS) */ typedef struct stc_CPUSS_CM4_INT4_STATUS_field { uint32 u10SYSTEM_INT_IDX:10; uint32 :21; uint32 u1SYSTEM_INT_VALID:1; } stc_CPUSS_CM4_INT4_STATUS_field_t; typedef union un_CPUSS_CM4_INT4_STATUS { uint32 u32Register; stc_CPUSS_CM4_INT4_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM4_INT4_STATUS_t; /** * \brief CM4 interrupt 5 status (CPUSS_CM4_INT5_STATUS) */ typedef struct stc_CPUSS_CM4_INT5_STATUS_field { uint32 u10SYSTEM_INT_IDX:10; uint32 :21; uint32 u1SYSTEM_INT_VALID:1; } stc_CPUSS_CM4_INT5_STATUS_field_t; typedef union un_CPUSS_CM4_INT5_STATUS { uint32 u32Register; stc_CPUSS_CM4_INT5_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM4_INT5_STATUS_t; /** * \brief CM4 interrupt 6 status (CPUSS_CM4_INT6_STATUS) */ typedef struct stc_CPUSS_CM4_INT6_STATUS_field { uint32 u10SYSTEM_INT_IDX:10; uint32 :21; uint32 u1SYSTEM_INT_VALID:1; } stc_CPUSS_CM4_INT6_STATUS_field_t; typedef union un_CPUSS_CM4_INT6_STATUS { uint32 u32Register; stc_CPUSS_CM4_INT6_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM4_INT6_STATUS_t; /** * \brief CM4 interrupt 7 status (CPUSS_CM4_INT7_STATUS) */ typedef struct stc_CPUSS_CM4_INT7_STATUS_field { uint32 u10SYSTEM_INT_IDX:10; uint32 :21; uint32 u1SYSTEM_INT_VALID:1; } stc_CPUSS_CM4_INT7_STATUS_field_t; typedef union un_CPUSS_CM4_INT7_STATUS { uint32 u32Register; stc_CPUSS_CM4_INT7_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM4_INT7_STATUS_t; /** * \brief CM4 vector table base (CPUSS_CM4_VECTOR_TABLE_BASE) */ typedef struct stc_CPUSS_CM4_VECTOR_TABLE_BASE_field { uint32 :10; uint32 u22ADDR22:22; } stc_CPUSS_CM4_VECTOR_TABLE_BASE_field_t; typedef union un_CPUSS_CM4_VECTOR_TABLE_BASE { uint32 u32Register; stc_CPUSS_CM4_VECTOR_TABLE_BASE_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM4_VECTOR_TABLE_BASE_t; /** * \brief CM4 NMI control (CPUSS_CM4_NMI_CTL) */ typedef struct stc_CPUSS_CM4_NMI_CTL_field { uint32 u10SYSTEM_INT_IDX:10; uint32 :22; } stc_CPUSS_CM4_NMI_CTL_field_t; typedef union un_CPUSS_CM4_NMI_CTL { uint32 u32Register; stc_CPUSS_CM4_NMI_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM4_NMI_CTL_t; /** * \brief UDB power control (CPUSS_UDB_PWR_CTL) */ typedef struct stc_CPUSS_UDB_PWR_CTL_field { uint32 u2PWR_MODE:2; uint32 :14; uint32 u16VECTKEYSTAT:16; } stc_CPUSS_UDB_PWR_CTL_field_t; typedef union un_CPUSS_UDB_PWR_CTL { uint32 u32Register; stc_CPUSS_UDB_PWR_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_UDB_PWR_CTL_t; /** * \brief UDB power control (CPUSS_UDB_PWR_DELAY_CTL) */ typedef struct stc_CPUSS_UDB_PWR_DELAY_CTL_field { uint32 u10UP:10; uint32 :22; } stc_CPUSS_UDB_PWR_DELAY_CTL_field_t; typedef union un_CPUSS_UDB_PWR_DELAY_CTL { uint32 u32Register; stc_CPUSS_UDB_PWR_DELAY_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_UDB_PWR_DELAY_CTL_t; /** * \brief CM0+ control (CPUSS_CM0_CTL) */ typedef struct stc_CPUSS_CM0_CTL_field { uint32 u1SLV_STALL:1; uint32 u1ENABLED:1; uint32 :14; uint32 u16VECTKEYSTAT:16; } stc_CPUSS_CM0_CTL_field_t; typedef union un_CPUSS_CM0_CTL { uint32 u32Register; stc_CPUSS_CM0_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_CTL_t; /** * \brief CM0+ status (CPUSS_CM0_STATUS) */ typedef struct stc_CPUSS_CM0_STATUS_field { uint32 u1SLEEPING:1; uint32 u1SLEEPDEEP:1; uint32 :30; } stc_CPUSS_CM0_STATUS_field_t; typedef union un_CPUSS_CM0_STATUS { uint32 u32Register; stc_CPUSS_CM0_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_STATUS_t; /** * \brief CM0+ clock control (CPUSS_CM0_CLOCK_CTL) */ typedef struct stc_CPUSS_CM0_CLOCK_CTL_field { uint32 :8; uint32 u8SLOW_INT_DIV:8; uint32 :8; uint32 u8PERI_INT_DIV:8; } stc_CPUSS_CM0_CLOCK_CTL_field_t; typedef union un_CPUSS_CM0_CLOCK_CTL { uint32 u32Register; stc_CPUSS_CM0_CLOCK_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_CLOCK_CTL_t; /** * \brief CM0+ interrupt 0 status (CPUSS_CM0_INT0_STATUS) */ typedef struct stc_CPUSS_CM0_INT0_STATUS_field { uint32 u10SYSTEM_INT_IDX:10; uint32 :21; uint32 u1SYSTEM_INT_VALID:1; } stc_CPUSS_CM0_INT0_STATUS_field_t; typedef union un_CPUSS_CM0_INT0_STATUS { uint32 u32Register; stc_CPUSS_CM0_INT0_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_INT0_STATUS_t; /** * \brief CM0+ interrupt 1 status (CPUSS_CM0_INT1_STATUS) */ typedef struct stc_CPUSS_CM0_INT1_STATUS_field { uint32 u10SYSTEM_INT_IDX:10; uint32 :21; uint32 u1SYSTEM_INT_VALID:1; } stc_CPUSS_CM0_INT1_STATUS_field_t; typedef union un_CPUSS_CM0_INT1_STATUS { uint32 u32Register; stc_CPUSS_CM0_INT1_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_INT1_STATUS_t; /** * \brief CM0+ interrupt 2 status (CPUSS_CM0_INT2_STATUS) */ typedef struct stc_CPUSS_CM0_INT2_STATUS_field { uint32 u10SYSTEM_INT_IDX:10; uint32 :21; uint32 u1SYSTEM_INT_VALID:1; } stc_CPUSS_CM0_INT2_STATUS_field_t; typedef union un_CPUSS_CM0_INT2_STATUS { uint32 u32Register; stc_CPUSS_CM0_INT2_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_INT2_STATUS_t; /** * \brief CM0+ interrupt 3 status (CPUSS_CM0_INT3_STATUS) */ typedef struct stc_CPUSS_CM0_INT3_STATUS_field { uint32 u10SYSTEM_INT_IDX:10; uint32 :21; uint32 u1SYSTEM_INT_VALID:1; } stc_CPUSS_CM0_INT3_STATUS_field_t; typedef union un_CPUSS_CM0_INT3_STATUS { uint32 u32Register; stc_CPUSS_CM0_INT3_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_INT3_STATUS_t; /** * \brief CM0+ interrupt 4 status (CPUSS_CM0_INT4_STATUS) */ typedef struct stc_CPUSS_CM0_INT4_STATUS_field { uint32 u10SYSTEM_INT_IDX:10; uint32 :21; uint32 u1SYSTEM_INT_VALID:1; } stc_CPUSS_CM0_INT4_STATUS_field_t; typedef union un_CPUSS_CM0_INT4_STATUS { uint32 u32Register; stc_CPUSS_CM0_INT4_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_INT4_STATUS_t; /** * \brief CM0+ interrupt 5 status (CPUSS_CM0_INT5_STATUS) */ typedef struct stc_CPUSS_CM0_INT5_STATUS_field { uint32 u10SYSTEM_INT_IDX:10; uint32 :21; uint32 u1SYSTEM_INT_VALID:1; } stc_CPUSS_CM0_INT5_STATUS_field_t; typedef union un_CPUSS_CM0_INT5_STATUS { uint32 u32Register; stc_CPUSS_CM0_INT5_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_INT5_STATUS_t; /** * \brief CM0+ interrupt 6 status (CPUSS_CM0_INT6_STATUS) */ typedef struct stc_CPUSS_CM0_INT6_STATUS_field { uint32 u10SYSTEM_INT_IDX:10; uint32 :21; uint32 u1SYSTEM_INT_VALID:1; } stc_CPUSS_CM0_INT6_STATUS_field_t; typedef union un_CPUSS_CM0_INT6_STATUS { uint32 u32Register; stc_CPUSS_CM0_INT6_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_INT6_STATUS_t; /** * \brief CM0+ interrupt 7 status (CPUSS_CM0_INT7_STATUS) */ typedef struct stc_CPUSS_CM0_INT7_STATUS_field { uint32 u10SYSTEM_INT_IDX:10; uint32 :21; uint32 u1SYSTEM_INT_VALID:1; } stc_CPUSS_CM0_INT7_STATUS_field_t; typedef union un_CPUSS_CM0_INT7_STATUS { uint32 u32Register; stc_CPUSS_CM0_INT7_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_INT7_STATUS_t; /** * \brief CM0+ vector table base (CPUSS_CM0_VECTOR_TABLE_BASE) */ typedef struct stc_CPUSS_CM0_VECTOR_TABLE_BASE_field { uint32 :8; uint32 u24ADDR24:24; } stc_CPUSS_CM0_VECTOR_TABLE_BASE_field_t; typedef union un_CPUSS_CM0_VECTOR_TABLE_BASE { uint32 u32Register; stc_CPUSS_CM0_VECTOR_TABLE_BASE_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_VECTOR_TABLE_BASE_t; /** * \brief CM0+ NMI control (CPUSS_CM0_NMI_CTL) */ typedef struct stc_CPUSS_CM0_NMI_CTL_field { uint32 u10SYSTEM_INT_IDX:10; uint32 :22; } stc_CPUSS_CM0_NMI_CTL_field_t; typedef union un_CPUSS_CM0_NMI_CTL { uint32 u32Register; stc_CPUSS_CM0_NMI_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_NMI_CTL_t; /** * \brief CM4 power control (CPUSS_CM4_PWR_CTL) */ typedef struct stc_CPUSS_CM4_PWR_CTL_field { uint32 u2PWR_MODE:2; uint32 :14; uint32 u16VECTKEYSTAT:16; } stc_CPUSS_CM4_PWR_CTL_field_t; typedef union un_CPUSS_CM4_PWR_CTL { uint32 u32Register; stc_CPUSS_CM4_PWR_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM4_PWR_CTL_t; /** * \brief CM4 power control (CPUSS_CM4_PWR_DELAY_CTL) */ typedef struct stc_CPUSS_CM4_PWR_DELAY_CTL_field { uint32 u10UP:10; uint32 :22; } stc_CPUSS_CM4_PWR_DELAY_CTL_field_t; typedef union un_CPUSS_CM4_PWR_DELAY_CTL { uint32 u32Register; stc_CPUSS_CM4_PWR_DELAY_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM4_PWR_DELAY_CTL_t; /** * \brief RAM 0 control (CPUSS_RAM0_CTL0) */ typedef struct stc_CPUSS_RAM0_CTL0_field { uint32 u2SLOW_WS:2; uint32 :6; uint32 u2FAST_WS:2; uint32 :6; uint32 u1ECC_EN:1; uint32 u1ECC_AUTO_CORRECT:1; uint32 u1ECC_INJ_EN:1; uint32 :13; } stc_CPUSS_RAM0_CTL0_field_t; typedef union un_CPUSS_RAM0_CTL0 { uint32 u32Register; stc_CPUSS_RAM0_CTL0_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_RAM0_CTL0_t; /** * \brief RAM 0 status (CPUSS_RAM0_STATUS) */ typedef struct stc_CPUSS_RAM0_STATUS_field { uint32 u1WB_EMPTY:1; uint32 :31; } stc_CPUSS_RAM0_STATUS_field_t; typedef union un_CPUSS_RAM0_STATUS { uint32 u32Register; stc_CPUSS_RAM0_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_RAM0_STATUS_t; /** * \brief RAM 0 power control (CPUSS_RAM0_PWR_MACRO_CTL) */ typedef struct stc_CPUSS_RAM0_PWR_MACRO_CTL_field { uint32 u2PWR_MODE:2; uint32 :14; uint32 u16VECTKEYSTAT:16; } stc_CPUSS_RAM0_PWR_MACRO_CTL_field_t; typedef union un_CPUSS_RAM0_PWR_MACRO_CTL { uint32 u32Register; stc_CPUSS_RAM0_PWR_MACRO_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_RAM0_PWR_MACRO_CTL_t; /** * \brief RAM 1 control (CPUSS_RAM1_CTL0) */ typedef struct stc_CPUSS_RAM1_CTL0_field { uint32 u2SLOW_WS:2; uint32 :6; uint32 u2FAST_WS:2; uint32 :6; uint32 u1ECC_EN:1; uint32 u1ECC_AUTO_CORRECT:1; uint32 u1ECC_INJ_EN:1; uint32 :13; } stc_CPUSS_RAM1_CTL0_field_t; typedef union un_CPUSS_RAM1_CTL0 { uint32 u32Register; stc_CPUSS_RAM1_CTL0_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_RAM1_CTL0_t; /** * \brief RAM 1 status (CPUSS_RAM1_STATUS) */ typedef struct stc_CPUSS_RAM1_STATUS_field { uint32 u1WB_EMPTY:1; uint32 :31; } stc_CPUSS_RAM1_STATUS_field_t; typedef union un_CPUSS_RAM1_STATUS { uint32 u32Register; stc_CPUSS_RAM1_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_RAM1_STATUS_t; /** * \brief RAM 1 power control (CPUSS_RAM1_PWR_CTL) */ typedef struct stc_CPUSS_RAM1_PWR_CTL_field { uint32 u2PWR_MODE:2; uint32 :14; uint32 u16VECTKEYSTAT:16; } stc_CPUSS_RAM1_PWR_CTL_field_t; typedef union un_CPUSS_RAM1_PWR_CTL { uint32 u32Register; stc_CPUSS_RAM1_PWR_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_RAM1_PWR_CTL_t; /** * \brief RAM 2 control (CPUSS_RAM2_CTL0) */ typedef struct stc_CPUSS_RAM2_CTL0_field { uint32 u2SLOW_WS:2; uint32 :6; uint32 u2FAST_WS:2; uint32 :6; uint32 u1ECC_EN:1; uint32 u1ECC_AUTO_CORRECT:1; uint32 u1ECC_INJ_EN:1; uint32 :13; } stc_CPUSS_RAM2_CTL0_field_t; typedef union un_CPUSS_RAM2_CTL0 { uint32 u32Register; stc_CPUSS_RAM2_CTL0_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_RAM2_CTL0_t; /** * \brief RAM 2 status (CPUSS_RAM2_STATUS) */ typedef struct stc_CPUSS_RAM2_STATUS_field { uint32 u1WB_EMPTY:1; uint32 :31; } stc_CPUSS_RAM2_STATUS_field_t; typedef union un_CPUSS_RAM2_STATUS { uint32 u32Register; stc_CPUSS_RAM2_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_RAM2_STATUS_t; /** * \brief RAM 2 power control (CPUSS_RAM2_PWR_CTL) */ typedef struct stc_CPUSS_RAM2_PWR_CTL_field { uint32 u2PWR_MODE:2; uint32 :14; uint32 u16VECTKEYSTAT:16; } stc_CPUSS_RAM2_PWR_CTL_field_t; typedef union un_CPUSS_RAM2_PWR_CTL { uint32 u32Register; stc_CPUSS_RAM2_PWR_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_RAM2_PWR_CTL_t; /** * \brief Power up delay used for all SRAM power domains (CPUSS_RAM_PWR_DELAY_CTL) */ typedef struct stc_CPUSS_RAM_PWR_DELAY_CTL_field { uint32 u10UP:10; uint32 :22; } stc_CPUSS_RAM_PWR_DELAY_CTL_field_t; typedef union un_CPUSS_RAM_PWR_DELAY_CTL { uint32 u32Register; stc_CPUSS_RAM_PWR_DELAY_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_RAM_PWR_DELAY_CTL_t; /** * \brief ROM control (CPUSS_ROM_CTL) */ typedef struct stc_CPUSS_ROM_CTL_field { uint32 u2SLOW_WS:2; uint32 :6; uint32 u2FAST_WS:2; uint32 :22; } stc_CPUSS_ROM_CTL_field_t; typedef union un_CPUSS_ROM_CTL { uint32 u32Register; stc_CPUSS_ROM_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_ROM_CTL_t; /** * \brief ECC control (CPUSS_ECC_CTL) */ typedef struct stc_CPUSS_ECC_CTL_field { uint32 u25WORD_ADDR:25; uint32 u7PARITY:7; } stc_CPUSS_ECC_CTL_field_t; typedef union un_CPUSS_ECC_CTL { uint32 u32Register; stc_CPUSS_ECC_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_ECC_CTL_t; /** * \brief Product identifier and version (same as CoreSight RomTables) (CPUSS_PRODUCT_ID) */ typedef struct stc_CPUSS_PRODUCT_ID_field { uint32 u12FAMILY_ID:12; uint32 :4; uint32 u4MAJOR_REV:4; uint32 u4MINOR_REV:4; uint32 :8; } stc_CPUSS_PRODUCT_ID_field_t; typedef union un_CPUSS_PRODUCT_ID { uint32 u32Register; stc_CPUSS_PRODUCT_ID_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_PRODUCT_ID_t; /** * \brief Debug port status (CPUSS_DP_STATUS) */ typedef struct stc_CPUSS_DP_STATUS_field { uint32 u1SWJ_CONNECTED:1; uint32 u1SWJ_DEBUG_EN:1; uint32 u1SWJ_JTAG_SEL:1; uint32 :29; } stc_CPUSS_DP_STATUS_field_t; typedef union un_CPUSS_DP_STATUS { uint32 u32Register; stc_CPUSS_DP_STATUS_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_DP_STATUS_t; /** * \brief Access port control (CPUSS_AP_CTL) */ typedef struct stc_CPUSS_AP_CTL_field { uint32 u1CM0_ENABLE:1; uint32 u1CM4_ENABLE:1; uint32 u1SYS_ENABLE:1; uint32 :13; uint32 u1CM0_DISABLE:1; uint32 u1CM4_DISABLE:1; uint32 u1SYS_DISABLE:1; uint32 :13; } stc_CPUSS_AP_CTL_field_t; typedef union un_CPUSS_AP_CTL { uint32 u32Register; stc_CPUSS_AP_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_AP_CTL_t; /** * \brief Buffer control (CPUSS_BUFF_CTL) */ typedef struct stc_CPUSS_BUFF_CTL_field { uint32 u1WRITE_BUFF:1; uint32 :31; } stc_CPUSS_BUFF_CTL_field_t; typedef union un_CPUSS_BUFF_CTL { uint32 u32Register; stc_CPUSS_BUFF_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_BUFF_CTL_t; /** * \brief SysTick timer control (CPUSS_SYSTICK_CTL) */ typedef struct stc_CPUSS_SYSTICK_CTL_field { uint32 u24TENMS:24; uint32 u2CLOCK_SOURCE:2; uint32 :4; uint32 u1SKEW:1; uint32 u1NOREF:1; } stc_CPUSS_SYSTICK_CTL_field_t; typedef union un_CPUSS_SYSTICK_CTL { uint32 u32Register; stc_CPUSS_SYSTICK_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_SYSTICK_CTL_t; /** * \brief Memory BIST status (CPUSS_MBIST_STAT) */ typedef struct stc_CPUSS_MBIST_STAT_field { uint32 u1SFP_READY:1; uint32 u1SFP_FAIL:1; uint32 :30; } stc_CPUSS_MBIST_STAT_field_t; typedef union un_CPUSS_MBIST_STAT { uint32 u32Register; stc_CPUSS_MBIST_STAT_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_MBIST_STAT_t; /** * \brief Calibration support set and read (CPUSS_CAL_SUP_SET) */ typedef struct stc_CPUSS_CAL_SUP_SET_field { uint32 u32DATA:32; } stc_CPUSS_CAL_SUP_SET_field_t; typedef union un_CPUSS_CAL_SUP_SET { uint32 u32Register; stc_CPUSS_CAL_SUP_SET_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CAL_SUP_SET_t; /** * \brief Calibration support clear and reset (CPUSS_CAL_SUP_CLR) */ typedef struct stc_CPUSS_CAL_SUP_CLR_field { uint32 u32DATA:32; } stc_CPUSS_CAL_SUP_CLR_field_t; typedef union un_CPUSS_CAL_SUP_CLR { uint32 u32Register; stc_CPUSS_CAL_SUP_CLR_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CAL_SUP_CLR_t; /** * \brief CM0+ protection context control (CPUSS_CM0_PC_CTL) */ typedef struct stc_CPUSS_CM0_PC_CTL_field { uint32 u4VALID:4; uint32 :28; } stc_CPUSS_CM0_PC_CTL_field_t; typedef union un_CPUSS_CM0_PC_CTL { uint32 u32Register; stc_CPUSS_CM0_PC_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_PC_CTL_t; /** * \brief CM0+ protection context 0 handler (CPUSS_CM0_PC0_HANDLER) */ typedef struct stc_CPUSS_CM0_PC0_HANDLER_field { uint32 u32ADDR:32; } stc_CPUSS_CM0_PC0_HANDLER_field_t; typedef union un_CPUSS_CM0_PC0_HANDLER { uint32 u32Register; stc_CPUSS_CM0_PC0_HANDLER_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_PC0_HANDLER_t; /** * \brief CM0+ protection context 1 handler (CPUSS_CM0_PC1_HANDLER) */ typedef struct stc_CPUSS_CM0_PC1_HANDLER_field { uint32 u32ADDR:32; } stc_CPUSS_CM0_PC1_HANDLER_field_t; typedef union un_CPUSS_CM0_PC1_HANDLER { uint32 u32Register; stc_CPUSS_CM0_PC1_HANDLER_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_PC1_HANDLER_t; /** * \brief CM0+ protection context 2 handler (CPUSS_CM0_PC2_HANDLER) */ typedef struct stc_CPUSS_CM0_PC2_HANDLER_field { uint32 u32ADDR:32; } stc_CPUSS_CM0_PC2_HANDLER_field_t; typedef union un_CPUSS_CM0_PC2_HANDLER { uint32 u32Register; stc_CPUSS_CM0_PC2_HANDLER_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_PC2_HANDLER_t; /** * \brief CM0+ protection context 3 handler (CPUSS_CM0_PC3_HANDLER) */ typedef struct stc_CPUSS_CM0_PC3_HANDLER_field { uint32 u32ADDR:32; } stc_CPUSS_CM0_PC3_HANDLER_field_t; typedef union un_CPUSS_CM0_PC3_HANDLER { uint32 u32Register; stc_CPUSS_CM0_PC3_HANDLER_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_PC3_HANDLER_t; /** * \brief Protection status (CPUSS_PROTECTION) */ typedef struct stc_CPUSS_PROTECTION_field { uint32 u3STATE:3; uint32 :29; } stc_CPUSS_PROTECTION_field_t; typedef union un_CPUSS_PROTECTION { uint32 u32Register; stc_CPUSS_PROTECTION_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_PROTECTION_t; /** * \brief ROM trim control (CPUSS_TRIM_ROM_CTL) */ typedef struct stc_CPUSS_TRIM_ROM_CTL_field { uint32 u32TRIM:32; } stc_CPUSS_TRIM_ROM_CTL_field_t; typedef union un_CPUSS_TRIM_ROM_CTL { uint32 u32Register; stc_CPUSS_TRIM_ROM_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_TRIM_ROM_CTL_t; /** * \brief RAM trim control (CPUSS_TRIM_RAM_CTL) */ typedef struct stc_CPUSS_TRIM_RAM_CTL_field { uint32 u32TRIM:32; } stc_CPUSS_TRIM_RAM_CTL_field_t; typedef union un_CPUSS_TRIM_RAM_CTL { uint32 u32Register; stc_CPUSS_TRIM_RAM_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_TRIM_RAM_CTL_t; /** * \brief CM0+ system interrupt control (CPUSS_CM0_SYSTEM_INT_CTL) */ typedef struct stc_CPUSS_CM0_SYSTEM_INT_CTL_field { uint32 u3CPU_INT_IDX:3; uint32 :28; uint32 u1CPU_INT_VALID:1; } stc_CPUSS_CM0_SYSTEM_INT_CTL_field_t; typedef union un_CPUSS_CM0_SYSTEM_INT_CTL { uint32 u32Register; stc_CPUSS_CM0_SYSTEM_INT_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM0_SYSTEM_INT_CTL_t; /** * \brief CM4 system interrupt control (CPUSS_CM4_SYSTEM_INT_CTL) */ typedef struct stc_CPUSS_CM4_SYSTEM_INT_CTL_field { uint32 u3CPU_INT_IDX:3; uint32 :28; uint32 u1CPU_INT_VALID:1; } stc_CPUSS_CM4_SYSTEM_INT_CTL_field_t; typedef union un_CPUSS_CM4_SYSTEM_INT_CTL { uint32 u32Register; stc_CPUSS_CM4_SYSTEM_INT_CTL_field_t stcField; uint8 au8Byte[4]; uint16 au16Halfword[2]; } un_CPUSS_CM4_SYSTEM_INT_CTL_t; /** * \brief CPU subsystem (CPUSS) (CPUSS) */ typedef struct stc_CPUSS { un_CPUSS_IDENTITY_t unIDENTITY; /*!< 0x00000000 Identity */ un_CPUSS_CM4_STATUS_t unCM4_STATUS; /*!< 0x00000004 CM4 status */ un_CPUSS_CM4_CLOCK_CTL_t unCM4_CLOCK_CTL; /*!< 0x00000008 CM4 clock control */ un_CPUSS_CM4_CTL_t unCM4_CTL; /*!< 0x0000000C CM4 control */ uint32 au32Reserved[60]; un_CPUSS_CM4_INT0_STATUS_t unCM4_INT0_STATUS; /*!< 0x00000100 CM4 interrupt 0 status */ un_CPUSS_CM4_INT1_STATUS_t unCM4_INT1_STATUS; /*!< 0x00000104 CM4 interrupt 1 status */ un_CPUSS_CM4_INT2_STATUS_t unCM4_INT2_STATUS; /*!< 0x00000108 CM4 interrupt 2 status */ un_CPUSS_CM4_INT3_STATUS_t unCM4_INT3_STATUS; /*!< 0x0000010C CM4 interrupt 3 status */ un_CPUSS_CM4_INT4_STATUS_t unCM4_INT4_STATUS; /*!< 0x00000110 CM4 interrupt 4 status */ un_CPUSS_CM4_INT5_STATUS_t unCM4_INT5_STATUS; /*!< 0x00000114 CM4 interrupt 5 status */ un_CPUSS_CM4_INT6_STATUS_t unCM4_INT6_STATUS; /*!< 0x00000118 CM4 interrupt 6 status */ un_CPUSS_CM4_INT7_STATUS_t unCM4_INT7_STATUS; /*!< 0x0000011C CM4 interrupt 7 status */ uint32 au32Reserved1[56]; un_CPUSS_CM4_VECTOR_TABLE_BASE_t unCM4_VECTOR_TABLE_BASE; /*!< 0x00000200 CM4 vector table base */ uint32 au32Reserved2[15]; un_CPUSS_CM4_NMI_CTL_t unCM4_NMI_CTL[4]; /*!< 0x00000240 CM4 NMI control */ uint32 au32Reserved3[44]; un_CPUSS_UDB_PWR_CTL_t unUDB_PWR_CTL; /*!< 0x00000300 UDB power control */ un_CPUSS_UDB_PWR_DELAY_CTL_t unUDB_PWR_DELAY_CTL; /*!< 0x00000304 UDB power control */ uint32 au32Reserved4[830]; un_CPUSS_CM0_CTL_t unCM0_CTL; /*!< 0x00001000 CM0+ control */ un_CPUSS_CM0_STATUS_t unCM0_STATUS; /*!< 0x00001004 CM0+ status */ un_CPUSS_CM0_CLOCK_CTL_t unCM0_CLOCK_CTL; /*!< 0x00001008 CM0+ clock control */ uint32 au32Reserved5[61]; un_CPUSS_CM0_INT0_STATUS_t unCM0_INT0_STATUS; /*!< 0x00001100 CM0+ interrupt 0 status */ un_CPUSS_CM0_INT1_STATUS_t unCM0_INT1_STATUS; /*!< 0x00001104 CM0+ interrupt 1 status */ un_CPUSS_CM0_INT2_STATUS_t unCM0_INT2_STATUS; /*!< 0x00001108 CM0+ interrupt 2 status */ un_CPUSS_CM0_INT3_STATUS_t unCM0_INT3_STATUS; /*!< 0x0000110C CM0+ interrupt 3 status */ un_CPUSS_CM0_INT4_STATUS_t unCM0_INT4_STATUS; /*!< 0x00001110 CM0+ interrupt 4 status */ un_CPUSS_CM0_INT5_STATUS_t unCM0_INT5_STATUS; /*!< 0x00001114 CM0+ interrupt 5 status */ un_CPUSS_CM0_INT6_STATUS_t unCM0_INT6_STATUS; /*!< 0x00001118 CM0+ interrupt 6 status */ un_CPUSS_CM0_INT7_STATUS_t unCM0_INT7_STATUS; /*!< 0x0000111C CM0+ interrupt 7 status */ un_CPUSS_CM0_VECTOR_TABLE_BASE_t unCM0_VECTOR_TABLE_BASE; /*!< 0x00001120 CM0+ vector table base */ uint32 au32Reserved6[7]; un_CPUSS_CM0_NMI_CTL_t unCM0_NMI_CTL[4]; /*!< 0x00001140 CM0+ NMI control */ uint32 au32Reserved7[44]; un_CPUSS_CM4_PWR_CTL_t unCM4_PWR_CTL; /*!< 0x00001200 CM4 power control */ un_CPUSS_CM4_PWR_DELAY_CTL_t unCM4_PWR_DELAY_CTL; /*!< 0x00001204 CM4 power control */ uint32 au32Reserved8[62]; un_CPUSS_RAM0_CTL0_t unRAM0_CTL0; /*!< 0x00001300 RAM 0 control */ un_CPUSS_RAM0_STATUS_t unRAM0_STATUS; /*!< 0x00001304 RAM 0 status */ uint32 au32Reserved9[14]; un_CPUSS_RAM0_PWR_MACRO_CTL_t unRAM0_PWR_MACRO_CTL[16]; /*!< 0x00001340 RAM 0 power control */ un_CPUSS_RAM1_CTL0_t unRAM1_CTL0; /*!< 0x00001380 RAM 1 control */ un_CPUSS_RAM1_STATUS_t unRAM1_STATUS; /*!< 0x00001384 RAM 1 status */ un_CPUSS_RAM1_PWR_CTL_t unRAM1_PWR_CTL; /*!< 0x00001388 RAM 1 power control */ uint32 au32Reserved10[5]; un_CPUSS_RAM2_CTL0_t unRAM2_CTL0; /*!< 0x000013A0 RAM 2 control */ un_CPUSS_RAM2_STATUS_t unRAM2_STATUS; /*!< 0x000013A4 RAM 2 status */ un_CPUSS_RAM2_PWR_CTL_t unRAM2_PWR_CTL; /*!< 0x000013A8 RAM 2 power control */ uint32 au32Reserved11[5]; un_CPUSS_RAM_PWR_DELAY_CTL_t unRAM_PWR_DELAY_CTL; /*!< 0x000013C0 Power up delay used for all SRAM power domains */ un_CPUSS_ROM_CTL_t unROM_CTL; /*!< 0x000013C4 ROM control */ un_CPUSS_ECC_CTL_t unECC_CTL; /*!< 0x000013C8 ECC control */ uint32 au32Reserved12[13]; un_CPUSS_PRODUCT_ID_t unPRODUCT_ID; /*!< 0x00001400 Product identifier and version (same as CoreSight RomTables) */ uint32 au32Reserved13[3]; un_CPUSS_DP_STATUS_t unDP_STATUS; /*!< 0x00001410 Debug port status */ un_CPUSS_AP_CTL_t unAP_CTL; /*!< 0x00001414 Access port control */ uint32 au32Reserved14[58]; un_CPUSS_BUFF_CTL_t unBUFF_CTL; /*!< 0x00001500 Buffer control */ uint32 au32Reserved15[63]; un_CPUSS_SYSTICK_CTL_t unSYSTICK_CTL; /*!< 0x00001600 SysTick timer control */ uint32 au32Reserved16[64]; un_CPUSS_MBIST_STAT_t unMBIST_STAT; /*!< 0x00001704 Memory BIST status */ uint32 au32Reserved17[62]; un_CPUSS_CAL_SUP_SET_t unCAL_SUP_SET; /*!< 0x00001800 Calibration support set and read */ un_CPUSS_CAL_SUP_CLR_t unCAL_SUP_CLR; /*!< 0x00001804 Calibration support clear and reset */ uint32 au32Reserved18[510]; un_CPUSS_CM0_PC_CTL_t unCM0_PC_CTL; /*!< 0x00002000 CM0+ protection context control */ uint32 au32Reserved19[15]; un_CPUSS_CM0_PC0_HANDLER_t unCM0_PC0_HANDLER; /*!< 0x00002040 CM0+ protection context 0 handler */ un_CPUSS_CM0_PC1_HANDLER_t unCM0_PC1_HANDLER; /*!< 0x00002044 CM0+ protection context 1 handler */ un_CPUSS_CM0_PC2_HANDLER_t unCM0_PC2_HANDLER; /*!< 0x00002048 CM0+ protection context 2 handler */ un_CPUSS_CM0_PC3_HANDLER_t unCM0_PC3_HANDLER; /*!< 0x0000204C CM0+ protection context 3 handler */ uint32 au32Reserved20[29]; un_CPUSS_PROTECTION_t unPROTECTION; /*!< 0x000020C4 Protection status */ uint32 au32Reserved21[14]; un_CPUSS_TRIM_ROM_CTL_t unTRIM_ROM_CTL; /*!< 0x00002100 ROM trim control */ un_CPUSS_TRIM_RAM_CTL_t unTRIM_RAM_CTL; /*!< 0x00002104 RAM trim control */ uint32 au32Reserved22[6078]; un_CPUSS_CM0_SYSTEM_INT_CTL_t unCM0_SYSTEM_INT_CTL[1023]; /*!< 0x00008000 CM0+ system interrupt control */ uint32 au32Reserved23[1025]; un_CPUSS_CM4_SYSTEM_INT_CTL_t unCM4_SYSTEM_INT_CTL[1023]; /*!< 0x0000A000 CM4 system interrupt control */ } stc_CPUSS_t; /*!< Size = 45052 (0xAFFC) */ #define CPUSS_BASE 0x40200000UL #define CPUSS ((volatile stc_CPUSS_t* /*const*/) CPUSS_BASE) /* 0x40200000 */ /******************************************************************************* * CM4 NVIC *******************************************************************************/ typedef struct { uint32 ISER[8]; uint32 RESERVED0[24]; uint32 ICER[8]; uint32 RSERVED1[24]; uint32 ISPR[8]; uint32 RESERVED2[24]; uint32 ICPR[8]; uint32 RESERVED3[24]; uint32 IABR[8]; uint32 RESERVED4[56]; uint8 IP[240]; uint32 RESERVED5[644]; uint32 STIR; } NVIC_Type; #define NVIC_BASE (0xE000E100UL) #define NVIC ((volatile NVIC_Type* /*const*/) NVIC_BASE) //============================================================================= // Defines //============================================================================= #define SCB_UART ((volatile stc_SCB_t* /*const*/) SCB3_BASE) #endif /* DEVICE_2020_06_08_H_ */