//***************************************************************************** // (C) Automotive Lighting Reutlingen GmbH // Tuebinger Strasse 123, 72762 Reutlingen, Germany // // Automotive Lighting Reutlingen GmbH owns all the rights to this work. // This work shall not be copied, reproduced, used, modified, transferred // or its information shall not be disclosed without the prior written // authorization of Automotive Lighting Reutlingen GmbH. //***************************************************************************** //----------------------------------------------------------------------------- /// \file CddMlcNxp_Reg.h /// /// \brief MLC ASL5115SH Register definition header file. /// /// \descr /// //----------------------------------------------------------------------------- #ifndef __CDDMLCNXP_REG_H_24_09_2020__ #define __CDDMLCNXP_REG_H_24_09_2020__ //============================================================================= // Includes //============================================================================= #include "Std_Types.h" //============================================================================= // REGISTERS //============================================================================= #define CDD_MLC_NXP_REG_DIRECT_CH1_LB (uint8)0x00U #define CDD_MLC_NXP_REG_DIRECT_CH1_UB (uint8)0x01U #define CDD_MLC_NXP_REG_DIRECT_CH2_LB (uint8)0x02U #define CDD_MLC_NXP_REG_DIRECT_CH2_UB (uint8)0x03U #define CDD_MLC_NXP_REG_DIRECT_CH3_LB (uint8)0x04U #define CDD_MLC_NXP_REG_DIRECT_CH3_UB (uint8)0x05U #define CDD_MLC_NXP_REG_DIRECT_CH4_LB (uint8)0x06U #define CDD_MLC_NXP_REG_DIRECT_CH4_UB (uint8)0x07U #define CDD_MLC_NXP_REG_DIRECT_CH5_LB (uint8)0x08U #define CDD_MLC_NXP_REG_DIRECT_CH5_UB (uint8)0x09U #define CDD_MLC_NXP_REG_DIRECT_CH6_LB (uint8)0x0AU #define CDD_MLC_NXP_REG_DIRECT_CH6_UB (uint8)0x0BU #define CDD_MLC_NXP_REG_DIRECT_CH7_LB (uint8)0x0CU #define CDD_MLC_NXP_REG_DIRECT_CH7_UB (uint8)0x0DU #define CDD_MLC_NXP_REG_DIRECT_CH8_LB (uint8)0x0EU #define CDD_MLC_NXP_REG_DIRECT_CH8_UB (uint8)0x0FU #define CDD_MLC_NXP_REG_DIRECT_CH9_LB (uint8)0x10U #define CDD_MLC_NXP_REG_DIRECT_CH9_UB (uint8)0x11U #define CDD_MLC_NXP_REG_DIRECT_CH10_LB (uint8)0x12U #define CDD_MLC_NXP_REG_DIRECT_CH10_UB (uint8)0x13U #define CDD_MLC_NXP_REG_DIRECT_CH11_LB (uint8)0x14U #define CDD_MLC_NXP_REG_DIRECT_CH11_UB (uint8)0x15U #define CDD_MLC_NXP_REG_DIRECT_CH12_LB (uint8)0x16U #define CDD_MLC_NXP_REG_DIRECT_CH12_UB (uint8)0x17U #define CDD_MLC_NXP_REG_IMMOFF1 (uint8)0x30U #define CDD_MLC_NXP_REG_IMMOFF2 (uint8)0x31U #define CDD_MLC_NXP_REG_START1 (uint8)0x32U #define CDD_MLC_NXP_REG_START2 (uint8)0x33U #define CDD_MLC_NXP_REG_CLEAR (uint8)0x34U #define CDD_MLC_NXP_REG_READ_OC1 (uint8)0x35U #define CDD_MLC_NXP_REG_READ_OC2 (uint8)0x36U #define CDD_MLC_NXP_REG_READ_SC1 (uint8)0x37U #define CDD_MLC_NXP_REG_READ_SC2 (uint8)0x38U #define CDD_MLC_NXP_REG_NTC (uint8)0x39U #define CDD_MLC_NXP_REG_BIN (uint8)0x3AU #define CDD_MLC_NXP_REG_INTERNAL_STATUS (uint8)0x3BU #define CDD_MLC_NXP_REG_LHM (uint8)0x3CU #define CDD_MLC_NXP_REG_MTP_WRITE_CTL1 (uint8)0x3DU #define CDD_MLC_NXP_REG_MTP_WRITE_D1 (uint8)0x3EU #define CDD_MLC_NXP_REG_MTP_WRITE_D2 (uint8)0x3FU #define CDD_MLC_NXP_REG_MTP_READ_D1 (uint8)0x40U #define CDD_MLC_NXP_REG_MTP_READ_D2 (uint8)0x41U //============================================================================= // CAN COMMANDS ID //============================================================================= #define CDD_MLC_NXP_CMD_SEL_CONSECUTIVE_REGISTER_WRITE (uint8) 0U #define CDD_MLC_NXP_CMD_SEL_SELECTIVE_REGISTER_WRITE (uint8) 1U #define CDD_MLC_NXP_CMD_SEL_LHM_EXIT (uint8) 3U #define CDD_MLC_NXP_CMD_SEL_MLC_CHANNEL_START (uint8) 4U #define CDD_MLC_NXP_CMD_SEL_MLC_CHANNEL_IMMEDIATE_OFF (uint8) 5U #define CDD_MLC_NXP_CMD_SEL_LHM_REFRESH (uint8) 6U #define CDD_MLC_NXP_CMD_SEL_DUMMY_TRIMMING (uint8) 7U #define CDD_MLC_NXP_CMD_SEL_WRITE_DIRECT_PWM_CH_1_2_3_4 (uint8) 8U #define CDD_MLC_NXP_CMD_SEL_WRITE_DIRECT_PWM_CH_5_6_7_8 (uint8) 9U #define CDD_MLC_NXP_CMD_SEL_WRITE_DIRECT_PWM_CH_9_10_11_12 (uint8)10U #define CDD_MLC_NXP_CMD_SEL_DIAGNOSIS_ADC_TRIGGER (uint8)13U #define CDD_MLC_NXP_CMD_SEL_MTP_WRITE (uint8)14U #define CDD_MLC_NXP_CMD_SEL_CONSECUTIVE_REGISTER_READ (uint8)16U #define CDD_MLC_NXP_CMD_SEL_SELECTIVE_REGISTER_READ (uint8)17U #define CDD_MLC_NXP_CMD_SEL_DIAGNOSIS_READ (uint8)18U #define CDD_MLC_NXP_CMD_BRD_MTP_READ (uint8)30U #define CDD_MLC_NXP_CMD_BRD_MLC_CHANNEL_START (uint8)32U #define CDD_MLC_NXP_CMD_BRD_MLC_CHANNEL_IMMEDIATE_OFF (uint8)33U #define CDD_MLC_NXP_CMD_BRD_DUMMY_TRIMMING (uint8)34U #define CDD_MLC_NXP_CMD_BRD_POK_REGISTER_READ (uint8)35U #define CDD_MLC_NXP_CMD_BRD_POR_REGISTER_READ (uint8)36U #define CDD_MLC_NXP_CMD_BRD_LHM_REFRESH (uint8)37U #define CDD_MLC_NXP_CMD_BRD_LHM_EXIT (uint8)38U #define CDD_MLC_NXP_CMD_BRD_CLEAR_ALL_OC_SC_FLAGS (uint8)39U #define CDD_MLC_NXP_CMD_BRD_DIAGNOSIS_READ (uint8)40U #define CDD_MLC_NXP_CMD_BRD_GO_TO_SLEEP (uint8)41U #define CDD_MLC_NXP_CMD_BRD_PARTIAL_SLEEP (uint8)42U #define CDD_MLC_NXP_CMD_BRD_PARTIAL_WAKE (uint8)43U #define CDD_MLC_NXP_CMD_BRD_DIAGNOSIS_ADC_TRIGGER (uint8)46U #define CDD_MLC_NXP_CMD_BRD_JUNCTION_TEMPERATURE_READ (uint8)64U //============================================================================= // Defines //============================================================================= #define CDD_MLC_NXP_BROADCAST_ADDRESS (uint8)0U #define CDD_MLC_NXP_LHM_EXIT_STEP_1 (uint8)0x1EU #define CDD_MLC_NXP_LHM_EXIT_STEP_2 (uint8)0x2EU #define CDD_MLC_NXP_LHM_EXIT_STEP_3 (uint8)0x4EU #define CDD_MLC_NXP_WD_CONFIG (uint8)0x7EU #define CDD_MLC_NXP_CLEAR_FLAG_MASK (uint8)0x9FU #define CDD_MLC_NXP_XC1_LAST_SW 8U #define CDD_MLC_NXP_XC2_LAST_SW 12U //============================================================================= // Types definition //============================================================================= typedef struct { uint8 u1CLR_SC :1; uint8 u1CLR_OC :1; uint8 u1MTP_ACCESS_STATUS :1; uint8 u1MTP_ILLEGAL_ACCESS:1; uint8 u1REG_ILLEGAL_ACCESS:1; uint8 u1MTP_LOCKED :1; uint8 u1ILLEGAL_COMMAND :1; uint8 u1POR :1; }sCddMlcNxp_ClearRegType; typedef struct { uint8 u1OC1:1; uint8 u1OC2:1; uint8 u1OC3:1; uint8 u1OC4:1; uint8 u1OC5:1; uint8 u1OC6:1; uint8 u1OC7:1; uint8 u1OC8:1; }sCddMlcNxp_ReadOc1RegType; typedef union { uint8 ucRaw; sCddMlcNxp_ReadOc1RegType sBit; }uCddMlcNxp_ReadOc1RegType; typedef struct { uint8 u1OC9:1; uint8 u1OC10:1; uint8 u1OC11:1; uint8 u1OC12:1; uint8 :4; }sCddMlcNxp_ReadOc2RegType; typedef union { uint8 ucRaw; sCddMlcNxp_ReadOc2RegType sBit; }uCddMlcNxp_ReadOc2RegType; typedef struct { uint8 u1SC1:1; uint8 u1SC2:1; uint8 u1SC3:1; uint8 u1SC4:1; uint8 u1SC5:1; uint8 u1SC6:1; uint8 u1SC7:1; uint8 u1SC8:1; }sCddMlcNxp_ReadSc1RegType; typedef union { uint8 ucRaw; sCddMlcNxp_ReadSc1RegType sBit; }uCddMlcNxp_ReadSc1RegType; typedef struct { uint8 u1SC9:1; uint8 u1SC10:1; uint8 u1SC11:1; uint8 u1SC12:1; uint8 :4; }sCddMlcNxp_ReadSc2RegType; typedef union { uint8 ucRaw; sCddMlcNxp_ReadSc2RegType sBit; }uCddMlcNxp_ReadSc2RegType; typedef struct { uint8 u1NTCFAIL:1; uint8 u6NTC:6; uint8 u1CPFAIL:1; }sCddMlcNxp_NtcRegType; typedef struct { uint8 u1BINFAIL:1; uint8 u3BIN:3; uint8 u1LHM_STATUS:1; uint8 u1POK:1; uint8 u1OTW_2:1; uint8 u1OTW_1:1; }sCddMlcNxp_BinRegType; typedef struct { uint8 :7; uint8 u1TXD_BUFFER_FULL:1; }sCddMlcNxp_InternalStatusRegType; typedef struct { sCddMlcNxp_ClearRegType Clear; uCddMlcNxp_ReadOc1RegType ReadOc1; uCddMlcNxp_ReadOc2RegType ReadOc2; uCddMlcNxp_ReadSc1RegType ReadSc1; uCddMlcNxp_ReadSc2RegType ReadSc2; sCddMlcNxp_NtcRegType Ntc; sCddMlcNxp_BinRegType Bin; sCddMlcNxp_InternalStatusRegType InternalStatus; }sCddMlcNxp_DiagReadType; typedef union { uint8 aucRaw[8]; sCddMlcNxp_DiagReadType sReg ; }uCddMlcNxp_DiagReadType; #endif // __CDDMLCNXP_H_24_09_2020__