/**********************************************************************************************************************
 *  COPYRIGHT
 *  -------------------------------------------------------------------------------------------------------------------
 *  \verbatim
 *
 *                This software is copyright protected and proprietary to Vector Informatik GmbH.
 *                Vector Informatik GmbH grants to you only those rights as set out in the license conditions.
 *                All other rights remain with Vector Informatik GmbH.
 *  \endverbatim
 *  -------------------------------------------------------------------------------------------------------------------
 *  FILE DESCRIPTION
 *  -------------------------------------------------------------------------------------------------------------------
 *             File:  SchM_ComM.h
 *           Config:  CBD2200592_D00_demo.dpa
 *      ECU-Project:  CBD2200592_D00_demo
 *
 *        Generator:  MICROSAR RTE Generator Version 4.31.0
 *                    RTE Core Version 4.31.0
 *          License:  CBD2201205
 *
 *      Description:  Header of BSW Scheduler for BSW Module <ComM>
 *********************************************************************************************************************/
#ifndef SCHM_COMM_H
# define SCHM_COMM_H

# ifdef __cplusplus
extern "C" {
# endif  /* __cplusplus */

# include "SchM_ComM_Type.h"

# include "Os.h" /* PRQA S 0828, 0883 */ /* MD_MSR_Dir1.1, MD_Rte_Os */

# define COMM_START_SEC_CODE
# include "ComM_MemMap.h" /* PRQA S 5087 */ /* MD_MSR_MemMap */

FUNC(void, COMM_CODE) ComM_MainFunction_0(void); /* PRQA S 3451, 3449 */ /* MD_Rte_3451, MD_Rte_3449 */
FUNC(void, COMM_CODE) ComM_MainFunction_1(void); /* PRQA S 3451, 3449 */ /* MD_Rte_3451, MD_Rte_3449 */
FUNC(void, COMM_CODE) ComM_MainFunction_2(void); /* PRQA S 3451, 3449 */ /* MD_Rte_3451, MD_Rte_3449 */
FUNC(void, COMM_CODE) ComM_MainFunction_3(void); /* PRQA S 3451, 3449 */ /* MD_Rte_3451, MD_Rte_3449 */

# define COMM_STOP_SEC_CODE
# include "ComM_MemMap.h" /* PRQA S 5087 */ /* MD_MSR_MemMap */

# define SchM_Enter_ComM_COMM_EXCLUSIVE_AREA_0() SuspendAllInterrupts()  /* RteAnalyzer(ExclusiveArea, ALL_INTERRUPT_BLOCKING) */

# define SchM_Exit_ComM_COMM_EXCLUSIVE_AREA_0() ResumeAllInterrupts()  /* RteAnalyzer(ExclusiveArea, ALL_INTERRUPT_BLOCKING) */

# define SchM_Enter_ComM_COMM_EXCLUSIVE_AREA_1() SuspendAllInterrupts()  /* RteAnalyzer(ExclusiveArea, ALL_INTERRUPT_BLOCKING) */

# define SchM_Exit_ComM_COMM_EXCLUSIVE_AREA_1() ResumeAllInterrupts()  /* RteAnalyzer(ExclusiveArea, ALL_INTERRUPT_BLOCKING) */

# define SchM_Enter_ComM_COMM_EXCLUSIVE_AREA_2()  /* RteAnalyzer(ExclusiveArea, NONE) */

# define SchM_Exit_ComM_COMM_EXCLUSIVE_AREA_2()  /* RteAnalyzer(ExclusiveArea, NONE) */

# define SchM_Enter_ComM_COMM_EXCLUSIVE_AREA_3()  /* RteAnalyzer(ExclusiveArea, NONE) */

# define SchM_Exit_ComM_COMM_EXCLUSIVE_AREA_3()  /* RteAnalyzer(ExclusiveArea, NONE) */

# define SchM_Enter_ComM_COMM_EXCLUSIVE_AREA_4()  /* RteAnalyzer(ExclusiveArea, NONE) */

# define SchM_Exit_ComM_COMM_EXCLUSIVE_AREA_4()  /* RteAnalyzer(ExclusiveArea, NONE) */

# define SchM_Enter_ComM_COMM_EXCLUSIVE_AREA_5()  /* RteAnalyzer(ExclusiveArea, NONE) */

# define SchM_Exit_ComM_COMM_EXCLUSIVE_AREA_5()  /* RteAnalyzer(ExclusiveArea, NONE) */

# define SchM_Enter_ComM_COMM_EXCLUSIVE_AREA_6()  /* RteAnalyzer(ExclusiveArea, NONE) */

# define SchM_Exit_ComM_COMM_EXCLUSIVE_AREA_6()  /* RteAnalyzer(ExclusiveArea, NONE) */

# define SchM_Enter_ComM_COMM_EXCLUSIVE_AREA_7()  /* RteAnalyzer(ExclusiveArea, NONE) */

# define SchM_Exit_ComM_COMM_EXCLUSIVE_AREA_7()  /* RteAnalyzer(ExclusiveArea, NONE) */


# ifdef __cplusplus
} /* extern "C" */
# endif  /* __cplusplus */

#endif /* SCHM_COMM_H */

/**********************************************************************************************************************
 MISRA 2012 violations and justifications
 *********************************************************************************************************************/

/* module specific MISRA deviations:
   MD_Rte_3449:  MISRA rule: Rule8.5
     Reason:     Schedulable entities are declared by the RTE and also by the BSW modules.
     Risk:       No functional risk.
     Prevention: Not required.

   MD_Rte_3451:  MISRA rule: Rule8.5
     Reason:     Schedulable entities are declared by the RTE and also by the BSW modules.
     Risk:       No functional risk.
     Prevention: Not required.

   MD_Rte_Os:
     Reason:     This justification is used as summary justification for all deviations caused by the MICROSAR OS
                 which is for testing of the RTE. Those deviations are no issues in the RTE code.
     Risk:       No functional risk.
     Prevention: Not required.

*/