//***************************************************************************** // (C) Automotive Lighting China // // Automotive Lighting Reutlingen GmbH owns all the rights to this work. // This work shall not be copied, reproduced, used, modified, transferred // or its information shall not be disclosed without the prior written // authorization of Automotive Lighting China. //***************************************************************************** // ---------------------------------------------------------------------------- /// \file DummyLoad.c /// /// \author f24301c [mailto:walker.lv@marelli.com] /// /// \date 05.27.2024 /// /// \brief stand alone test code for UartEng test /// // ---------------------------------------------------------------------------- //============================================================================= // Includes //============================================================================= #include "DummyLoad.h" #include #include #include #include #if (UEE_STANDALONE_TEST == STD_ON) static ProtocolBuf_t test01 = { // tcb { 4, // channel 0, // address, dummy 0, // primitive, dummy 0, // broadcasting 0, // retransmitAttempt 3, // retransmitLimit 0, // transactionDelay UUE_TRANSACTION_TIMEOUT, // transactionTimeout, 1000us TransactionError_NoError, // errorState TransactionState_RequestReady, // transactionState #if (UUE_TRANSACTION_PROFILE == STD_ON) 0, 0, 0, 0 #endif }, // tcb, transaction control block { 0x55, 0xaa, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, /* 8 bytes */ 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, /* 16 bytes */ 0x0e, 0x0f, 0x10, 0x11, /* 20 bytes */ 0x12, 0x13, 0x14, 0x15, /* 24 bytes */ 0x16, 0x17, 0x18, 0x19 /* 28 bytes */ }, // reqPduBuffer */ (uint8*)NULL_PTR, // resPduBuffer UUE_MAX_REQUEST_LEN, // reqPduLength 0, // resPduLength }; void AddTestPdu0(void) { { // transaction state change after transfer, need to reset to request ready before enqueue test01.tcb.transactionState = TransactionState_RequestReady; test01.tcb.retransmitAttempt = 0; test01.tcb.tsDequeue = 0; test01.tcb.tsEnQueue = 0; test01.tcb.tsTransactionStart = 0; test01.tcb.tsTransactionEnd = 0; CddUartEng_AddPud(&test01); } } void AddPrimitive(ProtocolBuf_t* pdu) { // transaction state change after transfer, need to reset to request ready before enqueue pdu->tcb.transactionState = TransactionState_RequestReady; pdu->tcb.retransmitAttempt = 0; pdu->tcb.tsDequeue = 0; pdu->tcb.tsEnQueue = 0; pdu->tcb.tsTransactionStart = 0; pdu->tcb.tsTransactionEnd = 0; CddUartEng_AddPud(pdu); } // 929140 primitive test // BYTE0, sync #define SYNC ((uint8)0x55u) // BYTE1, address, data len, r/w, broadcasting /* Data length setting */ #define DATA_LENGTH_1 ((uint8)0x00u) #define DATA_LENGTH_4 ((uint8)0x10u) #define DATA_LENGTH_16 ((uint8)0x20u) #define DATA_LENGTH_24 ((uint8)0x30u) #define NON_BROADCASTING ((uint8)0x00U) #define BROADCASTING ((uint8)0x40U) #define READ_MODE ((uint8)0x00u) #define WRITE_MODE ((uint8)0x80u) // BYTE2, register /* Register address */ #define PWMMA0_ADDR ((uint8)0x00u) #define OUTEN0_ADDR ((uint8)0x40u) #define SLSDAC0_ADDR ((uint8)0x78u) #define DIM_ADDR ((uint8)0x7Eu) #define CLR_ADDR ((uint8)0x91u) #define LOCK_ADDR ((uint8)0x93u) #define CTRLGATE_ADDR ((uint8)0x96u) #define FLAG_ERR_ADDR ((uint8)0xA0u) #define FLAG_STATUS_ADDR ((uint8)0xA1u) #define FLAG_SLS1_ADDR ((uint8)0xA4u) #define FLAG_OPEN1_ADDR ((uint8)0xA8u) #define FLAG_SHORT1_ADDR ((uint8)0xACu) static const uint8 crcArray[256] = { 0x00u,0x5eu,0xbcu,0xe2u,0x61u,0x3fu,0xddu,0x83u,0xc2u,0x9cu,0x7eu,0x20u,0xa3u,0xfdu,0x1fu,0x41u, 0x9du,0xc3u,0x21u,0x7fu,0xfcu,0xa2u,0x40u,0x1eu,0x5fu,0x01u,0xe3u,0xbdu,0x3eu,0x60u,0x82u,0xdcu, 0x23u,0x7du,0x9fu,0xc1u,0x42u,0x1cu,0xfeu,0xa0u,0xe1u,0xbfu,0x5du,0x03u,0x80u,0xdeu,0x3cu,0x62u, 0xbeu,0xe0u,0x02u,0x5cu,0xdfu,0x81u,0x63u,0x3du,0x7cu,0x22u,0xc0u,0x9eu,0x1du,0x43u,0xa1u,0xffu, 0x46u,0x18u,0xfau,0xa4u,0x27u,0x79u,0x9bu,0xc5u,0x84u,0xdau,0x38u,0x66u,0xe5u,0xbbu,0x59u,0x07u, 0xdbu,0x85u,0x67u,0x39u,0xbau,0xe4u,0x06u,0x58u,0x19u,0x47u,0xa5u,0xfbu,0x78u,0x26u,0xc4u,0x9au, 0x65u,0x3bu,0xd9u,0x87u,0x04u,0x5au,0xb8u,0xe6u,0xa7u,0xf9u,0x1bu,0x45u,0xc6u,0x98u,0x7au,0x24u, 0xf8u,0xa6u,0x44u,0x1au,0x99u,0xc7u,0x25u,0x7bu,0x3au,0x64u,0x86u,0xd8u,0x5bu,0x05u,0xe7u,0xb9u, 0x8cu,0xd2u,0x30u,0x6eu,0xedu,0xb3u,0x51u,0x0fu,0x4eu,0x10u,0xf2u,0xacu,0x2fu,0x71u,0x93u,0xcdu, 0x11u,0x4fu,0xadu,0xf3u,0x70u,0x2eu,0xccu,0x92u,0xd3u,0x8du,0x6fu,0x31u,0xb2u,0xecu,0x0eu,0x50u, 0xafu,0xf1u,0x13u,0x4du,0xceu,0x90u,0x72u,0x2cu,0x6du,0x33u,0xd1u,0x8fu,0x0cu,0x52u,0xb0u,0xeeu, 0x32u,0x6cu,0x8eu,0xd0u,0x53u,0x0du,0xefu,0xb1u,0xf0u,0xaeu,0x4cu,0x12u,0x91u,0xcfu,0x2du,0x73u, 0xcau,0x94u,0x76u,0x28u,0xabu,0xf5u,0x17u,0x49u,0x08u,0x56u,0xb4u,0xeau,0x69u,0x37u,0xd5u,0x8bu, 0x57u,0x09u,0xebu,0xb5u,0x36u,0x68u,0x8au,0xd4u,0x95u,0xcbu,0x29u,0x77u,0xf4u,0xaau,0x48u,0x16u, 0xe9u,0xb7u,0x55u,0x0bu,0x88u,0xd6u,0x34u,0x6au,0x2bu,0x75u,0x97u,0xc9u,0x4au,0x14u,0xf6u,0xa8u, 0x74u,0x2au,0xc8u,0x96u,0x15u,0x4bu,0xa9u,0xf7u,0xb6u,0xe8u,0x0au,0x54u,0xd7u,0x89u,0x6bu,0x35u }; static uint8 Tps929240_CRC(uint8* stream, uint8 len) { uint8 k; uint8 remainder; uint8 tempData; remainder = 0xFF; //assign the initial value 0xFF for (k = 0; k < len; k++) //the first SYNC byte not engage CRC calculation { tempData = remainder ^ stream[k]; remainder = crcArray[tempData]; } // we have to reverse the final remainder to get the CRC value, for example, // if final remainder = 0010 1100, we need to reverse it to 0011 0100 remainder = ((remainder & 0x80) >> 7) + ((remainder & 0x40) >> 5) + ((remainder & 0x20) >> 3) + ((remainder & 0x10) >> 1) + ((remainder & 0x08) << 1) + ((remainder & 0x04) << 3) + ((remainder & 0x02) << 5) + ((remainder & 0x01) << 7); return remainder; } static void test_primitive_unlock(uint8 channel) { ProtocolBuf_t pdu_unlock_0 = { // tcb, transaction control block { 4, // channel 0, // address, broadcasting Prim_Tps929x_WRITE_CTRLGATE_0, // primitive 0, // broadcasting 0, // retransmitAttempt 3, // retransmitLimit UUE_TRANSACTION_DELAY, // transactionDelay UUE_TRANSACTION_TIMEOUT, // transactionTimeout, 1000us TransactionError_NoError, // errorState TransactionState_RequestReady, // transactionState #if (UUE_TRANSACTION_PROFILE == STD_ON) 0, 0, 0, 0 #endif }, { SYNC, // sync WRITE_MODE | BROADCASTING | DATA_LENGTH_1 | 0x0, // control CTRLGATE_ADDR, // register 0x43u, // unlock 1st byte 0xFF, // CRC to be update }, // reqPduBuffer (uint8*)NULL_PTR, // resPduBuffer 5, // reqPduLength 0, // resPduLength }; pdu_unlock_0.reqPduBuffer[pdu_unlock_0.reqPduLength - 1] = Tps929240_CRC(&pdu_unlock_0.reqPduBuffer[1], sizeof(pdu_unlock_0.reqPduLength) - 2); AddPrimitive(&pdu_unlock_0); ProtocolBuf_t pdu_unlock_1 = { // tcb, transaction control block { 4, // channel 0, // address, broadcasting Prim_Tps929x_WRITE_CTRLGATE_1, // primitive 0, // broadcasting 0, // retransmitAttempt 3, // retransmitLimit UUE_TRANSACTION_DELAY, // transactionDelay UUE_TRANSACTION_TIMEOUT, // transactionTimeout, 1000us TransactionError_NoError, // errorState TransactionState_RequestReady, // transactionState #if (UUE_TRANSACTION_PROFILE == STD_ON) 0, 0, 0, 0 #endif }, { SYNC, // sync WRITE_MODE | BROADCASTING | DATA_LENGTH_1 | 0x0, // control CTRLGATE_ADDR, // register 0x4Fu, // unlock 2nd byte 0xFF, // CRC to be update }, // reqPduBuffer (uint8*)NULL_PTR, // resPduBuffer 5, // reqPduLength 0, // resPduLength }; pdu_unlock_1.reqPduBuffer[pdu_unlock_1.reqPduLength - 1] = Tps929240_CRC(&pdu_unlock_1.reqPduBuffer[1], sizeof(pdu_unlock_1.reqPduLength) - 2); AddPrimitive(&pdu_unlock_1); ProtocolBuf_t pdu_unlock_2 = { // tcb, transaction control block { 4, // channel 0, // address, broadcasting Prim_Tps929x_WRITE_CTRLGATE_2, // primitive 0, // broadcasting 0, // retransmitAttempt 3, // retransmitLimit UUE_TRANSACTION_DELAY, // transactionDelay UUE_TRANSACTION_TIMEOUT, // transactionTimeout, 1000us TransactionError_NoError, // errorState TransactionState_RequestReady, // transactionState #if (UUE_TRANSACTION_PROFILE == STD_ON) 0, 0, 0, 0 #endif }, { SYNC, // sync WRITE_MODE | BROADCASTING | DATA_LENGTH_1 | 0x0, // control CTRLGATE_ADDR, // register 0x44u, // unlock 2nd byte 0xFF, // CRC to be update }, // reqPduBuffer (uint8*)NULL_PTR, // resPduBuffer 5, // reqPduLength 0, // resPduLength }; pdu_unlock_2.reqPduBuffer[pdu_unlock_2.reqPduLength - 1] = Tps929240_CRC(&pdu_unlock_2.reqPduBuffer[1], sizeof(pdu_unlock_2.reqPduLength) - 2); AddPrimitive(&pdu_unlock_2); ProtocolBuf_t pdu_unlock_3 = { // tcb, transaction control block { 4, // channel 0, // address, broadcasting Prim_Tps929x_WRITE_CTRLGATE_3, // primitive 0, // broadcasting 0, // retransmitAttempt 3, // retransmitLimit UUE_TRANSACTION_DELAY, // transactionDelay UUE_TRANSACTION_TIMEOUT, // transactionTimeout, 1000us TransactionError_NoError, // errorState TransactionState_RequestReady, // transactionState #if (UUE_TRANSACTION_PROFILE == STD_ON) 0, 0, 0, 0 #endif }, { SYNC, // sync WRITE_MODE | BROADCASTING | DATA_LENGTH_1 | 0x0, // control CTRLGATE_ADDR, // register 0x45u, // unlock 2nd byte 0xFF, // CRC to be update }, // reqPduBuffer (uint8*)NULL_PTR, // resPduBuffer 5, // reqPduLength 0, // resPduLength }; pdu_unlock_3.reqPduBuffer[pdu_unlock_3.reqPduLength - 1] = Tps929240_CRC(&pdu_unlock_3.reqPduBuffer[1], sizeof(pdu_unlock_3.reqPduLength) - 2); AddPrimitive(&pdu_unlock_3); } static void test_primitive_PWM(uint8 channel, uint8 devAddr) { static uint8 resBuf_PWM[] = { 0xee, 0xee }; ProtocolBuf_t pdu_PWM = { // tcb, transaction control block { 4, // channel devAddr, // address, Prim_Tps929x_WRITE_PWM, // primitive 0, // broadcasting 0, // retransmitAttempt 3, // retransmitLimit UUE_TRANSACTION_DELAY, // transactionDelay UUE_TRANSACTION_TIMEOUT, // transactionTimeout, 1000us TransactionError_NoError, // errorState TransactionState_RequestReady, // transactionState #if (UUE_TRANSACTION_PROFILE == STD_ON) 0, 0, 0, 0 #endif }, { SYNC, WRITE_MODE | NON_BROADCASTING | DATA_LENGTH_24, PWMMA0_ADDR, 0xF0, 0xF0, 0xC0, 0xC0, 0xA0, 0xA0, 0x80, 0x80, 0x60, 0x60, 0x50, 0x50, 0x40, 0x40, 0x30, 0x30, 0x20, 0x20, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0xFF, }, // reqPduBuffer resBuf_PWM, // resPduBuffer 28, // reqPduLength sizeof(resBuf_PWM), // resPduLength }; pdu_PWM.reqPduBuffer[1] |= (uint8)(devAddr & 0x0f); pdu_PWM.reqPduBuffer[pdu_PWM.reqPduLength - 1] = Tps929240_CRC(&pdu_PWM.reqPduBuffer[1], pdu_PWM.reqPduLength - 2); AddPrimitive(&pdu_PWM); } static void test_primitive_EnableOutPut(uint8 channel, uint8 devAddr) { static uint8 resBuf_EnableOutput[] = { 0xee, 0xee }; ProtocolBuf_t pdu_EnableOutput = { // tcb, transaction control block { 4, // channel devAddr, // address, Prim_Tps929x_WRITE_OUTEN, // primitive 0, // broadcasting 0, // retransmitAttempt 3, // retransmitLimit UUE_TRANSACTION_DELAY, // transactionDelay UUE_TRANSACTION_TIMEOUT, // transactionTimeout, 1000us TransactionError_NoError, // errorState TransactionState_RequestReady, // transactionState #if (UUE_TRANSACTION_PROFILE == STD_ON) 0, 0, 0, 0 #endif }, { SYNC, WRITE_MODE | NON_BROADCASTING | DATA_LENGTH_4, OUTEN0_ADDR, 0x77, 0x77, 0x77, 0x03, 0xFF, }, // reqPduBuffer resBuf_EnableOutput, // resPduBuffer 8, // reqPduLength sizeof(resBuf_EnableOutput), // resPduLength }; pdu_EnableOutput.reqPduBuffer[1] |= (uint8)(devAddr & 0x0f); pdu_EnableOutput.reqPduBuffer[pdu_EnableOutput.reqPduLength - 1] = Tps929240_CRC(&pdu_EnableOutput.reqPduBuffer[1], pdu_EnableOutput.reqPduLength - 2); AddPrimitive(&pdu_EnableOutput); } static void test_primitive_ReadClearFlags(uint8 channel, uint8 devAddr) { static uint8 resBuf_ReadFlags[17] = { 0xee }; ProtocolBuf_t pdu_ReadFlags = { // tcb, transaction control block { 4, // channel devAddr, // address, Prim_Tps929x_READ_FLAG, // primitive 0, // broadcasting 0, // retransmitAttempt 3, // retransmitLimit UUE_TRANSACTION_DELAY, // transactionDelay UUE_TRANSACTION_TIMEOUT, // transactionTimeout, 1000us TransactionError_NoError, // errorState TransactionState_RequestReady, // transactionState #if (UUE_TRANSACTION_PROFILE == STD_ON) 0, 0, 0, 0 #endif }, { SYNC, READ_MODE | NON_BROADCASTING | DATA_LENGTH_16, FLAG_ERR_ADDR, 0xFF, }, // reqPduBuffer resBuf_ReadFlags, // resPduBuffer 4, // reqPduLength sizeof(resBuf_ReadFlags), // resPduLength }; uint8* reqBuf = pdu_ReadFlags.reqPduBuffer; uint16 reqLen = pdu_ReadFlags.reqPduLength; reqBuf[1] |= (uint8)(devAddr & 0x0f); reqBuf[reqLen - 1] = Tps929240_CRC(&reqBuf[1], reqLen - 2); AddPrimitive(&pdu_ReadFlags); static uint8 resBuf_ClearFlags[2] = { 0xee }; ProtocolBuf_t pdu_ClearFlags = { // tcb, transaction control block { 4, // channel devAddr, // address, Prim_Tps929x_CLEAR_FLAG, // primitive 0, // broadcasting 0, // retransmitAttempt 3, // retransmitLimit UUE_TRANSACTION_DELAY, // transactionDelay UUE_TRANSACTION_TIMEOUT, // transactionTimeout, 1000us TransactionError_NoError, // errorState TransactionState_RequestReady, // transactionState #if (UUE_TRANSACTION_PROFILE == STD_ON) 0, 0, 0, 0 #endif }, { SYNC, WRITE_MODE | NON_BROADCASTING | DATA_LENGTH_1, CLR_ADDR, 0x07, // clear all fault flag, clear POR flag, clear FS flag 0xFF, }, // reqPduBuffer resBuf_ClearFlags, // resPduBuffer 5, // reqPduLength sizeof(resBuf_ClearFlags), // resPduLength }; reqBuf = pdu_ClearFlags.reqPduBuffer; reqLen = pdu_ClearFlags.reqPduLength; reqBuf[1] |= (uint8)(devAddr & 0x0f); reqBuf[reqLen - 1] = Tps929240_CRC(&reqBuf[1], reqLen - 2); AddPrimitive(&pdu_ClearFlags); } // add some test pdu to queue per channel void AddTestPeroidPdu(void) { // bus stress test // it is not tps929240 valid command, for general test only, do not mix with TPS functional pdu #if 0 AddTestPdu0(); AddTestPdu0(); AddTestPdu0(); AddTestPdu0(); AddTestPdu0(); AddTestPdu0(); AddTestPdu0(); AddTestPdu0(); AddTestPdu0(); AddTestPdu0(); AddTestPdu0(); AddTestPdu0(); AddTestPdu0(); AddTestPdu0(); // bus load is about 88% with FIFO depth = 10 #else test_primitive_PWM(4, 5); test_primitive_PWM(4, 6); test_primitive_PWM(4, 7); test_primitive_PWM(4, 13); test_primitive_PWM(4, 14); test_primitive_PWM(4, 15); static uint8 divider = 0; divider++; if ((divider % 5) == 0) { test_primitive_ReadClearFlags(4, 5); } // bus load is about 41,5% with FIFO depth = 10 #endif } // add some test pdu to queue per channel void AddTestRunOncePdu(void) { test_primitive_unlock(4); test_primitive_EnableOutPut(4, 5); test_primitive_EnableOutPut(4, 6); test_primitive_EnableOutPut(4, 7); test_primitive_EnableOutPut(4, 13); test_primitive_EnableOutPut(4, 14); test_primitive_EnableOutPut(4, 15); } #endif