#if defined(CORE5_IS_ASR)
#if defined(__PROC_TC39X__)
group Core5_RAM( ordered, run_addr = mem:mpe:dspr5 )
{
   /* lets pretend that currently there is no near */
   /* thus you won't need the stack safety gap */
   /* start with the stacks */
   group osAllStacksCore5(ordered, contiguous, fill, align=8)
   {
      #define OS_LINK_KERNEL_STACKS
      #include OS_LINK_CORE5_STACKS_LSL
   }
   "osEndOf_Core5Stack" = "_lc_ge_osAllStacksCore5";
   "osEndOf_Core5StackInAlias" = (("_lc_ge_osAllStacksCore5")&~0xF0000000)|0xD0000000;

   group osFarCore5(ordered, contiguous, fill, align=8)
   {
      /* Kernel Variables */
      group osFarKernelCore5
      {
         #define OS_LINK_VAR_KERNEL
         #include OS_LINK_CORE5_LSL
      }
      /* Kernel Barriers */
      group osBarriersFarOnCore5
      {
         #define OS_LINK_KERNEL_BARRIERS
         #include OS_LINK_CORE5_LSL
      }
      /* Kernel Corestatus */
      group osCoreStatusFarOnCore5
      {
         #define OS_LINK_KERNEL_CORESTATUS
         #include OS_LINK_CORE5_LSL
      }
  }
}
#else
  "osEndOf_Core5Stack" = 0x10000000; /* Seems not to be continuous, logically would be 0x20000000,
                                      * but have a look at the datasheet pg. 125 */
#endif
#endif