#if defined(CORE3_IS_ASR)
#if defined(__PROC_TC39X__)
group Core3_RAM( ordered, run_addr = mem:mpe:dspr3 )
{
   /* lets pretend that currently there is no near */
   /* thus you won't need the stack safety gap */
   /* start with the stacks */
   group osAllStacksCore3(ordered, contiguous, fill, align=8)
   {
      #define OS_LINK_KERNEL_STACKS
      #include OS_LINK_CORE3_STACKS_LSL
   }
   "osEndOf_Core3Stack" = "_lc_ge_osAllStacksCore3";
   "osEndOf_Core3StackInAlias" = (("_lc_ge_osAllStacksCore3")&~0xF0000000)|0xD0000000;

   group osFarCore3(ordered, contiguous, fill, align=8)
   {
      /* Kernel Variables */
      group osFarKernelCore3
      {
         #define OS_LINK_VAR_KERNEL
         #include OS_LINK_CORE3_LSL
      }
      /* Kernel Barriers */
      group osBarriersFarOnCore3
      {
         #define OS_LINK_KERNEL_BARRIERS
         #include OS_LINK_CORE3_LSL
      }
      /* Kernel Corestatus */
      group osCoreStatusFarOnCore3
      {
         #define OS_LINK_KERNEL_CORESTATUS
         #include OS_LINK_CORE3_LSL
      }
  }
}
#else
  "osEndOf_Core3Stack" = 0x40000000;
#endif
#endif