/***************************************************************************//**
 * @file     bl_bom.c
 * @brief    This file develop the BOM of bootloader.
 * @version  V1.0.0
 * @date     Nov-2023
 * @author   Marelli SW Team
 *
 * @note
 * Copyright (C) 2023 Marelli Ltd. All rights reserved.
 *
 ******************************************************************************/
#include "bl_bom.h"
#include "regfile_drv.h"

#define FALSE 0
#define TRUE  1
#define Sram_l_start 0x1ffe0000
#define Sram_l_end   0x1fffffff
#define Flsdrv_ram_start 0x20000000
#define Flsdrv_ram_end   0x200007ff
#define Commonnoinit_ram_start 0x20000800
#define Commonnoinit_ram_end   0x2000098f
#define Fbl_ram_start 0x20000990
#define Fbl_ram_end   0x2001FFFF

#define Mcu_WarmReset 1U

extern uint32_t __REPROG_FLAG;

static srmc_reg_t* const srmcRegPtr = (srmc_reg_t*)SRMC_BASE_ADDR;         /* SRMC Register */

bool Boot_ChkExtReProgFlag(void)
{
    bool boAppEnterIntoFBL = FALSE;
    if((*(uint32_t*)&__REPROG_FLAG == 0x55AA55AA))
    {
        boAppEnterIntoFBL = TRUE;
    }
    return boAppEnterIntoFBL;
}

FlagStatus_t ChkFLU_JumpTo_FBLFlag(void)
{
    uint32_t flag;
    REGFILE_ReadByRegId(BL_FLU_JUMPTO_FBL_FLAG_REGFILE_ID, &flag);
    if(flag == BL_FLU_JUMPTO_FBL_FLAG_VALUE)
    {
        return SET;
    }
    return RESET;
}

ResultStatus_t ClearFLU_JumpTo_FBLFlag(void)
{
    uint32_t flag;
    flag = BL_FLU_JUMPTO_FBL_FLAG_CLEAR;
    if(ERR == REGFILE_WriteByRegId(BL_FLU_JUMPTO_FBL_FLAG_REGFILE_ID, &flag))
    {
        return ERR;
    }
    return SUCC;
}


void init_data_ram(void)
{
    
    uint32_t * sram_l_start;/*0x1ffe0000~0x1fffffff,length 0x20000 */
    uint32_t * flsdrv_ram_start;/*0x20000000~0x200007FF,length 0x800 */
    uint32_t * commonnoinit_ram_start;/*0x20000800~0x2000098F,length 0x190 */
    uint32_t * fbl_ram_start;/*0x20000990~0x2001FFFF,length 0x1F670 */
    uint32_t * sram_l_end, * flsdrv_ram_end;
    uint32_t * commonnoinit_ram_end, * fbl_ram_end;
    sram_l_start           = (uint32_t *)Sram_l_start;
    sram_l_end             = (uint32_t *)Sram_l_end;
    flsdrv_ram_start       = (uint32_t *)Flsdrv_ram_start;
    flsdrv_ram_end         = (uint32_t *)Flsdrv_ram_end;
    commonnoinit_ram_start = (uint32_t *)Commonnoinit_ram_start;
    commonnoinit_ram_end   = (uint32_t *)Commonnoinit_ram_end;
    fbl_ram_start          = (uint32_t *)Fbl_ram_start;
    fbl_ram_end            = (uint32_t *)Fbl_ram_end;
    /* Clear the zero-initialized data section: SRAM_L */
    while(sram_l_start < sram_l_end)
    {
        *sram_l_start = 0;
         sram_l_start++;
    }
    /* Clear the zero-initialized data section: Flash Drv */
    while(flsdrv_ram_start < flsdrv_ram_end)
    {
        *flsdrv_ram_start = 0;
         flsdrv_ram_start++;
    }
    /* Clear the no-initialized data section if system reset is cold reset*/
    if(Mcu_WarmReset == srmcRegPtr->SRMC_SRS.SW)
    {
        /*When MCU is Warm Reset, nothing to to and no need to init noinit RAM*/
    }
    else
    {
        /*Current MCU is Cold reset, reinit noinit RAM to prevent SRAM ECC Hard Fault Exception*/
        while(commonnoinit_ram_start < commonnoinit_ram_end)
        {
           *commonnoinit_ram_start = 0;
           commonnoinit_ram_start++;
        }
    }
    /* Clear the zero-initialized data section:partial SRAM_U which used by FBL system*/
    while(fbl_ram_start < fbl_ram_end)
    {
        *fbl_ram_start = 0;
         fbl_ram_start++;
    }
}