C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 1 C51 COMPILER V9.60.7.0, COMPILATION OF MODULE SC92F8003_SSI OBJECT MODULE PLACED IN .\Objects\sc92f8003_ssi.obj COMPILER INVOKED BY: d:\Keil\C51\BIN\C51.EXE SC92F8003_Lib\src\sc92f8003_ssi.c OPTIMIZE(8,SPEED) BROWSE INCDIR(.\Src;.\T -ask;.\Task\cpu_port\S92F8003A;.\Task\cfg;.\Task\pt_thread;.\SC92F8003_Lib\Inc) DEBUG OBJECTEXTEND CODE LISTINCLUDE SYMBO -LS PRINT(.\Listings\sc92f8003_ssi.lst) PREPRINT(.\Listings\sc92f8003_ssi.i) OBJECT(.\Objects\sc92f8003_ssi.obj) line level source 1 //************************************************************ 2 // Copyright (c) ÉîÛÚÊÐÈüԪ΢µç×ÓÓÐÏÞ¹«Ë¾ 3 // ÎļþÃû³Æ : sc92f8003_ssi.c 4 // ×÷Õß : 5 // Ä£¿é¹¦ÄÜ : SSI¹Ì¼þ¿âº¯ÊýCÎļþ 6 // ¾Ö²¿º¯ÊýÁбí: 7 // ×îºó¸üÕýÈÕÆÚ: 2018/9/4 8 // °æ±¾ : V1.0 9 // ˵Ã÷ £º 10 //************************************************************* 11 12 #include "sc92f8003_ssi.h" 1 =1 //************************************************************ 2 =1 // Copyright (c) ÉîÛÚÊÐÈüԪ΢µç×ÓÓÐÏÞ¹«Ë¾ 3 =1 // ÎļþÃû³Æ : sc92f8003_ssi.h 4 =1 // ×÷Õß : 5 =1 // Ä£¿é¹¦ÄÜ : SSI¹Ì¼þ¿âº¯ÊýÍ·Îļþ 6 =1 // ¾Ö²¿º¯ÊýÁбí: 7 =1 // ×îºó¸üÕýÈÕÆÚ: 2018/9/4 8 =1 // °æ±¾ : V1.0 9 =1 // ˵Ã÷ £º 10 =1 //************************************************************* 11 =1 12 =1 #ifndef __SC92F8003_SSI_H 13 =1 #define __SC92F8003_SSI_H 14 =1 15 =1 #include "sc92f8003.h" 1 =2 #ifndef _SC92F8003_H 2 =2 #define _SC92F8003_H 3 =2 4 =2 #include "SC92F8003_C.H" 1 =3 /*-------------------------------------------------------------------------- 2 =3 SC92F8003_C.H 3 =3 4 =3 C Header file for SC92F8003 microcontroller. 5 =3 Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. 6 =3 All rights reserved. 7 =3 ÉîÛÚÊÐÈüԪ΢µç×ÓÓÐÏÞ¹«Ë¾ 8 =3 °æ±¾ºÅ: V1.0 9 =3 ÈÕÆÚ: 2018.05.02 10 =3 --------------------------------------------------------------------------*/ 11 =3 #ifndef _SC92F8003_H_ 12 =3 #define _SC92F8003_H_ 13 =3 14 =3 /* ------------------- ×ֽڼĴæÆ÷-------------------- */ 15 =3 ///*CPU*/ 16 =3 sfr ACC = 0xE0; //ÀÛ¼ÓÆ÷£Á 17 =3 sfr B = 0xF0; //ͨÓüĴæÆ÷B 18 =3 sfr PSW = 0xD0; //³ÌÐò״̬×Ö 19 =3 sfr DPH = 0x83; //Êý¾ÝÖ¸Õë¸ß8λ 20 =3 sfr DPL = 0x82; //Êý¾ÝÖ¸ÕëµÍ8λ 21 =3 sfr SP = 0x81; //¶ÑÕ»Ö¸Õë 22 =3 C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 2 23 =3 24 =3 /*system*/ 25 =3 sfr PCON = 0x87; //µçÔ´¹ÜÀí¿ØÖƼĴæÆ÷ 26 =3 27 =3 /*interrupt*/ 28 =3 sfr IP1 = 0XB9; //ÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷1 29 =3 sfr IP = 0xB8; //ÖжÏÓÅÏÈȨ¿ØÖƼĴæÆ÷ 30 =3 sfr IE = 0xA8; //ÖжϿØÖƼĴæÆ÷ 31 =3 sfr IE1 = 0XA9; //ÖжϿØÖƼĴæÆ÷1 32 =3 33 =3 /*PORT*/ 34 =3 sfr P2PH = 0xA2; //P2¿Úģʽ¿ØÖƼĴæÆ÷ 35 =3 sfr P2CON = 0xA1; //P2¿Úģʽ¿ØÖƼĴæÆ÷ 36 =3 sfr P2 = 0xA0; //P2¿ÚÊý¾Ý¼Ä´æÆ÷ 37 =3 sfr P1PH = 0x92; //P1¿Úģʽ¿ØÖƼĴæÆ÷ 38 =3 sfr P1CON = 0x91; //P1¿Úģʽ¿ØÖƼĴæÆ÷ 39 =3 sfr P1 = 0x90; //P1¿ÚÊý¾Ý¼Ä´æÆ÷ 40 =3 sfr P0PH = 0x9B; //P0¿Úģʽ¿ØÖƼĴæÆ÷ 41 =3 sfr P0CON = 0x9A; //P0¿Úģʽ¿ØÖƼĴæÆ÷ 42 =3 sfr P0 = 0x80; //P0¿ÚÊý¾Ý¼Ä´æÆ÷ 43 =3 44 =3 /*TIMER*/ 45 =3 sfr TMCON = 0x8E; //¶¨Ê±Æ÷ƵÂÊ¿ØÖƼĴæÆ÷ 46 =3 sfr TH1 = 0x8D; //¶¨Ê±Æ÷1¸ß8λ 47 =3 sfr TH0 = 0x8C; //¶¨Ê±Æ÷0¸ß8λ 48 =3 sfr TL1 = 0x8B; //¶¨Ê±Æ÷1µÍ8λ 49 =3 sfr TL0 = 0x8A; //¶¨Ê±Æ÷0µÍ8λ 50 =3 sfr TMOD = 0x89; //¶¨Ê±Æ÷¹¤×÷ģʽ¼Ä´æÆ÷ 51 =3 sfr TCON = 0x88; //¶¨Ê±Æ÷¿ØÖƼĴæÆ÷ 52 =3 sfr T2CON = 0xC8; //¶¨Ê±Æ÷2¿ØÖƼĴæÆ÷ 53 =3 sfr T2MOD = 0xC9; //¶¨Ê±Æ÷2¹¤×÷ģʽ¼Ä´æÆ÷ 54 =3 sfr RCAP2L = 0xCA; //¶¨Ê±Æ÷2ÖØÔØ/²¶×½µÍ8λ 55 =3 sfr RCAP2H = 0xCB; //¶¨Ê±Æ÷2ÖØÔØ/²¶×½¸ß8λ 56 =3 sfr TL2 = 0xCC; //¶¨Ê±Æ÷2µÍ8λ 57 =3 sfr TH2 = 0xCD; //¶¨Ê±Æ÷2¸ß8λ 58 =3 59 =3 60 =3 /*ADC*/ 61 =3 sfr ADCCFG1 = 0xAA; //ADC¹¦ÄÜÅäÖüĴæÆ÷0 62 =3 sfr ADCCFG0 = 0xAB; //ADC¹¦ÄÜÅäÖüĴæÆ÷1 63 =3 sfr ADCCON = 0XAD; //ADC¿ØÖƼĴæÆ÷ 64 =3 sfr ADCVL = 0xAE; //ADC ½á¹û¼Ä´æÆ÷ 65 =3 sfr ADCVH = 0xAF; //ADC ½á¹û¼Ä´æÆ÷ 66 =3 67 =3 /*PWM*/ 68 =3 sfr PWMCFG = 0xD1; //PWMÉèÖüĴæÆ÷ 69 =3 sfr PWMCON0 = 0xD2; //PWM¿ØÖƼĴæÆ÷ 70 =3 sfr PWMPRD = 0xD3; //PWMÖÜÆÚÉèÖüĴæÆ÷ 71 =3 sfr PWMDTYA = 0xD4; //PWMÕ¼¿Õ±ÈÉèÖüĴæÆ÷A 72 =3 sfr PWMDTY0 = 0xD5; //PWM0ÉèÖüĴæÆ÷ 73 =3 sfr PWMDTY1 = 0xD6; //PWM1ÉèÖüĴæÆ÷ 74 =3 sfr PWMDTY2 = 0xD7; //PWM2ÉèÖüĴæÆ÷ 75 =3 sfr PWMCON1 = 0xDA; //PWM¿ØÖƼĴæÆ÷ 76 =3 sfr PWMDTYB = 0xDB; //PWMÕ¼¿Õ±ÈÉèÖüĴæÆ÷B 77 =3 sfr PWMDTY3 = 0xDC; //PWM3ÉèÖüĴæÆ÷ 78 =3 sfr PWMDTY4 = 0xDD; //PWM4ÉèÖüĴæÆ÷ 79 =3 sfr PWMDTY5 = 0xDE; //PWM5ÉèÖüĴæÆ÷ 80 =3 sfr PWMDTY6 = 0xDF; //PWM6ÉèÖüĴæÆ÷ 81 =3 82 =3 83 =3 // 84 =3 ///*WatchDog*/ C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 3 85 =3 sfr BTMCON = 0XCE; //µÍƵ¶¨Ê±Æ÷¿ØÖƼĴæÆ÷ 86 =3 sfr WDTCON = 0xCF; //WDT¿ØÖƼĴæÆ÷ 87 =3 88 =3 89 =3 sfr OTCON = 0X8F; //Êä³ö¿ØÖƼĴæÆ÷ 90 =3 91 =3 /*INT*/ 92 =3 sfr INT0F = 0XBA; //INT0 ϽµÑØÖжϿØÖƼĴæÆ÷ 93 =3 sfr INT0R = 0XBB; //INT0 ÉϽµÑØÖжϿØÖƼĴæÆ÷ 94 =3 sfr INT1F = 0XBC; //INT1 ϽµÑØÖжϿØÖƼĴæÆ÷ 95 =3 sfr INT1R = 0XBD; //INT1 ÉϽµÑØÖжϿØÖƼĴæÆ÷ 96 =3 sfr INT2F = 0XC6; //INT2 ϽµÑØÖжϿØÖƼĴæÆ÷ 97 =3 sfr INT2R = 0XC7; //INT2 ÉϽµÑØÖжϿØÖƼĴæÆ÷ 98 =3 99 =3 /*IAP */ 100 =3 sfr IAPCTL = 0xF6; //IAP¿ØÖƼĴæÆ÷ 101 =3 sfr IAPDAT = 0xF5; //IAPÊý¾Ý¼Ä´æÆ÷ 102 =3 sfr IAPADE = 0xF4; //IAPÀ©Õ¹µØÖ·¼Ä´æÆ÷ 103 =3 sfr IAPADH = 0xF3; //IAPдÈëµØÖ·¸ßλ¼Ä´æÆ÷ 104 =3 sfr IAPADL = 0xF2; //IAPдÈëµØÖ·µÍ8λ¼Ä´æÆ÷ 105 =3 sfr IAPKEY = 0xF1; //IAP±£»¤¼Ä´æÆ÷ 106 =3 107 =3 /*uart0*/ 108 =3 sfr SCON = 0X98; //uart¿ØÖƼĴæÆ÷ 109 =3 sfr SBUF = 0X99; //uart0Êý¾Ý¼Ä´æÆ÷ 110 =3 111 =3 /*ÈýºÏÒ»*/ 112 =3 sfr SSCON0 = 0X9D; //SSI¿ØÖƼĴæÆ÷0 113 =3 sfr SSCON1 = 0X9E; //SSI¿ØÖƼĴæÆ÷1 114 =3 sfr SSCON2 = 0X95; //SSI¿ØÖƼĴæÆ÷2 115 =3 sfr SSDAT = 0X9F; //SSIÊý¾Ý¼Ä´æÆ÷ 116 =3 117 =3 sfr OPINX = 0XFE; 118 =3 sfr OPREG = 0XFF; 119 =3 120 =3 /*Check Sum*/ 121 =3 sfr CHKSUML = 0XFC; //Check Sum½á¹û¼Ä´æÆ÷µÍλ 122 =3 sfr CHKSUMH = 0XFD; //Check Sum½á¹û¼Ä´æÆ÷¸ßλ 123 =3 124 =3 sfr OPERCON = 0xEF; //ÔËËã¿ØÖƼĴæÆ÷ 125 =3 126 =3 ///* ------------------- λ¼Ä´æÆ÷-------------------- */ 127 =3 /*PSW*/ 128 =3 sbit CY = PSW^7; //±ê־λ 0:¼Ó·¨ÔËËã×î¸ßλÎÞ½ø룬»òÕß¼õ·¨ÔËËã×î¸ßλÎÞ½èλʱ 1:¼Ó·¨ÔËËã×î¸ßλÓнø -룬»òÕß¼õ·¨ÔËËã×î¸ßλÓнèλʱ 129 =3 sbit AC = PSW^6; //½øλ¸¨Öú±ê־λ 0:ÎÞ½èλ¡¢½øλ 1:¼Ó·¨ÔËËãʱÔÚbit3λÓнø룬»ò¼õ·¨ÔËËãÔÚbit3λÓн -èλʱ 130 =3 sbit F0 = PSW^5; //Óû§±ê־λ 131 =3 sbit RS1 = PSW^4; //¹¤×÷¼Ä´æÆ÷×éÑ¡Ôñλ 132 =3 sbit RS0 = PSW^3; //¹¤×÷¼Ä´æÆ÷×éÑ¡Ôñλ 133 =3 sbit OV = PSW^2; //Òç³ö±ê־λ 134 =3 sbit F1 = PSW^1; //F1±êÖ¾ 135 =3 sbit P = PSW^0; //Ææż±ê־λ 0:ACCÖÐ1µÄ¸öÊýΪżÊý£¨°üÀ¨0¸ö£© 1:ACCÖÐ1µÄ¸öÊýΪÆæÊý 136 =3 137 =3 /*T2CON*/ 138 =3 sbit TF2 = T2CON^7; 139 =3 sbit EXF2 = T2CON^6; 140 =3 sbit RCLK = T2CON^5; 141 =3 sbit TCLK = T2CON^4; 142 =3 sbit EXEN2 = T2CON^3; 143 =3 sbit TR2 = T2CON^2; 144 =3 sbit T2 = T2CON^1; C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 4 145 =3 sbit CP = T2CON^0; 146 =3 147 =3 148 =3 /*IP*/ 149 =3 sbit IPADC = IP^6; //ADCÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 ADCµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 ADCµÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß¡ -± 150 =3 sbit IPT2 = IP^5; //PWMÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 PWMµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 PWM µÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß -¡± 151 =3 sbit IPUART = IP^4; //SIFÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 SIFµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 SIFµÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß¡ -± 152 =3 sbit IPT1 = IP^3; //Timer1ÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 Timer 1µÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 Timer 1µÄÖжÏÓÅÏÈÈ -¨ÊÇ ¡°¸ß¡± 153 =3 sbit IPINT1 = IP^2; //32K Base TimerÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 32KµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 32KµÄÖжÏÓÅ -ÏÈȨÊÇ ¡°¸ß¡± 154 =3 sbit IPT0 = IP^1; //Timer0ÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 Timer 0µÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 Timer 0µÄÖжÏÓÅÏÈÈ -¨ÊÇ ¡°¸ß¡± 155 =3 sbit IPINT0 = IP^0; 156 =3 157 =3 /*IE*/ 158 =3 sbit EA = IE^7; //ÖжÏʹÄܵÄ×Ü¿ØÖÆ 0:¹Ø±ÕËùÓеÄÖÐ¶Ï 1:´ò¿ªËùÓеÄÖÐ¶Ï 159 =3 sbit EADC = IE^6; //ADCÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕADCÖÐ¶Ï 1:´ò¿ªADCÖÐ¶Ï 160 =3 sbit ET2 = IE^5; //PWMÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕPWMÖÐ¶Ï 1:´ò¿ªPWMÖÐ¶Ï 161 =3 sbit EUART = IE^4; //UARTÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕSIFÖÐ¶Ï 1:´ò¿ªSIFÖÐ¶Ï 162 =3 sbit ET1 = IE^3; //Timer1ÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTIMER1ÖÐ¶Ï 1:´ò¿ªTIMER1ÖÐ¶Ï 163 =3 sbit EINT1 = IE^2; //32K Base TimerÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±Õ32KÖÐ¶Ï 1:´ò¿ª32KÖÐ¶Ï 164 =3 sbit ET0 = IE^1; //Timer0ÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTIMER0ÖÐ¶Ï 1:´ò¿ªTIMER0ÖÐ¶Ï 165 =3 sbit EINT0 = IE^0; //TouchKeyµÄÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTouchKeyÖÐ¶Ï 1:´ò¿ªTouchKeyÖÐ¶Ï 166 =3 167 =3 /*TCON*/ 168 =3 sbit TF1 = TCON^7; //T1Òç³öÖжÏÇëÇó±ê־λ T1²úÉúÒç³ö£¬·¢ÉúÖжÏʱ£¬Ó²¼þ½«TF1ÖÃΪ¡°1¡±£¬ÉêÇëÖжϣ¬CPU -ÏìӦʱ£¬Ó²¼þÇå¡°0¡±¡£ 169 =3 sbit TR1 = TCON^6; //¶¨Ê±Æ÷T1µÄÔËÐпØÖÆλ 0:Timer1½ûÖ¹¼ÆÊý 1:Timer1¿ªÊ¼¼ÆÊý 170 =3 sbit TF0 = TCON^5; //T0Òç³öÖжÏÇëÇó±ê־λ T0²úÉúÒç³ö£¬·¢ÉúÖжÏʱ£¬Ó²¼þ½«TF0ÖÃΪ¡°1¡±£¬ÉêÇëÖжϣ¬CPU -ÏìӦʱ£¬Ó²¼þÇå¡°0¡±¡£ 171 =3 sbit TR0 = TCON^4; //¶¨Ê±Æ÷T0µÄÔËÐпØÖÆλ 0:Timer0½ûÖ¹¼ÆÊý 1:Timer0¿ªÊ¼¼ÆÊý 172 =3 173 =3 /*SCON*/ 174 =3 sbit SM0 = SCON^7; 175 =3 sbit SM1 = SCON^6; 176 =3 sbit SM2 = SCON^5; 177 =3 sbit REN = SCON^4; 178 =3 sbit TB8 = SCON^3; 179 =3 sbit RB8 = SCON^2; 180 =3 sbit TI = SCON^1; 181 =3 sbit RI = SCON^0; 182 =3 183 =3 /* P0 */ 184 =3 sbit P01 = P0^1; 185 =3 sbit P00 = P0^0; 186 =3 187 =3 /* P1 */ 188 =3 sbit P17 = P1^7; 189 =3 sbit P16 = P1^6; 190 =3 sbit P15 = P1^5; 191 =3 sbit P14 = P1^4; 192 =3 sbit P13 = P1^3; 193 =3 sbit P12 = P1^2; 194 =3 sbit P11 = P1^1; 195 =3 sbit P10 = P1^0; 196 =3 197 =3 /* P2 */ 198 =3 sbit P27 = P2^7; C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 5 199 =3 sbit P26 = P2^6; 200 =3 sbit P25 = P2^5; 201 =3 sbit P24 = P2^4; 202 =3 sbit P23 = P2^3; 203 =3 sbit P22 = P2^2; 204 =3 sbit P21 = P2^1; 205 =3 sbit P20 = P2^0; 206 =3 207 =3 #endif 5 =2 6 =2 #define enableInterrupts() EA=1 /** ¿ªÆô×ÜÖÐ¶Ï **/ 7 =2 #define disableInterrupts() EA=0 /** ¹Ø±Õ×ÜÖÐ¶Ï **/ 8 =2 9 =2 #define __I volatile const /*!< defines 'read only' permissions */ 10 =2 #define __O volatile /*!< defines 'write only' permissions */ 11 =2 #define __IO volatile /*!< defines 'read / write' permissions */ 12 =2 13 =2 /*!< Signed integer types */ 14 =2 typedef signed char int8_t; 15 =2 typedef signed short int16_t; 16 =2 typedef signed long int32_t; 17 =2 18 =2 /*!< Unsigned integer types */ 19 =2 typedef unsigned char uint8_t; 20 =2 typedef unsigned short uint16_t; 21 =2 typedef unsigned long uint32_t; 22 =2 23 =2 typedef int32_t s32; 24 =2 typedef int16_t s16; 25 =2 typedef int8_t s8; 26 =2 27 =2 typedef uint32_t u32; 28 =2 typedef uint16_t u16; 29 =2 typedef uint8_t u8; 30 =2 31 =2 32 =2 typedef enum {FALSE = 0, TRUE = !FALSE} bool; 33 =2 34 =2 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus; 35 =2 36 =2 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 37 =2 38 =2 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; 39 =2 40 =2 typedef enum {LOW = 0, HIGH = !LOW} PriorityStatus; 41 =2 42 =2 #endif 16 =1 17 =1 typedef enum { 18 =1 SSI_PinSelection_P10P27P26 = (uint8_t)0x00, //SSI¹²ÓÃÒý½ÅΪP10£¬P27£¬P26 19 =1 SSI_PinSelection_P21P22P23 = (uint8_t)0x20 //SSI¹²ÓÃÒý½ÅΪP21£¬P22£¬P23 20 =1 } SSI_PinSelection_TypeDef; 21 =1 22 =1 typedef enum { 23 =1 SPI_FIRSTBIT_MSB = (uint8_t)0x00, //MSBÓÅÏÈ·¢ËÍ 24 =1 SPI_FIRSTBIT_LSB = (uint8_t)0x04 //LSBÓÅÏÈ·¢ËÍ 25 =1 } SPI_FirstBit_TypeDef; 26 =1 27 =1 typedef enum { 28 =1 SPI_BAUDRATEPRESCALER_4 = (uint8_t)0x00, //SPIʱÖÓËÙÂÊΪFsys/4 29 =1 SPI_BAUDRATEPRESCALER_8 = (uint8_t)0x01, //SPIʱÖÓËÙÂÊΪFsys/8 30 =1 SPI_BAUDRATEPRESCALER_16 = (uint8_t)0x02, //SPIʱÖÓËÙÂÊΪFsys/16 C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 6 31 =1 SPI_BAUDRATEPRESCALER_32 = (uint8_t)0x03, //SPIʱÖÓËÙÂÊΪFsys/32 32 =1 SPI_BAUDRATEPRESCALER_64 = (uint8_t)0x04, //SPIʱÖÓËÙÂÊΪFsys/64 33 =1 SPI_BAUDRATEPRESCALER_128 = (uint8_t)0x05, //SPIʱÖÓËÙÂÊΪFsys/128 34 =1 SPI_BAUDRATEPRESCALER_256 = (uint8_t)0x06, //SPIʱÖÓËÙÂÊΪFsys/256 35 =1 SPI_BAUDRATEPRESCALER_512 = (uint8_t)0x07 //SPIʱÖÓËÙÂÊΪFsys/512 36 =1 } SPI_BaudRatePrescaler_TypeDef; 37 =1 38 =1 typedef enum { 39 =1 SPI_MODE_MASTER = (uint8_t)0x20, //SPIΪÖ÷É豸 40 =1 SPI_MODE_SLAVE = (uint8_t)0x00 //SPIΪ´ÓÉ豸 41 =1 } SPI_Mode_TypeDef; 42 =1 43 =1 typedef enum { 44 =1 SPI_CLOCKPOLARITY_LOW = (uint8_t)0x00, //SCKÔÚ¿ÕÏÐ״̬ÏÂΪµÍµçƽ 45 =1 SPI_CLOCKPOLARITY_HIGH = (uint8_t)0x10 //SCKÔÚ¿ÕÏÐ״̬ÏÂΪ¸ßµçƽ 46 =1 } SPI_ClockPolarity_TypeDef; 47 =1 48 =1 typedef enum { 49 =1 SPI_CLOCKPHASE_1EDGE = (uint8_t)0x00, //SCKµÄµÚÒ»Ñزɼ¯Êý¾Ý 50 =1 SPI_CLOCKPHASE_2EDGE = (uint8_t)0x08 //SCKµÄµÚ¶þÑزɼ¯Êý¾Ý 51 =1 } SPI_ClockPhase_TypeDef; 52 =1 53 =1 typedef enum { 54 =1 SPI_TXE_DISINT = (uint8_t)0x00, //TXEΪ0ʱ²»ÔÊÐí·¢ËÍÖÐ¶Ï 55 =1 SPI_TXE_ENINT = (uint8_t)0x01 //TXEΪ1ʱÔÊÐí·¢ËÍÖÐ¶Ï 56 =1 } SPI_TXE_INT_TypeDef; 57 =1 58 =1 59 =1 typedef enum { 60 =1 UART1_Mode_10B = 0X00, //UART1ÉèÖÃΪ10λģʽ 61 =1 UART1_Mode_11B = 0X80 //UART1ÉèÖÃΪ11λģʽ 62 =1 } UART1_Mode_TypeDef; 63 =1 64 =1 typedef enum { 65 =1 UART1_RX_ENABLE = 0X10, //UART1ÔÊÐí½ÓÊÕ 66 =1 UART1_RX_DISABLE = 0X00 //UART1½ûÖ¹½ÓÊÕ 67 =1 } UART1_RX_TypeDef; 68 =1 69 =1 typedef enum { 70 =1 SPI_FLAG_SPIF = (uint8_t)0x80, //SPIÊý¾Ý´«Ëͱê־λSPIF 71 =1 SPI_FLAG_WCOL = (uint8_t)0x40, //SPIдÈë³åÍ»±ê־λWCOL 72 =1 SPI_FLAG_TXE = (uint8_t)0x08, //SPI·¢ËÍ»º´æÆ÷¿Õ±êÖ¾TXE 73 =1 TWI_FLAG_TWIF = (uint8_t)0x40, //TWIÖжϱê־λTWIF 74 =1 TWI_FLAG_GCA = (uint8_t)0x10, //TWIͨÓõØÖ·ÏìÓ¦±ê־λGCA 75 =1 UART1_FLAG_TI = (uint8_t)0x02, //UART1·¢ËÍÖжϱê־λTI 76 =1 UART1_FLAG_RI = (uint8_t)0x01 //UART1½ÓÊÕÖжϱê־λRI 77 =1 } SSI_Flag_TypeDef; 78 =1 79 =1 void SSI_DeInit(void); 80 =1 void SSI_PinSelection(SSI_PinSelection_TypeDef PinSeletion); 81 =1 void SSI_SPI_Init(SPI_FirstBit_TypeDef FirstBit,SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler,SPI_Mode_T -ypeDef Mode,SPI_ClockPolarity_TypeDef ClockPolarity,SPI_ClockPhase_TypeDef ClockPhase,SPI_TXE_INT_TypeDef SPI_TXE_INT); 82 =1 void SSI_SPI_Cmd(FunctionalState NewState); 83 =1 void SSI_SPI_SendData(uint8_t Data); 84 =1 uint8_t SSI_SPI_ReceiveData(void); 85 =1 void SSI_TWI_Init(uint8_t TWI_Address); 86 =1 void SSI_TWI_AcknowledgeConfig(FunctionalState NewState); 87 =1 void SSI_TWI_GeneralCallCmd(FunctionalState NewState); 88 =1 void SSI_TWI_Cmd(FunctionalState NewState); 89 =1 void SSI_TWI_SendData(uint8_t Data); 90 =1 uint8_t SSI_TWI_ReceiveData(void); 91 =1 void SSI_UART1_Init(uint32_t UART1Fsys, uint32_t BaudRate, UART1_Mode_TypeDef Mode, UART1_RX_TypeDef RxMod C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 7 -e); 92 =1 void SSI_UART1_SendData8(uint8_t Data); 93 =1 uint8_t SSI_UART1_ReceiveData8(void); 94 =1 void SSI_UART1_SendData9(uint16_t Data); 95 =1 uint16_t SSI_UART1_ReceiveData9(void); 96 =1 void SSI_ITConfig(FunctionalState NewState, PriorityStatus Priority); 97 =1 FlagStatus SSI_GetFlagStatus(SSI_Flag_TypeDef SSI_FLAG); 98 =1 void SSI_ClearFlag(SSI_Flag_TypeDef SSI_FLAG); 99 =1 100 =1 #endif 101 =1 102 =1 /******************* (C) COPYRIGHT 2018 SinOne Microelectronics *****END OF FILE****/ 13 14 /************************************************** 15 *º¯ÊýÃû³Æ£ºvoid SSI_DeInit(void) 16 *º¯Êý¹¦ÄÜ£ºSSIÏà¹Ø¼Ä´æÆ÷¸´Î»ÖÁȱʡֵ 17 *Èë¿Ú²ÎÊý£ºvoid 18 *³ö¿Ú²ÎÊý£ºvoid 19 **************************************************/ 20 void SSI_DeInit(void) 21 { 22 1 OTCON &= 0X1F; 23 1 SSCON0 = 0X00; 24 1 SSCON1 = 0X00; 25 1 SSCON2 = 0X00; 26 1 SSDAT = 0X00; 27 1 IE1 &= (~0X01); 28 1 IP1 &= (~0X01); 29 1 } 30 31 /************************************************** 32 *º¯ÊýÃû³Æ£ºSSI_PinSelection(SSI_PinSelection_TypeDef PinSeletion) 33 *º¯Êý¹¦ÄÜ£ºSSIÒý½ÅÑ¡Ôñ 34 *Èë¿Ú²ÎÊý£ºPinSeletion Ñ¡ÔñSSIÒý½ÅΪP10P27P26»òP21P22P23 35 *³ö¿Ú²ÎÊý£ºvoid 36 **************************************************/ 37 void SSI_PinSelection(SSI_PinSelection_TypeDef PinSeletion) 38 { 39 1 OTCON = OTCON & 0XDF | PinSeletion; 40 1 } 41 42 /************************************************** 43 *º¯ÊýÃû³Æ£ºvoid SSI_SPI_Init(SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescale -r,SPI_Mode_TypeDef Mode, 44 SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase,SPI_TXE_INT_TypeDef SPI -_TXE_INT) 45 *º¯Êý¹¦ÄÜ£ºSPI³õʼ»¯ÅäÖú¯Êý 46 *Èë¿Ú²ÎÊý£ºFirstBit ÓÅÏÈ´«ËÍλѡÔñ£¨MSB/LSB£© 47 BaudRatePrescaler SPIʱÖÓƵÂÊÑ¡Ôñ 48 Mode SPI¹¤×÷ģʽѡÔñ 49 ClockPolarity SPIʱÖÓ¼«ÐÔÑ¡Ôñ 50 ClockPhase SPIʱÖÓÏàλѡÔñ 51 SPI_TXE_INT ·¢ËÍ»º´æÆ÷ÖжÏÔÊÐíÑ¡Ôñ 52 *³ö¿Ú²ÎÊý£ºvoid 53 **************************************************/ 54 void SSI_SPI_Init(SPI_FirstBit_TypeDef FirstBit, 55 SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, 56 SPI_Mode_TypeDef Mode, 57 SPI_ClockPolarity_TypeDef ClockPolarity, 58 SPI_ClockPhase_TypeDef ClockPhase, 59 SPI_TXE_INT_TypeDef SPI_TXE_INT) 60 { C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 8 61 1 OTCON = (OTCON & 0X3F) | 0X40; 62 1 SSCON1 = SSCON1 & (~0X05) | FirstBit | SPI_TXE_INT; 63 1 SSCON0 = SSCON0 & 0X80 | BaudRatePrescaler | Mode | ClockPolarity | ClockPhase; 64 1 } 65 66 /***************************************************** 67 *º¯ÊýÃû³Æ£ºvoid SSI_SPI_Cmd(FunctionalState NewState) 68 *º¯Êý¹¦ÄÜ£ºSPI¹¦ÄÜ¿ª¹Øº¯Êý 69 *Èë¿Ú²ÎÊý£ºFunctionalState NewState ¹¦ÄÜÆô¶¯/¹Ø±ÕÑ¡Ôñ 70 *³ö¿Ú²ÎÊý£ºvoid 71 *****************************************************/ 72 void SSI_SPI_Cmd(FunctionalState NewState) 73 { 74 1 if(NewState != DISABLE) 75 1 { 76 2 SSCON0 |= 0X80; 77 2 } 78 1 else 79 1 { 80 2 SSCON0 &= (~0X80); 81 2 } 82 1 } 83 84 /***************************************************** 85 *º¯ÊýÃû³Æ£ºvoid SSI_SPI_SendData(uint8_t Data) 86 *º¯Êý¹¦ÄÜ£ºSPI·¢ËÍÊý¾Ý 87 *Èë¿Ú²ÎÊý£ºData ·¢Ë͵ÄÊý¾Ý 88 *³ö¿Ú²ÎÊý£ºvoid 89 *****************************************************/ 90 void SSI_SPI_SendData(uint8_t Data) 91 { 92 1 SSDAT = Data; 93 1 } 94 95 /***************************************************** 96 *º¯ÊýÃû³Æ£ºuint8_t SSI_SPI_ReceiveData(void) 97 *º¯Êý¹¦ÄÜ£º»ñµÃSSDATÖеÄÖµ 98 *Èë¿Ú²ÎÊý£ºvoid 99 *³ö¿Ú²ÎÊý£ºuint8_t 100 *****************************************************/ 101 uint8_t SSI_SPI_ReceiveData(void) 102 { 103 1 return SSDAT; 104 1 } 105 106 /************************************************** 107 *º¯ÊýÃû³Æ£ºvoid SSI_TWI_Init(uint8_t TWI_Address) 108 *º¯Êý¹¦ÄÜ£ºTWI³õʼ»¯ÅäÖú¯Êý 109 *Èë¿Ú²ÎÊý£ºTWI_Address 7λ´Ó»úµØÖ·ÅäÖü°Í¨ÓõØַʹÄÜÑ¡Ôñ 110 *³ö¿Ú²ÎÊý£ºvoid 111 **************************************************/ 112 void SSI_TWI_Init(uint8_t TWI_Address) 113 { 114 1 OTCON = OTCON & 0X3F | 0X80; 115 1 SSCON1 = TWI_Address & 0XFE; 116 1 } 117 118 /************************************************** 119 *º¯ÊýÃû³Æ£ºvoid SSI_TWI_AcknowledgeConfig(FunctionalState NewState) 120 *º¯Êý¹¦ÄÜ£ºTWI½ÓÊÕÓ¦´ðʹÄܺ¯Êý 121 *Èë¿Ú²ÎÊý£ºFunctionalState NewState ½ÓÊÕÓ¦´ðʹÄÜ/ʧÄÜÑ¡Ôñ 122 *³ö¿Ú²ÎÊý£ºvoid C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 9 123 **************************************************/ 124 void SSI_TWI_AcknowledgeConfig(FunctionalState NewState) 125 { 126 1 if (NewState != DISABLE) 127 1 { 128 2 SSCON0 |= 0X08; 129 2 } 130 1 else 131 1 { 132 2 SSCON0 &= 0XF7; 133 2 } 134 1 } 135 136 /************************************************** 137 *º¯ÊýÃû³Æ£ºvoid SSI_TWI_GeneralCallCmd(FunctionalState NewState) 138 *º¯Êý¹¦ÄÜ£ºTWIͨÓõØÖ·ÏìӦʹÄܺ¯Êý 139 *Èë¿Ú²ÎÊý£ºFunctionalState NewState ͨÓõØÖ·ÏìӦʹÄÜ/ʧÄÜÑ¡Ôñ 140 *³ö¿Ú²ÎÊý£ºvoid 141 **************************************************/ 142 void SSI_TWI_GeneralCallCmd(FunctionalState NewState) 143 { 144 1 if (NewState != DISABLE) 145 1 { 146 2 SSCON1 |= 0X01; 147 2 } 148 1 else 149 1 { 150 2 SSCON1 &= 0XFE; 151 2 } 152 1 } 153 154 /***************************************************** 155 *º¯ÊýÃû³Æ£ºvoid SSI_TWI_Cmd(FunctionalState NewState) 156 *º¯Êý¹¦ÄÜ£ºTWI¹¦ÄÜ¿ª¹Øº¯Êý 157 *Èë¿Ú²ÎÊý£ºFunctionalState NewState ¹¦ÄÜÆô¶¯/¹Ø±ÕÑ¡Ôñ 158 *³ö¿Ú²ÎÊý£ºvoid 159 *****************************************************/ 160 void SSI_TWI_Cmd(FunctionalState NewState) 161 { 162 1 if(NewState != DISABLE) 163 1 { 164 2 SSCON0 |= 0X80; 165 2 } 166 1 else 167 1 { 168 2 SSCON0 &= (~0X80); 169 2 } 170 1 } 171 172 /***************************************************** 173 *º¯ÊýÃû³Æ£ºvoid SSI_TWI_SendData(uint8_t Data) 174 *º¯Êý¹¦ÄÜ£ºTWI·¢ËÍÊý¾Ý 175 *Èë¿Ú²ÎÊý£ºData ·¢Ë͵ÄÊý¾Ý 176 *³ö¿Ú²ÎÊý£ºvoid 177 *****************************************************/ 178 void SSI_TWI_SendData(uint8_t Data) 179 { 180 1 SSDAT = Data; 181 1 } 182 183 /***************************************************** 184 *º¯ÊýÃû³Æ£ºuint8_t SSI_TWI_ReceiveData(void) C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 10 185 *º¯Êý¹¦ÄÜ£º»ñµÃSSDATÖеÄÖµ 186 *Èë¿Ú²ÎÊý£ºvoid 187 *³ö¿Ú²ÎÊý£ºuint8_t 188 *****************************************************/ 189 uint8_t SSI_TWI_ReceiveData(void) 190 { 191 1 return SSDAT; 192 1 } 193 194 /************************************************** 195 *º¯ÊýÃû³Æ£ºvoid SSI_UART1_Init(uint32_t UART1Fsys, uint32_t BaudRate, UART1_Mode_TypeDef Mode, UART1_RX_Ty -peDef RxMode) 196 *º¯Êý¹¦ÄÜ£ºUART1³õʼ»¯ÅäÖú¯Êý 197 *Èë¿Ú²ÎÊý£ºUART1Fsys ϵͳʱÖÓƵÂÊ 198 BaudRate ²¨ÌØÂÊ 199 Mode UART1¹¤×÷ģʽ 200 RxMode ½ÓÊÕÔÊÐíÑ¡Ôñ 201 *³ö¿Ú²ÎÊý£ºvoid 202 **************************************************/ 203 void SSI_UART1_Init(uint32_t UART1Fsys, uint32_t BaudRate, UART1_Mode_TypeDef Mode, UART1_RX_TypeDef RxMod -e) 204 { 205 1 OTCON |= 0xC0; 206 1 SSCON0 = SSCON0 & 0X0F | Mode | RxMode; 207 1 SSCON2 = UART1Fsys / BaudRate / 256; 208 1 SSCON1 = UART1Fsys / BaudRate % 256; 209 1 } 210 211 /***************************************************** 212 *º¯ÊýÃû³Æ£ºvoid SSI_UART1_SendData8(uint8_t Data) 213 *º¯Êý¹¦ÄÜ£ºUART1·¢ËÍ8λÊý¾Ý 214 *Èë¿Ú²ÎÊý£ºData ·¢Ë͵ÄÊý¾Ý 215 *³ö¿Ú²ÎÊý£ºvoid 216 *****************************************************/ 217 void SSI_UART1_SendData8(uint8_t Data) 218 { 219 1 SSDAT = Data; 220 1 } 221 222 /***************************************************** 223 *º¯ÊýÃû³Æ£ºuint8_t SSI_UART1_ReceiveData8(void) 224 *º¯Êý¹¦ÄÜ£º»ñµÃSSDATÖеÄÖµ 225 *Èë¿Ú²ÎÊý£ºvoid 226 *³ö¿Ú²ÎÊý£ºuint8_t 227 *****************************************************/ 228 uint8_t SSI_UART1_ReceiveData8(void) 229 { 230 1 return SSDAT; 231 1 } 232 233 /***************************************************** 234 *º¯ÊýÃû³Æ£ºvoid SSI_UART1_SendData9(uint16_t Data) 235 *º¯Êý¹¦ÄÜ£ºUART1·¢ËÍ9λÊý¾Ý 236 *Èë¿Ú²ÎÊý£ºData ·¢Ë͵ÄÊý¾Ý 237 *³ö¿Ú²ÎÊý£ºvoid 238 *****************************************************/ 239 void SSI_UART1_SendData9(uint16_t Data) 240 { 241 1 uint8_t Data_9Bit; 242 1 Data_9Bit = (Data>>8); 243 1 if(Data_9Bit) 244 1 { C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 11 245 2 SSCON0 |= 0x08; 246 2 } 247 1 else 248 1 { 249 2 SSCON0 &= 0xf7; 250 2 } 251 1 252 1 SSDAT = (uint8_t)Data; 253 1 } 254 255 /***************************************************** 256 *º¯ÊýÃû³Æ£ºuint16_t SSI_UART1_ReceiveData9(void) 257 *º¯Êý¹¦ÄÜ£º»ñµÃSSDATÖеÄÖµ¼°µÚ¾ÅλµÄÖµ 258 *Èë¿Ú²ÎÊý£ºvoid 259 *³ö¿Ú²ÎÊý£ºuint16_t 260 *****************************************************/ 261 uint16_t SSI_UART1_ReceiveData9(void) 262 { 263 1 uint16_t Data9; 264 1 Data9 = SSDAT + ((uint16_t)(SSCON0&0X04)<<6); 265 1 SSCON0 &= 0XFB; 266 1 return Data9; 267 1 } 268 269 /***************************************************** 270 *º¯ÊýÃû³Æ£ºvoid SSI_ITConfig(FunctionalState NewState, PriorityStatus Priority) 271 *º¯Êý¹¦ÄÜ£ºSSIÖжϳõʼ»¯ 272 *Èë¿Ú²ÎÊý£ºFunctionalState NewState ÖжÏʹÄÜ/¹Ø±ÕÑ¡Ôñ 273 PriorityStatus Priority ÖжÏÓÅÏȼ¶Ñ¡Ôñ 274 *³ö¿Ú²ÎÊý£ºvoid 275 *****************************************************/ 276 void SSI_ITConfig(FunctionalState NewState, PriorityStatus Priority) 277 { 278 1 //ÖжÏʹÄÜ/¹Ø±ÕÉèÖà 279 1 if(NewState != DISABLE) 280 1 { 281 2 IE1 |= 0x01; 282 2 } 283 1 else 284 1 { 285 2 IE1 &= 0xFE; 286 2 } 287 1 //ÖжÏÓÅÏȼ¶ÉèÖà 288 1 if(Priority != LOW) 289 1 { 290 2 IP1 |= 0x01; 291 2 } 292 1 else 293 1 { 294 2 IP1 &= 0xFE; 295 2 } 296 1 } 297 298 /***************************************************** 299 *º¯ÊýÃû³Æ£ºFlagStatus SSI_GetFlagStatus(SSI_Flag_TypeDef SSI_FLAG) 300 *º¯Êý¹¦ÄÜ£º»ñµÃSSI±ê־״̬ 301 *Èë¿Ú²ÎÊý£ºSSI_FLAG ËùÐè»ñÈ¡µÄ±ê־λ 302 *³ö¿Ú²ÎÊý£ºFlagStatus SSI±ê־״̬ 303 *****************************************************/ 304 FlagStatus SSI_GetFlagStatus(SSI_Flag_TypeDef SSI_FLAG) 305 { 306 1 FlagStatus bitstatus = RESET; C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 12 307 1 308 1 if((SSI_FLAG==SPI_FLAG_SPIF) || (SSI_FLAG==SPI_FLAG_WCOL) || (SSI_FLAG==SPI_FLAG_TXE)) 309 1 { 310 2 if((SSI_FLAG & SSCON1) != (uint8_t)RESET) 311 2 { 312 3 bitstatus = SET; 313 3 } 314 2 else 315 2 { 316 3 bitstatus = RESET; 317 3 } 318 2 } 319 1 else 320 1 { 321 2 if((SSI_FLAG & SSCON0) != (uint8_t)RESET) 322 2 { 323 3 bitstatus = SET; 324 3 } 325 2 else 326 2 { 327 3 bitstatus = RESET; 328 3 } 329 2 } 330 1 331 1 return bitstatus; 332 1 } 333 334 /***************************************************** 335 *º¯ÊýÃû³Æ£ºvoid SSI_ClearFlag(SSI_Flag_TypeDef SSI_FLAG) 336 *º¯Êý¹¦ÄÜ£ºÇå³ýSSI±ê־״̬ 337 *Èë¿Ú²ÎÊý£ºSSI_FLAG ËùÐèÇå³ýµÄ±ê־λ 338 *³ö¿Ú²ÎÊý£ºvoid 339 *****************************************************/ 340 void SSI_ClearFlag(SSI_Flag_TypeDef SSI_FLAG) 341 { 342 1 if((SSI_FLAG==SPI_FLAG_SPIF) || (SSI_FLAG==SPI_FLAG_WCOL) || (SSI_FLAG==SPI_FLAG_TXE)) 343 1 { 344 2 SSCON1 &= (~SSI_FLAG); 345 2 } 346 1 else 347 1 { 348 2 SSCON0 &= (~SSI_FLAG); 349 2 } 350 1 } 351 352 /******************* (C) COPYRIGHT 2018 SinOne Microelectronics *****END OF FILE****/ C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 13 ASSEMBLY LISTING OF GENERATED OBJECT CODE ; FUNCTION SSI_DeInit (BEGIN) ; SOURCE LINE # 20 ; SOURCE LINE # 21 ; SOURCE LINE # 22 0000 538F1F ANL OTCON,#01FH ; SOURCE LINE # 23 0003 E4 CLR A 0004 F59D MOV SSCON0,A ; SOURCE LINE # 24 0006 F59E MOV SSCON1,A ; SOURCE LINE # 25 0008 F595 MOV SSCON2,A ; SOURCE LINE # 26 000A F59F MOV SSDAT,A ; SOURCE LINE # 27 000C 53A9FE ANL IE1,#0FEH ; SOURCE LINE # 28 000F 53B9FE ANL IP1,#0FEH ; SOURCE LINE # 29 0012 22 RET ; FUNCTION SSI_DeInit (END) ; FUNCTION _SSI_PinSelection (BEGIN) ; SOURCE LINE # 37 ;---- Variable 'PinSeletion' assigned to Register 'R7' ---- ; SOURCE LINE # 38 ; SOURCE LINE # 39 0000 E58F MOV A,OTCON 0002 54DF ANL A,#0DFH 0004 4F ORL A,R7 0005 F58F MOV OTCON,A ; SOURCE LINE # 40 0007 22 RET ; FUNCTION _SSI_PinSelection (END) ; FUNCTION _SSI_SPI_Init (BEGIN) ; SOURCE LINE # 54 ;---- Variable 'FirstBit' assigned to Register 'R7' ---- ;---- Variable 'Mode' assigned to Register 'R3' ---- ;---- Variable 'BaudRatePrescaler' assigned to Register 'R5' ---- ; SOURCE LINE # 60 ; SOURCE LINE # 61 0000 E58F MOV A,OTCON 0002 543F ANL A,#03FH 0004 4440 ORL A,#040H 0006 F58F MOV OTCON,A ; SOURCE LINE # 62 0008 E59E MOV A,SSCON1 000A 54FA ANL A,#0FAH 000C 4F ORL A,R7 000D 4500 R ORL A,SPI_TXE_INT 000F F59E MOV SSCON1,A ; SOURCE LINE # 63 0011 E59D MOV A,SSCON0 0013 5480 ANL A,#080H 0015 4D ORL A,R5 0016 4B ORL A,R3 0017 4500 R ORL A,ClockPolarity 0019 4500 R ORL A,ClockPhase C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 14 001B F59D MOV SSCON0,A ; SOURCE LINE # 64 001D 22 RET ; FUNCTION _SSI_SPI_Init (END) ; FUNCTION _SSI_SPI_Cmd (BEGIN) ; SOURCE LINE # 72 ;---- Variable 'NewState' assigned to Register 'R7' ---- ; SOURCE LINE # 73 ; SOURCE LINE # 74 0000 EF MOV A,R7 0001 6004 JZ ?C0004 ; SOURCE LINE # 75 ; SOURCE LINE # 76 0003 439D80 ORL SSCON0,#080H ; SOURCE LINE # 77 0006 22 RET 0007 ?C0004: ; SOURCE LINE # 79 ; SOURCE LINE # 80 0007 539D7F ANL SSCON0,#07FH ; SOURCE LINE # 81 ; SOURCE LINE # 82 000A ?C0006: 000A 22 RET ; FUNCTION _SSI_SPI_Cmd (END) ; FUNCTION _SSI_SPI_SendData (BEGIN) ; SOURCE LINE # 90 ;---- Variable 'Data' assigned to Register 'R7' ---- ; SOURCE LINE # 91 ; SOURCE LINE # 92 0000 8F9F MOV SSDAT,R7 ; SOURCE LINE # 93 0002 22 RET ; FUNCTION _SSI_SPI_SendData (END) ; FUNCTION SSI_SPI_ReceiveData (BEGIN) ; SOURCE LINE # 101 ; SOURCE LINE # 102 ; SOURCE LINE # 103 0000 AF9F MOV R7,SSDAT ; SOURCE LINE # 104 0002 22 RET ; FUNCTION SSI_SPI_ReceiveData (END) ; FUNCTION _SSI_TWI_Init (BEGIN) ; SOURCE LINE # 112 ;---- Variable 'TWI_Address' assigned to Register 'R7' ---- ; SOURCE LINE # 113 ; SOURCE LINE # 114 0000 E58F MOV A,OTCON 0002 543F ANL A,#03FH 0004 4480 ORL A,#080H 0006 F58F MOV OTCON,A ; SOURCE LINE # 115 0008 EF MOV A,R7 0009 54FE ANL A,#0FEH 000B F59E MOV SSCON1,A ; SOURCE LINE # 116 000D 22 RET ; FUNCTION _SSI_TWI_Init (END) C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 15 ; FUNCTION _SSI_TWI_AcknowledgeConfig (BEGIN) ; SOURCE LINE # 124 ;---- Variable 'NewState' assigned to Register 'R7' ---- ; SOURCE LINE # 125 ; SOURCE LINE # 126 0000 EF MOV A,R7 0001 6004 JZ ?C0010 ; SOURCE LINE # 127 ; SOURCE LINE # 128 0003 439D08 ORL SSCON0,#08H ; SOURCE LINE # 129 0006 22 RET 0007 ?C0010: ; SOURCE LINE # 131 ; SOURCE LINE # 132 0007 539DF7 ANL SSCON0,#0F7H ; SOURCE LINE # 133 ; SOURCE LINE # 134 000A ?C0012: 000A 22 RET ; FUNCTION _SSI_TWI_AcknowledgeConfig (END) ; FUNCTION _SSI_TWI_GeneralCallCmd (BEGIN) ; SOURCE LINE # 142 ;---- Variable 'NewState' assigned to Register 'R7' ---- ; SOURCE LINE # 143 ; SOURCE LINE # 144 0000 EF MOV A,R7 0001 6004 JZ ?C0013 ; SOURCE LINE # 145 ; SOURCE LINE # 146 0003 439E01 ORL SSCON1,#01H ; SOURCE LINE # 147 0006 22 RET 0007 ?C0013: ; SOURCE LINE # 149 ; SOURCE LINE # 150 0007 539EFE ANL SSCON1,#0FEH ; SOURCE LINE # 151 ; SOURCE LINE # 152 000A ?C0015: 000A 22 RET ; FUNCTION _SSI_TWI_GeneralCallCmd (END) ; FUNCTION _SSI_TWI_Cmd (BEGIN) ; SOURCE LINE # 160 ;---- Variable 'NewState' assigned to Register 'R7' ---- ; SOURCE LINE # 161 ; SOURCE LINE # 162 0000 EF MOV A,R7 0001 6004 JZ ?C0016 ; SOURCE LINE # 163 ; SOURCE LINE # 164 0003 439D80 ORL SSCON0,#080H ; SOURCE LINE # 165 0006 22 RET 0007 ?C0016: ; SOURCE LINE # 167 ; SOURCE LINE # 168 0007 539D7F ANL SSCON0,#07FH ; SOURCE LINE # 169 C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 16 ; SOURCE LINE # 170 000A ?C0018: 000A 22 RET ; FUNCTION _SSI_TWI_Cmd (END) ; FUNCTION _SSI_TWI_SendData (BEGIN) ; SOURCE LINE # 178 ;---- Variable 'Data' assigned to Register 'R7' ---- ; SOURCE LINE # 179 ; SOURCE LINE # 180 0000 8F9F MOV SSDAT,R7 ; SOURCE LINE # 181 0002 22 RET ; FUNCTION _SSI_TWI_SendData (END) ; FUNCTION SSI_TWI_ReceiveData (BEGIN) ; SOURCE LINE # 189 ; SOURCE LINE # 190 ; SOURCE LINE # 191 0000 AF9F MOV R7,SSDAT ; SOURCE LINE # 192 0002 22 RET ; FUNCTION SSI_TWI_ReceiveData (END) ; FUNCTION _SSI_UART1_Init (BEGIN) ; SOURCE LINE # 203 0000 8F00 R MOV UART1Fsys+03H,R7 0002 8E00 R MOV UART1Fsys+02H,R6 0004 8D00 R MOV UART1Fsys+01H,R5 0006 8C00 R MOV UART1Fsys,R4 ; SOURCE LINE # 204 ; SOURCE LINE # 205 0008 438FC0 ORL OTCON,#0C0H ; SOURCE LINE # 206 000B E59D MOV A,SSCON0 000D 540F ANL A,#0FH 000F 4500 R ORL A,Mode 0011 4500 R ORL A,RxMode 0013 F59D MOV SSCON0,A ; SOURCE LINE # 207 0015 AB00 R MOV R3,BaudRate+03H 0017 AA00 R MOV R2,BaudRate+02H 0019 A900 R MOV R1,BaudRate+01H 001B A800 R MOV R0,BaudRate 001D AF00 R MOV R7,UART1Fsys+03H 001F AE00 R MOV R6,UART1Fsys+02H 0021 AD00 R MOV R5,UART1Fsys+01H 0023 AC00 R MOV R4,UART1Fsys 0025 120000 E LCALL ?C?ULDIV 0028 E4 CLR A 0029 FB MOV R3,A 002A 7A01 MOV R2,#01H 002C F9 MOV R1,A 002D F8 MOV R0,A 002E 120000 E LCALL ?C?ULDIV 0031 8F95 MOV SSCON2,R7 ; SOURCE LINE # 208 0033 AB00 R MOV R3,BaudRate+03H 0035 AA00 R MOV R2,BaudRate+02H 0037 A900 R MOV R1,BaudRate+01H 0039 A800 R MOV R0,BaudRate 003B AF00 R MOV R7,UART1Fsys+03H C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 17 003D AE00 R MOV R6,UART1Fsys+02H 003F AD00 R MOV R5,UART1Fsys+01H 0041 AC00 R MOV R4,UART1Fsys 0043 120000 E LCALL ?C?ULDIV 0046 8F9E MOV SSCON1,R7 ; SOURCE LINE # 209 0048 22 RET ; FUNCTION _SSI_UART1_Init (END) ; FUNCTION _SSI_UART1_SendData8 (BEGIN) ; SOURCE LINE # 217 ;---- Variable 'Data' assigned to Register 'R7' ---- ; SOURCE LINE # 218 ; SOURCE LINE # 219 0000 8F9F MOV SSDAT,R7 ; SOURCE LINE # 220 0002 22 RET ; FUNCTION _SSI_UART1_SendData8 (END) ; FUNCTION SSI_UART1_ReceiveData8 (BEGIN) ; SOURCE LINE # 228 ; SOURCE LINE # 229 ; SOURCE LINE # 230 0000 AF9F MOV R7,SSDAT ; SOURCE LINE # 231 0002 22 RET ; FUNCTION SSI_UART1_ReceiveData8 (END) ; FUNCTION _SSI_UART1_SendData9 (BEGIN) ; SOURCE LINE # 239 ;---- Variable 'Data' assigned to Register 'R4/R5' ---- 0000 AD07 MOV R5,AR7 0002 AC06 MOV R4,AR6 ; SOURCE LINE # 240 ; SOURCE LINE # 242 ;---- Variable 'Data_9Bit' assigned to Register 'R7' ---- ; SOURCE LINE # 243 0004 EC MOV A,R4 0005 6005 JZ ?C0024 ; SOURCE LINE # 244 ; SOURCE LINE # 245 0007 439D08 ORL SSCON0,#08H ; SOURCE LINE # 246 000A 8003 SJMP ?C0025 000C ?C0024: ; SOURCE LINE # 248 ; SOURCE LINE # 249 000C 539DF7 ANL SSCON0,#0F7H ; SOURCE LINE # 250 000F ?C0025: ; SOURCE LINE # 252 000F 8D9F MOV SSDAT,R5 ; SOURCE LINE # 253 0011 22 RET ; FUNCTION _SSI_UART1_SendData9 (END) ; FUNCTION SSI_UART1_ReceiveData9 (BEGIN) ; SOURCE LINE # 261 ; SOURCE LINE # 262 ; SOURCE LINE # 264 0000 E59D MOV A,SSCON0 0002 5404 ANL A,#04H C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 18 0004 75F040 MOV B,#040H 0007 A4 MUL AB 0008 AD9F MOV R5,SSDAT 000A 7C00 MOV R4,#00H 000C 2D ADD A,R5 000D FF MOV R7,A 000E EC MOV A,R4 000F 35F0 ADDC A,B 0011 FE MOV R6,A ;---- Variable 'Data9' assigned to Register 'R6/R7' ---- ; SOURCE LINE # 265 0012 539DFB ANL SSCON0,#0FBH ; SOURCE LINE # 266 ; SOURCE LINE # 267 0015 22 RET ; FUNCTION SSI_UART1_ReceiveData9 (END) ; FUNCTION _SSI_ITConfig (BEGIN) ; SOURCE LINE # 276 ;---- Variable 'Priority' assigned to Register 'R5' ---- ;---- Variable 'NewState' assigned to Register 'R7' ---- ; SOURCE LINE # 277 ; SOURCE LINE # 279 0000 EF MOV A,R7 0001 6005 JZ ?C0028 ; SOURCE LINE # 280 ; SOURCE LINE # 281 0003 43A901 ORL IE1,#01H ; SOURCE LINE # 282 0006 8003 SJMP ?C0029 0008 ?C0028: ; SOURCE LINE # 284 ; SOURCE LINE # 285 0008 53A9FE ANL IE1,#0FEH ; SOURCE LINE # 286 000B ?C0029: ; SOURCE LINE # 288 000B ED MOV A,R5 000C 6004 JZ ?C0030 ; SOURCE LINE # 289 ; SOURCE LINE # 290 000E 43B901 ORL IP1,#01H ; SOURCE LINE # 291 0011 22 RET 0012 ?C0030: ; SOURCE LINE # 293 ; SOURCE LINE # 294 0012 53B9FE ANL IP1,#0FEH ; SOURCE LINE # 295 ; SOURCE LINE # 296 0015 ?C0032: 0015 22 RET ; FUNCTION _SSI_ITConfig (END) ; FUNCTION _SSI_GetFlagStatus (BEGIN) ; SOURCE LINE # 304 ;---- Variable 'SSI_FLAG' assigned to Register 'R7' ---- ; SOURCE LINE # 305 ; SOURCE LINE # 306 ;---- Variable 'bitstatus' assigned to Register 'R6' ---- ; SOURCE LINE # 308 0000 EF MOV A,R7 C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 19 0001 6480 XRL A,#080H 0003 6008 JZ ?C0034 0005 EF MOV A,R7 0006 6440 XRL A,#040H 0008 6003 JZ ?C0034 000A BF080D CJNE R7,#08H,?C0033 000D ?C0034: ; SOURCE LINE # 309 ; SOURCE LINE # 310 000D E59E MOV A,SSCON1 000F 5F ANL A,R7 0010 6004 JZ ?C0035 ; SOURCE LINE # 311 ; SOURCE LINE # 312 0012 7E01 MOV R6,#01H ; SOURCE LINE # 313 0014 800F SJMP ?C0037 0016 ?C0035: ; SOURCE LINE # 315 ; SOURCE LINE # 316 0016 E4 CLR A 0017 FE MOV R6,A ; SOURCE LINE # 317 ; SOURCE LINE # 318 0018 800B SJMP ?C0037 001A ?C0033: ; SOURCE LINE # 320 ; SOURCE LINE # 321 001A E59D MOV A,SSCON0 001C 5F ANL A,R7 001D 6004 JZ ?C0038 ; SOURCE LINE # 322 ; SOURCE LINE # 323 001F 7E01 MOV R6,#01H ; SOURCE LINE # 324 0021 8002 SJMP ?C0037 0023 ?C0038: ; SOURCE LINE # 326 ; SOURCE LINE # 327 0023 E4 CLR A 0024 FE MOV R6,A ; SOURCE LINE # 328 ; SOURCE LINE # 329 0025 ?C0037: ; SOURCE LINE # 331 0025 AF06 MOV R7,AR6 ; SOURCE LINE # 332 0027 22 RET ; FUNCTION _SSI_GetFlagStatus (END) ; FUNCTION _SSI_ClearFlag (BEGIN) ; SOURCE LINE # 340 ;---- Variable 'SSI_FLAG' assigned to Register 'R7' ---- ; SOURCE LINE # 341 ; SOURCE LINE # 342 0000 EF MOV A,R7 0001 6480 XRL A,#080H 0003 6008 JZ ?C0042 0005 EF MOV A,R7 0006 6440 XRL A,#040H 0008 6003 JZ ?C0042 000A BF0805 CJNE R7,#08H,?C0041 C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 20 000D ?C0042: ; SOURCE LINE # 343 ; SOURCE LINE # 344 000D EF MOV A,R7 000E F4 CPL A 000F 529E ANL SSCON1,A ; SOURCE LINE # 345 0011 22 RET 0012 ?C0041: ; SOURCE LINE # 347 ; SOURCE LINE # 348 0012 EF MOV A,R7 0013 F4 CPL A 0014 529D ANL SSCON0,A ; SOURCE LINE # 349 ; SOURCE LINE # 350 0016 ?C0044: 0016 22 RET ; FUNCTION _SSI_ClearFlag (END) C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 21 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== uint16_t . . . . . . . . . . . . . . . TYPEDEF ----- U_INT ----- 2 SPI_FLAG_WCOL. . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 P0 . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0080H 1 SSDAT. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009FH 1 P1 . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0090H 1 P2 . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A0H 1 UART1_RX_ENABLE. . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SPI_BAUDRATEPRESCALER_32 . . . . . . . E_CONST ----- U_CHAR ----- 1 FlagStatus . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 RESET. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 OTCON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008FH 1 SPI_BAUDRATEPRESCALER_16 . . . . . . . E_CONST ----- U_CHAR ----- 1 int32_t. . . . . . . . . . . . . . . . TYPEDEF ----- LONG ----- 4 SPI_CLOCKPOLARITY_LOW. . . . . . . . . E_CONST ----- U_CHAR ----- 1 int16_t. . . . . . . . . . . . . . . . TYPEDEF ----- INT ----- 2 SPI_BAUDRATEPRESCALER_64 . . . . . . . E_CONST ----- U_CHAR ----- 1 ERROR. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 TWI_FLAG_TWIF. . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 IE . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A8H 1 UART1_RX_TypeDef . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 SPI_FirstBit_TypeDef . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 SSI_DeInit . . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- ErrorStatus. . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 SPI_BaudRatePrescaler_TypeDef. . . . . TYPEDEF ----- U_CHAR ----- 1 IP . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00B8H 1 SUCCESS. . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SSI_UART1_ReceiveData8 . . . . . . . . PUBLIC CODE PROC 0000H ----- TWI_FLAG_GCA . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SSI_UART1_ReceiveData9 . . . . . . . . PUBLIC CODE PROC 0000H ----- Data9. . . . . . . . . . . . . . . . * REG * DATA U_INT 0006H 2 FunctionalState. . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 SPI_TXE_ENINT. . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 HIGH . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SPI_TXE_INT_TypeDef. . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 SPI_MODE_MASTER. . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 _SSI_PinSelection. . . . . . . . . . . PUBLIC CODE PROC 0000H ----- PinSeletion. . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 SSI_PinSelection_P21P22P23 . . . . . . E_CONST ----- U_CHAR ----- 1 ITStatus . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 _SSI_SPI_SendData. . . . . . . . . . . PUBLIC CODE PROC 0000H ----- Data . . . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 ENABLE . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 BitStatus. . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 s8 . . . . . . . . . . . . . . . . . . TYPEDEF ----- CHAR ----- 1 SSI_PinSelection_P10P27P26 . . . . . . E_CONST ----- U_CHAR ----- 1 SPI_ClockPolarity_TypeDef. . . . . . . TYPEDEF ----- U_CHAR ----- 1 u8 . . . . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 bool . . . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 _SSI_TWI_SendData. . . . . . . . . . . PUBLIC CODE PROC 0000H ----- Data . . . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 _SSI_SPI_Cmd . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- NewState . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 _SSI_SPI_Init. . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- FirstBit . . . . . . . . . . . . . . AUTO DATA U_CHAR 0007H 1 BaudRatePrescaler. . . . . . . . . . AUTO DATA U_CHAR 0005H 1 Mode . . . . . . . . . . . . . . . . AUTO DATA U_CHAR 0003H 1 ClockPolarity. . . . . . . . . . . . AUTO DATA U_CHAR 0003H 1 C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 22 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== ClockPhase . . . . . . . . . . . . . AUTO DATA U_CHAR 0004H 1 SPI_TXE_INT. . . . . . . . . . . . . AUTO DATA U_CHAR 0005H 1 SCON . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0098H 1 TCON . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0088H 1 _SSI_UART1_Init. . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- UART1Fsys. . . . . . . . . . . . . . AUTO DATA U_LONG 0000H 4 BaudRate . . . . . . . . . . . . . . AUTO DATA U_LONG 0004H 4 Mode . . . . . . . . . . . . . . . . AUTO DATA U_CHAR 0008H 1 RxMode . . . . . . . . . . . . . . . AUTO DATA U_CHAR 0009H 1 SPI_CLOCKPOLARITY_HIGH . . . . . . . . E_CONST ----- U_CHAR ----- 1 _SSI_ClearFlag . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- SSI_FLAG . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 SPI_BAUDRATEPRESCALER_512. . . . . . . E_CONST ----- U_CHAR ----- 1 SSCON0 . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009DH 1 SSCON1 . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009EH 1 SSCON2 . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0095H 1 _SSI_TWI_Cmd . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- NewState . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 SPI_FLAG_TXE . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SPI_BAUDRATEPRESCALER_128. . . . . . . E_CONST ----- U_CHAR ----- 1 _SSI_TWI_Init. . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- TWI_Address. . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 SSI_PinSelection_TypeDef . . . . . . . TYPEDEF ----- U_CHAR ----- 1 SPI_BAUDRATEPRESCALER_256. . . . . . . E_CONST ----- U_CHAR ----- 1 IE1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A9H 1 TRUE . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SPI_ClockPhase_TypeDef . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 _SSI_ITConfig. . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- NewState . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 Priority . . . . . . . . . . . . . . * REG * DATA U_CHAR 0005H 1 IP1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00B9H 1 uint8_t. . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 UART1_RX_DISABLE . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SPI_MODE_SLAVE . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SPI_BAUDRATEPRESCALER_4. . . . . . . . E_CONST ----- U_CHAR ----- 1 SPI_CLOCKPHASE_1EDGE . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SPI_BAUDRATEPRESCALER_8. . . . . . . . E_CONST ----- U_CHAR ----- 1 SPI_CLOCKPHASE_2EDGE . . . . . . . . . E_CONST ----- U_CHAR ----- 1 s32. . . . . . . . . . . . . . . . . . TYPEDEF ----- LONG ----- 4 int8_t . . . . . . . . . . . . . . . . TYPEDEF ----- CHAR ----- 1 UART1_Mode_10B . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 u32. . . . . . . . . . . . . . . . . . TYPEDEF ----- U_LONG ----- 4 s16. . . . . . . . . . . . . . . . . . TYPEDEF ----- INT ----- 2 UART1_Mode_11B . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 u16. . . . . . . . . . . . . . . . . . TYPEDEF ----- U_INT ----- 2 _SSI_UART1_SendData8 . . . . . . . . . PUBLIC CODE PROC 0000H ----- Data . . . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 _SSI_UART1_SendData9 . . . . . . . . . PUBLIC CODE PROC 0000H ----- Data . . . . . . . . . . . . . . . . * REG * DATA U_INT 0004H 2 Data_9Bit. . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 SSI_SPI_ReceiveData. . . . . . . . . . PUBLIC CODE PROC 0000H ----- SSI_Flag_TypeDef . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 UART1_FLAG_RI. . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 T2CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C8H 1 UART1_FLAG_TI. . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SSI_TWI_ReceiveData. . . . . . . . . . PUBLIC CODE PROC 0000H ----- SPI_Mode_TypeDef . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 C51 COMPILER V9.60.7.0 SC92F8003_SSI 05/12/2024 15:18:35 PAGE 23 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== _SSI_TWI_AcknowledgeConfig . . . . . . PUBLIC CODE PROC 0000H ----- NewState . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 UART1_Mode_TypeDef . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 SET. . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 FALSE. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SPI_TXE_DISINT . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 PriorityStatus . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 LOW. . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 DISABLE. . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 _SSI_GetFlagStatus . . . . . . . . . . PUBLIC CODE PROC 0000H ----- SSI_FLAG . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 bitstatus. . . . . . . . . . . . . . * REG * DATA U_CHAR 0006H 1 SPI_FIRSTBIT_LSB . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 PSW. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D0H 1 SPI_FIRSTBIT_MSB . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SPI_FLAG_SPIF. . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 uint32_t . . . . . . . . . . . . . . . TYPEDEF ----- U_LONG ----- 4 _SSI_TWI_GeneralCallCmd. . . . . . . . PUBLIC CODE PROC 0000H ----- NewState . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 331 ---- CONSTANT SIZE = ---- ---- XDATA SIZE = ---- ---- PDATA SIZE = ---- ---- DATA SIZE = ---- 16 IDATA SIZE = ---- ---- BIT SIZE = ---- ---- END OF MODULE INFORMATION. C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)