C51 COMPILER V9.60.7.0 SPI 05/13/2024 00:07:49 PAGE 1 C51 COMPILER V9.60.7.0, COMPILATION OF MODULE SPI OBJECT MODULE PLACED IN .\Objects\spi.obj COMPILER INVOKED BY: d:\Keil\C51\BIN\C51.EXE Src\spi.c OMF2 OPTIMIZE(8,SPEED) BROWSE INCDIR(.\Src;.\Task;.\Task\cpu_port -\S92F8003A;.\Task\cfg;.\Task\pt_thread;.\SC92F8003_Lib\Inc) DEBUG CODE LISTINCLUDE SYMBOLS PRINT(.\Listings\spi.lst) PRE -PRINT(.\Listings\spi.i) OBJECT(.\Objects\spi.obj) line level source 1 2 #include 1 =1 #ifndef _SC92F8003_H 2 =1 #define _SC92F8003_H 3 =1 4 =1 #include "SC92F8003_C.H" 1 =2 /*-------------------------------------------------------------------------- 2 =2 SC92F8003_C.H 3 =2 4 =2 C Header file for SC92F8003 microcontroller. 5 =2 Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. 6 =2 All rights reserved. 7 =2 ÉîÛÚÊÐÈüԪ΢µç×ÓÓÐÏÞ¹«Ë¾ 8 =2 °æ±¾ºÅ: V1.0 9 =2 ÈÕÆÚ: 2018.05.02 10 =2 --------------------------------------------------------------------------*/ 11 =2 #ifndef _SC92F8003_H_ 12 =2 #define _SC92F8003_H_ 13 =2 14 =2 /* ------------------- ×ֽڼĴæÆ÷-------------------- */ 15 =2 ///*CPU*/ 16 =2 sfr ACC = 0xE0; //ÀÛ¼ÓÆ÷£Á 17 =2 sfr B = 0xF0; //ͨÓüĴæÆ÷B 18 =2 sfr PSW = 0xD0; //³ÌÐò״̬×Ö 19 =2 sfr DPH = 0x83; //Êý¾ÝÖ¸Õë¸ß8λ 20 =2 sfr DPL = 0x82; //Êý¾ÝÖ¸ÕëµÍ8λ 21 =2 sfr SP = 0x81; //¶ÑÕ»Ö¸Õë 22 =2 23 =2 24 =2 /*system*/ 25 =2 sfr PCON = 0x87; //µçÔ´¹ÜÀí¿ØÖƼĴæÆ÷ 26 =2 27 =2 /*interrupt*/ 28 =2 sfr IP1 = 0XB9; //ÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷1 29 =2 sfr IP = 0xB8; //ÖжÏÓÅÏÈȨ¿ØÖƼĴæÆ÷ 30 =2 sfr IE = 0xA8; //ÖжϿØÖƼĴæÆ÷ 31 =2 sfr IE1 = 0XA9; //ÖжϿØÖƼĴæÆ÷1 32 =2 33 =2 /*PORT*/ 34 =2 sfr P2PH = 0xA2; //P2¿Úģʽ¿ØÖƼĴæÆ÷ 35 =2 sfr P2CON = 0xA1; //P2¿Úģʽ¿ØÖƼĴæÆ÷ 36 =2 sfr P2 = 0xA0; //P2¿ÚÊý¾Ý¼Ä´æÆ÷ 37 =2 sfr P1PH = 0x92; //P1¿Úģʽ¿ØÖƼĴæÆ÷ 38 =2 sfr P1CON = 0x91; //P1¿Úģʽ¿ØÖƼĴæÆ÷ 39 =2 sfr P1 = 0x90; //P1¿ÚÊý¾Ý¼Ä´æÆ÷ 40 =2 sfr P0PH = 0x9B; //P0¿Úģʽ¿ØÖƼĴæÆ÷ 41 =2 sfr P0CON = 0x9A; //P0¿Úģʽ¿ØÖƼĴæÆ÷ 42 =2 sfr P0 = 0x80; //P0¿ÚÊý¾Ý¼Ä´æÆ÷ 43 =2 44 =2 /*TIMER*/ 45 =2 sfr TMCON = 0x8E; //¶¨Ê±Æ÷ƵÂÊ¿ØÖƼĴæÆ÷ 46 =2 sfr TH1 = 0x8D; //¶¨Ê±Æ÷1¸ß8λ 47 =2 sfr TH0 = 0x8C; //¶¨Ê±Æ÷0¸ß8λ C51 COMPILER V9.60.7.0 SPI 05/13/2024 00:07:49 PAGE 2 48 =2 sfr TL1 = 0x8B; //¶¨Ê±Æ÷1µÍ8λ 49 =2 sfr TL0 = 0x8A; //¶¨Ê±Æ÷0µÍ8λ 50 =2 sfr TMOD = 0x89; //¶¨Ê±Æ÷¹¤×÷ģʽ¼Ä´æÆ÷ 51 =2 sfr TCON = 0x88; //¶¨Ê±Æ÷¿ØÖƼĴæÆ÷ 52 =2 sfr T2CON = 0xC8; //¶¨Ê±Æ÷2¿ØÖƼĴæÆ÷ 53 =2 sfr T2MOD = 0xC9; //¶¨Ê±Æ÷2¹¤×÷ģʽ¼Ä´æÆ÷ 54 =2 sfr RCAP2L = 0xCA; //¶¨Ê±Æ÷2ÖØÔØ/²¶×½µÍ8λ 55 =2 sfr RCAP2H = 0xCB; //¶¨Ê±Æ÷2ÖØÔØ/²¶×½¸ß8λ 56 =2 sfr TL2 = 0xCC; //¶¨Ê±Æ÷2µÍ8λ 57 =2 sfr TH2 = 0xCD; //¶¨Ê±Æ÷2¸ß8λ 58 =2 59 =2 60 =2 /*ADC*/ 61 =2 sfr ADCCFG1 = 0xAA; //ADC¹¦ÄÜÅäÖüĴæÆ÷0 62 =2 sfr ADCCFG0 = 0xAB; //ADC¹¦ÄÜÅäÖüĴæÆ÷1 63 =2 sfr ADCCON = 0XAD; //ADC¿ØÖƼĴæÆ÷ 64 =2 sfr ADCVL = 0xAE; //ADC ½á¹û¼Ä´æÆ÷ 65 =2 sfr ADCVH = 0xAF; //ADC ½á¹û¼Ä´æÆ÷ 66 =2 67 =2 /*PWM*/ 68 =2 sfr PWMCFG = 0xD1; //PWMÉèÖüĴæÆ÷ 69 =2 sfr PWMCON0 = 0xD2; //PWM¿ØÖƼĴæÆ÷ 70 =2 sfr PWMPRD = 0xD3; //PWMÖÜÆÚÉèÖüĴæÆ÷ 71 =2 sfr PWMDTYA = 0xD4; //PWMÕ¼¿Õ±ÈÉèÖüĴæÆ÷A 72 =2 sfr PWMDTY0 = 0xD5; //PWM0ÉèÖüĴæÆ÷ 73 =2 sfr PWMDTY1 = 0xD6; //PWM1ÉèÖüĴæÆ÷ 74 =2 sfr PWMDTY2 = 0xD7; //PWM2ÉèÖüĴæÆ÷ 75 =2 sfr PWMCON1 = 0xDA; //PWM¿ØÖƼĴæÆ÷ 76 =2 sfr PWMDTYB = 0xDB; //PWMÕ¼¿Õ±ÈÉèÖüĴæÆ÷B 77 =2 sfr PWMDTY3 = 0xDC; //PWM3ÉèÖüĴæÆ÷ 78 =2 sfr PWMDTY4 = 0xDD; //PWM4ÉèÖüĴæÆ÷ 79 =2 sfr PWMDTY5 = 0xDE; //PWM5ÉèÖüĴæÆ÷ 80 =2 sfr PWMDTY6 = 0xDF; //PWM6ÉèÖüĴæÆ÷ 81 =2 82 =2 83 =2 // 84 =2 ///*WatchDog*/ 85 =2 sfr BTMCON = 0XCE; //µÍƵ¶¨Ê±Æ÷¿ØÖƼĴæÆ÷ 86 =2 sfr WDTCON = 0xCF; //WDT¿ØÖƼĴæÆ÷ 87 =2 88 =2 89 =2 sfr OTCON = 0X8F; //Êä³ö¿ØÖƼĴæÆ÷ 90 =2 91 =2 /*INT*/ 92 =2 sfr INT0F = 0XBA; //INT0 ϽµÑØÖжϿØÖƼĴæÆ÷ 93 =2 sfr INT0R = 0XBB; //INT0 ÉϽµÑØÖжϿØÖƼĴæÆ÷ 94 =2 sfr INT1F = 0XBC; //INT1 ϽµÑØÖжϿØÖƼĴæÆ÷ 95 =2 sfr INT1R = 0XBD; //INT1 ÉϽµÑØÖжϿØÖƼĴæÆ÷ 96 =2 sfr INT2F = 0XC6; //INT2 ϽµÑØÖжϿØÖƼĴæÆ÷ 97 =2 sfr INT2R = 0XC7; //INT2 ÉϽµÑØÖжϿØÖƼĴæÆ÷ 98 =2 99 =2 /*IAP */ 100 =2 sfr IAPCTL = 0xF6; //IAP¿ØÖƼĴæÆ÷ 101 =2 sfr IAPDAT = 0xF5; //IAPÊý¾Ý¼Ä´æÆ÷ 102 =2 sfr IAPADE = 0xF4; //IAPÀ©Õ¹µØÖ·¼Ä´æÆ÷ 103 =2 sfr IAPADH = 0xF3; //IAPдÈëµØÖ·¸ßλ¼Ä´æÆ÷ 104 =2 sfr IAPADL = 0xF2; //IAPдÈëµØÖ·µÍ8λ¼Ä´æÆ÷ 105 =2 sfr IAPKEY = 0xF1; //IAP±£»¤¼Ä´æÆ÷ 106 =2 107 =2 /*uart0*/ 108 =2 sfr SCON = 0X98; //uart¿ØÖƼĴæÆ÷ 109 =2 sfr SBUF = 0X99; //uart0Êý¾Ý¼Ä´æÆ÷ C51 COMPILER V9.60.7.0 SPI 05/13/2024 00:07:49 PAGE 3 110 =2 111 =2 /*ÈýºÏÒ»*/ 112 =2 sfr SSCON0 = 0X9D; //SSI¿ØÖƼĴæÆ÷0 113 =2 sfr SSCON1 = 0X9E; //SSI¿ØÖƼĴæÆ÷1 114 =2 sfr SSCON2 = 0X95; //SSI¿ØÖƼĴæÆ÷2 115 =2 sfr SSDAT = 0X9F; //SSIÊý¾Ý¼Ä´æÆ÷ 116 =2 117 =2 sfr OPINX = 0XFE; 118 =2 sfr OPREG = 0XFF; 119 =2 120 =2 /*Check Sum*/ 121 =2 sfr CHKSUML = 0XFC; //Check Sum½á¹û¼Ä´æÆ÷µÍλ 122 =2 sfr CHKSUMH = 0XFD; //Check Sum½á¹û¼Ä´æÆ÷¸ßλ 123 =2 124 =2 sfr OPERCON = 0xEF; //ÔËËã¿ØÖƼĴæÆ÷ 125 =2 126 =2 ///* ------------------- λ¼Ä´æÆ÷-------------------- */ 127 =2 /*PSW*/ 128 =2 sbit CY = PSW^7; //±ê־λ 0:¼Ó·¨ÔËËã×î¸ßλÎÞ½ø룬»òÕß¼õ·¨ÔËËã×î¸ßλÎÞ½èλʱ 1:¼Ó·¨ÔËËã×î¸ßλÓнø -룬»òÕß¼õ·¨ÔËËã×î¸ßλÓнèλʱ 129 =2 sbit AC = PSW^6; //½øλ¸¨Öú±ê־λ 0:ÎÞ½èλ¡¢½øλ 1:¼Ó·¨ÔËËãʱÔÚbit3λÓнø룬»ò¼õ·¨ÔËËãÔÚbit3λÓн -èλʱ 130 =2 sbit F0 = PSW^5; //Óû§±ê־λ 131 =2 sbit RS1 = PSW^4; //¹¤×÷¼Ä´æÆ÷×éÑ¡Ôñλ 132 =2 sbit RS0 = PSW^3; //¹¤×÷¼Ä´æÆ÷×éÑ¡Ôñλ 133 =2 sbit OV = PSW^2; //Òç³ö±ê־λ 134 =2 sbit F1 = PSW^1; //F1±êÖ¾ 135 =2 sbit P = PSW^0; //Ææż±ê־λ 0:ACCÖÐ1µÄ¸öÊýΪżÊý£¨°üÀ¨0¸ö£© 1:ACCÖÐ1µÄ¸öÊýΪÆæÊý 136 =2 137 =2 /*T2CON*/ 138 =2 sbit TF2 = T2CON^7; 139 =2 sbit EXF2 = T2CON^6; 140 =2 sbit RCLK = T2CON^5; 141 =2 sbit TCLK = T2CON^4; 142 =2 sbit EXEN2 = T2CON^3; 143 =2 sbit TR2 = T2CON^2; 144 =2 sbit T2 = T2CON^1; 145 =2 sbit CP = T2CON^0; 146 =2 147 =2 148 =2 /*IP*/ 149 =2 sbit IPADC = IP^6; //ADCÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 ADCµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 ADCµÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß¡ -± 150 =2 sbit IPT2 = IP^5; //PWMÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 PWMµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 PWM µÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß -¡± 151 =2 sbit IPUART = IP^4; //SIFÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 SIFµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 SIFµÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß¡ -± 152 =2 sbit IPT1 = IP^3; //Timer1ÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 Timer 1µÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 Timer 1µÄÖжÏÓÅÏÈÈ -¨ÊÇ ¡°¸ß¡± 153 =2 sbit IPINT1 = IP^2; //32K Base TimerÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 32KµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 32KµÄÖжÏÓÅ -ÏÈȨÊÇ ¡°¸ß¡± 154 =2 sbit IPT0 = IP^1; //Timer0ÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 Timer 0µÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 Timer 0µÄÖжÏÓÅÏÈÈ -¨ÊÇ ¡°¸ß¡± 155 =2 sbit IPINT0 = IP^0; 156 =2 157 =2 /*IE*/ 158 =2 sbit EA = IE^7; //ÖжÏʹÄܵÄ×Ü¿ØÖÆ 0:¹Ø±ÕËùÓеÄÖÐ¶Ï 1:´ò¿ªËùÓеÄÖÐ¶Ï 159 =2 sbit EADC = IE^6; //ADCÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕADCÖÐ¶Ï 1:´ò¿ªADCÖÐ¶Ï 160 =2 sbit ET2 = IE^5; //PWMÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕPWMÖÐ¶Ï 1:´ò¿ªPWMÖÐ¶Ï 161 =2 sbit EUART = IE^4; //UARTÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕSIFÖÐ¶Ï 1:´ò¿ªSIFÖÐ¶Ï 162 =2 sbit ET1 = IE^3; //Timer1ÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTIMER1ÖÐ¶Ï 1:´ò¿ªTIMER1ÖÐ¶Ï 163 =2 sbit EINT1 = IE^2; //32K Base TimerÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±Õ32KÖÐ¶Ï 1:´ò¿ª32KÖÐ¶Ï C51 COMPILER V9.60.7.0 SPI 05/13/2024 00:07:49 PAGE 4 164 =2 sbit ET0 = IE^1; //Timer0ÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTIMER0ÖÐ¶Ï 1:´ò¿ªTIMER0ÖÐ¶Ï 165 =2 sbit EINT0 = IE^0; //TouchKeyµÄÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTouchKeyÖÐ¶Ï 1:´ò¿ªTouchKeyÖÐ¶Ï 166 =2 167 =2 /*TCON*/ 168 =2 sbit TF1 = TCON^7; //T1Òç³öÖжÏÇëÇó±ê־λ T1²úÉúÒç³ö£¬·¢ÉúÖжÏʱ£¬Ó²¼þ½«TF1ÖÃΪ¡°1¡±£¬ÉêÇëÖжϣ¬CPU -ÏìӦʱ£¬Ó²¼þÇå¡°0¡±¡£ 169 =2 sbit TR1 = TCON^6; //¶¨Ê±Æ÷T1µÄÔËÐпØÖÆλ 0:Timer1½ûÖ¹¼ÆÊý 1:Timer1¿ªÊ¼¼ÆÊý 170 =2 sbit TF0 = TCON^5; //T0Òç³öÖжÏÇëÇó±ê־λ T0²úÉúÒç³ö£¬·¢ÉúÖжÏʱ£¬Ó²¼þ½«TF0ÖÃΪ¡°1¡±£¬ÉêÇëÖжϣ¬CPU -ÏìӦʱ£¬Ó²¼þÇå¡°0¡±¡£ 171 =2 sbit TR0 = TCON^4; //¶¨Ê±Æ÷T0µÄÔËÐпØÖÆλ 0:Timer0½ûÖ¹¼ÆÊý 1:Timer0¿ªÊ¼¼ÆÊý 172 =2 173 =2 /*SCON*/ 174 =2 sbit SM0 = SCON^7; 175 =2 sbit SM1 = SCON^6; 176 =2 sbit SM2 = SCON^5; 177 =2 sbit REN = SCON^4; 178 =2 sbit TB8 = SCON^3; 179 =2 sbit RB8 = SCON^2; 180 =2 sbit TI = SCON^1; 181 =2 sbit RI = SCON^0; 182 =2 183 =2 /* P0 */ 184 =2 sbit P01 = P0^1; 185 =2 sbit P00 = P0^0; 186 =2 187 =2 /* P1 */ 188 =2 sbit P17 = P1^7; 189 =2 sbit P16 = P1^6; 190 =2 sbit P15 = P1^5; 191 =2 sbit P14 = P1^4; 192 =2 sbit P13 = P1^3; 193 =2 sbit P12 = P1^2; 194 =2 sbit P11 = P1^1; 195 =2 sbit P10 = P1^0; 196 =2 197 =2 /* P2 */ 198 =2 sbit P27 = P2^7; 199 =2 sbit P26 = P2^6; 200 =2 sbit P25 = P2^5; 201 =2 sbit P24 = P2^4; 202 =2 sbit P23 = P2^3; 203 =2 sbit P22 = P2^2; 204 =2 sbit P21 = P2^1; 205 =2 sbit P20 = P2^0; 206 =2 207 =2 #endif 5 =1 6 =1 #define enableInterrupts() EA=1 /** ¿ªÆô×ÜÖÐ¶Ï **/ 7 =1 #define disableInterrupts() EA=0 /** ¹Ø±Õ×ÜÖÐ¶Ï **/ 8 =1 9 =1 #define __I volatile const /*!< defines 'read only' permissions */ 10 =1 #define __O volatile /*!< defines 'write only' permissions */ 11 =1 #define __IO volatile /*!< defines 'read / write' permissions */ 12 =1 13 =1 /*!< Signed integer types */ 14 =1 typedef signed char int8_t; 15 =1 typedef signed short int16_t; 16 =1 typedef signed long int32_t; 17 =1 18 =1 /*!< Unsigned integer types */ 19 =1 typedef unsigned char uint8_t; 20 =1 typedef unsigned short uint16_t; C51 COMPILER V9.60.7.0 SPI 05/13/2024 00:07:49 PAGE 5 21 =1 typedef unsigned long uint32_t; 22 =1 23 =1 typedef int32_t s32; 24 =1 typedef int16_t s16; 25 =1 typedef int8_t s8; 26 =1 27 =1 typedef uint32_t u32; 28 =1 typedef uint16_t u16; 29 =1 typedef uint8_t u8; 30 =1 31 =1 32 =1 typedef enum {FALSE = 0, TRUE = !FALSE} bool; 33 =1 34 =1 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus; 35 =1 36 =1 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 37 =1 38 =1 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; 39 =1 40 =1 typedef enum {LOW = 0, HIGH = !LOW} PriorityStatus; 41 =1 42 =1 #endif 3 #include "intrins.h" 1 =1 /*-------------------------------------------------------------------------- 2 =1 INTRINS.H 3 =1 4 =1 Intrinsic functions for C51. 5 =1 Copyright (c) 1988-2010 Keil Elektronik GmbH and ARM Germany GmbH 6 =1 All rights reserved. 7 =1 --------------------------------------------------------------------------*/ 8 =1 9 =1 #ifndef __INTRINS_H__ 10 =1 #define __INTRINS_H__ 11 =1 12 =1 #pragma SAVE 13 =1 14 =1 #if defined (__CX2__) =1 #pragma FUNCTIONS(STATIC) =1 /* intrinsic functions are reentrant, but need static attribute */ =1 #endif 18 =1 19 =1 extern void _nop_ (void); 20 =1 extern bit _testbit_ (bit); 21 =1 extern unsigned char _cror_ (unsigned char, unsigned char); 22 =1 extern unsigned int _iror_ (unsigned int, unsigned char); 23 =1 extern unsigned long _lror_ (unsigned long, unsigned char); 24 =1 extern unsigned char _crol_ (unsigned char, unsigned char); 25 =1 extern unsigned int _irol_ (unsigned int, unsigned char); 26 =1 extern unsigned long _lrol_ (unsigned long, unsigned char); 27 =1 extern unsigned char _chkfloat_(float); 28 =1 #if defined (__CX2__) =1 extern int abs (int); =1 extern void _illop_ (void); =1 #endif 32 =1 #if !defined (__CX2__) 33 =1 extern void _push_ (unsigned char _sfr); 34 =1 extern void _pop_ (unsigned char _sfr); 35 =1 #endif 36 =1 37 =1 #pragma RESTORE 38 =1 39 =1 #endif C51 COMPILER V9.60.7.0 SPI 05/13/2024 00:07:49 PAGE 6 40 =1 4 5 #include "spi.h" 1 =1 #ifndef _SPI_H_ 2 =1 #define _SPI_H_ 3 =1 unsigned char spiReadWrite(unsigned char Byte); 4 =1 void CS_HIGH(void); 5 =1 void CS_LOW(void); 6 =1 #endif 7 =1 6 #include "spi_cfg.h" 1 =1 #ifndef _SPI_CFG_H_ 2 =1 #define _SPI_CFG_H_ 3 =1 sbit SS = P1^5; 4 =1 sbit SCLK = P1^4; 5 =1 sbit MOSI = P1^2; 6 =1 sbit MISO = P1^3; 7 =1 #endif 8 =1 7 #define Delay10us() {_nop_();_nop_();} 8 //----------------------------------------------------------------------------- 9 10 void CS_HIGH(void) 11 { 12 1 SS = 1; 13 1 } 14 void CS_LOW(void) 15 { 16 1 SS = 0 ; 17 1 } 18 19 unsigned char spiReadWrite(unsigned char Byte) 20 { 21 1 unsigned char i; 22 1 EA = 0; 23 1 for (i = 0; i < 8; i++) 24 1 { 25 2 MOSI = (Byte & 0x80); 26 2 SCLK = 1; 27 2 Delay10us(); 28 2 Byte <<= 1; 29 2 Byte |= MISO; 30 2 SCLK = 0; 31 2 Delay10us(); 32 2 } 33 1 EA = 1; 34 1 35 1 return (Byte); 36 1 } 37 C51 COMPILER V9.60.7.0 SPI 05/13/2024 00:07:49 PAGE 7 ASSEMBLY LISTING OF GENERATED OBJECT CODE ; FUNCTION CS_HIGH (BEGIN) ; SOURCE LINE # 10 ; SOURCE LINE # 11 ; SOURCE LINE # 12 0000 D295 SETB SS ; SOURCE LINE # 13 0002 22 RET ; FUNCTION CS_HIGH (END) ; FUNCTION CS_LOW (BEGIN) ; SOURCE LINE # 14 ; SOURCE LINE # 15 ; SOURCE LINE # 16 0000 C295 CLR SS ; SOURCE LINE # 17 0002 22 RET ; FUNCTION CS_LOW (END) ; FUNCTION _spiReadWrite (BEGIN) ; SOURCE LINE # 19 ;---- Variable 'Byte' assigned to Register 'R7' ---- ; SOURCE LINE # 20 ; SOURCE LINE # 22 0000 C2AF CLR EA ; SOURCE LINE # 23 ;---- Variable 'i' assigned to Register 'R6' ---- 0002 E4 CLR A 0003 FE MOV R6,A 0004 ?C0003: ; SOURCE LINE # 24 ; SOURCE LINE # 25 0004 EF MOV A,R7 0005 33 RLC A 0006 9292 MOV MOSI,C ; SOURCE LINE # 26 0008 D294 SETB SCLK ; SOURCE LINE # 27 000A 00 NOP 000B 00 NOP ; SOURCE LINE # 28 000C EF MOV A,R7 000D 25E0 ADD A,ACC 000F FF MOV R7,A ; SOURCE LINE # 29 0010 A293 MOV C,MISO 0012 E4 CLR A 0013 33 RLC A 0014 4207 ORL AR7,A ; SOURCE LINE # 30 0016 C294 CLR SCLK ; SOURCE LINE # 31 0018 00 NOP 0019 00 NOP ; SOURCE LINE # 32 001A 0E INC R6 001B BE08E6 CJNE R6,#08H,?C0003 001E ?C0004: ; SOURCE LINE # 33 001E D2AF SETB EA C51 COMPILER V9.60.7.0 SPI 05/13/2024 00:07:49 PAGE 8 ; SOURCE LINE # 35 ; SOURCE LINE # 36 0020 22 RET ; FUNCTION _spiReadWrite (END) C51 COMPILER V9.60.7.0 SPI 05/13/2024 00:07:49 PAGE 9 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== uint16_t . . . . . . . . . . . . . . . TYPEDEF ----- U_INT ----- 2 OPREG. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FFH 1 P0 . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0080H 1 SSDAT. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009FH 1 P1 . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0090H 1 P2 . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A0H 1 EUART. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00ACH 1 TMCON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008EH 1 AC . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D6H 1 FlagStatus . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 RESET. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 OTCON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008FH 1 EA . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00AFH 1 T2 . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00C9H 1 int32_t. . . . . . . . . . . . . . . . TYPEDEF ----- LONG ----- 4 PWMCON0. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D2H 1 PWMCON1. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DAH 1 int16_t. . . . . . . . . . . . . . . . TYPEDEF ----- INT ----- 2 ERROR. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 EADC . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00AEH 1 IE . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A8H 1 OPINX. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FEH 1 CP . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00C8H 1 ErrorStatus. . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 EXF2 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CEH 1 CHKSUMH. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FDH 1 CS_HIGH. . . . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- PWMDTY0. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D5H 1 OPERCON. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00EFH 1 PWMDTY1. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D6H 1 P0PH . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009BH 1 IP . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00B8H 1 CHKSUML. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FCH 1 PWMDTY2. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D7H 1 P1PH . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0092H 1 RI . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0098H 1 PWMDTY3. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DCH 1 P2PH . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A2H 1 SUCCESS. . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 CY . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D7H 1 PWMDTY4. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DDH 1 TI . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0099H 1 PWMDTY5. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DEH 1 IPT0 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00B9H 1 PWMDTY6. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DFH 1 FunctionalState. . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 IPT1 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BBH 1 IPT2 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BDH 1 HIGH . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 RCAP2H . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CBH 1 SP . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0081H 1 OV . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D2H 1 SS . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0095H 1 ITStatus . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 IAPADE . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F4H 1 RCAP2L . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CAH 1 ENABLE . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 C51 COMPILER V9.60.7.0 SPI 05/13/2024 00:07:49 PAGE 10 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== BitStatus. . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 IAPADH . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F3H 1 PWMDTYA. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D4H 1 PWMDTYB. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DBH 1 ADCCON . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00ADH 1 s8 . . . . . . . . . . . . . . . . . . TYPEDEF ----- CHAR ----- 1 u8 . . . . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 RCLK . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CDH 1 IAPADL . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F2H 1 SCLK . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0094H 1 bool . . . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 TCLK . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CCH 1 P00. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0080H 1 P10. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0090H 1 P01. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0081H 1 SBUF . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0099H 1 PCON . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0087H 1 P20. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A0H 1 P11. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0091H 1 P21. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A1H 1 P12. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0092H 1 P22. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A2H 1 P13. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0093H 1 SCON . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0098H 1 P23. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A3H 1 P14. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0094H 1 IAPDAT . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F5H 1 TCON . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0088H 1 TMOD . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0089H 1 P24. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A4H 1 P15. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0095H 1 IPINT0 . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00B8H 1 P25. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A5H 1 P16. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0096H 1 IPINT1 . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BAH 1 P26. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A6H 1 P17. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0097H 1 SSCON0 . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009DH 1 MISO . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0093H 1 MOSI . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0092H 1 P27. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A7H 1 SSCON1 . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009EH 1 SSCON2 . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0095H 1 IAPCTL . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F6H 1 IE1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A9H 1 TRUE . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 B. . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F0H 1 IAPKEY . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F1H 1 BTMCON . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CEH 1 PWMCFG . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D1H 1 ACC. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00E0H 1 ET0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A9H 1 TF0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008DH 1 ET1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00ABH 1 ADCCFG0. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00ABH 1 IP1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00B9H 1 TF1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008FH 1 C51 COMPILER V9.60.7.0 SPI 05/13/2024 00:07:49 PAGE 11 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== ET2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00ADH 1 ADCCFG1. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00AAH 1 RB8. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009AH 1 TF2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CFH 1 TH0. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008CH 1 TH1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008DH 1 TB8. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009BH 1 TH2. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CDH 1 uint8_t. . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 P. . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D0H 1 SM0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009FH 1 TL0. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008AH 1 SM1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009EH 1 WDTCON . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CFH 1 TL1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008BH 1 SM2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009DH 1 TL2. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CCH 1 RS0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D3H 1 TR0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008CH 1 RS1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D4H 1 TR1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008EH 1 IPUART . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BCH 1 s32. . . . . . . . . . . . . . . . . . TYPEDEF ----- LONG ----- 4 TR2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CAH 1 int8_t . . . . . . . . . . . . . . . . TYPEDEF ----- CHAR ----- 1 u32. . . . . . . . . . . . . . . . . . TYPEDEF ----- U_LONG ----- 4 s16. . . . . . . . . . . . . . . . . . TYPEDEF ----- INT ----- 2 _spiReadWrite. . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- Byte . . . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 i. . . . . . . . . . . . . . . . . . * REG * DATA U_CHAR 0006H 1 u16. . . . . . . . . . . . . . . . . . TYPEDEF ----- U_INT ----- 2 PWMPRD . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D3H 1 DPH. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0083H 1 DPL. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0082H 1 EINT0. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A8H 1 P0CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009AH 1 EINT1. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00AAH 1 IPADC. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BEH 1 INT0F. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BAH 1 P1CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0091H 1 EXEN2. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CBH 1 INT1F. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BCH 1 P2CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A1H 1 INT2F. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C6H 1 REN. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009CH 1 ADCVH. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00AFH 1 T2MOD. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C9H 1 T2CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C8H 1 CS_LOW . . . . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- ADCVL. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00AEH 1 SET. . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 FALSE. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 INT0R. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BBH 1 INT1R. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BDH 1 PriorityStatus . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 INT2R. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C7H 1 LOW. . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 C51 COMPILER V9.60.7.0 SPI 05/13/2024 00:07:49 PAGE 12 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== F0 . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D5H 1 DISABLE. . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 F1 . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D1H 1 PSW. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D0H 1 uint32_t . . . . . . . . . . . . . . . TYPEDEF ----- U_LONG ----- 4 MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 39 ---- CONSTANT SIZE = ---- ---- XDATA SIZE = ---- ---- PDATA SIZE = ---- ---- DATA SIZE = ---- ---- IDATA SIZE = ---- ---- BIT SIZE = ---- ---- EDATA SIZE = ---- ---- HDATA SIZE = ---- ---- XDATA CONST SIZE = ---- ---- FAR CONST SIZE = ---- ---- END OF MODULE INFORMATION. C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)