C51 COMPILER V9.60.7.0 SC92F8003_UART0 05/13/2024 00:07:51 PAGE 1 C51 COMPILER V9.60.7.0, COMPILATION OF MODULE SC92F8003_UART0 OBJECT MODULE PLACED IN .\Objects\sc92f8003_uart0.obj COMPILER INVOKED BY: d:\Keil\C51\BIN\C51.EXE SC92F8003_Lib\src\sc92f8003_uart0.c OMF2 OPTIMIZE(8,SPEED) BROWSE INCDIR(.\ -Src;.\Task;.\Task\cpu_port\S92F8003A;.\Task\cfg;.\Task\pt_thread;.\SC92F8003_Lib\Inc) DEBUG CODE LISTINCLUDE SYMBOLS PRI -NT(.\Listings\sc92f8003_uart0.lst) PREPRINT(.\Listings\sc92f8003_uart0.i) OBJECT(.\Objects\sc92f8003_uart0.obj) line level source 1 //************************************************************ 2 // Copyright (c) ÉîÛÚÊÐÈüԪ΢µç×ÓÓÐÏÞ¹«Ë¾ 3 // ÎļþÃû³Æ : sc92f8003_uart0.c 4 // ×÷Õß : 5 // Ä£¿é¹¦ÄÜ : UART0¹Ì¼þ¿âº¯ÊýCÎļþ 6 // ¾Ö²¿º¯ÊýÁбí: 7 // ×îºó¸üÕýÈÕÆÚ: 2018/9/4 8 // °æ±¾ : V1.0 9 // ˵Ã÷ £º 10 //************************************************************* 11 12 #include "sc92f8003_uart0.h" 1 =1 //************************************************************ 2 =1 // Copyright (c) ÉîÛÚÊÐÈüԪ΢µç×ÓÓÐÏÞ¹«Ë¾ 3 =1 // ÎļþÃû³Æ : sc92f8003_uart0.h 4 =1 // ×÷Õß : 5 =1 // Ä£¿é¹¦ÄÜ : UART0¹Ì¼þ¿âº¯ÊýÍ·Îļþ 6 =1 // ¾Ö²¿º¯ÊýÁбí: 7 =1 // ×îºó¸üÕýÈÕÆÚ: 2018/9/4 8 =1 // °æ±¾ : V1.0 9 =1 // ˵Ã÷ £º 10 =1 //************************************************************* 11 =1 12 =1 #ifndef __SC92F8003_UART0_H 13 =1 #define __SC92F8003_UART0_H 14 =1 15 =1 #include "sc92f8003.h" 1 =2 #ifndef _SC92F8003_H 2 =2 #define _SC92F8003_H 3 =2 4 =2 #include "SC92F8003_C.H" 1 =3 /*-------------------------------------------------------------------------- 2 =3 SC92F8003_C.H 3 =3 4 =3 C Header file for SC92F8003 microcontroller. 5 =3 Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. 6 =3 All rights reserved. 7 =3 ÉîÛÚÊÐÈüԪ΢µç×ÓÓÐÏÞ¹«Ë¾ 8 =3 °æ±¾ºÅ: V1.0 9 =3 ÈÕÆÚ: 2018.05.02 10 =3 --------------------------------------------------------------------------*/ 11 =3 #ifndef _SC92F8003_H_ 12 =3 #define _SC92F8003_H_ 13 =3 14 =3 /* ------------------- ×ֽڼĴæÆ÷-------------------- */ 15 =3 ///*CPU*/ 16 =3 sfr ACC = 0xE0; //ÀÛ¼ÓÆ÷£Á 17 =3 sfr B = 0xF0; //ͨÓüĴæÆ÷B 18 =3 sfr PSW = 0xD0; //³ÌÐò״̬×Ö 19 =3 sfr DPH = 0x83; //Êý¾ÝÖ¸Õë¸ß8λ 20 =3 sfr DPL = 0x82; //Êý¾ÝÖ¸ÕëµÍ8λ 21 =3 sfr SP = 0x81; //¶ÑÕ»Ö¸Õë 22 =3 C51 COMPILER V9.60.7.0 SC92F8003_UART0 05/13/2024 00:07:51 PAGE 2 23 =3 24 =3 /*system*/ 25 =3 sfr PCON = 0x87; //µçÔ´¹ÜÀí¿ØÖƼĴæÆ÷ 26 =3 27 =3 /*interrupt*/ 28 =3 sfr IP1 = 0XB9; //ÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷1 29 =3 sfr IP = 0xB8; //ÖжÏÓÅÏÈȨ¿ØÖƼĴæÆ÷ 30 =3 sfr IE = 0xA8; //ÖжϿØÖƼĴæÆ÷ 31 =3 sfr IE1 = 0XA9; //ÖжϿØÖƼĴæÆ÷1 32 =3 33 =3 /*PORT*/ 34 =3 sfr P2PH = 0xA2; //P2¿Úģʽ¿ØÖƼĴæÆ÷ 35 =3 sfr P2CON = 0xA1; //P2¿Úģʽ¿ØÖƼĴæÆ÷ 36 =3 sfr P2 = 0xA0; //P2¿ÚÊý¾Ý¼Ä´æÆ÷ 37 =3 sfr P1PH = 0x92; //P1¿Úģʽ¿ØÖƼĴæÆ÷ 38 =3 sfr P1CON = 0x91; //P1¿Úģʽ¿ØÖƼĴæÆ÷ 39 =3 sfr P1 = 0x90; //P1¿ÚÊý¾Ý¼Ä´æÆ÷ 40 =3 sfr P0PH = 0x9B; //P0¿Úģʽ¿ØÖƼĴæÆ÷ 41 =3 sfr P0CON = 0x9A; //P0¿Úģʽ¿ØÖƼĴæÆ÷ 42 =3 sfr P0 = 0x80; //P0¿ÚÊý¾Ý¼Ä´æÆ÷ 43 =3 44 =3 /*TIMER*/ 45 =3 sfr TMCON = 0x8E; //¶¨Ê±Æ÷ƵÂÊ¿ØÖƼĴæÆ÷ 46 =3 sfr TH1 = 0x8D; //¶¨Ê±Æ÷1¸ß8λ 47 =3 sfr TH0 = 0x8C; //¶¨Ê±Æ÷0¸ß8λ 48 =3 sfr TL1 = 0x8B; //¶¨Ê±Æ÷1µÍ8λ 49 =3 sfr TL0 = 0x8A; //¶¨Ê±Æ÷0µÍ8λ 50 =3 sfr TMOD = 0x89; //¶¨Ê±Æ÷¹¤×÷ģʽ¼Ä´æÆ÷ 51 =3 sfr TCON = 0x88; //¶¨Ê±Æ÷¿ØÖƼĴæÆ÷ 52 =3 sfr T2CON = 0xC8; //¶¨Ê±Æ÷2¿ØÖƼĴæÆ÷ 53 =3 sfr T2MOD = 0xC9; //¶¨Ê±Æ÷2¹¤×÷ģʽ¼Ä´æÆ÷ 54 =3 sfr RCAP2L = 0xCA; //¶¨Ê±Æ÷2ÖØÔØ/²¶×½µÍ8λ 55 =3 sfr RCAP2H = 0xCB; //¶¨Ê±Æ÷2ÖØÔØ/²¶×½¸ß8λ 56 =3 sfr TL2 = 0xCC; //¶¨Ê±Æ÷2µÍ8λ 57 =3 sfr TH2 = 0xCD; //¶¨Ê±Æ÷2¸ß8λ 58 =3 59 =3 60 =3 /*ADC*/ 61 =3 sfr ADCCFG1 = 0xAA; //ADC¹¦ÄÜÅäÖüĴæÆ÷0 62 =3 sfr ADCCFG0 = 0xAB; //ADC¹¦ÄÜÅäÖüĴæÆ÷1 63 =3 sfr ADCCON = 0XAD; //ADC¿ØÖƼĴæÆ÷ 64 =3 sfr ADCVL = 0xAE; //ADC ½á¹û¼Ä´æÆ÷ 65 =3 sfr ADCVH = 0xAF; //ADC ½á¹û¼Ä´æÆ÷ 66 =3 67 =3 /*PWM*/ 68 =3 sfr PWMCFG = 0xD1; //PWMÉèÖüĴæÆ÷ 69 =3 sfr PWMCON0 = 0xD2; //PWM¿ØÖƼĴæÆ÷ 70 =3 sfr PWMPRD = 0xD3; //PWMÖÜÆÚÉèÖüĴæÆ÷ 71 =3 sfr PWMDTYA = 0xD4; //PWMÕ¼¿Õ±ÈÉèÖüĴæÆ÷A 72 =3 sfr PWMDTY0 = 0xD5; //PWM0ÉèÖüĴæÆ÷ 73 =3 sfr PWMDTY1 = 0xD6; //PWM1ÉèÖüĴæÆ÷ 74 =3 sfr PWMDTY2 = 0xD7; //PWM2ÉèÖüĴæÆ÷ 75 =3 sfr PWMCON1 = 0xDA; //PWM¿ØÖƼĴæÆ÷ 76 =3 sfr PWMDTYB = 0xDB; //PWMÕ¼¿Õ±ÈÉèÖüĴæÆ÷B 77 =3 sfr PWMDTY3 = 0xDC; //PWM3ÉèÖüĴæÆ÷ 78 =3 sfr PWMDTY4 = 0xDD; //PWM4ÉèÖüĴæÆ÷ 79 =3 sfr PWMDTY5 = 0xDE; //PWM5ÉèÖüĴæÆ÷ 80 =3 sfr PWMDTY6 = 0xDF; //PWM6ÉèÖüĴæÆ÷ 81 =3 82 =3 83 =3 // 84 =3 ///*WatchDog*/ C51 COMPILER V9.60.7.0 SC92F8003_UART0 05/13/2024 00:07:51 PAGE 3 85 =3 sfr BTMCON = 0XCE; //µÍƵ¶¨Ê±Æ÷¿ØÖƼĴæÆ÷ 86 =3 sfr WDTCON = 0xCF; //WDT¿ØÖƼĴæÆ÷ 87 =3 88 =3 89 =3 sfr OTCON = 0X8F; //Êä³ö¿ØÖƼĴæÆ÷ 90 =3 91 =3 /*INT*/ 92 =3 sfr INT0F = 0XBA; //INT0 ϽµÑØÖжϿØÖƼĴæÆ÷ 93 =3 sfr INT0R = 0XBB; //INT0 ÉϽµÑØÖжϿØÖƼĴæÆ÷ 94 =3 sfr INT1F = 0XBC; //INT1 ϽµÑØÖжϿØÖƼĴæÆ÷ 95 =3 sfr INT1R = 0XBD; //INT1 ÉϽµÑØÖжϿØÖƼĴæÆ÷ 96 =3 sfr INT2F = 0XC6; //INT2 ϽµÑØÖжϿØÖƼĴæÆ÷ 97 =3 sfr INT2R = 0XC7; //INT2 ÉϽµÑØÖжϿØÖƼĴæÆ÷ 98 =3 99 =3 /*IAP */ 100 =3 sfr IAPCTL = 0xF6; //IAP¿ØÖƼĴæÆ÷ 101 =3 sfr IAPDAT = 0xF5; //IAPÊý¾Ý¼Ä´æÆ÷ 102 =3 sfr IAPADE = 0xF4; //IAPÀ©Õ¹µØÖ·¼Ä´æÆ÷ 103 =3 sfr IAPADH = 0xF3; //IAPдÈëµØÖ·¸ßλ¼Ä´æÆ÷ 104 =3 sfr IAPADL = 0xF2; //IAPдÈëµØÖ·µÍ8λ¼Ä´æÆ÷ 105 =3 sfr IAPKEY = 0xF1; //IAP±£»¤¼Ä´æÆ÷ 106 =3 107 =3 /*uart0*/ 108 =3 sfr SCON = 0X98; //uart¿ØÖƼĴæÆ÷ 109 =3 sfr SBUF = 0X99; //uart0Êý¾Ý¼Ä´æÆ÷ 110 =3 111 =3 /*ÈýºÏÒ»*/ 112 =3 sfr SSCON0 = 0X9D; //SSI¿ØÖƼĴæÆ÷0 113 =3 sfr SSCON1 = 0X9E; //SSI¿ØÖƼĴæÆ÷1 114 =3 sfr SSCON2 = 0X95; //SSI¿ØÖƼĴæÆ÷2 115 =3 sfr SSDAT = 0X9F; //SSIÊý¾Ý¼Ä´æÆ÷ 116 =3 117 =3 sfr OPINX = 0XFE; 118 =3 sfr OPREG = 0XFF; 119 =3 120 =3 /*Check Sum*/ 121 =3 sfr CHKSUML = 0XFC; //Check Sum½á¹û¼Ä´æÆ÷µÍλ 122 =3 sfr CHKSUMH = 0XFD; //Check Sum½á¹û¼Ä´æÆ÷¸ßλ 123 =3 124 =3 sfr OPERCON = 0xEF; //ÔËËã¿ØÖƼĴæÆ÷ 125 =3 126 =3 ///* ------------------- λ¼Ä´æÆ÷-------------------- */ 127 =3 /*PSW*/ 128 =3 sbit CY = PSW^7; //±ê־λ 0:¼Ó·¨ÔËËã×î¸ßλÎÞ½ø룬»òÕß¼õ·¨ÔËËã×î¸ßλÎÞ½èλʱ 1:¼Ó·¨ÔËËã×î¸ßλÓнø -룬»òÕß¼õ·¨ÔËËã×î¸ßλÓнèλʱ 129 =3 sbit AC = PSW^6; //½øλ¸¨Öú±ê־λ 0:ÎÞ½èλ¡¢½øλ 1:¼Ó·¨ÔËËãʱÔÚbit3λÓнø룬»ò¼õ·¨ÔËËãÔÚbit3λÓн -èλʱ 130 =3 sbit F0 = PSW^5; //Óû§±ê־λ 131 =3 sbit RS1 = PSW^4; //¹¤×÷¼Ä´æÆ÷×éÑ¡Ôñλ 132 =3 sbit RS0 = PSW^3; //¹¤×÷¼Ä´æÆ÷×éÑ¡Ôñλ 133 =3 sbit OV = PSW^2; //Òç³ö±ê־λ 134 =3 sbit F1 = PSW^1; //F1±êÖ¾ 135 =3 sbit P = PSW^0; //Ææż±ê־λ 0:ACCÖÐ1µÄ¸öÊýΪżÊý£¨°üÀ¨0¸ö£© 1:ACCÖÐ1µÄ¸öÊýΪÆæÊý 136 =3 137 =3 /*T2CON*/ 138 =3 sbit TF2 = T2CON^7; 139 =3 sbit EXF2 = T2CON^6; 140 =3 sbit RCLK = T2CON^5; 141 =3 sbit TCLK = T2CON^4; 142 =3 sbit EXEN2 = T2CON^3; 143 =3 sbit TR2 = T2CON^2; 144 =3 sbit T2 = T2CON^1; C51 COMPILER V9.60.7.0 SC92F8003_UART0 05/13/2024 00:07:51 PAGE 4 145 =3 sbit CP = T2CON^0; 146 =3 147 =3 148 =3 /*IP*/ 149 =3 sbit IPADC = IP^6; //ADCÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 ADCµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 ADCµÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß¡ -± 150 =3 sbit IPT2 = IP^5; //PWMÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 PWMµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 PWM µÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß -¡± 151 =3 sbit IPUART = IP^4; //SIFÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 SIFµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 SIFµÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß¡ -± 152 =3 sbit IPT1 = IP^3; //Timer1ÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 Timer 1µÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 Timer 1µÄÖжÏÓÅÏÈÈ -¨ÊÇ ¡°¸ß¡± 153 =3 sbit IPINT1 = IP^2; //32K Base TimerÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 32KµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 32KµÄÖжÏÓÅ -ÏÈȨÊÇ ¡°¸ß¡± 154 =3 sbit IPT0 = IP^1; //Timer0ÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 Timer 0µÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 Timer 0µÄÖжÏÓÅÏÈÈ -¨ÊÇ ¡°¸ß¡± 155 =3 sbit IPINT0 = IP^0; 156 =3 157 =3 /*IE*/ 158 =3 sbit EA = IE^7; //ÖжÏʹÄܵÄ×Ü¿ØÖÆ 0:¹Ø±ÕËùÓеÄÖÐ¶Ï 1:´ò¿ªËùÓеÄÖÐ¶Ï 159 =3 sbit EADC = IE^6; //ADCÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕADCÖÐ¶Ï 1:´ò¿ªADCÖÐ¶Ï 160 =3 sbit ET2 = IE^5; //PWMÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕPWMÖÐ¶Ï 1:´ò¿ªPWMÖÐ¶Ï 161 =3 sbit EUART = IE^4; //UARTÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕSIFÖÐ¶Ï 1:´ò¿ªSIFÖÐ¶Ï 162 =3 sbit ET1 = IE^3; //Timer1ÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTIMER1ÖÐ¶Ï 1:´ò¿ªTIMER1ÖÐ¶Ï 163 =3 sbit EINT1 = IE^2; //32K Base TimerÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±Õ32KÖÐ¶Ï 1:´ò¿ª32KÖÐ¶Ï 164 =3 sbit ET0 = IE^1; //Timer0ÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTIMER0ÖÐ¶Ï 1:´ò¿ªTIMER0ÖÐ¶Ï 165 =3 sbit EINT0 = IE^0; //TouchKeyµÄÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTouchKeyÖÐ¶Ï 1:´ò¿ªTouchKeyÖÐ¶Ï 166 =3 167 =3 /*TCON*/ 168 =3 sbit TF1 = TCON^7; //T1Òç³öÖжÏÇëÇó±ê־λ T1²úÉúÒç³ö£¬·¢ÉúÖжÏʱ£¬Ó²¼þ½«TF1ÖÃΪ¡°1¡±£¬ÉêÇëÖжϣ¬CPU -ÏìӦʱ£¬Ó²¼þÇå¡°0¡±¡£ 169 =3 sbit TR1 = TCON^6; //¶¨Ê±Æ÷T1µÄÔËÐпØÖÆλ 0:Timer1½ûÖ¹¼ÆÊý 1:Timer1¿ªÊ¼¼ÆÊý 170 =3 sbit TF0 = TCON^5; //T0Òç³öÖжÏÇëÇó±ê־λ T0²úÉúÒç³ö£¬·¢ÉúÖжÏʱ£¬Ó²¼þ½«TF0ÖÃΪ¡°1¡±£¬ÉêÇëÖжϣ¬CPU -ÏìӦʱ£¬Ó²¼þÇå¡°0¡±¡£ 171 =3 sbit TR0 = TCON^4; //¶¨Ê±Æ÷T0µÄÔËÐпØÖÆλ 0:Timer0½ûÖ¹¼ÆÊý 1:Timer0¿ªÊ¼¼ÆÊý 172 =3 173 =3 /*SCON*/ 174 =3 sbit SM0 = SCON^7; 175 =3 sbit SM1 = SCON^6; 176 =3 sbit SM2 = SCON^5; 177 =3 sbit REN = SCON^4; 178 =3 sbit TB8 = SCON^3; 179 =3 sbit RB8 = SCON^2; 180 =3 sbit TI = SCON^1; 181 =3 sbit RI = SCON^0; 182 =3 183 =3 /* P0 */ 184 =3 sbit P01 = P0^1; 185 =3 sbit P00 = P0^0; 186 =3 187 =3 /* P1 */ 188 =3 sbit P17 = P1^7; 189 =3 sbit P16 = P1^6; 190 =3 sbit P15 = P1^5; 191 =3 sbit P14 = P1^4; 192 =3 sbit P13 = P1^3; 193 =3 sbit P12 = P1^2; 194 =3 sbit P11 = P1^1; 195 =3 sbit P10 = P1^0; 196 =3 197 =3 /* P2 */ 198 =3 sbit P27 = P2^7; C51 COMPILER V9.60.7.0 SC92F8003_UART0 05/13/2024 00:07:51 PAGE 5 199 =3 sbit P26 = P2^6; 200 =3 sbit P25 = P2^5; 201 =3 sbit P24 = P2^4; 202 =3 sbit P23 = P2^3; 203 =3 sbit P22 = P2^2; 204 =3 sbit P21 = P2^1; 205 =3 sbit P20 = P2^0; 206 =3 207 =3 #endif 5 =2 6 =2 #define enableInterrupts() EA=1 /** ¿ªÆô×ÜÖÐ¶Ï **/ 7 =2 #define disableInterrupts() EA=0 /** ¹Ø±Õ×ÜÖÐ¶Ï **/ 8 =2 9 =2 #define __I volatile const /*!< defines 'read only' permissions */ 10 =2 #define __O volatile /*!< defines 'write only' permissions */ 11 =2 #define __IO volatile /*!< defines 'read / write' permissions */ 12 =2 13 =2 /*!< Signed integer types */ 14 =2 typedef signed char int8_t; 15 =2 typedef signed short int16_t; 16 =2 typedef signed long int32_t; 17 =2 18 =2 /*!< Unsigned integer types */ 19 =2 typedef unsigned char uint8_t; 20 =2 typedef unsigned short uint16_t; 21 =2 typedef unsigned long uint32_t; 22 =2 23 =2 typedef int32_t s32; 24 =2 typedef int16_t s16; 25 =2 typedef int8_t s8; 26 =2 27 =2 typedef uint32_t u32; 28 =2 typedef uint16_t u16; 29 =2 typedef uint8_t u8; 30 =2 31 =2 32 =2 typedef enum {FALSE = 0, TRUE = !FALSE} bool; 33 =2 34 =2 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus; 35 =2 36 =2 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 37 =2 38 =2 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; 39 =2 40 =2 typedef enum {LOW = 0, HIGH = !LOW} PriorityStatus; 41 =2 42 =2 #endif 16 =1 17 =1 #define UART0_BaudRate_FsysDIV12 0X00 //½öģʽ0¿ÉÓ㬴®Ðж˿ÚÔÚϵͳʱÖÓµÄ1/12ÏÂÔËÐÐ 18 =1 #define UART0_BaudRate_FsysDIV4 0X01 //½öģʽ0¿ÉÓ㬴®Ðж˿ÚÔÚϵͳʱÖÓµÄ1/4ÏÂÔËÐÐ 19 =1 20 =1 typedef enum { 21 =1 UART0_PinSelection_P15P16 = (uint8_t)0x00, //UART0Òý½ÅΪP15£¬P16 22 =1 UART0_PinSelection_P11P20 = (uint8_t)0x10 //UART0Òý½ÅΪP11£¬P20 23 =1 } UART0_PinSelection_TypeDef; 24 =1 25 =1 typedef enum { 26 =1 UART0_CLOCK_TIMER1 = (uint8_t)0X00, //TIMER1×ö²¨ÌØÂÊ·¢ÉúÆ÷ 27 =1 UART0_CLOCK_TIMER2 = (uint8_t)0X30 //TIMER2×ö²¨ÌØÂÊ·¢ÉúÆ÷ 28 =1 } UART0_Clock_Typedef; 29 =1 30 =1 typedef enum { C51 COMPILER V9.60.7.0 SC92F8003_UART0 05/13/2024 00:07:51 PAGE 6 31 =1 UART0_Mode_8B = 0X00, //UART¹¤×÷ģʽ£º8λ°ëË«¹¤ 32 =1 UART0_Mode_10B = 0X40, //UART¹¤×÷ģʽ£º10λȫ˫¹¤ 33 =1 UART0_Mode_11B = 0XC0 //UART¹¤×÷ģʽ£º11λȫ˫¹¤ 34 =1 } UART0_Mode_Typedef; 35 =1 36 =1 typedef enum { 37 =1 UART0_RX_ENABLE = 0x10, //ÔÊÐí½ÓÊÕÊý¾Ý 38 =1 UART0_RX_DISABLE = 0x00 //²»ÔÊÐí½ÓÊÕÊý¾Ý 39 =1 } UART0_RX_Typedef; 40 =1 41 =1 typedef enum { 42 =1 UART0_FLAG_RI = 0X01, //½ÓÊÕÖжϱê־λRI 43 =1 UART0_FLAG_TI = 0X02 //·¢ËÍÖжϱê־λTI 44 =1 } UART0_Flag_Typedef; 45 =1 46 =1 void UART0_DeInit(void); 47 =1 void UART0_PinSelection(UART0_PinSelection_TypeDef PinSeletion); 48 =1 void UART0_Init(uint32_t Uart0Fsys, uint32_t BaudRate, UART0_Mode_Typedef Mode, 49 =1 UART0_Clock_Typedef ClockMode, UART0_RX_Typedef RxMode); 50 =1 void UART0_SendData8(uint8_t Data); 51 =1 uint8_t UART0_ReceiveData8(void); 52 =1 void UART0_SendData9(uint16_t Data); 53 =1 uint16_t UART0_ReceiveData9(void); 54 =1 void UART0_ITConfig(FunctionalState NewState, PriorityStatus Priority); 55 =1 FlagStatus UART0_GetFlagStatus(UART0_Flag_Typedef UART0_Flag); 56 =1 void UART0_ClearFlag(UART0_Flag_Typedef UART0_Flag); 57 =1 58 =1 #endif 59 =1 60 =1 /******************* (C) COPYRIGHT 2018 SinOne Microelectronics *****END OF FILE****/ 13 14 /************************************************** 15 *º¯ÊýÃû³Æ£ºvoid UART0_DeInit(void) 16 *º¯Êý¹¦ÄÜ£ºUART0Ïà¹Ø¼Ä´æÆ÷¸´Î»ÖÁȱʡֵ 17 *Èë¿Ú²ÎÊý£ºvoid 18 *³ö¿Ú²ÎÊý£ºvoid 19 **************************************************/ 20 void UART0_DeInit(void) 21 { 22 1 OTCON &= 0XEF; 23 1 SCON = 0X00; 24 1 PCON &= 0X7F; 25 1 IE &= (~0X10); 26 1 IP &= (~0X10); 27 1 } 28 29 /************************************************** 30 *º¯ÊýÃû³Æ£ºUART0_PinSelection(UART0_PinSelection_TypeDef PinSeletion) 31 *º¯Êý¹¦ÄÜ£ºUART0Òý½ÅÑ¡Ôñ 32 *Èë¿Ú²ÎÊý£ºPinSeletion Ñ¡ÔñUART0Òý½ÅΪP15P16»òP11P20 33 *³ö¿Ú²ÎÊý£ºvoid 34 **************************************************/ 35 void UART0_PinSelection(UART0_PinSelection_TypeDef PinSeletion) 36 { 37 1 OTCON = OTCON & 0XDF | PinSeletion; 38 1 } 39 40 /************************************************** 41 *º¯ÊýÃû³Æ£ºvoid UART0_Init(uint32_t Uart0Fsys, uint32_t BaudRate, UART0_Mode_Typedef Mode, 42 UART0_Clock_Typedef ClockMode, UART0_RX_Typedef RxMode) 43 *º¯Êý¹¦ÄÜ£ºUART0³õʼ»¯ÅäÖú¯Êý 44 *Èë¿Ú²ÎÊý£ºUart0Fsys ϵͳʱÖÓƵÂÊ C51 COMPILER V9.60.7.0 SC92F8003_UART0 05/13/2024 00:07:51 PAGE 7 45 BaudRate ²¨ÌØÂÊ(ģʽ0ÏÂÖ»¿ÉÑ¡ÔñUART0_BaudRate_FsysDIV12»òUART0_BaudRate_FsysDIV4) 46 Mode UART0¹¤×÷ģʽ 47 ClockMode ²¨ÌØÂÊʱÖÓÔ´£¨TIMER1/TIMER2£© 48 RxMode ½ÓÊÕÔÊÐíÑ¡Ôñ 49 *³ö¿Ú²ÎÊý£ºvoid 50 **************************************************/ 51 void UART0_Init(uint32_t Uart0Fsys, uint32_t BaudRate, UART0_Mode_Typedef Mode, 52 UART0_Clock_Typedef ClockMode, UART0_RX_Typedef RxMode) 53 { 54 1 SCON = (SCON & 0X2F) | Mode | RxMode; //ÉèÖÃUART¹¤×÷ģʽ,ÉèÖýÓÊÕÔÊÐíλ 55 1 56 1 if(Mode == UART0_Mode_8B) 57 1 { 58 2 if(BaudRate == UART0_BaudRate_FsysDIV12) 59 2 { 60 3 PCON &= 0X7F; 61 3 } 62 2 else if(BaudRate == UART0_BaudRate_FsysDIV4) 63 2 { 64 3 PCON |= 0X80; 65 3 } 66 2 } 67 1 68 1 else 69 1 { 70 2 T2CON = (T2CON & 0xCF) | ClockMode; //ÉèÖò¨ÌØÂÊʱÖÓÔ´ 71 2 if(ClockMode == UART0_CLOCK_TIMER1) 72 2 { 73 3 TH1 = (Uart0Fsys / BaudRate) / 256; 74 3 TL1 = (Uart0Fsys / BaudRate) % 256; 75 3 TR1 = 0; 76 3 } 77 2 else if(ClockMode == UART0_CLOCK_TIMER2) 78 2 { 79 3 RCAP2H = (Uart0Fsys / BaudRate) / 256; 80 3 RCAP2L = (Uart0Fsys / BaudRate) % 256; 81 3 TR2 = 1; 82 3 } 83 2 } 84 1 } 85 86 /***************************************************** 87 *º¯ÊýÃû³Æ£ºvoid UART0_SendData8(uint8_t Data) 88 *º¯Êý¹¦ÄÜ£ºUART0·¢ËÍ8λÊý¾Ý 89 *Èë¿Ú²ÎÊý£ºuint8_t Data ·¢Ë͵ÄÊý¾Ý 90 *³ö¿Ú²ÎÊý£ºvoid 91 *****************************************************/ 92 void UART0_SendData8(uint8_t Data) 93 { 94 1 SBUF = Data; 95 1 } 96 97 /************************************************** 98 *º¯ÊýÃû³Æ£ºuint8_t UART0_ReceiveData8(void) 99 *º¯Êý¹¦ÄÜ£º»ñµÃSBUFÖеÄÖµ 100 *Èë¿Ú²ÎÊý£ºvoid 101 *³ö¿Ú²ÎÊý£ºuint8_t 102 **************************************************/ 103 uint8_t UART0_ReceiveData8(void) 104 { 105 1 return SBUF; 106 1 } C51 COMPILER V9.60.7.0 SC92F8003_UART0 05/13/2024 00:07:51 PAGE 8 107 108 /***************************************************** 109 *º¯ÊýÃû³Æ£ºvoid UART0_SendData9(uint16_t Data) 110 *º¯Êý¹¦ÄÜ£ºUART0·¢ËÍ9λÊý¾Ý 111 *Èë¿Ú²ÎÊý£ºuint16_t Data ·¢Ë͵ÄÊý¾Ý 112 *³ö¿Ú²ÎÊý£ºvoid 113 *****************************************************/ 114 void UART0_SendData9(uint16_t Data) 115 { 116 1 uint8_t Data_9Bit; 117 1 Data_9Bit = (Data >> 8); 118 1 if(Data_9Bit) 119 1 { 120 2 SCON |= 0X08; 121 2 } 122 1 else 123 1 { 124 2 SCON &= 0XF7; 125 2 } 126 1 SBUF = (uint8_t)Data; 127 1 } 128 129 /************************************************** 130 *º¯ÊýÃû³Æ£ºuint16_t UART0_ReceiveData9(void) 131 *º¯Êý¹¦ÄÜ£º»ñµÃSBUFÖеÄÖµ¼°µÚ¾ÅλµÄÖµ 132 *Èë¿Ú²ÎÊý£ºvoid 133 *³ö¿Ú²ÎÊý£ºuint16_t 134 **************************************************/ 135 uint16_t UART0_ReceiveData9(void) 136 { 137 1 uint16_t Data9; 138 1 Data9 = SBUF + ((uint16_t)(SCON & 0X04) << 6); 139 1 SCON &= 0XFB; 140 1 return Data9; 141 1 } 142 143 /***************************************************** 144 *º¯ÊýÃû³Æ£ºvoid UART0_ITConfig(FunctionalState NewState, PriorityStatus Priority) 145 *º¯Êý¹¦ÄÜ£ºUART0Öжϳõʼ»¯ 146 *Èë¿Ú²ÎÊý£ºFunctionalState NewState ÖжÏʹÄÜ/¹Ø±ÕÑ¡Ôñ 147 PriorityStatus Priority ÖжÏÓÅÏȼ¶Ñ¡Ôñ 148 *³ö¿Ú²ÎÊý£ºvoid 149 *****************************************************/ 150 void UART0_ITConfig(FunctionalState NewState, PriorityStatus Priority) 151 { 152 1 //ÖжÏʹÄÜ/¹Ø±ÕÉèÖà 153 1 if(NewState == DISABLE) 154 1 { 155 2 EUART = 0; 156 2 } 157 1 else 158 1 { 159 2 EUART = 1; 160 2 } 161 1 162 1 //ÖжÏÓÅÏȼ¶ÉèÖà 163 1 if(Priority == LOW) 164 1 { 165 2 IPUART = 0; 166 2 } 167 1 else 168 1 { C51 COMPILER V9.60.7.0 SC92F8003_UART0 05/13/2024 00:07:51 PAGE 9 169 2 IPUART = 1; 170 2 } 171 1 } 172 173 /***************************************************** 174 *º¯ÊýÃû³Æ£ºFlagStatus UART0_GetFlagStatus(UART0_Flag_Typedef UART0_Flag) 175 *º¯Êý¹¦ÄÜ£º»ñµÃUART0Öжϱê־״̬ 176 *Èë¿Ú²ÎÊý£ºUART0_Flag Öжϱê־λѡÔñ 177 *³ö¿Ú²ÎÊý£ºFlagStatus UART0Öжϱê־״̬ 178 *****************************************************/ 179 FlagStatus UART0_GetFlagStatus(UART0_Flag_Typedef UART0_Flag) 180 { 181 1 return (FlagStatus)(SCON & UART0_Flag); 182 1 } 183 184 /***************************************************** 185 *º¯ÊýÃû³Æ£ºvoid UART0_ClearFlag(UART0_Flag_Typedef UART0_Flag) 186 *º¯Êý¹¦ÄÜ£ºÇå³ýUART0Öжϱê־״̬ 187 *Èë¿Ú²ÎÊý£ºUART0_Flag Öжϱê־λѡÔñ 188 *³ö¿Ú²ÎÊý£ºvoid 189 *****************************************************/ 190 void UART0_ClearFlag(UART0_Flag_Typedef UART0_Flag) 191 { 192 1 SCON &= (~UART0_Flag); 193 1 } 194 195 /******************* (C) COPYRIGHT 2018 SinOne Microelectronics *****END OF FILE****/ C51 COMPILER V9.60.7.0 SC92F8003_UART0 05/13/2024 00:07:51 PAGE 10 ASSEMBLY LISTING OF GENERATED OBJECT CODE ; FUNCTION UART0_DeInit (BEGIN) ; SOURCE LINE # 20 ; SOURCE LINE # 21 ; SOURCE LINE # 22 0000 538FEF ANL OTCON,#0EFH ; SOURCE LINE # 23 0003 E4 CLR A 0004 F598 MOV SCON,A ; SOURCE LINE # 24 0006 53877F ANL PCON,#07FH ; SOURCE LINE # 25 0009 53A8EF ANL IE,#0EFH ; SOURCE LINE # 26 000C 53B8EF ANL IP,#0EFH ; SOURCE LINE # 27 000F 22 RET ; FUNCTION UART0_DeInit (END) ; FUNCTION _UART0_PinSelection (BEGIN) ; SOURCE LINE # 35 ;---- Variable 'PinSeletion' assigned to Register 'R7' ---- ; SOURCE LINE # 36 ; SOURCE LINE # 37 0000 E58F MOV A,OTCON 0002 54DF ANL A,#0DFH 0004 4F ORL A,R7 0005 F58F MOV OTCON,A ; SOURCE LINE # 38 0007 22 RET ; FUNCTION _UART0_PinSelection (END) ; FUNCTION _UART0_Init (BEGIN) ; SOURCE LINE # 51 0000 8F00 R MOV Uart0Fsys+03H,R7 0002 8E00 R MOV Uart0Fsys+02H,R6 0004 8D00 R MOV Uart0Fsys+01H,R5 0006 8C00 R MOV Uart0Fsys,R4 ; SOURCE LINE # 53 ; SOURCE LINE # 54 0008 E598 MOV A,SCON 000A 542F ANL A,#02FH 000C 4500 R ORL A,Mode 000E 4500 R ORL A,RxMode 0010 F598 MOV SCON,A ; SOURCE LINE # 56 0012 E500 R MOV A,Mode 0014 7031 JNZ ?C0003 ; SOURCE LINE # 57 ; SOURCE LINE # 58 0016 FF MOV R7,A 0017 FE MOV R6,A 0018 FD MOV R5,A 0019 FC MOV R4,A 001A AB00 R MOV R3,BaudRate+03H 001C AA00 R MOV R2,BaudRate+02H 001E A900 R MOV R1,BaudRate+01H 0020 A800 R MOV R0,BaudRate 0022 C3 CLR C 0023 120000 E LCALL ?C?ULCMP C51 COMPILER V9.60.7.0 SC92F8003_UART0 05/13/2024 00:07:51 PAGE 11 0026 7004 JNZ ?C0004 ; SOURCE LINE # 59 ; SOURCE LINE # 60 0028 53877F ANL PCON,#07FH ; SOURCE LINE # 61 002B 22 RET 002C ?C0004: ; SOURCE LINE # 62 002C E4 CLR A 002D 7F01 MOV R7,#01H 002F FE MOV R6,A 0030 FD MOV R5,A 0031 FC MOV R4,A 0032 AB00 R MOV R3,BaudRate+03H 0034 AA00 R MOV R2,BaudRate+02H 0036 A900 R MOV R1,BaudRate+01H 0038 A800 R MOV R0,BaudRate 003A C3 CLR C 003B 120000 E LCALL ?C?ULCMP 003E 6003 JZ $ + 5H 0040 020000 R LJMP ?C0011 ; SOURCE LINE # 63 ; SOURCE LINE # 64 0043 438780 ORL PCON,#080H ; SOURCE LINE # 65 ; SOURCE LINE # 66 0046 22 RET 0047 ?C0003: ; SOURCE LINE # 69 ; SOURCE LINE # 70 0047 E5C8 MOV A,T2CON 0049 54CF ANL A,#0CFH 004B 4500 R ORL A,ClockMode 004D F5C8 MOV T2CON,A ; SOURCE LINE # 71 004F E500 R MOV A,ClockMode 0051 7036 JNZ ?C0008 ; SOURCE LINE # 72 ; SOURCE LINE # 73 0053 AB00 R MOV R3,BaudRate+03H 0055 AA00 R MOV R2,BaudRate+02H 0057 A900 R MOV R1,BaudRate+01H 0059 A800 R MOV R0,BaudRate 005B AF00 R MOV R7,Uart0Fsys+03H 005D AE00 R MOV R6,Uart0Fsys+02H 005F AD00 R MOV R5,Uart0Fsys+01H 0061 AC00 R MOV R4,Uart0Fsys 0063 120000 E LCALL ?C?ULDIV 0066 E4 CLR A 0067 FB MOV R3,A 0068 7A01 MOV R2,#01H 006A F9 MOV R1,A 006B F8 MOV R0,A 006C 120000 E LCALL ?C?ULDIV 006F 8F8D MOV TH1,R7 ; SOURCE LINE # 74 0071 AB00 R MOV R3,BaudRate+03H 0073 AA00 R MOV R2,BaudRate+02H 0075 A900 R MOV R1,BaudRate+01H 0077 A800 R MOV R0,BaudRate 0079 AF00 R MOV R7,Uart0Fsys+03H 007B AE00 R MOV R6,Uart0Fsys+02H C51 COMPILER V9.60.7.0 SC92F8003_UART0 05/13/2024 00:07:51 PAGE 12 007D AD00 R MOV R5,Uart0Fsys+01H 007F AC00 R MOV R4,Uart0Fsys 0081 120000 E LCALL ?C?ULDIV 0084 8F8B MOV TL1,R7 ; SOURCE LINE # 75 0086 C28E CLR TR1 ; SOURCE LINE # 76 0088 22 RET 0089 ?C0008: ; SOURCE LINE # 77 0089 E500 R MOV A,ClockMode 008B 6430 XRL A,#030H 008D 7035 JNZ ?C0011 ; SOURCE LINE # 78 ; SOURCE LINE # 79 008F AB00 R MOV R3,BaudRate+03H 0091 AA00 R MOV R2,BaudRate+02H 0093 A900 R MOV R1,BaudRate+01H 0095 A800 R MOV R0,BaudRate 0097 AF00 R MOV R7,Uart0Fsys+03H 0099 AE00 R MOV R6,Uart0Fsys+02H 009B AD00 R MOV R5,Uart0Fsys+01H 009D AC00 R MOV R4,Uart0Fsys 009F 120000 E LCALL ?C?ULDIV 00A2 E4 CLR A 00A3 FB MOV R3,A 00A4 7A01 MOV R2,#01H 00A6 F9 MOV R1,A 00A7 F8 MOV R0,A 00A8 120000 E LCALL ?C?ULDIV 00AB 8FCB MOV RCAP2H,R7 ; SOURCE LINE # 80 00AD AB00 R MOV R3,BaudRate+03H 00AF AA00 R MOV R2,BaudRate+02H 00B1 A900 R MOV R1,BaudRate+01H 00B3 A800 R MOV R0,BaudRate 00B5 AF00 R MOV R7,Uart0Fsys+03H 00B7 AE00 R MOV R6,Uart0Fsys+02H 00B9 AD00 R MOV R5,Uart0Fsys+01H 00BB AC00 R MOV R4,Uart0Fsys 00BD 120000 E LCALL ?C?ULDIV 00C0 8FCA MOV RCAP2L,R7 ; SOURCE LINE # 81 00C2 D2CA SETB TR2 ; SOURCE LINE # 82 ; SOURCE LINE # 83 ; SOURCE LINE # 84 00C4 ?C0011: 00C4 22 RET ; FUNCTION _UART0_Init (END) ; FUNCTION _UART0_SendData8 (BEGIN) ; SOURCE LINE # 92 ;---- Variable 'Data' assigned to Register 'R7' ---- ; SOURCE LINE # 93 ; SOURCE LINE # 94 0000 8F99 MOV SBUF,R7 ; SOURCE LINE # 95 0002 22 RET ; FUNCTION _UART0_SendData8 (END) ; FUNCTION UART0_ReceiveData8 (BEGIN) C51 COMPILER V9.60.7.0 SC92F8003_UART0 05/13/2024 00:07:51 PAGE 13 ; SOURCE LINE # 103 ; SOURCE LINE # 104 ; SOURCE LINE # 105 0000 AF99 MOV R7,SBUF ; SOURCE LINE # 106 0002 22 RET ; FUNCTION UART0_ReceiveData8 (END) ; FUNCTION _UART0_SendData9 (BEGIN) ; SOURCE LINE # 114 ;---- Variable 'Data' assigned to Register 'R4/R5' ---- 0000 AD07 MOV R5,AR7 0002 AC06 MOV R4,AR6 ; SOURCE LINE # 115 ; SOURCE LINE # 117 ;---- Variable 'Data_9Bit' assigned to Register 'R7' ---- ; SOURCE LINE # 118 0004 EC MOV A,R4 0005 6005 JZ ?C0014 ; SOURCE LINE # 119 ; SOURCE LINE # 120 0007 439808 ORL SCON,#08H ; SOURCE LINE # 121 000A 8003 SJMP ?C0015 000C ?C0014: ; SOURCE LINE # 123 ; SOURCE LINE # 124 000C 5398F7 ANL SCON,#0F7H ; SOURCE LINE # 125 000F ?C0015: ; SOURCE LINE # 126 000F 8D99 MOV SBUF,R5 ; SOURCE LINE # 127 0011 22 RET ; FUNCTION _UART0_SendData9 (END) ; FUNCTION UART0_ReceiveData9 (BEGIN) ; SOURCE LINE # 135 ; SOURCE LINE # 136 ; SOURCE LINE # 138 0000 E598 MOV A,SCON 0002 5404 ANL A,#04H 0004 75F040 MOV B,#040H 0007 A4 MUL AB 0008 AD99 MOV R5,SBUF 000A 7C00 MOV R4,#00H 000C 2D ADD A,R5 000D FF MOV R7,A 000E EC MOV A,R4 000F 35F0 ADDC A,B 0011 FE MOV R6,A ;---- Variable 'Data9' assigned to Register 'R6/R7' ---- ; SOURCE LINE # 139 0012 5398FB ANL SCON,#0FBH ; SOURCE LINE # 140 ; SOURCE LINE # 141 0015 22 RET ; FUNCTION UART0_ReceiveData9 (END) ; FUNCTION _UART0_ITConfig (BEGIN) ; SOURCE LINE # 150 ;---- Variable 'Priority' assigned to Register 'R5' ---- C51 COMPILER V9.60.7.0 SC92F8003_UART0 05/13/2024 00:07:51 PAGE 14 ;---- Variable 'NewState' assigned to Register 'R7' ---- ; SOURCE LINE # 151 ; SOURCE LINE # 153 0000 EF MOV A,R7 0001 7004 JNZ ?C0018 ; SOURCE LINE # 154 ; SOURCE LINE # 155 0003 C2AC CLR EUART ; SOURCE LINE # 156 0005 8002 SJMP ?C0019 0007 ?C0018: ; SOURCE LINE # 158 ; SOURCE LINE # 159 0007 D2AC SETB EUART ; SOURCE LINE # 160 0009 ?C0019: ; SOURCE LINE # 163 0009 ED MOV A,R5 000A 7003 JNZ ?C0020 ; SOURCE LINE # 164 ; SOURCE LINE # 165 000C C2BC CLR IPUART ; SOURCE LINE # 166 000E 22 RET 000F ?C0020: ; SOURCE LINE # 168 ; SOURCE LINE # 169 000F D2BC SETB IPUART ; SOURCE LINE # 170 ; SOURCE LINE # 171 0011 ?C0022: 0011 22 RET ; FUNCTION _UART0_ITConfig (END) ; FUNCTION _UART0_GetFlagStatus (BEGIN) ; SOURCE LINE # 179 ;---- Variable 'UART0_Flag' assigned to Register 'R7' ---- ; SOURCE LINE # 180 ; SOURCE LINE # 181 0000 E598 MOV A,SCON 0002 5F ANL A,R7 0003 FF MOV R7,A ; SOURCE LINE # 182 0004 22 RET ; FUNCTION _UART0_GetFlagStatus (END) ; FUNCTION _UART0_ClearFlag (BEGIN) ; SOURCE LINE # 190 ;---- Variable 'UART0_Flag' assigned to Register 'R7' ---- ; SOURCE LINE # 191 ; SOURCE LINE # 192 0000 EF MOV A,R7 0001 F4 CPL A 0002 5298 ANL SCON,A ; SOURCE LINE # 193 0004 22 RET ; FUNCTION _UART0_ClearFlag (END) C51 COMPILER V9.60.7.0 SC92F8003_UART0 05/13/2024 00:07:51 PAGE 15 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== uint16_t . . . . . . . . . . . . . . . TYPEDEF ----- U_INT ----- 2 OPREG. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FFH 1 P0 . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0080H 1 UART0_Flag_Typedef . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 SSDAT. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009FH 1 P1 . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0090H 1 P2 . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A0H 1 UART0_RX_ENABLE. . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 EUART. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00ACH 1 TMCON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008EH 1 AC . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D6H 1 FlagStatus . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 RESET. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 OTCON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008FH 1 EA . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00AFH 1 T2 . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00C9H 1 int32_t. . . . . . . . . . . . . . . . TYPEDEF ----- LONG ----- 4 PWMCON0. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D2H 1 PWMCON1. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DAH 1 int16_t. . . . . . . . . . . . . . . . TYPEDEF ----- INT ----- 2 UART0_Mode_Typedef . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 ERROR. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 EADC . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00AEH 1 IE . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A8H 1 UART0_DeInit . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- _UART0_SendData8 . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- Data . . . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 OPINX. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FEH 1 _UART0_SendData9 . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- Data . . . . . . . . . . . . . . . . * REG * DATA U_INT 0004H 2 Data_9Bit. . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 CP . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00C8H 1 ErrorStatus. . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 EXF2 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CEH 1 CHKSUMH. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FDH 1 PWMDTY0. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D5H 1 OPERCON. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00EFH 1 PWMDTY1. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D6H 1 P0PH . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009BH 1 IP . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00B8H 1 CHKSUML. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FCH 1 PWMDTY2. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D7H 1 P1PH . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0092H 1 RI . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0098H 1 PWMDTY3. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DCH 1 P2PH . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A2H 1 SUCCESS. . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 CY . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D7H 1 PWMDTY4. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DDH 1 TI . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0099H 1 PWMDTY5. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DEH 1 IPT0 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00B9H 1 PWMDTY6. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DFH 1 FunctionalState. . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 IPT1 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BBH 1 IPT2 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BDH 1 HIGH . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 C51 COMPILER V9.60.7.0 SC92F8003_UART0 05/13/2024 00:07:51 PAGE 16 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== RCAP2H . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CBH 1 SP . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0081H 1 _UART0_PinSelection. . . . . . . . . . PUBLIC CODE PROC 0000H ----- PinSeletion. . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 OV . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D2H 1 ITStatus . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 IAPADE . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F4H 1 RCAP2L . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CAH 1 ENABLE . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 BitStatus. . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 IAPADH . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F3H 1 PWMDTYA. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D4H 1 PWMDTYB. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DBH 1 ADCCON . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00ADH 1 s8 . . . . . . . . . . . . . . . . . . TYPEDEF ----- CHAR ----- 1 u8 . . . . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 RCLK . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CDH 1 IAPADL . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F2H 1 bool . . . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 UART0_RX_Typedef . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 TCLK . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CCH 1 UART0_Mode_8B. . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 P00. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0080H 1 P10. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0090H 1 P01. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0081H 1 SBUF . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0099H 1 PCON . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0087H 1 P20. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A0H 1 P11. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0091H 1 P21. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A1H 1 P12. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0092H 1 P22. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A2H 1 P13. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0093H 1 SCON . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0098H 1 _UART0_ClearFlag . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- UART0_Flag . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 P23. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A3H 1 P14. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0094H 1 IAPDAT . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F5H 1 TCON . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0088H 1 TMOD . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0089H 1 P24. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A4H 1 P15. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0095H 1 IPINT0 . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00B8H 1 P25. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A5H 1 P16. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0096H 1 IPINT1 . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BAH 1 P26. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A6H 1 P17. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0097H 1 SSCON0 . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009DH 1 P27. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A7H 1 SSCON1 . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009EH 1 UART0_PinSelection_TypeDef . . . . . . TYPEDEF ----- U_CHAR ----- 1 SSCON2 . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0095H 1 IAPCTL . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F6H 1 IE1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A9H 1 TRUE . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 C51 COMPILER V9.60.7.0 SC92F8003_UART0 05/13/2024 00:07:51 PAGE 17 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== B. . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F0H 1 IAPKEY . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F1H 1 BTMCON . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CEH 1 _UART0_ITConfig. . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- NewState . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 Priority . . . . . . . . . . . . . . * REG * DATA U_CHAR 0005H 1 PWMCFG . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D1H 1 ACC. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00E0H 1 ET0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A9H 1 TF0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008DH 1 ET1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00ABH 1 ADCCFG0. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00ABH 1 IP1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00B9H 1 UART0_ReceiveData8 . . . . . . . . . . PUBLIC CODE PROC 0000H ----- TF1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008FH 1 ET2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00ADH 1 ADCCFG1. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00AAH 1 UART0_ReceiveData9 . . . . . . . . . . PUBLIC CODE PROC 0000H ----- Data9. . . . . . . . . . . . . . . . * REG * DATA U_INT 0006H 2 RB8. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009AH 1 TF2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CFH 1 TH0. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008CH 1 TH1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008DH 1 TB8. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009BH 1 TH2. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CDH 1 uint8_t. . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 P. . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D0H 1 UART0_RX_DISABLE . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SM0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009FH 1 TL0. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008AH 1 UART0_CLOCK_TIMER1 . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SM1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009EH 1 WDTCON . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CFH 1 TL1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008BH 1 UART0_CLOCK_TIMER2 . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SM2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009DH 1 TL2. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CCH 1 RS0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D3H 1 TR0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008CH 1 RS1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D4H 1 TR1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008EH 1 IPUART . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BCH 1 s32. . . . . . . . . . . . . . . . . . TYPEDEF ----- LONG ----- 4 TR2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CAH 1 UART0_Mode_10B . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 int8_t . . . . . . . . . . . . . . . . TYPEDEF ----- CHAR ----- 1 UART0_Mode_11B . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 u32. . . . . . . . . . . . . . . . . . TYPEDEF ----- U_LONG ----- 4 s16. . . . . . . . . . . . . . . . . . TYPEDEF ----- INT ----- 2 u16. . . . . . . . . . . . . . . . . . TYPEDEF ----- U_INT ----- 2 PWMPRD . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D3H 1 DPH. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0083H 1 DPL. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0082H 1 EINT0. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A8H 1 P0CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009AH 1 EINT1. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00AAH 1 IPADC. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BEH 1 C51 COMPILER V9.60.7.0 SC92F8003_UART0 05/13/2024 00:07:51 PAGE 18 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== INT0F. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BAH 1 P1CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0091H 1 EXEN2. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CBH 1 INT1F. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BCH 1 P2CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A1H 1 _UART0_Init. . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- Uart0Fsys. . . . . . . . . . . . . . AUTO DATA U_LONG 0000H 4 BaudRate . . . . . . . . . . . . . . AUTO DATA U_LONG 0004H 4 Mode . . . . . . . . . . . . . . . . AUTO DATA U_CHAR 0008H 1 ClockMode. . . . . . . . . . . . . . AUTO DATA U_CHAR 0009H 1 RxMode . . . . . . . . . . . . . . . AUTO DATA U_CHAR 000AH 1 INT2F. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C6H 1 UART0_FLAG_RI. . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 REN. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009CH 1 UART0_FLAG_TI. . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 ADCVH. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00AFH 1 T2MOD. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C9H 1 T2CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C8H 1 UART0_PinSelection_P11P20. . . . . . . E_CONST ----- U_CHAR ----- 1 ADCVL. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00AEH 1 SET. . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 FALSE. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 INT0R. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BBH 1 INT1R. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BDH 1 PriorityStatus . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 INT2R. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C7H 1 LOW. . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 UART0_Clock_Typedef. . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 UART0_PinSelection_P15P16. . . . . . . E_CONST ----- U_CHAR ----- 1 _UART0_GetFlagStatus . . . . . . . . . PUBLIC CODE PROC 0000H ----- UART0_Flag . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 F0 . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D5H 1 DISABLE. . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 F1 . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D1H 1 PSW. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D0H 1 uint32_t . . . . . . . . . . . . . . . TYPEDEF ----- U_LONG ----- 4 MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 295 ---- CONSTANT SIZE = ---- ---- XDATA SIZE = ---- ---- PDATA SIZE = ---- ---- DATA SIZE = ---- 11 IDATA SIZE = ---- ---- BIT SIZE = ---- ---- EDATA SIZE = ---- ---- HDATA SIZE = ---- ---- XDATA CONST SIZE = ---- ---- FAR CONST SIZE = ---- ---- END OF MODULE INFORMATION. C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)