C51 COMPILER V9.60.7.0 SC92F8003_TIMER0 05/13/2024 00:07:50 PAGE 1 C51 COMPILER V9.60.7.0, COMPILATION OF MODULE SC92F8003_TIMER0 OBJECT MODULE PLACED IN .\Objects\sc92f8003_timer0.obj COMPILER INVOKED BY: d:\Keil\C51\BIN\C51.EXE SC92F8003_Lib\src\sc92f8003_timer0.c OMF2 OPTIMIZE(8,SPEED) BROWSE INCDIR(. -\Src;.\Task;.\Task\cpu_port\S92F8003A;.\Task\cfg;.\Task\pt_thread;.\SC92F8003_Lib\Inc) DEBUG CODE LISTINCLUDE SYMBOLS PR -INT(.\Listings\sc92f8003_timer0.lst) PREPRINT(.\Listings\sc92f8003_timer0.i) OBJECT(.\Objects\sc92f8003_timer0.obj) line level source 1 //************************************************************ 2 // Copyright (c) ÉîÛÚÊÐÈüԪ΢µç×ÓÓÐÏÞ¹«Ë¾ 3 // ÎļþÃû³Æ : sc92f8003_timer0.c 4 // ×÷Õß : 5 // Ä£¿é¹¦ÄÜ : TIMER0¹Ì¼þ¿âº¯ÊýCÎļþ 6 // ¾Ö²¿º¯ÊýÁбí: 7 // ×îºó¸üÕýÈÕÆÚ: 2018/9/4 8 // °æ±¾ : V1.0 9 // ˵Ã÷ £º 10 //************************************************************* 11 12 #include "sc92f8003_timer0.h" 1 =1 //************************************************************ 2 =1 // Copyright (c) ÉîÛÚÊÐÈüԪ΢µç×ÓÓÐÏÞ¹«Ë¾ 3 =1 // ÎļþÃû³Æ : sc92f8003_timer0.h 4 =1 // ×÷Õß : 5 =1 // Ä£¿é¹¦ÄÜ : TIMER0¹Ì¼þ¿âº¯ÊýÍ·Îļþ 6 =1 // ¾Ö²¿º¯ÊýÁбí: 7 =1 // ×îºó¸üÕýÈÕÆÚ: 2018/9/4 8 =1 // °æ±¾ : V1.0 9 =1 // ˵Ã÷ £º 10 =1 //************************************************************* 11 =1 12 =1 #ifndef _SC92F8003_TIMER0_H_ 13 =1 #define _SC92F8003_TIMER0_H_ 14 =1 15 =1 #include "sc92f8003.h" 1 =2 #ifndef _SC92F8003_H 2 =2 #define _SC92F8003_H 3 =2 4 =2 #include "SC92F8003_C.H" 1 =3 /*-------------------------------------------------------------------------- 2 =3 SC92F8003_C.H 3 =3 4 =3 C Header file for SC92F8003 microcontroller. 5 =3 Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. 6 =3 All rights reserved. 7 =3 ÉîÛÚÊÐÈüԪ΢µç×ÓÓÐÏÞ¹«Ë¾ 8 =3 °æ±¾ºÅ: V1.0 9 =3 ÈÕÆÚ: 2018.05.02 10 =3 --------------------------------------------------------------------------*/ 11 =3 #ifndef _SC92F8003_H_ 12 =3 #define _SC92F8003_H_ 13 =3 14 =3 /* ------------------- ×ֽڼĴæÆ÷-------------------- */ 15 =3 ///*CPU*/ 16 =3 sfr ACC = 0xE0; //ÀÛ¼ÓÆ÷£Á 17 =3 sfr B = 0xF0; //ͨÓüĴæÆ÷B 18 =3 sfr PSW = 0xD0; //³ÌÐò״̬×Ö 19 =3 sfr DPH = 0x83; //Êý¾ÝÖ¸Õë¸ß8λ 20 =3 sfr DPL = 0x82; //Êý¾ÝÖ¸ÕëµÍ8λ 21 =3 sfr SP = 0x81; //¶ÑÕ»Ö¸Õë 22 =3 C51 COMPILER V9.60.7.0 SC92F8003_TIMER0 05/13/2024 00:07:50 PAGE 2 23 =3 24 =3 /*system*/ 25 =3 sfr PCON = 0x87; //µçÔ´¹ÜÀí¿ØÖƼĴæÆ÷ 26 =3 27 =3 /*interrupt*/ 28 =3 sfr IP1 = 0XB9; //ÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷1 29 =3 sfr IP = 0xB8; //ÖжÏÓÅÏÈȨ¿ØÖƼĴæÆ÷ 30 =3 sfr IE = 0xA8; //ÖжϿØÖƼĴæÆ÷ 31 =3 sfr IE1 = 0XA9; //ÖжϿØÖƼĴæÆ÷1 32 =3 33 =3 /*PORT*/ 34 =3 sfr P2PH = 0xA2; //P2¿Úģʽ¿ØÖƼĴæÆ÷ 35 =3 sfr P2CON = 0xA1; //P2¿Úģʽ¿ØÖƼĴæÆ÷ 36 =3 sfr P2 = 0xA0; //P2¿ÚÊý¾Ý¼Ä´æÆ÷ 37 =3 sfr P1PH = 0x92; //P1¿Úģʽ¿ØÖƼĴæÆ÷ 38 =3 sfr P1CON = 0x91; //P1¿Úģʽ¿ØÖƼĴæÆ÷ 39 =3 sfr P1 = 0x90; //P1¿ÚÊý¾Ý¼Ä´æÆ÷ 40 =3 sfr P0PH = 0x9B; //P0¿Úģʽ¿ØÖƼĴæÆ÷ 41 =3 sfr P0CON = 0x9A; //P0¿Úģʽ¿ØÖƼĴæÆ÷ 42 =3 sfr P0 = 0x80; //P0¿ÚÊý¾Ý¼Ä´æÆ÷ 43 =3 44 =3 /*TIMER*/ 45 =3 sfr TMCON = 0x8E; //¶¨Ê±Æ÷ƵÂÊ¿ØÖƼĴæÆ÷ 46 =3 sfr TH1 = 0x8D; //¶¨Ê±Æ÷1¸ß8λ 47 =3 sfr TH0 = 0x8C; //¶¨Ê±Æ÷0¸ß8λ 48 =3 sfr TL1 = 0x8B; //¶¨Ê±Æ÷1µÍ8λ 49 =3 sfr TL0 = 0x8A; //¶¨Ê±Æ÷0µÍ8λ 50 =3 sfr TMOD = 0x89; //¶¨Ê±Æ÷¹¤×÷ģʽ¼Ä´æÆ÷ 51 =3 sfr TCON = 0x88; //¶¨Ê±Æ÷¿ØÖƼĴæÆ÷ 52 =3 sfr T2CON = 0xC8; //¶¨Ê±Æ÷2¿ØÖƼĴæÆ÷ 53 =3 sfr T2MOD = 0xC9; //¶¨Ê±Æ÷2¹¤×÷ģʽ¼Ä´æÆ÷ 54 =3 sfr RCAP2L = 0xCA; //¶¨Ê±Æ÷2ÖØÔØ/²¶×½µÍ8λ 55 =3 sfr RCAP2H = 0xCB; //¶¨Ê±Æ÷2ÖØÔØ/²¶×½¸ß8λ 56 =3 sfr TL2 = 0xCC; //¶¨Ê±Æ÷2µÍ8λ 57 =3 sfr TH2 = 0xCD; //¶¨Ê±Æ÷2¸ß8λ 58 =3 59 =3 60 =3 /*ADC*/ 61 =3 sfr ADCCFG1 = 0xAA; //ADC¹¦ÄÜÅäÖüĴæÆ÷0 62 =3 sfr ADCCFG0 = 0xAB; //ADC¹¦ÄÜÅäÖüĴæÆ÷1 63 =3 sfr ADCCON = 0XAD; //ADC¿ØÖƼĴæÆ÷ 64 =3 sfr ADCVL = 0xAE; //ADC ½á¹û¼Ä´æÆ÷ 65 =3 sfr ADCVH = 0xAF; //ADC ½á¹û¼Ä´æÆ÷ 66 =3 67 =3 /*PWM*/ 68 =3 sfr PWMCFG = 0xD1; //PWMÉèÖüĴæÆ÷ 69 =3 sfr PWMCON0 = 0xD2; //PWM¿ØÖƼĴæÆ÷ 70 =3 sfr PWMPRD = 0xD3; //PWMÖÜÆÚÉèÖüĴæÆ÷ 71 =3 sfr PWMDTYA = 0xD4; //PWMÕ¼¿Õ±ÈÉèÖüĴæÆ÷A 72 =3 sfr PWMDTY0 = 0xD5; //PWM0ÉèÖüĴæÆ÷ 73 =3 sfr PWMDTY1 = 0xD6; //PWM1ÉèÖüĴæÆ÷ 74 =3 sfr PWMDTY2 = 0xD7; //PWM2ÉèÖüĴæÆ÷ 75 =3 sfr PWMCON1 = 0xDA; //PWM¿ØÖƼĴæÆ÷ 76 =3 sfr PWMDTYB = 0xDB; //PWMÕ¼¿Õ±ÈÉèÖüĴæÆ÷B 77 =3 sfr PWMDTY3 = 0xDC; //PWM3ÉèÖüĴæÆ÷ 78 =3 sfr PWMDTY4 = 0xDD; //PWM4ÉèÖüĴæÆ÷ 79 =3 sfr PWMDTY5 = 0xDE; //PWM5ÉèÖüĴæÆ÷ 80 =3 sfr PWMDTY6 = 0xDF; //PWM6ÉèÖüĴæÆ÷ 81 =3 82 =3 83 =3 // 84 =3 ///*WatchDog*/ C51 COMPILER V9.60.7.0 SC92F8003_TIMER0 05/13/2024 00:07:50 PAGE 3 85 =3 sfr BTMCON = 0XCE; //µÍƵ¶¨Ê±Æ÷¿ØÖƼĴæÆ÷ 86 =3 sfr WDTCON = 0xCF; //WDT¿ØÖƼĴæÆ÷ 87 =3 88 =3 89 =3 sfr OTCON = 0X8F; //Êä³ö¿ØÖƼĴæÆ÷ 90 =3 91 =3 /*INT*/ 92 =3 sfr INT0F = 0XBA; //INT0 ϽµÑØÖжϿØÖƼĴæÆ÷ 93 =3 sfr INT0R = 0XBB; //INT0 ÉϽµÑØÖжϿØÖƼĴæÆ÷ 94 =3 sfr INT1F = 0XBC; //INT1 ϽµÑØÖжϿØÖƼĴæÆ÷ 95 =3 sfr INT1R = 0XBD; //INT1 ÉϽµÑØÖжϿØÖƼĴæÆ÷ 96 =3 sfr INT2F = 0XC6; //INT2 ϽµÑØÖжϿØÖƼĴæÆ÷ 97 =3 sfr INT2R = 0XC7; //INT2 ÉϽµÑØÖжϿØÖƼĴæÆ÷ 98 =3 99 =3 /*IAP */ 100 =3 sfr IAPCTL = 0xF6; //IAP¿ØÖƼĴæÆ÷ 101 =3 sfr IAPDAT = 0xF5; //IAPÊý¾Ý¼Ä´æÆ÷ 102 =3 sfr IAPADE = 0xF4; //IAPÀ©Õ¹µØÖ·¼Ä´æÆ÷ 103 =3 sfr IAPADH = 0xF3; //IAPдÈëµØÖ·¸ßλ¼Ä´æÆ÷ 104 =3 sfr IAPADL = 0xF2; //IAPдÈëµØÖ·µÍ8λ¼Ä´æÆ÷ 105 =3 sfr IAPKEY = 0xF1; //IAP±£»¤¼Ä´æÆ÷ 106 =3 107 =3 /*uart0*/ 108 =3 sfr SCON = 0X98; //uart¿ØÖƼĴæÆ÷ 109 =3 sfr SBUF = 0X99; //uart0Êý¾Ý¼Ä´æÆ÷ 110 =3 111 =3 /*ÈýºÏÒ»*/ 112 =3 sfr SSCON0 = 0X9D; //SSI¿ØÖƼĴæÆ÷0 113 =3 sfr SSCON1 = 0X9E; //SSI¿ØÖƼĴæÆ÷1 114 =3 sfr SSCON2 = 0X95; //SSI¿ØÖƼĴæÆ÷2 115 =3 sfr SSDAT = 0X9F; //SSIÊý¾Ý¼Ä´æÆ÷ 116 =3 117 =3 sfr OPINX = 0XFE; 118 =3 sfr OPREG = 0XFF; 119 =3 120 =3 /*Check Sum*/ 121 =3 sfr CHKSUML = 0XFC; //Check Sum½á¹û¼Ä´æÆ÷µÍλ 122 =3 sfr CHKSUMH = 0XFD; //Check Sum½á¹û¼Ä´æÆ÷¸ßλ 123 =3 124 =3 sfr OPERCON = 0xEF; //ÔËËã¿ØÖƼĴæÆ÷ 125 =3 126 =3 ///* ------------------- λ¼Ä´æÆ÷-------------------- */ 127 =3 /*PSW*/ 128 =3 sbit CY = PSW^7; //±ê־λ 0:¼Ó·¨ÔËËã×î¸ßλÎÞ½ø룬»òÕß¼õ·¨ÔËËã×î¸ßλÎÞ½èλʱ 1:¼Ó·¨ÔËËã×î¸ßλÓнø -룬»òÕß¼õ·¨ÔËËã×î¸ßλÓнèλʱ 129 =3 sbit AC = PSW^6; //½øλ¸¨Öú±ê־λ 0:ÎÞ½èλ¡¢½øλ 1:¼Ó·¨ÔËËãʱÔÚbit3λÓнø룬»ò¼õ·¨ÔËËãÔÚbit3λÓн -èλʱ 130 =3 sbit F0 = PSW^5; //Óû§±ê־λ 131 =3 sbit RS1 = PSW^4; //¹¤×÷¼Ä´æÆ÷×éÑ¡Ôñλ 132 =3 sbit RS0 = PSW^3; //¹¤×÷¼Ä´æÆ÷×éÑ¡Ôñλ 133 =3 sbit OV = PSW^2; //Òç³ö±ê־λ 134 =3 sbit F1 = PSW^1; //F1±êÖ¾ 135 =3 sbit P = PSW^0; //Ææż±ê־λ 0:ACCÖÐ1µÄ¸öÊýΪżÊý£¨°üÀ¨0¸ö£© 1:ACCÖÐ1µÄ¸öÊýΪÆæÊý 136 =3 137 =3 /*T2CON*/ 138 =3 sbit TF2 = T2CON^7; 139 =3 sbit EXF2 = T2CON^6; 140 =3 sbit RCLK = T2CON^5; 141 =3 sbit TCLK = T2CON^4; 142 =3 sbit EXEN2 = T2CON^3; 143 =3 sbit TR2 = T2CON^2; 144 =3 sbit T2 = T2CON^1; C51 COMPILER V9.60.7.0 SC92F8003_TIMER0 05/13/2024 00:07:50 PAGE 4 145 =3 sbit CP = T2CON^0; 146 =3 147 =3 148 =3 /*IP*/ 149 =3 sbit IPADC = IP^6; //ADCÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 ADCµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 ADCµÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß¡ -± 150 =3 sbit IPT2 = IP^5; //PWMÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 PWMµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 PWM µÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß -¡± 151 =3 sbit IPUART = IP^4; //SIFÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 SIFµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 SIFµÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß¡ -± 152 =3 sbit IPT1 = IP^3; //Timer1ÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 Timer 1µÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 Timer 1µÄÖжÏÓÅÏÈÈ -¨ÊÇ ¡°¸ß¡± 153 =3 sbit IPINT1 = IP^2; //32K Base TimerÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 32KµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 32KµÄÖжÏÓÅ -ÏÈȨÊÇ ¡°¸ß¡± 154 =3 sbit IPT0 = IP^1; //Timer0ÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 Timer 0µÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 Timer 0µÄÖжÏÓÅÏÈÈ -¨ÊÇ ¡°¸ß¡± 155 =3 sbit IPINT0 = IP^0; 156 =3 157 =3 /*IE*/ 158 =3 sbit EA = IE^7; //ÖжÏʹÄܵÄ×Ü¿ØÖÆ 0:¹Ø±ÕËùÓеÄÖÐ¶Ï 1:´ò¿ªËùÓеÄÖÐ¶Ï 159 =3 sbit EADC = IE^6; //ADCÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕADCÖÐ¶Ï 1:´ò¿ªADCÖÐ¶Ï 160 =3 sbit ET2 = IE^5; //PWMÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕPWMÖÐ¶Ï 1:´ò¿ªPWMÖÐ¶Ï 161 =3 sbit EUART = IE^4; //UARTÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕSIFÖÐ¶Ï 1:´ò¿ªSIFÖÐ¶Ï 162 =3 sbit ET1 = IE^3; //Timer1ÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTIMER1ÖÐ¶Ï 1:´ò¿ªTIMER1ÖÐ¶Ï 163 =3 sbit EINT1 = IE^2; //32K Base TimerÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±Õ32KÖÐ¶Ï 1:´ò¿ª32KÖÐ¶Ï 164 =3 sbit ET0 = IE^1; //Timer0ÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTIMER0ÖÐ¶Ï 1:´ò¿ªTIMER0ÖÐ¶Ï 165 =3 sbit EINT0 = IE^0; //TouchKeyµÄÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTouchKeyÖÐ¶Ï 1:´ò¿ªTouchKeyÖÐ¶Ï 166 =3 167 =3 /*TCON*/ 168 =3 sbit TF1 = TCON^7; //T1Òç³öÖжÏÇëÇó±ê־λ T1²úÉúÒç³ö£¬·¢ÉúÖжÏʱ£¬Ó²¼þ½«TF1ÖÃΪ¡°1¡±£¬ÉêÇëÖжϣ¬CPU -ÏìӦʱ£¬Ó²¼þÇå¡°0¡±¡£ 169 =3 sbit TR1 = TCON^6; //¶¨Ê±Æ÷T1µÄÔËÐпØÖÆλ 0:Timer1½ûÖ¹¼ÆÊý 1:Timer1¿ªÊ¼¼ÆÊý 170 =3 sbit TF0 = TCON^5; //T0Òç³öÖжÏÇëÇó±ê־λ T0²úÉúÒç³ö£¬·¢ÉúÖжÏʱ£¬Ó²¼þ½«TF0ÖÃΪ¡°1¡±£¬ÉêÇëÖжϣ¬CPU -ÏìӦʱ£¬Ó²¼þÇå¡°0¡±¡£ 171 =3 sbit TR0 = TCON^4; //¶¨Ê±Æ÷T0µÄÔËÐпØÖÆλ 0:Timer0½ûÖ¹¼ÆÊý 1:Timer0¿ªÊ¼¼ÆÊý 172 =3 173 =3 /*SCON*/ 174 =3 sbit SM0 = SCON^7; 175 =3 sbit SM1 = SCON^6; 176 =3 sbit SM2 = SCON^5; 177 =3 sbit REN = SCON^4; 178 =3 sbit TB8 = SCON^3; 179 =3 sbit RB8 = SCON^2; 180 =3 sbit TI = SCON^1; 181 =3 sbit RI = SCON^0; 182 =3 183 =3 /* P0 */ 184 =3 sbit P01 = P0^1; 185 =3 sbit P00 = P0^0; 186 =3 187 =3 /* P1 */ 188 =3 sbit P17 = P1^7; 189 =3 sbit P16 = P1^6; 190 =3 sbit P15 = P1^5; 191 =3 sbit P14 = P1^4; 192 =3 sbit P13 = P1^3; 193 =3 sbit P12 = P1^2; 194 =3 sbit P11 = P1^1; 195 =3 sbit P10 = P1^0; 196 =3 197 =3 /* P2 */ 198 =3 sbit P27 = P2^7; C51 COMPILER V9.60.7.0 SC92F8003_TIMER0 05/13/2024 00:07:50 PAGE 5 199 =3 sbit P26 = P2^6; 200 =3 sbit P25 = P2^5; 201 =3 sbit P24 = P2^4; 202 =3 sbit P23 = P2^3; 203 =3 sbit P22 = P2^2; 204 =3 sbit P21 = P2^1; 205 =3 sbit P20 = P2^0; 206 =3 207 =3 #endif 5 =2 6 =2 #define enableInterrupts() EA=1 /** ¿ªÆô×ÜÖÐ¶Ï **/ 7 =2 #define disableInterrupts() EA=0 /** ¹Ø±Õ×ÜÖÐ¶Ï **/ 8 =2 9 =2 #define __I volatile const /*!< defines 'read only' permissions */ 10 =2 #define __O volatile /*!< defines 'write only' permissions */ 11 =2 #define __IO volatile /*!< defines 'read / write' permissions */ 12 =2 13 =2 /*!< Signed integer types */ 14 =2 typedef signed char int8_t; 15 =2 typedef signed short int16_t; 16 =2 typedef signed long int32_t; 17 =2 18 =2 /*!< Unsigned integer types */ 19 =2 typedef unsigned char uint8_t; 20 =2 typedef unsigned short uint16_t; 21 =2 typedef unsigned long uint32_t; 22 =2 23 =2 typedef int32_t s32; 24 =2 typedef int16_t s16; 25 =2 typedef int8_t s8; 26 =2 27 =2 typedef uint32_t u32; 28 =2 typedef uint16_t u16; 29 =2 typedef uint8_t u8; 30 =2 31 =2 32 =2 typedef enum {FALSE = 0, TRUE = !FALSE} bool; 33 =2 34 =2 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus; 35 =2 36 =2 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 37 =2 38 =2 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; 39 =2 40 =2 typedef enum {LOW = 0, HIGH = !LOW} PriorityStatus; 41 =2 42 =2 #endif 16 =1 17 =1 typedef enum { 18 =1 TIM0_PRESSEL_FSYS_D12 = ((uint8_t)0x00), //TIMER0¼ÆÊýÔ´À´×ÔϵͳʱÖÓ12·ÖƵ 19 =1 TIM0_PRESSEL_FSYS_D1 = ((uint8_t)0x01) //TIMER0¼ÆÊýÔ´À´×ÔϵͳʱÖÓ 20 =1 }TIM0_PresSel_TypeDef; 21 =1 22 =1 typedef enum { 23 =1 TIM0_MODE_TIMER = ((uint8_t)0x01), //TIMER0×ö¶¨Ê±Æ÷ 24 =1 TIM0_MODE_COUNTER = ((uint8_t)0x02) //TIMER0×ö¼ÆÊýÆ÷ 25 =1 }TIM0_CountMode_TypeDef; 26 =1 27 =1 void TIM0_DeInit(void); 28 =1 void TIM0_TimeBaseInit(TIM0_PresSel_TypeDef TIM0_PrescalerSelection,TIM0_CountMode_TypeDef TIM0_CountMode) -; 29 =1 void TIM0_WorkMode0Config(uint16_t TIM0_SetCounter); C51 COMPILER V9.60.7.0 SC92F8003_TIMER0 05/13/2024 00:07:50 PAGE 6 30 =1 void TIM0_WorkMode1Config(uint16_t TIM0_SetCounter); 31 =1 void TIM0_WorkMode2Config(uint8_t TIM0_SetCounter); 32 =1 void TIM0_WorkMode3Config(uint8_t TIM0_SetCounter, uint8_t TIM1_SetCounter); 33 =1 void TIM0_Mode0SetReloadCounter(uint16_t TIM0_SetCounter); 34 =1 void TIM0_Mode1SetReloadCounter(uint16_t TIM0_SetCounter); 35 =1 void TIM0_SetTL0Counter(uint8_t TIM0_SetCounter); 36 =1 void TIM0_SetTH0Counter(uint8_t TIM0_SetCounter); 37 =1 void TIM0_Cmd(FunctionalState NewState); 38 =1 void TIM0_ITConfig(FunctionalState NewState, PriorityStatus Priority); 39 =1 FlagStatus TIM0_GetFlagStatus(void); 40 =1 void TIM0_ClearFlag(void); 41 =1 42 =1 #endif 43 =1 44 =1 /******************* (C) COPYRIGHT 2018 SinOne Microelectronics *****END OF FILE****/ 13 14 /************************************************** 15 *º¯ÊýÃû³Æ£ºvoid TIM0_DeInit(void) 16 *º¯Êý¹¦ÄÜ£ºTIMER0Ïà¹Ø¼Ä´æÆ÷¸´Î»ÖÁȱʡֵ 17 *Èë¿Ú²ÎÊý£ºvoid 18 *³ö¿Ú²ÎÊý£ºvoid 19 **************************************************/ 20 void TIM0_DeInit(void) 21 { 22 1 TMOD &= 0XF0; 23 1 TCON &= 0XCD; 24 1 TMCON &=0XFE; 25 1 TH0 = 0X00; 26 1 TL0 = 0X00; 27 1 ET0 = 0; 28 1 IPT0 = 0; 29 1 } 30 31 /************************************************** 32 *º¯ÊýÃû³Æ£ºvoid TIM0_TimeBaseInit(TIM0_PresSel_TypeDef TIM0_PrescalerSelection, TIM0_CountMode_TypeDef TIM -0_CountMode) 33 *º¯Êý¹¦ÄÜ£ºTIMER0»ù±¾ÉèÖÃÅäÖú¯Êý 34 *Èë¿Ú²ÎÊý£ºTIM0_PrescalerSelection Ô¤·ÖƵѡÔñ 35 TIM0_CountMode ¼ÆÊý/¶¨Ê±Ä£Ê½Ñ¡Ôñ 36 *³ö¿Ú²ÎÊý£ºvoid 37 **************************************************/ 38 void TIM0_TimeBaseInit(TIM0_PresSel_TypeDef TIM0_PrescalerSelection, TIM0_CountMode_TypeDef TIM0_CountMode -) 39 { 40 1 //Ô¤·ÖƵѡÔñ 41 1 if(TIM0_PrescalerSelection == TIM0_PRESSEL_FSYS_D12) 42 1 { 43 2 TMCON &= 0XFE; 44 2 } 45 1 else if(TIM0_PrescalerSelection == TIM0_PRESSEL_FSYS_D1) 46 1 { 47 2 TMCON |= 0X01; 48 2 } 49 1 50 1 //¶¨Ê±/¼ÆÊýģʽѡÔñ 51 1 if(TIM0_CountMode == TIM0_MODE_TIMER) 52 1 { 53 2 TMOD &= 0xFB; 54 2 } 55 1 else if(TIM0_CountMode == TIM0_MODE_COUNTER) 56 1 { 57 2 TMOD |= 0x04; C51 COMPILER V9.60.7.0 SC92F8003_TIMER0 05/13/2024 00:07:50 PAGE 7 58 2 } 59 1 } 60 61 /************************************************** 62 *º¯ÊýÃû³Æ£ºvoid TIM0_WorkMode0Config(uint16_t TIM0_SetCounter) 63 *º¯Êý¹¦ÄÜ£ºTIMER0¹¤×÷ģʽ0ÅäÖú¯Êý 64 *Èë¿Ú²ÎÊý£ºuint16_t TIM0_SetCounter ÅäÖüÆÊý³õÖµ 65 *³ö¿Ú²ÎÊý£ºvoid 66 **************************************************/ 67 void TIM0_WorkMode0Config(uint16_t TIM0_SetCounter) 68 { 69 1 TMOD &= 0XFC; 70 1 TL0 = (uint8_t)TIM0_SetCounter; 71 1 TH0 = (TIM0_SetCounter >> 5); 72 1 } 73 74 /************************************************** 75 *º¯ÊýÃû³Æ£ºvoid TIM0_WorkMode1Config(uint16_t TIM0_SetCounter) 76 *º¯Êý¹¦ÄÜ£ºTIMER0¹¤×÷ģʽ1ÅäÖú¯Êý 77 *Èë¿Ú²ÎÊý£ºuint16_t TIM0_SetCounter ÅäÖüÆÊý³õÖµ 78 *³ö¿Ú²ÎÊý£ºvoid 79 **************************************************/ 80 void TIM0_WorkMode1Config(uint16_t TIM0_SetCounter) 81 { 82 1 TMOD &= 0XFC; 83 1 TMOD |= 0X01; 84 1 TL0 = TIM0_SetCounter % 256; 85 1 TH0 = TIM0_SetCounter / 256; 86 1 } 87 88 /************************************************** 89 *º¯ÊýÃû³Æ£ºvoid TIM0_WorkMode2Config(uint8_t TIM0_SetCounter) 90 *º¯Êý¹¦ÄÜ£ºTIMER0¹¤×÷ģʽ2ÅäÖú¯Êý 91 *Èë¿Ú²ÎÊý£ºuint8_t TIM0_SetCounter ÅäÖüÆÊý³õÖµ 92 *³ö¿Ú²ÎÊý£ºvoid 93 **************************************************/ 94 void TIM0_WorkMode2Config(uint8_t TIM0_SetCounter) 95 { 96 1 TMOD &= 0XFC; 97 1 TMOD |= 0X02; 98 1 TL0 = TIM0_SetCounter; 99 1 TH0 = TIM0_SetCounter; 100 1 } 101 102 /************************************************** 103 *º¯ÊýÃû³Æ£ºvoid TIM0_WorkMode3Config(uint8_t TIM0_SetCounter, uint8_t TIM1_SetCounter) 104 *º¯Êý¹¦ÄÜ£ºTIMER0¹¤×÷ģʽ3ÅäÖú¯Êý 105 *Èë¿Ú²ÎÊý£ºuint8_t TIM0_SetCounter ÅäÖÃTIMER0_TL0¼ÆÊý³õÖµ 106 uint8_t TIM1_SetCounter ÅäÖÃTIMER0_TH0¼ÆÊý³õÖµ 107 *³ö¿Ú²ÎÊý£ºvoid 108 **************************************************/ 109 void TIM0_WorkMode3Config(uint8_t TIM0_SetCounter, uint8_t TIM1_SetCounter) 110 { 111 1 TMOD |= 0X03; 112 1 TL0 = TIM0_SetCounter; 113 1 TH0 = TIM1_SetCounter; 114 1 } 115 116 /************************************************** 117 *º¯ÊýÃû³Æ£ºvoid TIM0_Mode0SetReloadCounter(uint16_t TIM0_SetCounter) 118 *º¯Êý¹¦ÄÜ£ºTIMER0¹¤×÷ģʽ0³õÖµÖØÔغ¯Êý 119 *Èë¿Ú²ÎÊý£ºuint16_t TIM0_SetCounter ÅäÖÃTIMER0ÖØÔØÖµ C51 COMPILER V9.60.7.0 SC92F8003_TIMER0 05/13/2024 00:07:50 PAGE 8 120 *³ö¿Ú²ÎÊý£ºvoid 121 **************************************************/ 122 void TIM0_Mode0SetReloadCounter(uint16_t TIM0_SetCounter) 123 { 124 1 TL0 = (uint8_t)TIM0_SetCounter; 125 1 TH0 = (TIM0_SetCounter >> 5); 126 1 } 127 128 /************************************************** 129 *º¯ÊýÃû³Æ£ºvoid TIM0_Mode1SetReloadCounter(uint16_t TIM0_SetCounter) 130 *º¯Êý¹¦ÄÜ£ºTIMER0¹¤×÷ģʽ1³õÖµÖØÔغ¯Êý 131 *Èë¿Ú²ÎÊý£ºuint16_t TIM0_SetCounter ÅäÖÃTIMER0ÖØÔØÖµ 132 *³ö¿Ú²ÎÊý£ºvoid 133 **************************************************/ 134 void TIM0_Mode1SetReloadCounter(uint16_t TIM0_SetCounter) 135 { 136 1 TL0 = TIM0_SetCounter % 256; 137 1 TH0 = TIM0_SetCounter / 256; 138 1 } 139 140 /************************************************** 141 *º¯ÊýÃû³Æ£ºvoid TIM0_SetTL0Counter(uint8_t TIM0_SetCounter) 142 *º¯Êý¹¦ÄÜ£ºTIMER0 TL0¸³Öµº¯Êý 143 *Èë¿Ú²ÎÊý£ºuint8_t TIM0_SetCounter ÅäÖÃTL0 144 *³ö¿Ú²ÎÊý£ºvoid 145 **************************************************/ 146 void TIM0_SetTL0Counter(uint8_t TIM0_SetCounter) 147 { 148 1 TL0 = TIM0_SetCounter; 149 1 } 150 151 /************************************************** 152 *º¯ÊýÃû³Æ£ºvoid TIM0_SetTH0Counter(uint8_t TIM0_SetCounter) 153 *º¯Êý¹¦ÄÜ£ºTIMER0 TH0¸³Öµº¯Êý 154 *Èë¿Ú²ÎÊý£ºuint8_t TIM0_SetCounter ÅäÖÃTH0 155 *³ö¿Ú²ÎÊý£ºvoid 156 **************************************************/ 157 void TIM0_SetTH0Counter(uint8_t TIM0_SetCounter) 158 { 159 1 TH0 = TIM0_SetCounter; 160 1 } 161 162 /***************************************************** 163 *º¯ÊýÃû³Æ£ºvoid TIM0_Cmd(FunctionalState NewState) 164 *º¯Êý¹¦ÄÜ£ºTIMER0¹¦ÄÜ¿ª¹Øº¯Êý 165 *Èë¿Ú²ÎÊý£ºFunctionalState NewState ¹¦ÄÜÆô¶¯/¹Ø±ÕÑ¡Ôñ 166 *³ö¿Ú²ÎÊý£ºvoid 167 *****************************************************/ 168 void TIM0_Cmd(FunctionalState NewState) 169 { 170 1 if (NewState == DISABLE) 171 1 { 172 2 TR0 = 0; 173 2 } 174 1 else 175 1 { 176 2 TR0 = 1; 177 2 } 178 1 } 179 180 /***************************************************** 181 *º¯ÊýÃû³Æ£ºvoid TIM0_ITConfig(FunctionalState NewState, PriorityStatus Priority) C51 COMPILER V9.60.7.0 SC92F8003_TIMER0 05/13/2024 00:07:50 PAGE 9 182 *º¯Êý¹¦ÄÜ£ºTIMER0Öжϳõʼ»¯ 183 *Èë¿Ú²ÎÊý£ºFunctionalState NewState ÖжÏʹÄÜ/¹Ø±ÕÑ¡Ôñ 184 PriorityStatus Priority ÖжÏÓÅÏȼ¶Ñ¡Ôñ 185 *³ö¿Ú²ÎÊý£ºvoid 186 *****************************************************/ 187 void TIM0_ITConfig(FunctionalState NewState, PriorityStatus Priority) 188 { 189 1 //ÖжÏʹÄÜ/¹Ø±ÕÉèÖà 190 1 if(NewState == DISABLE) 191 1 { 192 2 ET0 = 0; 193 2 } 194 1 else 195 1 { 196 2 ET0 = 1; 197 2 } 198 1 199 1 //ÖжÏÓÅÏȼ¶ÉèÖà 200 1 if(Priority == LOW) 201 1 { 202 2 IPT0 = 0; 203 2 } 204 1 else 205 1 { 206 2 IPT0 = 1; 207 2 } 208 1 } 209 210 /***************************************************** 211 *º¯ÊýÃû³Æ£ºFlagStatus TIM0_GetFlagStatus(void) 212 *º¯Êý¹¦ÄÜ£º»ñµÃTIMER0Öжϱê־״̬ 213 *Èë¿Ú²ÎÊý£ºvoid 214 *³ö¿Ú²ÎÊý£ºFlagStatus TIMER0Öжϱê־״̬ 215 *****************************************************/ 216 FlagStatus TIM0_GetFlagStatus(void) 217 { 218 1 return TF0; 219 1 } 220 221 /***************************************************** 222 *º¯ÊýÃû³Æ£ºvoid TIM0_ClearFlag(void) 223 *º¯Êý¹¦ÄÜ£ºÇå³ýTIMER0Öжϱê־״̬ 224 *Èë¿Ú²ÎÊý£ºvoid 225 *³ö¿Ú²ÎÊý£ºvoid 226 *****************************************************/ 227 void TIM0_ClearFlag(void) 228 { 229 1 TF0 = 0; 230 1 } 231 232 /******************* (C) COPYRIGHT 2018 SinOne Microelectronics *****END OF FILE****/ C51 COMPILER V9.60.7.0 SC92F8003_TIMER0 05/13/2024 00:07:50 PAGE 10 ASSEMBLY LISTING OF GENERATED OBJECT CODE ; FUNCTION TIM0_DeInit (BEGIN) ; SOURCE LINE # 20 ; SOURCE LINE # 21 ; SOURCE LINE # 22 0000 5389F0 ANL TMOD,#0F0H ; SOURCE LINE # 23 0003 5388CD ANL TCON,#0CDH ; SOURCE LINE # 24 0006 538EFE ANL TMCON,#0FEH ; SOURCE LINE # 25 0009 E4 CLR A 000A F58C MOV TH0,A ; SOURCE LINE # 26 000C F58A MOV TL0,A ; SOURCE LINE # 27 000E C2A9 CLR ET0 ; SOURCE LINE # 28 0010 C2B9 CLR IPT0 ; SOURCE LINE # 29 0012 22 RET ; FUNCTION TIM0_DeInit (END) ; FUNCTION _TIM0_TimeBaseInit (BEGIN) ; SOURCE LINE # 38 ;---- Variable 'TIM0_CountMode' assigned to Register 'R5' ---- ;---- Variable 'TIM0_PrescalerSelection' assigned to Register 'R7' ---- ; SOURCE LINE # 39 ; SOURCE LINE # 41 0000 EF MOV A,R7 0001 7005 JNZ ?C0002 ; SOURCE LINE # 42 ; SOURCE LINE # 43 0003 538EFE ANL TMCON,#0FEH ; SOURCE LINE # 44 0006 8006 SJMP ?C0003 0008 ?C0002: ; SOURCE LINE # 45 0008 BF0103 CJNE R7,#01H,?C0003 ; SOURCE LINE # 46 ; SOURCE LINE # 47 000B 438E01 ORL TMCON,#01H ; SOURCE LINE # 48 000E ?C0003: ; SOURCE LINE # 51 000E BD0104 CJNE R5,#01H,?C0005 ; SOURCE LINE # 52 ; SOURCE LINE # 53 0011 5389FB ANL TMOD,#0FBH ; SOURCE LINE # 54 0014 22 RET 0015 ?C0005: ; SOURCE LINE # 55 0015 BD0203 CJNE R5,#02H,?C0008 ; SOURCE LINE # 56 ; SOURCE LINE # 57 0018 438904 ORL TMOD,#04H ; SOURCE LINE # 58 ; SOURCE LINE # 59 001B ?C0008: C51 COMPILER V9.60.7.0 SC92F8003_TIMER0 05/13/2024 00:07:50 PAGE 11 001B 22 RET ; FUNCTION _TIM0_TimeBaseInit (END) ; FUNCTION _TIM0_WorkMode0Config (BEGIN) ; SOURCE LINE # 67 ;---- Variable 'TIM0_SetCounter' assigned to Register 'R6/R7' ---- ; SOURCE LINE # 68 ; SOURCE LINE # 69 0000 5389FC ANL TMOD,#0FCH ; SOURCE LINE # 70 0003 8F8A MOV TL0,R7 ; SOURCE LINE # 71 0005 EF MOV A,R7 0006 7805 MOV R0,#05H 0008 ?C0027: 0008 CE XCH A,R6 0009 C3 CLR C 000A 13 RRC A 000B CE XCH A,R6 000C 13 RRC A 000D D8F9 DJNZ R0,?C0027 000F F58C MOV TH0,A ; SOURCE LINE # 72 0011 22 RET ; FUNCTION _TIM0_WorkMode0Config (END) ; FUNCTION _TIM0_WorkMode1Config (BEGIN) ; SOURCE LINE # 80 ;---- Variable 'TIM0_SetCounter' assigned to Register 'R6/R7' ---- ; SOURCE LINE # 81 ; SOURCE LINE # 82 0000 5389FC ANL TMOD,#0FCH ; SOURCE LINE # 83 0003 438901 ORL TMOD,#01H ; SOURCE LINE # 84 0006 AD07 MOV R5,AR7 0008 8D8A MOV TL0,R5 ; SOURCE LINE # 85 000A 8E8C MOV TH0,R6 ; SOURCE LINE # 86 000C 22 RET ; FUNCTION _TIM0_WorkMode1Config (END) ; FUNCTION _TIM0_WorkMode2Config (BEGIN) ; SOURCE LINE # 94 ;---- Variable 'TIM0_SetCounter' assigned to Register 'R7' ---- ; SOURCE LINE # 95 ; SOURCE LINE # 96 0000 5389FC ANL TMOD,#0FCH ; SOURCE LINE # 97 0003 438902 ORL TMOD,#02H ; SOURCE LINE # 98 0006 8F8A MOV TL0,R7 ; SOURCE LINE # 99 0008 8F8C MOV TH0,R7 ; SOURCE LINE # 100 000A 22 RET ; FUNCTION _TIM0_WorkMode2Config (END) ; FUNCTION _TIM0_WorkMode3Config (BEGIN) ; SOURCE LINE # 109 ;---- Variable 'TIM1_SetCounter' assigned to Register 'R5' ---- C51 COMPILER V9.60.7.0 SC92F8003_TIMER0 05/13/2024 00:07:50 PAGE 12 ;---- Variable 'TIM0_SetCounter' assigned to Register 'R7' ---- ; SOURCE LINE # 110 ; SOURCE LINE # 111 0000 438903 ORL TMOD,#03H ; SOURCE LINE # 112 0003 8F8A MOV TL0,R7 ; SOURCE LINE # 113 0005 8D8C MOV TH0,R5 ; SOURCE LINE # 114 0007 22 RET ; FUNCTION _TIM0_WorkMode3Config (END) ; FUNCTION _TIM0_Mode0SetReloadCounter (BEGIN) ; SOURCE LINE # 122 ;---- Variable 'TIM0_SetCounter' assigned to Register 'R6/R7' ---- ; SOURCE LINE # 123 ; SOURCE LINE # 124 0000 8F8A MOV TL0,R7 ; SOURCE LINE # 125 0002 EF MOV A,R7 0003 7805 MOV R0,#05H 0005 ?C0028: 0005 CE XCH A,R6 0006 C3 CLR C 0007 13 RRC A 0008 CE XCH A,R6 0009 13 RRC A 000A D8F9 DJNZ R0,?C0028 000C F58C MOV TH0,A ; SOURCE LINE # 126 000E 22 RET ; FUNCTION _TIM0_Mode0SetReloadCounter (END) ; FUNCTION _TIM0_Mode1SetReloadCounter (BEGIN) ; SOURCE LINE # 134 ;---- Variable 'TIM0_SetCounter' assigned to Register 'R6/R7' ---- ; SOURCE LINE # 135 ; SOURCE LINE # 136 0000 AD07 MOV R5,AR7 0002 8D8A MOV TL0,R5 ; SOURCE LINE # 137 0004 8E8C MOV TH0,R6 ; SOURCE LINE # 138 0006 22 RET ; FUNCTION _TIM0_Mode1SetReloadCounter (END) ; FUNCTION _TIM0_SetTL0Counter (BEGIN) ; SOURCE LINE # 146 ;---- Variable 'TIM0_SetCounter' assigned to Register 'R7' ---- ; SOURCE LINE # 147 ; SOURCE LINE # 148 0000 8F8A MOV TL0,R7 ; SOURCE LINE # 149 0002 22 RET ; FUNCTION _TIM0_SetTL0Counter (END) ; FUNCTION _TIM0_SetTH0Counter (BEGIN) ; SOURCE LINE # 157 ;---- Variable 'TIM0_SetCounter' assigned to Register 'R7' ---- ; SOURCE LINE # 158 ; SOURCE LINE # 159 0000 8F8C MOV TH0,R7 C51 COMPILER V9.60.7.0 SC92F8003_TIMER0 05/13/2024 00:07:50 PAGE 13 ; SOURCE LINE # 160 0002 22 RET ; FUNCTION _TIM0_SetTH0Counter (END) ; FUNCTION _TIM0_Cmd (BEGIN) ; SOURCE LINE # 168 ;---- Variable 'NewState' assigned to Register 'R7' ---- ; SOURCE LINE # 169 ; SOURCE LINE # 170 0000 EF MOV A,R7 0001 7003 JNZ ?C0017 ; SOURCE LINE # 171 ; SOURCE LINE # 172 0003 C28C CLR TR0 ; SOURCE LINE # 173 0005 22 RET 0006 ?C0017: ; SOURCE LINE # 175 ; SOURCE LINE # 176 0006 D28C SETB TR0 ; SOURCE LINE # 177 ; SOURCE LINE # 178 0008 ?C0019: 0008 22 RET ; FUNCTION _TIM0_Cmd (END) ; FUNCTION _TIM0_ITConfig (BEGIN) ; SOURCE LINE # 187 ;---- Variable 'Priority' assigned to Register 'R5' ---- ;---- Variable 'NewState' assigned to Register 'R7' ---- ; SOURCE LINE # 188 ; SOURCE LINE # 190 0000 EF MOV A,R7 0001 7004 JNZ ?C0020 ; SOURCE LINE # 191 ; SOURCE LINE # 192 0003 C2A9 CLR ET0 ; SOURCE LINE # 193 0005 8002 SJMP ?C0021 0007 ?C0020: ; SOURCE LINE # 195 ; SOURCE LINE # 196 0007 D2A9 SETB ET0 ; SOURCE LINE # 197 0009 ?C0021: ; SOURCE LINE # 200 0009 ED MOV A,R5 000A 7003 JNZ ?C0022 ; SOURCE LINE # 201 ; SOURCE LINE # 202 000C C2B9 CLR IPT0 ; SOURCE LINE # 203 000E 22 RET 000F ?C0022: ; SOURCE LINE # 205 ; SOURCE LINE # 206 000F D2B9 SETB IPT0 ; SOURCE LINE # 207 ; SOURCE LINE # 208 0011 ?C0024: 0011 22 RET ; FUNCTION _TIM0_ITConfig (END) C51 COMPILER V9.60.7.0 SC92F8003_TIMER0 05/13/2024 00:07:50 PAGE 14 ; FUNCTION TIM0_GetFlagStatus (BEGIN) ; SOURCE LINE # 216 ; SOURCE LINE # 217 ; SOURCE LINE # 218 0000 A28D MOV C,TF0 0002 E4 CLR A 0003 33 RLC A 0004 FF MOV R7,A ; SOURCE LINE # 219 0005 22 RET ; FUNCTION TIM0_GetFlagStatus (END) ; FUNCTION TIM0_ClearFlag (BEGIN) ; SOURCE LINE # 227 ; SOURCE LINE # 228 ; SOURCE LINE # 229 0000 C28D CLR TF0 ; SOURCE LINE # 230 0002 22 RET ; FUNCTION TIM0_ClearFlag (END) C51 COMPILER V9.60.7.0 SC92F8003_TIMER0 05/13/2024 00:07:50 PAGE 15 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== uint16_t . . . . . . . . . . . . . . . TYPEDEF ----- U_INT ----- 2 OPREG. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FFH 1 P0 . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0080H 1 SSDAT. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009FH 1 P1 . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0090H 1 P2 . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A0H 1 EUART. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00ACH 1 TMCON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008EH 1 AC . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D6H 1 FlagStatus . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 RESET. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 OTCON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008FH 1 TIM0_MODE_TIMER. . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 EA . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00AFH 1 T2 . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00C9H 1 int32_t. . . . . . . . . . . . . . . . TYPEDEF ----- LONG ----- 4 PWMCON0. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D2H 1 PWMCON1. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DAH 1 int16_t. . . . . . . . . . . . . . . . TYPEDEF ----- INT ----- 2 ERROR. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 EADC . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00AEH 1 IE . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A8H 1 OPINX. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FEH 1 _TIM0_Cmd. . . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- NewState . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 CP . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00C8H 1 ErrorStatus. . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 EXF2 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CEH 1 CHKSUMH. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FDH 1 PWMDTY0. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D5H 1 OPERCON. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00EFH 1 PWMDTY1. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D6H 1 P0PH . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009BH 1 IP . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00B8H 1 TIM0_PRESSEL_FSYS_D1 . . . . . . . . . E_CONST ----- U_CHAR ----- 1 CHKSUML. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FCH 1 PWMDTY2. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D7H 1 P1PH . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0092H 1 RI . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0098H 1 PWMDTY3. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DCH 1 P2PH . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A2H 1 SUCCESS. . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 CY . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D7H 1 PWMDTY4. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DDH 1 TI . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0099H 1 PWMDTY5. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DEH 1 IPT0 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00B9H 1 PWMDTY6. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DFH 1 FunctionalState. . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 IPT1 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BBH 1 IPT2 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BDH 1 HIGH . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 _TIM0_TimeBaseInit . . . . . . . . . . PUBLIC CODE PROC 0000H ----- TIM0_PrescalerSelection. . . . . . . * REG * DATA U_CHAR 0007H 1 TIM0_CountMode . . . . . . . . . . . * REG * DATA U_CHAR 0005H 1 RCAP2H . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CBH 1 TIM0_GetFlagStatus . . . . . . . . . . PUBLIC CODE PROC 0000H ----- C51 COMPILER V9.60.7.0 SC92F8003_TIMER0 05/13/2024 00:07:50 PAGE 16 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== _TIM0_Mode0SetReloadCounter. . . . . . PUBLIC CODE PROC 0000H ----- TIM0_SetCounter. . . . . . . . . . . * REG * DATA U_INT 0006H 2 SP . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0081H 1 _TIM0_Mode1SetReloadCounter. . . . . . PUBLIC CODE PROC 0000H ----- TIM0_SetCounter. . . . . . . . . . . * REG * DATA U_INT 0006H 2 OV . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D2H 1 TIM0_CountMode_TypeDef . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 TIM0_MODE_COUNTER. . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 ITStatus . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 IAPADE . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F4H 1 RCAP2L . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CAH 1 ENABLE . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 BitStatus. . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 IAPADH . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F3H 1 PWMDTYA. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D4H 1 PWMDTYB. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DBH 1 ADCCON . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00ADH 1 s8 . . . . . . . . . . . . . . . . . . TYPEDEF ----- CHAR ----- 1 u8 . . . . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 RCLK . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CDH 1 IAPADL . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F2H 1 bool . . . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 TCLK . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CCH 1 P00. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0080H 1 P10. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0090H 1 P01. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0081H 1 SBUF . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0099H 1 PCON . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0087H 1 P20. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A0H 1 P11. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0091H 1 P21. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A1H 1 P12. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0092H 1 _TIM0_WorkMode0Config. . . . . . . . . PUBLIC CODE PROC 0000H ----- TIM0_SetCounter. . . . . . . . . . . * REG * DATA U_INT 0006H 2 P22. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A2H 1 P13. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0093H 1 SCON . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0098H 1 _TIM0_WorkMode1Config. . . . . . . . . PUBLIC CODE PROC 0000H ----- TIM0_SetCounter. . . . . . . . . . . * REG * DATA U_INT 0006H 2 P23. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A3H 1 P14. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0094H 1 IAPDAT . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F5H 1 TCON . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0088H 1 TMOD . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0089H 1 _TIM0_WorkMode2Config. . . . . . . . . PUBLIC CODE PROC 0000H ----- TIM0_SetCounter. . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 P24. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A4H 1 P15. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0095H 1 IPINT0 . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00B8H 1 _TIM0_WorkMode3Config. . . . . . . . . PUBLIC CODE PROC 0000H ----- TIM0_SetCounter. . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 TIM1_SetCounter. . . . . . . . . . . * REG * DATA U_CHAR 0005H 1 P25. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A5H 1 P16. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0096H 1 IPINT1 . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BAH 1 P26. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A6H 1 P17. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0097H 1 C51 COMPILER V9.60.7.0 SC92F8003_TIMER0 05/13/2024 00:07:50 PAGE 17 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== SSCON0 . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009DH 1 P27. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A7H 1 SSCON1 . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009EH 1 SSCON2 . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0095H 1 TIM0_DeInit. . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- IAPCTL . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F6H 1 IE1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A9H 1 TRUE . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 B. . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F0H 1 IAPKEY . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F1H 1 BTMCON . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CEH 1 PWMCFG . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D1H 1 ACC. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00E0H 1 ET0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A9H 1 TF0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008DH 1 ET1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00ABH 1 ADCCFG0. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00ABH 1 IP1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00B9H 1 TF1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008FH 1 ET2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00ADH 1 ADCCFG1. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00AAH 1 TIM0_PRESSEL_FSYS_D12. . . . . . . . . E_CONST ----- U_CHAR ----- 1 RB8. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009AH 1 TF2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CFH 1 TH0. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008CH 1 TH1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008DH 1 TB8. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009BH 1 TH2. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CDH 1 uint8_t. . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 P. . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D0H 1 SM0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009FH 1 TL0. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008AH 1 SM1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009EH 1 WDTCON . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CFH 1 TL1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008BH 1 SM2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009DH 1 TL2. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CCH 1 TIM0_PresSel_TypeDef . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 RS0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D3H 1 TR0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008CH 1 RS1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D4H 1 TR1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008EH 1 IPUART . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BCH 1 s32. . . . . . . . . . . . . . . . . . TYPEDEF ----- LONG ----- 4 TR2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CAH 1 int8_t . . . . . . . . . . . . . . . . TYPEDEF ----- CHAR ----- 1 u32. . . . . . . . . . . . . . . . . . TYPEDEF ----- U_LONG ----- 4 s16. . . . . . . . . . . . . . . . . . TYPEDEF ----- INT ----- 2 _TIM0_SetTH0Counter. . . . . . . . . . PUBLIC CODE PROC 0000H ----- TIM0_SetCounter. . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 u16. . . . . . . . . . . . . . . . . . TYPEDEF ----- U_INT ----- 2 PWMPRD . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D3H 1 DPH. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0083H 1 _TIM0_SetTL0Counter. . . . . . . . . . PUBLIC CODE PROC 0000H ----- TIM0_SetCounter. . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 DPL. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0082H 1 EINT0. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A8H 1 C51 COMPILER V9.60.7.0 SC92F8003_TIMER0 05/13/2024 00:07:50 PAGE 18 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== P0CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009AH 1 TIM0_ClearFlag . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- EINT1. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00AAH 1 IPADC. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BEH 1 INT0F. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BAH 1 P1CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0091H 1 EXEN2. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CBH 1 INT1F. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BCH 1 P2CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A1H 1 INT2F. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C6H 1 REN. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009CH 1 ADCVH. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00AFH 1 T2MOD. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C9H 1 T2CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C8H 1 ADCVL. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00AEH 1 SET. . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 FALSE. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 INT0R. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BBH 1 INT1R. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BDH 1 PriorityStatus . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 INT2R. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C7H 1 LOW. . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 _TIM0_ITConfig . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- NewState . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 Priority . . . . . . . . . . . . . . * REG * DATA U_CHAR 0005H 1 F0 . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D5H 1 DISABLE. . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 F1 . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D1H 1 PSW. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D0H 1 uint32_t . . . . . . . . . . . . . . . TYPEDEF ----- U_LONG ----- 4 MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 161 ---- CONSTANT SIZE = ---- ---- XDATA SIZE = ---- ---- PDATA SIZE = ---- ---- DATA SIZE = ---- ---- IDATA SIZE = ---- ---- BIT SIZE = ---- ---- EDATA SIZE = ---- ---- HDATA SIZE = ---- ---- XDATA CONST SIZE = ---- ---- FAR CONST SIZE = ---- ---- END OF MODULE INFORMATION. C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)