C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 1 C51 COMPILER V9.60.7.0, COMPILATION OF MODULE SC92F8003_EXTI OBJECT MODULE PLACED IN .\Objects\sc92f8003_exti.obj COMPILER INVOKED BY: d:\Keil\C51\BIN\C51.EXE SC92F8003_Lib\src\sc92f8003_exti.c OMF2 OPTIMIZE(8,SPEED) BROWSE INCDIR(.\S -rc;.\Task;.\Task\cpu_port\S92F8003A;.\Task\cfg;.\Task\pt_thread;.\SC92F8003_Lib\Inc) DEBUG CODE LISTINCLUDE SYMBOLS PRIN -T(.\Listings\sc92f8003_exti.lst) PREPRINT(.\Listings\sc92f8003_exti.i) OBJECT(.\Objects\sc92f8003_exti.obj) line level source 1 //************************************************************ 2 // Copyright (c) ÉîÛÚÊÐÈüԪ΢µç×ÓÓÐÏÞ¹«Ë¾ 3 // ÎļþÃû³Æ : sc92f8003_exti.c 4 // ×÷Õß : 5 // Ä£¿é¹¦ÄÜ : EXTI¹Ì¼þ¿âº¯ÊýCÎļþ 6 // ¾Ö²¿º¯ÊýÁбí: 7 // ×îºó¸üÕýÈÕÆÚ: 2018/9/4 8 // °æ±¾ : V1.0 9 // ˵Ã÷ £º 10 //************************************************************* 11 12 #include "sc92f8003_exti.h" 1 =1 //************************************************************ 2 =1 // Copyright (c) ÉîÛÚÊÐÈüԪ΢µç×ÓÓÐÏÞ¹«Ë¾ 3 =1 // ÎļþÃû³Æ : sc92f8003_exti.h 4 =1 // ×÷Õß : 5 =1 // Ä£¿é¹¦ÄÜ : EXTI¹Ì¼þ¿âº¯ÊýÍ·Îļþ 6 =1 // ¾Ö²¿º¯ÊýÁбí: 7 =1 // ×îºó¸üÕýÈÕÆÚ: 2018/9/4 8 =1 // °æ±¾ : V1.0 9 =1 // ˵Ã÷ £º 10 =1 //************************************************************* 11 =1 12 =1 #ifndef _SC92F8003_EXTI_H_ 13 =1 #define _SC92F8003_EXTI_H_ 14 =1 15 =1 #include "sc92f8003.h" 1 =2 #ifndef _SC92F8003_H 2 =2 #define _SC92F8003_H 3 =2 4 =2 #include "SC92F8003_C.H" 1 =3 /*-------------------------------------------------------------------------- 2 =3 SC92F8003_C.H 3 =3 4 =3 C Header file for SC92F8003 microcontroller. 5 =3 Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. 6 =3 All rights reserved. 7 =3 ÉîÛÚÊÐÈüԪ΢µç×ÓÓÐÏÞ¹«Ë¾ 8 =3 °æ±¾ºÅ: V1.0 9 =3 ÈÕÆÚ: 2018.05.02 10 =3 --------------------------------------------------------------------------*/ 11 =3 #ifndef _SC92F8003_H_ 12 =3 #define _SC92F8003_H_ 13 =3 14 =3 /* ------------------- ×ֽڼĴæÆ÷-------------------- */ 15 =3 ///*CPU*/ 16 =3 sfr ACC = 0xE0; //ÀÛ¼ÓÆ÷£Á 17 =3 sfr B = 0xF0; //ͨÓüĴæÆ÷B 18 =3 sfr PSW = 0xD0; //³ÌÐò״̬×Ö 19 =3 sfr DPH = 0x83; //Êý¾ÝÖ¸Õë¸ß8λ 20 =3 sfr DPL = 0x82; //Êý¾ÝÖ¸ÕëµÍ8λ 21 =3 sfr SP = 0x81; //¶ÑÕ»Ö¸Õë 22 =3 C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 2 23 =3 24 =3 /*system*/ 25 =3 sfr PCON = 0x87; //µçÔ´¹ÜÀí¿ØÖƼĴæÆ÷ 26 =3 27 =3 /*interrupt*/ 28 =3 sfr IP1 = 0XB9; //ÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷1 29 =3 sfr IP = 0xB8; //ÖжÏÓÅÏÈȨ¿ØÖƼĴæÆ÷ 30 =3 sfr IE = 0xA8; //ÖжϿØÖƼĴæÆ÷ 31 =3 sfr IE1 = 0XA9; //ÖжϿØÖƼĴæÆ÷1 32 =3 33 =3 /*PORT*/ 34 =3 sfr P2PH = 0xA2; //P2¿Úģʽ¿ØÖƼĴæÆ÷ 35 =3 sfr P2CON = 0xA1; //P2¿Úģʽ¿ØÖƼĴæÆ÷ 36 =3 sfr P2 = 0xA0; //P2¿ÚÊý¾Ý¼Ä´æÆ÷ 37 =3 sfr P1PH = 0x92; //P1¿Úģʽ¿ØÖƼĴæÆ÷ 38 =3 sfr P1CON = 0x91; //P1¿Úģʽ¿ØÖƼĴæÆ÷ 39 =3 sfr P1 = 0x90; //P1¿ÚÊý¾Ý¼Ä´æÆ÷ 40 =3 sfr P0PH = 0x9B; //P0¿Úģʽ¿ØÖƼĴæÆ÷ 41 =3 sfr P0CON = 0x9A; //P0¿Úģʽ¿ØÖƼĴæÆ÷ 42 =3 sfr P0 = 0x80; //P0¿ÚÊý¾Ý¼Ä´æÆ÷ 43 =3 44 =3 /*TIMER*/ 45 =3 sfr TMCON = 0x8E; //¶¨Ê±Æ÷ƵÂÊ¿ØÖƼĴæÆ÷ 46 =3 sfr TH1 = 0x8D; //¶¨Ê±Æ÷1¸ß8λ 47 =3 sfr TH0 = 0x8C; //¶¨Ê±Æ÷0¸ß8λ 48 =3 sfr TL1 = 0x8B; //¶¨Ê±Æ÷1µÍ8λ 49 =3 sfr TL0 = 0x8A; //¶¨Ê±Æ÷0µÍ8λ 50 =3 sfr TMOD = 0x89; //¶¨Ê±Æ÷¹¤×÷ģʽ¼Ä´æÆ÷ 51 =3 sfr TCON = 0x88; //¶¨Ê±Æ÷¿ØÖƼĴæÆ÷ 52 =3 sfr T2CON = 0xC8; //¶¨Ê±Æ÷2¿ØÖƼĴæÆ÷ 53 =3 sfr T2MOD = 0xC9; //¶¨Ê±Æ÷2¹¤×÷ģʽ¼Ä´æÆ÷ 54 =3 sfr RCAP2L = 0xCA; //¶¨Ê±Æ÷2ÖØÔØ/²¶×½µÍ8λ 55 =3 sfr RCAP2H = 0xCB; //¶¨Ê±Æ÷2ÖØÔØ/²¶×½¸ß8λ 56 =3 sfr TL2 = 0xCC; //¶¨Ê±Æ÷2µÍ8λ 57 =3 sfr TH2 = 0xCD; //¶¨Ê±Æ÷2¸ß8λ 58 =3 59 =3 60 =3 /*ADC*/ 61 =3 sfr ADCCFG1 = 0xAA; //ADC¹¦ÄÜÅäÖüĴæÆ÷0 62 =3 sfr ADCCFG0 = 0xAB; //ADC¹¦ÄÜÅäÖüĴæÆ÷1 63 =3 sfr ADCCON = 0XAD; //ADC¿ØÖƼĴæÆ÷ 64 =3 sfr ADCVL = 0xAE; //ADC ½á¹û¼Ä´æÆ÷ 65 =3 sfr ADCVH = 0xAF; //ADC ½á¹û¼Ä´æÆ÷ 66 =3 67 =3 /*PWM*/ 68 =3 sfr PWMCFG = 0xD1; //PWMÉèÖüĴæÆ÷ 69 =3 sfr PWMCON0 = 0xD2; //PWM¿ØÖƼĴæÆ÷ 70 =3 sfr PWMPRD = 0xD3; //PWMÖÜÆÚÉèÖüĴæÆ÷ 71 =3 sfr PWMDTYA = 0xD4; //PWMÕ¼¿Õ±ÈÉèÖüĴæÆ÷A 72 =3 sfr PWMDTY0 = 0xD5; //PWM0ÉèÖüĴæÆ÷ 73 =3 sfr PWMDTY1 = 0xD6; //PWM1ÉèÖüĴæÆ÷ 74 =3 sfr PWMDTY2 = 0xD7; //PWM2ÉèÖüĴæÆ÷ 75 =3 sfr PWMCON1 = 0xDA; //PWM¿ØÖƼĴæÆ÷ 76 =3 sfr PWMDTYB = 0xDB; //PWMÕ¼¿Õ±ÈÉèÖüĴæÆ÷B 77 =3 sfr PWMDTY3 = 0xDC; //PWM3ÉèÖüĴæÆ÷ 78 =3 sfr PWMDTY4 = 0xDD; //PWM4ÉèÖüĴæÆ÷ 79 =3 sfr PWMDTY5 = 0xDE; //PWM5ÉèÖüĴæÆ÷ 80 =3 sfr PWMDTY6 = 0xDF; //PWM6ÉèÖüĴæÆ÷ 81 =3 82 =3 83 =3 // 84 =3 ///*WatchDog*/ C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 3 85 =3 sfr BTMCON = 0XCE; //µÍƵ¶¨Ê±Æ÷¿ØÖƼĴæÆ÷ 86 =3 sfr WDTCON = 0xCF; //WDT¿ØÖƼĴæÆ÷ 87 =3 88 =3 89 =3 sfr OTCON = 0X8F; //Êä³ö¿ØÖƼĴæÆ÷ 90 =3 91 =3 /*INT*/ 92 =3 sfr INT0F = 0XBA; //INT0 ϽµÑØÖжϿØÖƼĴæÆ÷ 93 =3 sfr INT0R = 0XBB; //INT0 ÉϽµÑØÖжϿØÖƼĴæÆ÷ 94 =3 sfr INT1F = 0XBC; //INT1 ϽµÑØÖжϿØÖƼĴæÆ÷ 95 =3 sfr INT1R = 0XBD; //INT1 ÉϽµÑØÖжϿØÖƼĴæÆ÷ 96 =3 sfr INT2F = 0XC6; //INT2 ϽµÑØÖжϿØÖƼĴæÆ÷ 97 =3 sfr INT2R = 0XC7; //INT2 ÉϽµÑØÖжϿØÖƼĴæÆ÷ 98 =3 99 =3 /*IAP */ 100 =3 sfr IAPCTL = 0xF6; //IAP¿ØÖƼĴæÆ÷ 101 =3 sfr IAPDAT = 0xF5; //IAPÊý¾Ý¼Ä´æÆ÷ 102 =3 sfr IAPADE = 0xF4; //IAPÀ©Õ¹µØÖ·¼Ä´æÆ÷ 103 =3 sfr IAPADH = 0xF3; //IAPдÈëµØÖ·¸ßλ¼Ä´æÆ÷ 104 =3 sfr IAPADL = 0xF2; //IAPдÈëµØÖ·µÍ8λ¼Ä´æÆ÷ 105 =3 sfr IAPKEY = 0xF1; //IAP±£»¤¼Ä´æÆ÷ 106 =3 107 =3 /*uart0*/ 108 =3 sfr SCON = 0X98; //uart¿ØÖƼĴæÆ÷ 109 =3 sfr SBUF = 0X99; //uart0Êý¾Ý¼Ä´æÆ÷ 110 =3 111 =3 /*ÈýºÏÒ»*/ 112 =3 sfr SSCON0 = 0X9D; //SSI¿ØÖƼĴæÆ÷0 113 =3 sfr SSCON1 = 0X9E; //SSI¿ØÖƼĴæÆ÷1 114 =3 sfr SSCON2 = 0X95; //SSI¿ØÖƼĴæÆ÷2 115 =3 sfr SSDAT = 0X9F; //SSIÊý¾Ý¼Ä´æÆ÷ 116 =3 117 =3 sfr OPINX = 0XFE; 118 =3 sfr OPREG = 0XFF; 119 =3 120 =3 /*Check Sum*/ 121 =3 sfr CHKSUML = 0XFC; //Check Sum½á¹û¼Ä´æÆ÷µÍλ 122 =3 sfr CHKSUMH = 0XFD; //Check Sum½á¹û¼Ä´æÆ÷¸ßλ 123 =3 124 =3 sfr OPERCON = 0xEF; //ÔËËã¿ØÖƼĴæÆ÷ 125 =3 126 =3 ///* ------------------- λ¼Ä´æÆ÷-------------------- */ 127 =3 /*PSW*/ 128 =3 sbit CY = PSW^7; //±ê־λ 0:¼Ó·¨ÔËËã×î¸ßλÎÞ½ø룬»òÕß¼õ·¨ÔËËã×î¸ßλÎÞ½èλʱ 1:¼Ó·¨ÔËËã×î¸ßλÓнø -룬»òÕß¼õ·¨ÔËËã×î¸ßλÓнèλʱ 129 =3 sbit AC = PSW^6; //½øλ¸¨Öú±ê־λ 0:ÎÞ½èλ¡¢½øλ 1:¼Ó·¨ÔËËãʱÔÚbit3λÓнø룬»ò¼õ·¨ÔËËãÔÚbit3λÓн -èλʱ 130 =3 sbit F0 = PSW^5; //Óû§±ê־λ 131 =3 sbit RS1 = PSW^4; //¹¤×÷¼Ä´æÆ÷×éÑ¡Ôñλ 132 =3 sbit RS0 = PSW^3; //¹¤×÷¼Ä´æÆ÷×éÑ¡Ôñλ 133 =3 sbit OV = PSW^2; //Òç³ö±ê־λ 134 =3 sbit F1 = PSW^1; //F1±êÖ¾ 135 =3 sbit P = PSW^0; //Ææż±ê־λ 0:ACCÖÐ1µÄ¸öÊýΪżÊý£¨°üÀ¨0¸ö£© 1:ACCÖÐ1µÄ¸öÊýΪÆæÊý 136 =3 137 =3 /*T2CON*/ 138 =3 sbit TF2 = T2CON^7; 139 =3 sbit EXF2 = T2CON^6; 140 =3 sbit RCLK = T2CON^5; 141 =3 sbit TCLK = T2CON^4; 142 =3 sbit EXEN2 = T2CON^3; 143 =3 sbit TR2 = T2CON^2; 144 =3 sbit T2 = T2CON^1; C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 4 145 =3 sbit CP = T2CON^0; 146 =3 147 =3 148 =3 /*IP*/ 149 =3 sbit IPADC = IP^6; //ADCÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 ADCµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 ADCµÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß¡ -± 150 =3 sbit IPT2 = IP^5; //PWMÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 PWMµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 PWM µÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß -¡± 151 =3 sbit IPUART = IP^4; //SIFÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 SIFµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 SIFµÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß¡ -± 152 =3 sbit IPT1 = IP^3; //Timer1ÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 Timer 1µÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 Timer 1µÄÖжÏÓÅÏÈÈ -¨ÊÇ ¡°¸ß¡± 153 =3 sbit IPINT1 = IP^2; //32K Base TimerÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 32KµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 32KµÄÖжÏÓÅ -ÏÈȨÊÇ ¡°¸ß¡± 154 =3 sbit IPT0 = IP^1; //Timer0ÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 Timer 0µÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 Timer 0µÄÖжÏÓÅÏÈÈ -¨ÊÇ ¡°¸ß¡± 155 =3 sbit IPINT0 = IP^0; 156 =3 157 =3 /*IE*/ 158 =3 sbit EA = IE^7; //ÖжÏʹÄܵÄ×Ü¿ØÖÆ 0:¹Ø±ÕËùÓеÄÖÐ¶Ï 1:´ò¿ªËùÓеÄÖÐ¶Ï 159 =3 sbit EADC = IE^6; //ADCÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕADCÖÐ¶Ï 1:´ò¿ªADCÖÐ¶Ï 160 =3 sbit ET2 = IE^5; //PWMÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕPWMÖÐ¶Ï 1:´ò¿ªPWMÖÐ¶Ï 161 =3 sbit EUART = IE^4; //UARTÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕSIFÖÐ¶Ï 1:´ò¿ªSIFÖÐ¶Ï 162 =3 sbit ET1 = IE^3; //Timer1ÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTIMER1ÖÐ¶Ï 1:´ò¿ªTIMER1ÖÐ¶Ï 163 =3 sbit EINT1 = IE^2; //32K Base TimerÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±Õ32KÖÐ¶Ï 1:´ò¿ª32KÖÐ¶Ï 164 =3 sbit ET0 = IE^1; //Timer0ÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTIMER0ÖÐ¶Ï 1:´ò¿ªTIMER0ÖÐ¶Ï 165 =3 sbit EINT0 = IE^0; //TouchKeyµÄÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTouchKeyÖÐ¶Ï 1:´ò¿ªTouchKeyÖÐ¶Ï 166 =3 167 =3 /*TCON*/ 168 =3 sbit TF1 = TCON^7; //T1Òç³öÖжÏÇëÇó±ê־λ T1²úÉúÒç³ö£¬·¢ÉúÖжÏʱ£¬Ó²¼þ½«TF1ÖÃΪ¡°1¡±£¬ÉêÇëÖжϣ¬CPU -ÏìӦʱ£¬Ó²¼þÇå¡°0¡±¡£ 169 =3 sbit TR1 = TCON^6; //¶¨Ê±Æ÷T1µÄÔËÐпØÖÆλ 0:Timer1½ûÖ¹¼ÆÊý 1:Timer1¿ªÊ¼¼ÆÊý 170 =3 sbit TF0 = TCON^5; //T0Òç³öÖжÏÇëÇó±ê־λ T0²úÉúÒç³ö£¬·¢ÉúÖжÏʱ£¬Ó²¼þ½«TF0ÖÃΪ¡°1¡±£¬ÉêÇëÖжϣ¬CPU -ÏìӦʱ£¬Ó²¼þÇå¡°0¡±¡£ 171 =3 sbit TR0 = TCON^4; //¶¨Ê±Æ÷T0µÄÔËÐпØÖÆλ 0:Timer0½ûÖ¹¼ÆÊý 1:Timer0¿ªÊ¼¼ÆÊý 172 =3 173 =3 /*SCON*/ 174 =3 sbit SM0 = SCON^7; 175 =3 sbit SM1 = SCON^6; 176 =3 sbit SM2 = SCON^5; 177 =3 sbit REN = SCON^4; 178 =3 sbit TB8 = SCON^3; 179 =3 sbit RB8 = SCON^2; 180 =3 sbit TI = SCON^1; 181 =3 sbit RI = SCON^0; 182 =3 183 =3 /* P0 */ 184 =3 sbit P01 = P0^1; 185 =3 sbit P00 = P0^0; 186 =3 187 =3 /* P1 */ 188 =3 sbit P17 = P1^7; 189 =3 sbit P16 = P1^6; 190 =3 sbit P15 = P1^5; 191 =3 sbit P14 = P1^4; 192 =3 sbit P13 = P1^3; 193 =3 sbit P12 = P1^2; 194 =3 sbit P11 = P1^1; 195 =3 sbit P10 = P1^0; 196 =3 197 =3 /* P2 */ 198 =3 sbit P27 = P2^7; C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 5 199 =3 sbit P26 = P2^6; 200 =3 sbit P25 = P2^5; 201 =3 sbit P24 = P2^4; 202 =3 sbit P23 = P2^3; 203 =3 sbit P22 = P2^2; 204 =3 sbit P21 = P2^1; 205 =3 sbit P20 = P2^0; 206 =3 207 =3 #endif 5 =2 6 =2 #define enableInterrupts() EA=1 /** ¿ªÆô×ÜÖÐ¶Ï **/ 7 =2 #define disableInterrupts() EA=0 /** ¹Ø±Õ×ÜÖÐ¶Ï **/ 8 =2 9 =2 #define __I volatile const /*!< defines 'read only' permissions */ 10 =2 #define __O volatile /*!< defines 'write only' permissions */ 11 =2 #define __IO volatile /*!< defines 'read / write' permissions */ 12 =2 13 =2 /*!< Signed integer types */ 14 =2 typedef signed char int8_t; 15 =2 typedef signed short int16_t; 16 =2 typedef signed long int32_t; 17 =2 18 =2 /*!< Unsigned integer types */ 19 =2 typedef unsigned char uint8_t; 20 =2 typedef unsigned short uint16_t; 21 =2 typedef unsigned long uint32_t; 22 =2 23 =2 typedef int32_t s32; 24 =2 typedef int16_t s16; 25 =2 typedef int8_t s8; 26 =2 27 =2 typedef uint32_t u32; 28 =2 typedef uint16_t u16; 29 =2 typedef uint8_t u8; 30 =2 31 =2 32 =2 typedef enum {FALSE = 0, TRUE = !FALSE} bool; 33 =2 34 =2 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus; 35 =2 36 =2 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 37 =2 38 =2 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; 39 =2 40 =2 typedef enum {LOW = 0, HIGH = !LOW} PriorityStatus; 41 =2 42 =2 #endif 16 =1 17 =1 typedef enum { 18 =1 EXTI_TRIGGER_RISE_ONLY = (uint8_t)0x01, //EXTI´¥·¢·½Ê½ÎªÉÏÉýÑØ 19 =1 EXTI_TRIGGER_FALL_ONLY = (uint8_t)0x02, //EXTI´¥·¢·½Ê½ÎªÏ½µÑØ 20 =1 EXTI_TRIGGER_RISE_FALL = (uint8_t)0x03, //EXTI´¥·¢·½Ê½ÎªÉÏÉýÑØÓëϽµÑØ 21 =1 EXTI_TRIGGER_DISABLE = (uint8_t)0x04 //¹Ø±ÕÍⲿÖжϴ¥·¢ 22 =1 } EXTI_TriggerMode_Typedef; 23 =1 24 =1 typedef enum { 25 =1 INT0 = (uint8_t)0x00, //ÍⲿÖжÏ0 26 =1 INT1 = (uint8_t)0x01, //ÍⲿÖжÏ1 27 =1 INT2 = (uint8_t)0x02 //ÍⲿÖжÏ2 28 =1 } EXTIx_Typedef; 29 =1 30 =1 typedef enum { C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 6 31 =1 INT00 = (uint8_t)0x01, //½«P00ÉèÖÃΪINT0½Å 32 =1 INT01 = (uint8_t)0x02 //½«P01ÉèÖÃΪINT0½Å 33 =1 } EXTI0x_Typedef; 34 =1 35 =1 typedef enum { 36 =1 INT10 = (uint8_t)0x01, //½«P10ÉèÖÃΪINT1½Å 37 =1 INT11 = (uint8_t)0x02, //½«P11ÉèÖÃΪINT1½Å 38 =1 INT12 = (uint8_t)0x04, //½«P12ÉèÖÃΪINT1½Å 39 =1 INT13 = (uint8_t)0x08, //½«P13ÉèÖÃΪINT1½Å 40 =1 INT14 = (uint8_t)0x10, //½«P14ÉèÖÃΪINT1½Å 41 =1 INT15 = (uint8_t)0x20, //½«P15ÉèÖÃΪINT1½Å 42 =1 INT16 = (uint8_t)0x40 //½«P16ÉèÖÃΪINT1½Å 43 =1 } EXTI1x_Typedef; 44 =1 45 =1 typedef enum { 46 =1 INT21 = (uint8_t)0x02, //½«P21ÉèÖÃΪINT2½Å 47 =1 INT22 = (uint8_t)0x04, //½«P22ÉèÖÃΪINT2½Å 48 =1 INT23 = (uint8_t)0x08, //½«P23ÉèÖÃΪINT2½Å 49 =1 INT24 = (uint8_t)0x10, //½«P24ÉèÖÃΪINT2½Å 50 =1 INT25 = (uint8_t)0x20, //½«P25ÉèÖÃΪINT2½Å 51 =1 INT26 = (uint8_t)0x40, //½«P26ÉèÖÃΪINT2½Å 52 =1 INT27 = (uint8_t)0x80 //½«P27ÉèÖÃΪINT2½Å 53 =1 } EXTI2x_Typedef; 54 =1 55 =1 void EXTI_DeInit(EXTIx_Typedef INTx); 56 =1 void EXTI_SetExtInt0xTriggerMode(uint8_t INT0x,EXTI_TriggerMode_Typedef TriggerMode); 57 =1 void EXTI_SetExtInt1xTriggerMode(uint8_t INT1x,EXTI_TriggerMode_Typedef TriggerMode); 58 =1 void EXTI_SetExtInt2xTriggerMode(uint8_t INT2x,EXTI_TriggerMode_Typedef TriggerMode); 59 =1 void EXTI_ITConfig(EXTIx_Typedef INTx,FunctionalState NewState,PriorityStatus Priority); 60 =1 61 =1 #endif 62 =1 63 =1 /******************* (C) COPYRIGHT 2018 SinOne Microelectronics *****END OF FILE****/ 13 14 /************************************************** 15 *º¯ÊýÃû³Æ£ºvoid EXTI_DeInit(EXTIx_Typedef INTx) 16 *º¯Êý¹¦ÄÜ£ºINTxÏà¹Ø¼Ä´æÆ÷¸´Î»ÖÁȱʡֵ 17 *Èë¿Ú²ÎÊý£ºINTx INTxÑ¡Ôñ 18 *³ö¿Ú²ÎÊý£ºvoid 19 **************************************************/ 20 void EXTI_DeInit(EXTIx_Typedef INTx) 21 { 22 1 switch(INTx) 23 1 { 24 2 case INT0: 25 2 INT0R = 0x00; 26 2 INT0F = 0x00; 27 2 IE &= (~0X01); 28 2 IP &= ~0X01; 29 2 TCON &= (~0X02); 30 2 break; 31 2 32 2 case INT1: 33 2 INT1R = 0x00; 34 2 INT1F = 0x00; 35 2 IE &= (~0X04); 36 2 IP &= ~0X04; 37 2 TCON &= (~0X08); 38 2 break; 39 2 40 2 case INT2: 41 2 INT2R = 0x00; C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 7 42 2 INT2F = 0x00; 43 2 IE1 &= (~0X08); 44 2 IP1 &= ~0X08; 45 2 break; 46 2 47 2 default: 48 2 break; 49 2 } 50 1 } 51 52 /************************************************** 53 *º¯ÊýÃû³Æ£ºvoid EXTI_SetExtInt0xTriggerMode(uint8_t INT0x, EXTI_TriggerMode_Typedef TriggerMode) 54 *º¯Êý¹¦ÄÜ£ºINT0xÖжϴ¥·¢·½Ê½ÅäÖú¯Êý 55 *Èë¿Ú²ÎÊý£ºINT0x INT0xÑ¡Ôñ 56 TriggerMode Öжϴ¥·¢·½Ê½Ñ¡Ôñ 57 *³ö¿Ú²ÎÊý£ºvoid 58 **************************************************/ 59 void EXTI_SetExtInt0xTriggerMode(uint8_t INT0x, EXTI_TriggerMode_Typedef TriggerMode) 60 { 61 1 switch(TriggerMode) 62 1 { 63 2 case EXTI_TRIGGER_RISE_ONLY: 64 2 INT0R |= INT0x; 65 2 INT0F &= (~INT0x); 66 2 break; 67 2 case EXTI_TRIGGER_FALL_ONLY: 68 2 INT0R &= (~INT0x); 69 2 INT0F |= INT0x; 70 2 break; 71 2 case EXTI_TRIGGER_RISE_FALL: 72 2 INT0R |= INT0x; 73 2 INT0F |= INT0x; 74 2 break; 75 2 case EXTI_TRIGGER_DISABLE: 76 2 INT0R &= (~INT0x); 77 2 INT0F &= (~INT0x); 78 2 default: 79 2 break; 80 2 } 81 1 } 82 83 /************************************************** 84 *º¯ÊýÃû³Æ£ºvoid EXTI_SetExtInt1xTriggerMode(uint8_t INT1x, EXTI_TriggerMode_Typedef TriggerMode) 85 *º¯Êý¹¦ÄÜ£ºINT1xÖжϴ¥·¢·½Ê½ÅäÖú¯Êý 86 *Èë¿Ú²ÎÊý£ºINT1x INT1xÑ¡Ôñ 87 TriggerMode Öжϴ¥·¢·½Ê½Ñ¡Ôñ 88 *³ö¿Ú²ÎÊý£ºvoid 89 **************************************************/ 90 void EXTI_SetExtInt1xTriggerMode(uint8_t INT1x, EXTI_TriggerMode_Typedef TriggerMode) 91 { 92 1 switch(TriggerMode) 93 1 { 94 2 case EXTI_TRIGGER_RISE_ONLY: 95 2 INT1R |= INT1x; 96 2 INT1F &= (~INT1x); 97 2 break; 98 2 case EXTI_TRIGGER_FALL_ONLY: 99 2 INT1R &= (~INT1x); 100 2 INT1F |= INT1x; 101 2 break; 102 2 case EXTI_TRIGGER_RISE_FALL: 103 2 INT1R |= INT1x; C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 8 104 2 INT1F |= INT1x; 105 2 break; 106 2 case EXTI_TRIGGER_DISABLE: 107 2 INT1R &= (~INT1x); 108 2 INT1F &= (~INT1x); 109 2 default: 110 2 break; 111 2 } 112 1 } 113 114 /************************************************** 115 *º¯ÊýÃû³Æ£ºvoid EXTI_SetExtInt2xTriggerMode(uint8_t INT2x, EXTI_TriggerMode_Typedef TriggerMode) 116 *º¯Êý¹¦ÄÜ£ºINT2xÖжϴ¥·¢·½Ê½ÅäÖú¯Êý 117 *Èë¿Ú²ÎÊý£ºINT2x INT2xÑ¡Ôñ 118 TriggerMode Öжϴ¥·¢·½Ê½Ñ¡Ôñ 119 *³ö¿Ú²ÎÊý£ºvoid 120 **************************************************/ 121 void EXTI_SetExtInt2xTriggerMode(uint8_t INT2x, EXTI_TriggerMode_Typedef TriggerMode) 122 { 123 1 switch(TriggerMode) 124 1 { 125 2 case EXTI_TRIGGER_RISE_ONLY: 126 2 INT2R |= INT2x; 127 2 INT2F &= (~INT2x); 128 2 break; 129 2 case EXTI_TRIGGER_FALL_ONLY: 130 2 INT2R &= (~INT2x); 131 2 INT2F |= INT2x; 132 2 break; 133 2 case EXTI_TRIGGER_RISE_FALL: 134 2 INT2R |= INT2x; 135 2 INT2F |= INT2x; 136 2 break; 137 2 case EXTI_TRIGGER_DISABLE: 138 2 INT2R &= (~INT2x); 139 2 INT2F &= (~INT2x); 140 2 default: 141 2 break; 142 2 } 143 1 } 144 145 /***************************************************** 146 *º¯ÊýÃû³Æ£ºvoid EXTI_ITConfig(EXTIx_Typedef INTx, FunctionalState NewState, PriorityStatus Priority) 147 *º¯Êý¹¦ÄÜ£ºINTxÖжϳõʼ»¯ 148 *Èë¿Ú²ÎÊý£ºINTx INTxÑ¡Ôñ 149 FunctionalState NewState ÖжÏʹÄÜ/¹Ø±ÕÑ¡Ôñ 150 PriorityStatus Priority ÖжÏÓÅÏȼ¶Ñ¡Ôñ 151 *³ö¿Ú²ÎÊý£ºvoid 152 *****************************************************/ 153 void EXTI_ITConfig(EXTIx_Typedef INTx, FunctionalState NewState, PriorityStatus Priority) 154 { 155 1 switch(INTx) 156 1 { 157 2 case INT0: 158 2 if(NewState != DISABLE) 159 2 { 160 3 IE |= 0X01; 161 3 } 162 2 else 163 2 { 164 3 IE &= (~0X01); 165 3 } C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 9 166 2 167 2 if(Priority == LOW) 168 2 { 169 3 IP &= ~0X01; 170 3 } 171 2 else 172 2 { 173 3 IP |= 0X01; 174 3 } 175 2 break; 176 2 177 2 case INT1: 178 2 if(NewState != DISABLE) 179 2 { 180 3 IE |= 0X04; 181 3 } 182 2 else 183 2 { 184 3 IE &= (~0X04); 185 3 } 186 2 187 2 if(Priority == LOW) 188 2 { 189 3 IP &= ~0X04; 190 3 } 191 2 else 192 2 { 193 3 IP |= 0X04; 194 3 } 195 2 break; 196 2 197 2 case INT2: 198 2 if(NewState != DISABLE) 199 2 { 200 3 IE1 |= 0X08; 201 3 } 202 2 else 203 2 { 204 3 IE1 &= (~0X08); 205 3 } 206 2 207 2 if(Priority == LOW) 208 2 { 209 3 IP1 &= ~0X08; 210 3 } 211 2 else 212 2 { 213 3 IP1 |= 0X08; 214 3 } 215 2 break; 216 2 217 2 default: 218 2 break; 219 2 } 220 1 } 221 222 /******************* (C) COPYRIGHT 2018 SinOne Microelectronics *****END OF FILE****/ C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 10 ASSEMBLY LISTING OF GENERATED OBJECT CODE ; FUNCTION _EXTI_DeInit (BEGIN) ; SOURCE LINE # 20 ;---- Variable 'INTx' assigned to Register 'R7' ---- ; SOURCE LINE # 21 ; SOURCE LINE # 22 0000 EF MOV A,R7 0001 14 DEC A 0002 6016 JZ ?C0003 0004 14 DEC A 0005 6022 JZ ?C0004 0007 2402 ADD A,#02H 0009 7029 JNZ ?C0006 ; SOURCE LINE # 23 ; SOURCE LINE # 24 000B ?C0002: ; SOURCE LINE # 25 000B E4 CLR A 000C F5BB MOV INT0R,A ; SOURCE LINE # 26 000E F5BA MOV INT0F,A ; SOURCE LINE # 27 0010 53A8FE ANL IE,#0FEH ; SOURCE LINE # 28 0013 53B8FE ANL IP,#0FEH ; SOURCE LINE # 29 0016 5388FD ANL TCON,#0FDH ; SOURCE LINE # 30 0019 22 RET ; SOURCE LINE # 32 001A ?C0003: ; SOURCE LINE # 33 001A E4 CLR A 001B F5BD MOV INT1R,A ; SOURCE LINE # 34 001D F5BC MOV INT1F,A ; SOURCE LINE # 35 001F 53A8FB ANL IE,#0FBH ; SOURCE LINE # 36 0022 53B8FB ANL IP,#0FBH ; SOURCE LINE # 37 0025 5388F7 ANL TCON,#0F7H ; SOURCE LINE # 38 0028 22 RET ; SOURCE LINE # 40 0029 ?C0004: ; SOURCE LINE # 41 0029 E4 CLR A 002A F5C7 MOV INT2R,A ; SOURCE LINE # 42 002C F5C6 MOV INT2F,A ; SOURCE LINE # 43 002E 53A9F7 ANL IE1,#0F7H ; SOURCE LINE # 44 0031 53B9F7 ANL IP1,#0F7H ; SOURCE LINE # 45 ; SOURCE LINE # 47 ; SOURCE LINE # 48 ; SOURCE LINE # 49 ; SOURCE LINE # 50 C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 11 0034 ?C0006: 0034 22 RET ; FUNCTION _EXTI_DeInit (END) ; FUNCTION _EXTI_SetExtInt0xTriggerMode (BEGIN) ; SOURCE LINE # 59 ;---- Variable 'INT0x' assigned to Register 'R7' ---- ;---- Variable 'TriggerMode' assigned to Register 'R5' ---- ; SOURCE LINE # 60 ; SOURCE LINE # 61 0000 ED MOV A,R5 0001 24FE ADD A,#0FEH 0003 6012 JZ ?C0009 0005 14 DEC A 0006 6015 JZ ?C0010 0008 14 DEC A 0009 6019 JZ ?C0011 000B 2403 ADD A,#03H 000D 701B JNZ ?C0013 ; SOURCE LINE # 62 ; SOURCE LINE # 63 000F ?C0008: ; SOURCE LINE # 64 000F EF MOV A,R7 0010 42BB ORL INT0R,A ; SOURCE LINE # 65 0012 EF MOV A,R7 0013 F4 CPL A 0014 52BA ANL INT0F,A ; SOURCE LINE # 66 0016 22 RET ; SOURCE LINE # 67 0017 ?C0009: ; SOURCE LINE # 68 0017 EF MOV A,R7 0018 F4 CPL A 0019 52BB ANL INT0R,A ; SOURCE LINE # 69 ; SOURCE LINE # 70 001B 8003 SJMP ?C0046 ; SOURCE LINE # 71 001D ?C0010: ; SOURCE LINE # 72 001D EF MOV A,R7 001E 42BB ORL INT0R,A ; SOURCE LINE # 73 0020 ?C0046: 0020 EF MOV A,R7 0021 42BA ORL INT0F,A ; SOURCE LINE # 74 0023 22 RET ; SOURCE LINE # 75 0024 ?C0011: ; SOURCE LINE # 76 0024 EF MOV A,R7 0025 F4 CPL A 0026 52BB ANL INT0R,A ; SOURCE LINE # 77 0028 52BA ANL INT0F,A ; SOURCE LINE # 78 ; SOURCE LINE # 79 ; SOURCE LINE # 80 C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 12 ; SOURCE LINE # 81 002A ?C0013: 002A 22 RET ; FUNCTION _EXTI_SetExtInt0xTriggerMode (END) ; FUNCTION _EXTI_SetExtInt1xTriggerMode (BEGIN) ; SOURCE LINE # 90 ;---- Variable 'INT1x' assigned to Register 'R7' ---- ;---- Variable 'TriggerMode' assigned to Register 'R5' ---- ; SOURCE LINE # 91 ; SOURCE LINE # 92 0000 ED MOV A,R5 0001 24FE ADD A,#0FEH 0003 6012 JZ ?C0016 0005 14 DEC A 0006 6015 JZ ?C0017 0008 14 DEC A 0009 6019 JZ ?C0018 000B 2403 ADD A,#03H 000D 701B JNZ ?C0020 ; SOURCE LINE # 93 ; SOURCE LINE # 94 000F ?C0015: ; SOURCE LINE # 95 000F EF MOV A,R7 0010 42BD ORL INT1R,A ; SOURCE LINE # 96 0012 EF MOV A,R7 0013 F4 CPL A 0014 52BC ANL INT1F,A ; SOURCE LINE # 97 0016 22 RET ; SOURCE LINE # 98 0017 ?C0016: ; SOURCE LINE # 99 0017 EF MOV A,R7 0018 F4 CPL A 0019 52BD ANL INT1R,A ; SOURCE LINE # 100 ; SOURCE LINE # 101 001B 8003 SJMP ?C0047 ; SOURCE LINE # 102 001D ?C0017: ; SOURCE LINE # 103 001D EF MOV A,R7 001E 42BD ORL INT1R,A ; SOURCE LINE # 104 0020 ?C0047: 0020 EF MOV A,R7 0021 42BC ORL INT1F,A ; SOURCE LINE # 105 0023 22 RET ; SOURCE LINE # 106 0024 ?C0018: ; SOURCE LINE # 107 0024 EF MOV A,R7 0025 F4 CPL A 0026 52BD ANL INT1R,A ; SOURCE LINE # 108 0028 52BC ANL INT1F,A ; SOURCE LINE # 109 ; SOURCE LINE # 110 C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 13 ; SOURCE LINE # 111 ; SOURCE LINE # 112 002A ?C0020: 002A 22 RET ; FUNCTION _EXTI_SetExtInt1xTriggerMode (END) ; FUNCTION _EXTI_SetExtInt2xTriggerMode (BEGIN) ; SOURCE LINE # 121 ;---- Variable 'INT2x' assigned to Register 'R7' ---- ;---- Variable 'TriggerMode' assigned to Register 'R5' ---- ; SOURCE LINE # 122 ; SOURCE LINE # 123 0000 ED MOV A,R5 0001 24FE ADD A,#0FEH 0003 6012 JZ ?C0023 0005 14 DEC A 0006 6015 JZ ?C0024 0008 14 DEC A 0009 6019 JZ ?C0025 000B 2403 ADD A,#03H 000D 701B JNZ ?C0027 ; SOURCE LINE # 124 ; SOURCE LINE # 125 000F ?C0022: ; SOURCE LINE # 126 000F EF MOV A,R7 0010 42C7 ORL INT2R,A ; SOURCE LINE # 127 0012 EF MOV A,R7 0013 F4 CPL A 0014 52C6 ANL INT2F,A ; SOURCE LINE # 128 0016 22 RET ; SOURCE LINE # 129 0017 ?C0023: ; SOURCE LINE # 130 0017 EF MOV A,R7 0018 F4 CPL A 0019 52C7 ANL INT2R,A ; SOURCE LINE # 131 ; SOURCE LINE # 132 001B 8003 SJMP ?C0048 ; SOURCE LINE # 133 001D ?C0024: ; SOURCE LINE # 134 001D EF MOV A,R7 001E 42C7 ORL INT2R,A ; SOURCE LINE # 135 0020 ?C0048: 0020 EF MOV A,R7 0021 42C6 ORL INT2F,A ; SOURCE LINE # 136 0023 22 RET ; SOURCE LINE # 137 0024 ?C0025: ; SOURCE LINE # 138 0024 EF MOV A,R7 0025 F4 CPL A 0026 52C7 ANL INT2R,A ; SOURCE LINE # 139 0028 52C6 ANL INT2F,A ; SOURCE LINE # 140 C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 14 ; SOURCE LINE # 141 ; SOURCE LINE # 142 ; SOURCE LINE # 143 002A ?C0027: 002A 22 RET ; FUNCTION _EXTI_SetExtInt2xTriggerMode (END) ; FUNCTION _EXTI_ITConfig (BEGIN) ; SOURCE LINE # 153 ;---- Variable 'INTx' assigned to Register 'R7' ---- ;---- Variable 'Priority' assigned to Register 'R3' ---- ;---- Variable 'NewState' assigned to Register 'R5' ---- ; SOURCE LINE # 154 ; SOURCE LINE # 155 0000 EF MOV A,R7 0001 14 DEC A 0002 601D JZ ?C0034 0004 14 DEC A 0005 6030 JZ ?C0039 0007 2402 ADD A,#02H 0009 7041 JNZ ?C0045 ; SOURCE LINE # 156 ; SOURCE LINE # 157 000B ?C0029: ; SOURCE LINE # 158 000B ED MOV A,R5 000C 6005 JZ ?C0030 ; SOURCE LINE # 159 ; SOURCE LINE # 160 000E 43A801 ORL IE,#01H ; SOURCE LINE # 161 0011 8003 SJMP ?C0031 0013 ?C0030: ; SOURCE LINE # 163 ; SOURCE LINE # 164 0013 53A8FE ANL IE,#0FEH ; SOURCE LINE # 165 0016 ?C0031: ; SOURCE LINE # 167 0016 EB MOV A,R3 0017 7004 JNZ ?C0032 ; SOURCE LINE # 168 ; SOURCE LINE # 169 0019 53B8FE ANL IP,#0FEH ; SOURCE LINE # 170 001C 22 RET 001D ?C0032: ; SOURCE LINE # 172 ; SOURCE LINE # 173 001D 43B801 ORL IP,#01H ; SOURCE LINE # 174 ; SOURCE LINE # 175 0020 22 RET ; SOURCE LINE # 177 0021 ?C0034: ; SOURCE LINE # 178 0021 ED MOV A,R5 0022 6005 JZ ?C0035 ; SOURCE LINE # 179 ; SOURCE LINE # 180 0024 43A804 ORL IE,#04H ; SOURCE LINE # 181 C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 15 0027 8003 SJMP ?C0036 0029 ?C0035: ; SOURCE LINE # 183 ; SOURCE LINE # 184 0029 53A8FB ANL IE,#0FBH ; SOURCE LINE # 185 002C ?C0036: ; SOURCE LINE # 187 002C EB MOV A,R3 002D 7004 JNZ ?C0037 ; SOURCE LINE # 188 ; SOURCE LINE # 189 002F 53B8FB ANL IP,#0FBH ; SOURCE LINE # 190 0032 22 RET 0033 ?C0037: ; SOURCE LINE # 192 ; SOURCE LINE # 193 0033 43B804 ORL IP,#04H ; SOURCE LINE # 194 ; SOURCE LINE # 195 0036 22 RET ; SOURCE LINE # 197 0037 ?C0039: ; SOURCE LINE # 198 0037 ED MOV A,R5 0038 6005 JZ ?C0040 ; SOURCE LINE # 199 ; SOURCE LINE # 200 003A 43A908 ORL IE1,#08H ; SOURCE LINE # 201 003D 8003 SJMP ?C0041 003F ?C0040: ; SOURCE LINE # 203 ; SOURCE LINE # 204 003F 53A9F7 ANL IE1,#0F7H ; SOURCE LINE # 205 0042 ?C0041: ; SOURCE LINE # 207 0042 EB MOV A,R3 0043 7004 JNZ ?C0042 ; SOURCE LINE # 208 ; SOURCE LINE # 209 0045 53B9F7 ANL IP1,#0F7H ; SOURCE LINE # 210 0048 22 RET 0049 ?C0042: ; SOURCE LINE # 212 ; SOURCE LINE # 213 0049 43B908 ORL IP1,#08H ; SOURCE LINE # 214 ; SOURCE LINE # 215 ; SOURCE LINE # 217 ; SOURCE LINE # 218 ; SOURCE LINE # 219 ; SOURCE LINE # 220 004C ?C0045: 004C 22 RET ; FUNCTION _EXTI_ITConfig (END) C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 16 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== uint16_t . . . . . . . . . . . . . . . TYPEDEF ----- U_INT ----- 2 OPREG. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FFH 1 P0 . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0080H 1 SSDAT. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009FH 1 P1 . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0090H 1 P2 . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A0H 1 EUART. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00ACH 1 TMCON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008EH 1 AC . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D6H 1 FlagStatus . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 RESET. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 OTCON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008FH 1 EA . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00AFH 1 T2 . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00C9H 1 int32_t. . . . . . . . . . . . . . . . TYPEDEF ----- LONG ----- 4 PWMCON0. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D2H 1 PWMCON1. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DAH 1 int16_t. . . . . . . . . . . . . . . . TYPEDEF ----- INT ----- 2 EXTI_TRIGGER_DISABLE . . . . . . . . . E_CONST ----- U_CHAR ----- 1 ERROR. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 EADC . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00AEH 1 IE . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A8H 1 OPINX. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FEH 1 CP . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00C8H 1 _EXTI_ITConfig . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- INTx . . . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 NewState . . . . . . . . . . . . . . * REG * DATA U_CHAR 0005H 1 Priority . . . . . . . . . . . . . . * REG * DATA U_CHAR 0003H 1 ErrorStatus. . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 EXF2 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CEH 1 CHKSUMH. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FDH 1 PWMDTY0. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D5H 1 OPERCON. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00EFH 1 PWMDTY1. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D6H 1 P0PH . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009BH 1 IP . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00B8H 1 CHKSUML. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FCH 1 PWMDTY2. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D7H 1 P1PH . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0092H 1 EXTI0x_Typedef . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 RI . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0098H 1 PWMDTY3. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DCH 1 P2PH . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A2H 1 EXTI1x_Typedef . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 INT0 . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SUCCESS. . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 CY . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D7H 1 PWMDTY4. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DDH 1 EXTI2x_Typedef . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 INT1 . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 TI . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0099H 1 PWMDTY5. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DEH 1 INT2 . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 IPT0 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00B9H 1 PWMDTY6. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DFH 1 FunctionalState. . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 IPT1 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BBH 1 C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 17 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== IPT2 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BDH 1 HIGH . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 RCAP2H . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CBH 1 SP . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0081H 1 OV . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D2H 1 ITStatus . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 IAPADE . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F4H 1 RCAP2L . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CAH 1 ENABLE . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 BitStatus. . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 IAPADH . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F3H 1 PWMDTYA. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D4H 1 PWMDTYB. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DBH 1 ADCCON . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00ADH 1 s8 . . . . . . . . . . . . . . . . . . TYPEDEF ----- CHAR ----- 1 u8 . . . . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 RCLK . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CDH 1 IAPADL . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F2H 1 bool . . . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 TCLK . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CCH 1 P00. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0080H 1 P10. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0090H 1 P01. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0081H 1 SBUF . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0099H 1 PCON . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0087H 1 P20. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A0H 1 P11. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0091H 1 EXTI_TriggerMode_Typedef . . . . . . . TYPEDEF ----- U_CHAR ----- 1 P21. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A1H 1 P12. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0092H 1 P22. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A2H 1 P13. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0093H 1 SCON . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0098H 1 _EXTI_SetExtInt0xTriggerMode . . . . . PUBLIC CODE PROC 0000H ----- INT0x. . . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 TriggerMode. . . . . . . . . . . . . * REG * DATA U_CHAR 0005H 1 P23. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A3H 1 P14. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0094H 1 IAPDAT . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F5H 1 TCON . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0088H 1 TMOD . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0089H 1 _EXTI_SetExtInt1xTriggerMode . . . . . PUBLIC CODE PROC 0000H ----- INT1x. . . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 TriggerMode. . . . . . . . . . . . . * REG * DATA U_CHAR 0005H 1 P24. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A4H 1 P15. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0095H 1 IPINT0 . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00B8H 1 _EXTI_SetExtInt2xTriggerMode . . . . . PUBLIC CODE PROC 0000H ----- INT2x. . . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 TriggerMode. . . . . . . . . . . . . * REG * DATA U_CHAR 0005H 1 P25. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A5H 1 P16. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0096H 1 IPINT1 . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BAH 1 P26. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A6H 1 P17. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0097H 1 SSCON0 . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009DH 1 P27. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A7H 1 C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 18 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== SSCON1 . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009EH 1 SSCON2 . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0095H 1 IAPCTL . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F6H 1 IE1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A9H 1 TRUE . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 B. . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F0H 1 IAPKEY . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F1H 1 BTMCON . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CEH 1 PWMCFG . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D1H 1 ACC. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00E0H 1 EXTI_TRIGGER_RISE_FALL . . . . . . . . E_CONST ----- U_CHAR ----- 1 ET0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A9H 1 TF0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008DH 1 ET1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00ABH 1 ADCCFG0. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00ABH 1 IP1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00B9H 1 TF1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008FH 1 ET2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00ADH 1 ADCCFG1. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00AAH 1 INT00. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 RB8. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009AH 1 TF2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CFH 1 TH0. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008CH 1 INT10. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 INT01. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 TH1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008DH 1 INT11. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 TB8. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009BH 1 TH2. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CDH 1 INT21. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 INT12. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 uint8_t. . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 P. . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D0H 1 INT22. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 INT13. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SM0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009FH 1 TL0. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008AH 1 INT23. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 INT14. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SM1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009EH 1 WDTCON . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CFH 1 TL1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008BH 1 INT24. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 INT15. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 SM2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009DH 1 TL2. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CCH 1 INT25. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 INT16. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 INT26. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 INT27. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 RS0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D3H 1 TR0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008CH 1 RS1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D4H 1 TR1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008EH 1 IPUART . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BCH 1 EXTI_TRIGGER_FALL_ONLY . . . . . . . . E_CONST ----- U_CHAR ----- 1 s32. . . . . . . . . . . . . . . . . . TYPEDEF ----- LONG ----- 4 C51 COMPILER V9.60.7.0 SC92F8003_EXTI 05/13/2024 00:07:50 PAGE 19 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== TR2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CAH 1 int8_t . . . . . . . . . . . . . . . . TYPEDEF ----- CHAR ----- 1 u32. . . . . . . . . . . . . . . . . . TYPEDEF ----- U_LONG ----- 4 s16. . . . . . . . . . . . . . . . . . TYPEDEF ----- INT ----- 2 _EXTI_DeInit . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- INTx . . . . . . . . . . . . . . . . * REG * DATA U_CHAR 0007H 1 u16. . . . . . . . . . . . . . . . . . TYPEDEF ----- U_INT ----- 2 PWMPRD . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D3H 1 DPH. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0083H 1 DPL. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0082H 1 EINT0. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A8H 1 P0CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009AH 1 EINT1. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00AAH 1 IPADC. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BEH 1 INT0F. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BAH 1 P1CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0091H 1 EXEN2. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CBH 1 INT1F. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BCH 1 P2CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A1H 1 INT2F. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C6H 1 REN. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009CH 1 ADCVH. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00AFH 1 T2MOD. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C9H 1 T2CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C8H 1 EXTIx_Typedef. . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 ADCVL. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00AEH 1 EXTI_TRIGGER_RISE_ONLY . . . . . . . . E_CONST ----- U_CHAR ----- 1 SET. . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 FALSE. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 INT0R. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BBH 1 INT1R. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BDH 1 PriorityStatus . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 INT2R. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C7H 1 LOW. . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 F0 . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D5H 1 DISABLE. . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 F1 . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D1H 1 PSW. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D0H 1 uint32_t . . . . . . . . . . . . . . . TYPEDEF ----- U_LONG ----- 4 MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 259 ---- CONSTANT SIZE = ---- ---- XDATA SIZE = ---- ---- PDATA SIZE = ---- ---- DATA SIZE = ---- ---- IDATA SIZE = ---- ---- BIT SIZE = ---- ---- EDATA SIZE = ---- ---- HDATA SIZE = ---- ---- XDATA CONST SIZE = ---- ---- FAR CONST SIZE = ---- ---- END OF MODULE INFORMATION. C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)