C51 COMPILER V9.60.7.0 INTERRUPT 05/12/2024 23:50:37 PAGE 1 C51 COMPILER V9.60.7.0, COMPILATION OF MODULE INTERRUPT OBJECT MODULE PLACED IN .\Objects\Interrupt.obj COMPILER INVOKED BY: d:\Keil\C51\BIN\C51.EXE Src\Interrupt.c OMF2 OPTIMIZE(8,SPEED) BROWSE INCDIR(.\Src;.\Task;.\Task\cp -u_port\S92F8003A;.\Task\cfg;.\Task\pt_thread;.\SC92F8003_Lib\Inc) DEBUG CODE LISTINCLUDE SYMBOLS PRINT(.\Listings\Interr -upt.lst) PREPRINT(.\Listings\Interrupt.i) OBJECT(.\Objects\Interrupt.obj) line level source 1 2 #include "task_hal_cfg.h" 1 =1 #ifndef _TASK_HAL_CFG_H_ 2 =1 #define _TASK_HAL_CFG_H_ 3 =1 4 =1 5 =1 #include 1 =2 #ifndef _SC92F8003_H 2 =2 #define _SC92F8003_H 3 =2 4 =2 #include "SC92F8003_C.H" 1 =3 /*-------------------------------------------------------------------------- 2 =3 SC92F8003_C.H 3 =3 4 =3 C Header file for SC92F8003 microcontroller. 5 =3 Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. 6 =3 All rights reserved. 7 =3 ÉîÛÚÊÐÈüԪ΢µç×ÓÓÐÏÞ¹«Ë¾ 8 =3 °æ±¾ºÅ: V1.0 9 =3 ÈÕÆÚ: 2018.05.02 10 =3 --------------------------------------------------------------------------*/ 11 =3 #ifndef _SC92F8003_H_ 12 =3 #define _SC92F8003_H_ 13 =3 14 =3 /* ------------------- ×ֽڼĴæÆ÷-------------------- */ 15 =3 ///*CPU*/ 16 =3 sfr ACC = 0xE0; //ÀÛ¼ÓÆ÷£Á 17 =3 sfr B = 0xF0; //ͨÓüĴæÆ÷B 18 =3 sfr PSW = 0xD0; //³ÌÐò״̬×Ö 19 =3 sfr DPH = 0x83; //Êý¾ÝÖ¸Õë¸ß8λ 20 =3 sfr DPL = 0x82; //Êý¾ÝÖ¸ÕëµÍ8λ 21 =3 sfr SP = 0x81; //¶ÑÕ»Ö¸Õë 22 =3 23 =3 24 =3 /*system*/ 25 =3 sfr PCON = 0x87; //µçÔ´¹ÜÀí¿ØÖƼĴæÆ÷ 26 =3 27 =3 /*interrupt*/ 28 =3 sfr IP1 = 0XB9; //ÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷1 29 =3 sfr IP = 0xB8; //ÖжÏÓÅÏÈȨ¿ØÖƼĴæÆ÷ 30 =3 sfr IE = 0xA8; //ÖжϿØÖƼĴæÆ÷ 31 =3 sfr IE1 = 0XA9; //ÖжϿØÖƼĴæÆ÷1 32 =3 33 =3 /*PORT*/ 34 =3 sfr P2PH = 0xA2; //P2¿Úģʽ¿ØÖƼĴæÆ÷ 35 =3 sfr P2CON = 0xA1; //P2¿Úģʽ¿ØÖƼĴæÆ÷ 36 =3 sfr P2 = 0xA0; //P2¿ÚÊý¾Ý¼Ä´æÆ÷ 37 =3 sfr P1PH = 0x92; //P1¿Úģʽ¿ØÖƼĴæÆ÷ 38 =3 sfr P1CON = 0x91; //P1¿Úģʽ¿ØÖƼĴæÆ÷ 39 =3 sfr P1 = 0x90; //P1¿ÚÊý¾Ý¼Ä´æÆ÷ 40 =3 sfr P0PH = 0x9B; //P0¿Úģʽ¿ØÖƼĴæÆ÷ 41 =3 sfr P0CON = 0x9A; //P0¿Úģʽ¿ØÖƼĴæÆ÷ 42 =3 sfr P0 = 0x80; //P0¿ÚÊý¾Ý¼Ä´æÆ÷ C51 COMPILER V9.60.7.0 INTERRUPT 05/12/2024 23:50:37 PAGE 2 43 =3 44 =3 /*TIMER*/ 45 =3 sfr TMCON = 0x8E; //¶¨Ê±Æ÷ƵÂÊ¿ØÖƼĴæÆ÷ 46 =3 sfr TH1 = 0x8D; //¶¨Ê±Æ÷1¸ß8λ 47 =3 sfr TH0 = 0x8C; //¶¨Ê±Æ÷0¸ß8λ 48 =3 sfr TL1 = 0x8B; //¶¨Ê±Æ÷1µÍ8λ 49 =3 sfr TL0 = 0x8A; //¶¨Ê±Æ÷0µÍ8λ 50 =3 sfr TMOD = 0x89; //¶¨Ê±Æ÷¹¤×÷ģʽ¼Ä´æÆ÷ 51 =3 sfr TCON = 0x88; //¶¨Ê±Æ÷¿ØÖƼĴæÆ÷ 52 =3 sfr T2CON = 0xC8; //¶¨Ê±Æ÷2¿ØÖƼĴæÆ÷ 53 =3 sfr T2MOD = 0xC9; //¶¨Ê±Æ÷2¹¤×÷ģʽ¼Ä´æÆ÷ 54 =3 sfr RCAP2L = 0xCA; //¶¨Ê±Æ÷2ÖØÔØ/²¶×½µÍ8λ 55 =3 sfr RCAP2H = 0xCB; //¶¨Ê±Æ÷2ÖØÔØ/²¶×½¸ß8λ 56 =3 sfr TL2 = 0xCC; //¶¨Ê±Æ÷2µÍ8λ 57 =3 sfr TH2 = 0xCD; //¶¨Ê±Æ÷2¸ß8λ 58 =3 59 =3 60 =3 /*ADC*/ 61 =3 sfr ADCCFG1 = 0xAA; //ADC¹¦ÄÜÅäÖüĴæÆ÷0 62 =3 sfr ADCCFG0 = 0xAB; //ADC¹¦ÄÜÅäÖüĴæÆ÷1 63 =3 sfr ADCCON = 0XAD; //ADC¿ØÖƼĴæÆ÷ 64 =3 sfr ADCVL = 0xAE; //ADC ½á¹û¼Ä´æÆ÷ 65 =3 sfr ADCVH = 0xAF; //ADC ½á¹û¼Ä´æÆ÷ 66 =3 67 =3 /*PWM*/ 68 =3 sfr PWMCFG = 0xD1; //PWMÉèÖüĴæÆ÷ 69 =3 sfr PWMCON0 = 0xD2; //PWM¿ØÖƼĴæÆ÷ 70 =3 sfr PWMPRD = 0xD3; //PWMÖÜÆÚÉèÖüĴæÆ÷ 71 =3 sfr PWMDTYA = 0xD4; //PWMÕ¼¿Õ±ÈÉèÖüĴæÆ÷A 72 =3 sfr PWMDTY0 = 0xD5; //PWM0ÉèÖüĴæÆ÷ 73 =3 sfr PWMDTY1 = 0xD6; //PWM1ÉèÖüĴæÆ÷ 74 =3 sfr PWMDTY2 = 0xD7; //PWM2ÉèÖüĴæÆ÷ 75 =3 sfr PWMCON1 = 0xDA; //PWM¿ØÖƼĴæÆ÷ 76 =3 sfr PWMDTYB = 0xDB; //PWMÕ¼¿Õ±ÈÉèÖüĴæÆ÷B 77 =3 sfr PWMDTY3 = 0xDC; //PWM3ÉèÖüĴæÆ÷ 78 =3 sfr PWMDTY4 = 0xDD; //PWM4ÉèÖüĴæÆ÷ 79 =3 sfr PWMDTY5 = 0xDE; //PWM5ÉèÖüĴæÆ÷ 80 =3 sfr PWMDTY6 = 0xDF; //PWM6ÉèÖüĴæÆ÷ 81 =3 82 =3 83 =3 // 84 =3 ///*WatchDog*/ 85 =3 sfr BTMCON = 0XCE; //µÍƵ¶¨Ê±Æ÷¿ØÖƼĴæÆ÷ 86 =3 sfr WDTCON = 0xCF; //WDT¿ØÖƼĴæÆ÷ 87 =3 88 =3 89 =3 sfr OTCON = 0X8F; //Êä³ö¿ØÖƼĴæÆ÷ 90 =3 91 =3 /*INT*/ 92 =3 sfr INT0F = 0XBA; //INT0 ϽµÑØÖжϿØÖƼĴæÆ÷ 93 =3 sfr INT0R = 0XBB; //INT0 ÉϽµÑØÖжϿØÖƼĴæÆ÷ 94 =3 sfr INT1F = 0XBC; //INT1 ϽµÑØÖжϿØÖƼĴæÆ÷ 95 =3 sfr INT1R = 0XBD; //INT1 ÉϽµÑØÖжϿØÖƼĴæÆ÷ 96 =3 sfr INT2F = 0XC6; //INT2 ϽµÑØÖжϿØÖƼĴæÆ÷ 97 =3 sfr INT2R = 0XC7; //INT2 ÉϽµÑØÖжϿØÖƼĴæÆ÷ 98 =3 99 =3 /*IAP */ 100 =3 sfr IAPCTL = 0xF6; //IAP¿ØÖƼĴæÆ÷ 101 =3 sfr IAPDAT = 0xF5; //IAPÊý¾Ý¼Ä´æÆ÷ 102 =3 sfr IAPADE = 0xF4; //IAPÀ©Õ¹µØÖ·¼Ä´æÆ÷ 103 =3 sfr IAPADH = 0xF3; //IAPдÈëµØÖ·¸ßλ¼Ä´æÆ÷ 104 =3 sfr IAPADL = 0xF2; //IAPдÈëµØÖ·µÍ8λ¼Ä´æÆ÷ C51 COMPILER V9.60.7.0 INTERRUPT 05/12/2024 23:50:37 PAGE 3 105 =3 sfr IAPKEY = 0xF1; //IAP±£»¤¼Ä´æÆ÷ 106 =3 107 =3 /*uart0*/ 108 =3 sfr SCON = 0X98; //uart¿ØÖƼĴæÆ÷ 109 =3 sfr SBUF = 0X99; //uart0Êý¾Ý¼Ä´æÆ÷ 110 =3 111 =3 /*ÈýºÏÒ»*/ 112 =3 sfr SSCON0 = 0X9D; //SSI¿ØÖƼĴæÆ÷0 113 =3 sfr SSCON1 = 0X9E; //SSI¿ØÖƼĴæÆ÷1 114 =3 sfr SSCON2 = 0X95; //SSI¿ØÖƼĴæÆ÷2 115 =3 sfr SSDAT = 0X9F; //SSIÊý¾Ý¼Ä´æÆ÷ 116 =3 117 =3 sfr OPINX = 0XFE; 118 =3 sfr OPREG = 0XFF; 119 =3 120 =3 /*Check Sum*/ 121 =3 sfr CHKSUML = 0XFC; //Check Sum½á¹û¼Ä´æÆ÷µÍλ 122 =3 sfr CHKSUMH = 0XFD; //Check Sum½á¹û¼Ä´æÆ÷¸ßλ 123 =3 124 =3 sfr OPERCON = 0xEF; //ÔËËã¿ØÖƼĴæÆ÷ 125 =3 126 =3 ///* ------------------- λ¼Ä´æÆ÷-------------------- */ 127 =3 /*PSW*/ 128 =3 sbit CY = PSW^7; //±ê־λ 0:¼Ó·¨ÔËËã×î¸ßλÎÞ½ø룬»òÕß¼õ·¨ÔËËã×î¸ßλÎÞ½èλʱ 1:¼Ó·¨ÔËËã×î¸ßλÓнø -룬»òÕß¼õ·¨ÔËËã×î¸ßλÓнèλʱ 129 =3 sbit AC = PSW^6; //½øλ¸¨Öú±ê־λ 0:ÎÞ½èλ¡¢½øλ 1:¼Ó·¨ÔËËãʱÔÚbit3λÓнø룬»ò¼õ·¨ÔËËãÔÚbit3λÓн -èλʱ 130 =3 sbit F0 = PSW^5; //Óû§±ê־λ 131 =3 sbit RS1 = PSW^4; //¹¤×÷¼Ä´æÆ÷×éÑ¡Ôñλ 132 =3 sbit RS0 = PSW^3; //¹¤×÷¼Ä´æÆ÷×éÑ¡Ôñλ 133 =3 sbit OV = PSW^2; //Òç³ö±ê־λ 134 =3 sbit F1 = PSW^1; //F1±êÖ¾ 135 =3 sbit P = PSW^0; //Ææż±ê־λ 0:ACCÖÐ1µÄ¸öÊýΪżÊý£¨°üÀ¨0¸ö£© 1:ACCÖÐ1µÄ¸öÊýΪÆæÊý 136 =3 137 =3 /*T2CON*/ 138 =3 sbit TF2 = T2CON^7; 139 =3 sbit EXF2 = T2CON^6; 140 =3 sbit RCLK = T2CON^5; 141 =3 sbit TCLK = T2CON^4; 142 =3 sbit EXEN2 = T2CON^3; 143 =3 sbit TR2 = T2CON^2; 144 =3 sbit T2 = T2CON^1; 145 =3 sbit CP = T2CON^0; 146 =3 147 =3 148 =3 /*IP*/ 149 =3 sbit IPADC = IP^6; //ADCÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 ADCµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 ADCµÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß¡ -± 150 =3 sbit IPT2 = IP^5; //PWMÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 PWMµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 PWM µÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß -¡± 151 =3 sbit IPUART = IP^4; //SIFÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 SIFµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 SIFµÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß¡ -± 152 =3 sbit IPT1 = IP^3; //Timer1ÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 Timer 1µÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 Timer 1µÄÖжÏÓÅÏÈÈ -¨ÊÇ ¡°¸ß¡± 153 =3 sbit IPINT1 = IP^2; //32K Base TimerÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 32KµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 32KµÄÖжÏÓÅ -ÏÈȨÊÇ ¡°¸ß¡± 154 =3 sbit IPT0 = IP^1; //Timer0ÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 Timer 0µÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 Timer 0µÄÖжÏÓÅÏÈÈ -¨ÊÇ ¡°¸ß¡± 155 =3 sbit IPINT0 = IP^0; 156 =3 157 =3 /*IE*/ 158 =3 sbit EA = IE^7; //ÖжÏʹÄܵÄ×Ü¿ØÖÆ 0:¹Ø±ÕËùÓеÄÖÐ¶Ï 1:´ò¿ªËùÓеÄÖÐ¶Ï C51 COMPILER V9.60.7.0 INTERRUPT 05/12/2024 23:50:37 PAGE 4 159 =3 sbit EADC = IE^6; //ADCÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕADCÖÐ¶Ï 1:´ò¿ªADCÖÐ¶Ï 160 =3 sbit ET2 = IE^5; //PWMÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕPWMÖÐ¶Ï 1:´ò¿ªPWMÖÐ¶Ï 161 =3 sbit EUART = IE^4; //UARTÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕSIFÖÐ¶Ï 1:´ò¿ªSIFÖÐ¶Ï 162 =3 sbit ET1 = IE^3; //Timer1ÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTIMER1ÖÐ¶Ï 1:´ò¿ªTIMER1ÖÐ¶Ï 163 =3 sbit EINT1 = IE^2; //32K Base TimerÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±Õ32KÖÐ¶Ï 1:´ò¿ª32KÖÐ¶Ï 164 =3 sbit ET0 = IE^1; //Timer0ÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTIMER0ÖÐ¶Ï 1:´ò¿ªTIMER0ÖÐ¶Ï 165 =3 sbit EINT0 = IE^0; //TouchKeyµÄÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTouchKeyÖÐ¶Ï 1:´ò¿ªTouchKeyÖÐ¶Ï 166 =3 167 =3 /*TCON*/ 168 =3 sbit TF1 = TCON^7; //T1Òç³öÖжÏÇëÇó±ê־λ T1²úÉúÒç³ö£¬·¢ÉúÖжÏʱ£¬Ó²¼þ½«TF1ÖÃΪ¡°1¡±£¬ÉêÇëÖжϣ¬CPU -ÏìӦʱ£¬Ó²¼þÇå¡°0¡±¡£ 169 =3 sbit TR1 = TCON^6; //¶¨Ê±Æ÷T1µÄÔËÐпØÖÆλ 0:Timer1½ûÖ¹¼ÆÊý 1:Timer1¿ªÊ¼¼ÆÊý 170 =3 sbit TF0 = TCON^5; //T0Òç³öÖжÏÇëÇó±ê־λ T0²úÉúÒç³ö£¬·¢ÉúÖжÏʱ£¬Ó²¼þ½«TF0ÖÃΪ¡°1¡±£¬ÉêÇëÖжϣ¬CPU -ÏìӦʱ£¬Ó²¼þÇå¡°0¡±¡£ 171 =3 sbit TR0 = TCON^4; //¶¨Ê±Æ÷T0µÄÔËÐпØÖÆλ 0:Timer0½ûÖ¹¼ÆÊý 1:Timer0¿ªÊ¼¼ÆÊý 172 =3 173 =3 /*SCON*/ 174 =3 sbit SM0 = SCON^7; 175 =3 sbit SM1 = SCON^6; 176 =3 sbit SM2 = SCON^5; 177 =3 sbit REN = SCON^4; 178 =3 sbit TB8 = SCON^3; 179 =3 sbit RB8 = SCON^2; 180 =3 sbit TI = SCON^1; 181 =3 sbit RI = SCON^0; 182 =3 183 =3 /* P0 */ 184 =3 sbit P01 = P0^1; 185 =3 sbit P00 = P0^0; 186 =3 187 =3 /* P1 */ 188 =3 sbit P17 = P1^7; 189 =3 sbit P16 = P1^6; 190 =3 sbit P15 = P1^5; 191 =3 sbit P14 = P1^4; 192 =3 sbit P13 = P1^3; 193 =3 sbit P12 = P1^2; 194 =3 sbit P11 = P1^1; 195 =3 sbit P10 = P1^0; 196 =3 197 =3 /* P2 */ 198 =3 sbit P27 = P2^7; 199 =3 sbit P26 = P2^6; 200 =3 sbit P25 = P2^5; 201 =3 sbit P24 = P2^4; 202 =3 sbit P23 = P2^3; 203 =3 sbit P22 = P2^2; 204 =3 sbit P21 = P2^1; 205 =3 sbit P20 = P2^0; 206 =3 207 =3 #endif 5 =2 6 =2 #define enableInterrupts() EA=1 /** ¿ªÆô×ÜÖÐ¶Ï **/ 7 =2 #define disableInterrupts() EA=0 /** ¹Ø±Õ×ÜÖÐ¶Ï **/ 8 =2 9 =2 #define __I volatile const /*!< defines 'read only' permissions */ 10 =2 #define __O volatile /*!< defines 'write only' permissions */ 11 =2 #define __IO volatile /*!< defines 'read / write' permissions */ 12 =2 13 =2 /*!< Signed integer types */ 14 =2 typedef signed char int8_t; 15 =2 typedef signed short int16_t; C51 COMPILER V9.60.7.0 INTERRUPT 05/12/2024 23:50:37 PAGE 5 16 =2 typedef signed long int32_t; 17 =2 18 =2 /*!< Unsigned integer types */ 19 =2 typedef unsigned char uint8_t; 20 =2 typedef unsigned short uint16_t; 21 =2 typedef unsigned long uint32_t; 22 =2 23 =2 typedef int32_t s32; 24 =2 typedef int16_t s16; 25 =2 typedef int8_t s8; 26 =2 27 =2 typedef uint32_t u32; 28 =2 typedef uint16_t u16; 29 =2 typedef uint8_t u8; 30 =2 31 =2 32 =2 typedef enum {FALSE = 0, TRUE = !FALSE} bool; 33 =2 34 =2 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus; 35 =2 36 =2 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 37 =2 38 =2 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; 39 =2 40 =2 typedef enum {LOW = 0, HIGH = !LOW} PriorityStatus; 41 =2 42 =2 #endif 6 =1 7 =1 #define INT_EXT0 0 8 =1 #define INT_T0 1 9 =1 #define INT_EXT1 2 10 =1 #define INT_T1 3 11 =1 #define INT_UART0 4 12 =1 #define INT_T2 5 13 =1 #define INT_ADC 6 14 =1 #define INT_SSI 7 15 =1 #define INT_PWM 8 16 =1 #define INT_BTM 9 17 =1 #define INT_EXT2 10 18 =1 19 =1 20 =1 21 =1 #define GPIOR GPIO1 22 =1 #define GPIOG GPIO2 23 =1 #define GPIOB GPIO2 24 =1 #define GPIOC GPIO2 25 =1 #define GPIOW GPIO2 26 =1 27 =1 #define LEDR GPIO_PIN_0 28 =1 #define LEDG GPIO_PIN_7 29 =1 #define LEDB GPIO_PIN_6 30 =1 #define LEDC GPIO_PIN_5 31 =1 #define LEDW GPIO_PIN_4 32 =1 33 =1 34 =1 35 =1 #endif 3 void EXT0_Handler(void) interrupt INT_EXT0 4 { 5 1 } 6 7 //void T0_Handler(void) interrupt INT_T0 C51 COMPILER V9.60.7.0 INTERRUPT 05/12/2024 23:50:37 PAGE 6 8 9 void EXT1_Handler(void) interrupt INT_EXT1 10 { 11 1 } 12 13 void T1_Handler(void) interrupt INT_T1 14 { 15 1 } 16 17 void UART_Handler(void) interrupt INT_UART0 18 { 19 1 } 20 21 void T2_Handler(void) interrupt INT_T2 22 { 23 1 } 24 25 void ADC_Handler(void) interrupt INT_ADC 26 { 27 1 } 28 29 void SSI_Handler(void) interrupt INT_SSI 30 { 31 1 } 32 33 void PWM_Handler(void) interrupt INT_PWM 34 { 35 1 } 36 37 void BTM_Handler(void) interrupt INT_BTM 38 { 39 1 } 40 41 void EXT2_Handler(void) interrupt INT_EXT2 42 { 43 1 } 44 C51 COMPILER V9.60.7.0 INTERRUPT 05/12/2024 23:50:37 PAGE 7 ASSEMBLY LISTING OF GENERATED OBJECT CODE ; FUNCTION EXT0_Handler (BEGIN) ; SOURCE LINE # 3 ; SOURCE LINE # 5 0000 32 RETI ; FUNCTION EXT0_Handler (END) ; FUNCTION EXT1_Handler (BEGIN) ; SOURCE LINE # 9 ; SOURCE LINE # 11 0000 32 RETI ; FUNCTION EXT1_Handler (END) ; FUNCTION T1_Handler (BEGIN) ; SOURCE LINE # 13 ; SOURCE LINE # 15 0000 32 RETI ; FUNCTION T1_Handler (END) ; FUNCTION UART_Handler (BEGIN) ; SOURCE LINE # 17 ; SOURCE LINE # 19 0000 32 RETI ; FUNCTION UART_Handler (END) ; FUNCTION T2_Handler (BEGIN) ; SOURCE LINE # 21 ; SOURCE LINE # 23 0000 32 RETI ; FUNCTION T2_Handler (END) ; FUNCTION ADC_Handler (BEGIN) ; SOURCE LINE # 25 ; SOURCE LINE # 27 0000 32 RETI ; FUNCTION ADC_Handler (END) ; FUNCTION SSI_Handler (BEGIN) ; SOURCE LINE # 29 ; SOURCE LINE # 31 0000 32 RETI ; FUNCTION SSI_Handler (END) ; FUNCTION PWM_Handler (BEGIN) ; SOURCE LINE # 33 ; SOURCE LINE # 35 0000 32 RETI ; FUNCTION PWM_Handler (END) ; FUNCTION BTM_Handler (BEGIN) ; SOURCE LINE # 37 ; SOURCE LINE # 39 0000 32 RETI ; FUNCTION BTM_Handler (END) ; FUNCTION EXT2_Handler (BEGIN) ; SOURCE LINE # 41 ; SOURCE LINE # 43 0000 32 RETI ; FUNCTION EXT2_Handler (END) C51 COMPILER V9.60.7.0 INTERRUPT 05/12/2024 23:50:37 PAGE 8 C51 COMPILER V9.60.7.0 INTERRUPT 05/12/2024 23:50:37 PAGE 9 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== uint16_t . . . . . . . . . . . . . . . TYPEDEF ----- U_INT ----- 2 OPREG. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FFH 1 P0 . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0080H 1 SSDAT. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009FH 1 P1 . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0090H 1 P2 . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A0H 1 EUART. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00ACH 1 TMCON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008EH 1 AC . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D6H 1 FlagStatus . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 RESET. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 OTCON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008FH 1 EA . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00AFH 1 T2 . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00C9H 1 BTM_Handler. . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- int32_t. . . . . . . . . . . . . . . . TYPEDEF ----- LONG ----- 4 PWMCON0. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D2H 1 PWMCON1. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DAH 1 int16_t. . . . . . . . . . . . . . . . TYPEDEF ----- INT ----- 2 ERROR. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 EADC . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00AEH 1 IE . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A8H 1 OPINX. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FEH 1 SSI_Handler. . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- CP . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00C8H 1 ErrorStatus. . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 EXF2 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CEH 1 CHKSUMH. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FDH 1 PWM_Handler. . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- PWMDTY0. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D5H 1 OPERCON. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00EFH 1 PWMDTY1. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D6H 1 P0PH . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009BH 1 IP . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00B8H 1 CHKSUML. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00FCH 1 PWMDTY2. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D7H 1 P1PH . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0092H 1 RI . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0098H 1 PWMDTY3. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DCH 1 P2PH . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A2H 1 SUCCESS. . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 CY . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D7H 1 PWMDTY4. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DDH 1 TI . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0099H 1 PWMDTY5. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DEH 1 IPT0 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00B9H 1 PWMDTY6. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DFH 1 FunctionalState. . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 IPT1 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BBH 1 IPT2 . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BDH 1 HIGH . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 RCAP2H . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CBH 1 SP . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0081H 1 OV . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D2H 1 ITStatus . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 IAPADE . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F4H 1 RCAP2L . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CAH 1 C51 COMPILER V9.60.7.0 INTERRUPT 05/12/2024 23:50:37 PAGE 10 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== T1_Handler . . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- T2_Handler . . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- ENABLE . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 BitStatus. . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 IAPADH . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F3H 1 PWMDTYA. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D4H 1 PWMDTYB. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00DBH 1 ADCCON . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00ADH 1 s8 . . . . . . . . . . . . . . . . . . TYPEDEF ----- CHAR ----- 1 u8 . . . . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 RCLK . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CDH 1 IAPADL . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F2H 1 bool . . . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 TCLK . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CCH 1 P00. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0080H 1 P10. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0090H 1 P01. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0081H 1 SBUF . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0099H 1 PCON . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0087H 1 P20. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A0H 1 P11. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0091H 1 P21. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A1H 1 P12. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0092H 1 P22. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A2H 1 P13. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0093H 1 SCON . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0098H 1 P23. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A3H 1 P14. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0094H 1 IAPDAT . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F5H 1 TCON . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0088H 1 TMOD . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0089H 1 P24. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A4H 1 P15. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0095H 1 IPINT0 . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00B8H 1 P25. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A5H 1 P16. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0096H 1 IPINT1 . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BAH 1 P26. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A6H 1 P17. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 0097H 1 SSCON0 . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009DH 1 P27. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A7H 1 SSCON1 . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009EH 1 SSCON2 . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0095H 1 IAPCTL . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F6H 1 IE1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A9H 1 TRUE . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 B. . . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F0H 1 EXT0_Handler . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- IAPKEY . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00F1H 1 BTMCON . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CEH 1 EXT1_Handler . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- PWMCFG . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D1H 1 EXT2_Handler . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- ACC. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00E0H 1 ET0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A9H 1 TF0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008DH 1 ET1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00ABH 1 C51 COMPILER V9.60.7.0 INTERRUPT 05/12/2024 23:50:37 PAGE 11 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== ADCCFG0. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00ABH 1 IP1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00B9H 1 TF1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008FH 1 ET2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00ADH 1 ADCCFG1. . . . . . . . . . . . . . . . SFR DATA U_CHAR 00AAH 1 RB8. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009AH 1 TF2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CFH 1 TH0. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008CH 1 TH1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008DH 1 TB8. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009BH 1 TH2. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CDH 1 uint8_t. . . . . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 P. . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D0H 1 SM0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009FH 1 TL0. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008AH 1 SM1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009EH 1 WDTCON . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CFH 1 TL1. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 008BH 1 SM2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009DH 1 TL2. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00CCH 1 RS0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D3H 1 TR0. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008CH 1 RS1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D4H 1 TR1. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 008EH 1 IPUART . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BCH 1 s32. . . . . . . . . . . . . . . . . . TYPEDEF ----- LONG ----- 4 TR2. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CAH 1 int8_t . . . . . . . . . . . . . . . . TYPEDEF ----- CHAR ----- 1 u32. . . . . . . . . . . . . . . . . . TYPEDEF ----- U_LONG ----- 4 s16. . . . . . . . . . . . . . . . . . TYPEDEF ----- INT ----- 2 u16. . . . . . . . . . . . . . . . . . TYPEDEF ----- U_INT ----- 2 PWMPRD . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D3H 1 DPH. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0083H 1 UART_Handler . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- DPL. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0082H 1 EINT0. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00A8H 1 P0CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 009AH 1 EINT1. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00AAH 1 IPADC. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00BEH 1 INT0F. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BAH 1 P1CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 0091H 1 EXEN2. . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00CBH 1 INT1F. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BCH 1 P2CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00A1H 1 INT2F. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C6H 1 REN. . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 009CH 1 ADCVH. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00AFH 1 T2MOD. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C9H 1 T2CON. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C8H 1 ADC_Handler. . . . . . . . . . . . . . PUBLIC CODE PROC 0000H ----- ADCVL. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00AEH 1 SET. . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 FALSE. . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 INT0R. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BBH 1 INT1R. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00BDH 1 PriorityStatus . . . . . . . . . . . . TYPEDEF ----- U_CHAR ----- 1 INT2R. . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00C7H 1 C51 COMPILER V9.60.7.0 INTERRUPT 05/12/2024 23:50:37 PAGE 12 NAME CLASS MSPACE TYPE OFFSET SIZE ==== ===== ====== ==== ====== ==== LOW. . . . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 F0 . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D5H 1 DISABLE. . . . . . . . . . . . . . . . E_CONST ----- U_CHAR ----- 1 F1 . . . . . . . . . . . . . . . . . . ABSBIT ----- BIT 00D1H 1 PSW. . . . . . . . . . . . . . . . . . SFR DATA U_CHAR 00D0H 1 uint32_t . . . . . . . . . . . . . . . TYPEDEF ----- U_LONG ----- 4 MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 40 ---- CONSTANT SIZE = ---- ---- XDATA SIZE = ---- ---- PDATA SIZE = ---- ---- DATA SIZE = ---- ---- IDATA SIZE = ---- ---- BIT SIZE = ---- ---- EDATA SIZE = ---- ---- HDATA SIZE = ---- ---- XDATA CONST SIZE = ---- ---- FAR CONST SIZE = ---- ---- END OF MODULE INFORMATION. C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)