ARM Macro Assembler Page 1 1 00000000 ;/* 2 00000000 ;* Copyright (c) 2006-2018, RT-Thread Development Team 3 00000000 ;* 4 00000000 ;* SPDX-License-Identifier: Apache-2.0 5 00000000 ;* 6 00000000 ; * Change Logs: 7 00000000 ; * Date Author Notes 8 00000000 ; * 2009-01-17 Bernard first version. 9 00000000 ; * 2012-01-01 aozima support context switch l oad/store FPU register. 10 00000000 ; * 2013-06-18 aozima add restore MSP feature. 11 00000000 ; * 2013-06-23 aozima support lazy stack optim ized. 12 00000000 ; * 2018-07-24 aozima enhancement hard fault e xception handler. 13 00000000 ; */ 14 00000000 15 00000000 ;/** 16 00000000 ; * @addtogroup cortex-m4 17 00000000 ; */ 18 00000000 ;/*@{*/ 19 00000000 20 00000000 E000ED08 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offs et Register 21 00000000 E000ED04 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register 22 00000000 E000ED20 NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority r egister (2) 23 00000000 00FF0000 NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority v alue (lowest) 24 00000000 10000000 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception 25 00000000 26 00000000 AREA |.text|, CODE, READONLY, ALIGN= 2 27 00000000 THUMB 28 00000000 REQUIRE8 29 00000000 PRESERVE8 30 00000000 31 00000000 IMPORT rt_thread_switch_interrupt_flag 32 00000000 IMPORT rt_interrupt_from_thread 33 00000000 IMPORT rt_interrupt_to_thread 34 00000000 35 00000000 ;/* 36 00000000 ; * rt_base_t rt_hw_interrupt_disable(); 37 00000000 ; */ 38 00000000 rt_hw_interrupt_disable PROC ARM Macro Assembler Page 2 39 00000000 EXPORT rt_hw_interrupt_disable 40 00000000 F3EF 8010 MRS r0, PRIMASK 41 00000004 B672 CPSID I 42 00000006 4770 BX LR 43 00000008 ENDP 44 00000008 45 00000008 ;/* 46 00000008 ; * void rt_hw_interrupt_enable(rt_base_t level); 47 00000008 ; */ 48 00000008 rt_hw_interrupt_enable PROC 49 00000008 EXPORT rt_hw_interrupt_enable 50 00000008 F380 8810 MSR PRIMASK, r0 51 0000000C 4770 BX LR 52 0000000E ENDP 53 0000000E 54 0000000E ;/* 55 0000000E ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); 56 0000000E ; * r0 --> from 57 0000000E ; * r1 --> to 58 0000000E ; */ 59 0000000E rt_hw_context_switch_interrupt 60 0000000E EXPORT rt_hw_context_switch_interrupt 61 0000000E rt_hw_context_switch PROC 62 0000000E EXPORT rt_hw_context_switch 63 0000000E 64 0000000E ; set rt_thread_switch_interrupt_flag to 1 65 0000000E 4A33 LDR r2, =rt_thread_switch_interrupt _flag 66 00000010 6813 LDR r3, [r2] 67 00000012 2B01 CMP r3, #1 68 00000014 D004 BEQ _reswitch 69 00000016 F04F 0301 MOV r3, #1 70 0000001A 6013 STR r3, [r2] 71 0000001C 72 0000001C 4A30 LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_f rom_thread 73 0000001E 6010 STR r0, [r2] 74 00000020 75 00000020 _reswitch 76 00000020 4A30 LDR r2, =rt_interrupt_to_thread ; s et rt_interrupt_to_ thread 77 00000022 6011 STR r1, [r2] 78 00000024 79 00000024 4830 LDR r0, =NVIC_INT_CTRL ; trigger th e PendSV exception (causes context swi tch) 80 00000026 F04F 5180 LDR r1, =NVIC_PENDSVSET 81 0000002A 6001 STR r1, [r0] 82 0000002C 4770 BX LR 83 0000002E ENDP 84 0000002E 85 0000002E ; r0 --> switch from thread stack 86 0000002E ; r1 --> switch to thread stack ARM Macro Assembler Page 3 87 0000002E ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from ] stack 88 0000002E PendSV_Handler PROC 89 0000002E EXPORT PendSV_Handler 90 0000002E 91 0000002E ; disable interrupt to protect context switch 92 0000002E F3EF 8210 MRS r2, PRIMASK 93 00000032 B672 CPSID I 94 00000034 95 00000034 ; get rt_thread_switch_interrupt_flag 96 00000034 4829 LDR r0, =rt_thread_switch_interrupt _flag 97 00000036 6801 LDR r1, [r0] 98 00000038 B191 CBZ r1, pendsv_exit ; pendsv alread y handled 99 0000003A 100 0000003A ; clear rt_thread_switch_interrupt_flag to 0 101 0000003A F04F 0100 MOV r1, #0x00 102 0000003E 6001 STR r1, [r0] 103 00000040 104 00000040 4827 LDR r0, =rt_interrupt_from_thread 105 00000042 6801 LDR r1, [r0] 106 00000044 B129 CBZ r1, switch_to_thread ; skip reg ister save at the f irst time 107 00000046 108 00000046 F3EF 8109 MRS r1, psp ; get from thread s tack pointer 109 0000004A 110 0000004A IF {FPU} != "SoftVFP" 113 ENDIF 114 0000004A 115 0000004A E921 0FF0 STMFD r1!, {r4 - r11} ; push r4 - r11 register 116 0000004E 117 0000004E IF {FPU} != "SoftVFP" 124 ENDIF 125 0000004E 126 0000004E 6800 LDR r0, [r0] 127 00000050 6001 STR r1, [r0] ; update from threa d stack pointer 128 00000052 129 00000052 switch_to_thread 130 00000052 4924 LDR r1, =rt_interrupt_to_thread 131 00000054 6809 LDR r1, [r1] 132 00000056 6809 LDR r1, [r1] ; load thread stack pointer 133 00000058 134 00000058 IF {FPU} != "SoftVFP" 136 ENDIF 137 00000058 138 00000058 E8B1 0FF0 LDMFD r1!, {r4 - r11} ; pop r4 - r11 register 139 0000005C 140 0000005C IF {FPU} != "SoftVFP" 143 ENDIF 144 0000005C 145 0000005C F381 8809 MSR psp, r1 ; update stack poin ARM Macro Assembler Page 4 ter 146 00000060 147 00000060 IF {FPU} != "SoftVFP" 151 ENDIF 152 00000060 153 00000060 pendsv_exit 154 00000060 ; restore interrupt 155 00000060 F382 8810 MSR PRIMASK, r2 156 00000064 157 00000064 F04E 0E04 ORR lr, lr, #0x04 158 00000068 4770 BX lr 159 0000006A ENDP 160 0000006A 161 0000006A ;/* 162 0000006A ; * void rt_hw_context_switch_to(rt_uint32 to); 163 0000006A ; * r0 --> to 164 0000006A ; * this fucntion is used to perform the first thread sw itch 165 0000006A ; */ 166 0000006A rt_hw_context_switch_to PROC 167 0000006A EXPORT rt_hw_context_switch_to 168 0000006A ; set to thread 169 0000006A 491E LDR r1, =rt_interrupt_to_thread 170 0000006C 6008 STR r0, [r1] 171 0000006E 172 0000006E IF {FPU} != "SoftVFP" 177 ENDIF 178 0000006E 179 0000006E ; set from thread to 0 180 0000006E 491C LDR r1, =rt_interrupt_from_thread 181 00000070 F04F 0000 MOV r0, #0x0 182 00000074 6008 STR r0, [r1] 183 00000076 184 00000076 ; set interrupt flag to 1 185 00000076 4919 LDR r1, =rt_thread_switch_interrupt _flag 186 00000078 F04F 0001 MOV r0, #1 187 0000007C 6008 STR r0, [r1] 188 0000007E 189 0000007E ; set the PendSV exception priority 190 0000007E 481B LDR r0, =NVIC_SYSPRI2 191 00000080 F44F 017F LDR r1, =NVIC_PENDSV_PRI 192 00000084 F8D0 2000 LDR.W r2, [r0,#0x00] ; read 193 00000088 EA41 0102 ORR r1,r1,r2 ; modify 194 0000008C 6001 STR r1, [r0] ; write-back 195 0000008E 196 0000008E ; trigger the PendSV exception (causes context switch) 197 0000008E 4816 LDR r0, =NVIC_INT_CTRL 198 00000090 F04F 5180 LDR r1, =NVIC_PENDSVSET 199 00000094 6001 STR r1, [r0] 200 00000096 201 00000096 ; restore MSP 202 00000096 4816 LDR r0, =SCB_VTOR 203 00000098 6800 LDR r0, [r0] 204 0000009A 6800 LDR r0, [r0] 205 0000009C F380 8808 MSR msp, r0 206 000000A0 207 000000A0 ; enable interrupts at processor level ARM Macro Assembler Page 5 208 000000A0 B661 CPSIE F 209 000000A2 B662 CPSIE I 210 000000A4 211 000000A4 ; never reach here! 212 000000A4 ENDP 213 000000A4 214 000000A4 ; compatible with old version 215 000000A4 rt_hw_interrupt_thread_switch PROC 216 000000A4 EXPORT rt_hw_interrupt_thread_switch 217 000000A4 4770 BX lr 218 000000A6 ENDP 219 000000A6 220 000000A6 IMPORT rt_hw_hard_fault_exception 221 000000A6 EXPORT HardFault_Handler 222 000000A6 HardFault_Handler PROC 223 000000A6 224 000000A6 ; get current context 225 000000A6 F01E 0F04 TST lr, #0x04 ; if(!EXC_RETURN[2] ) 226 000000AA BF0C ITE EQ 227 000000AC F3EF 8008 MRSEQ r0, msp ; [2]=0 ==> Z=1, ge t fault context fro m handler. 228 000000B0 F3EF 8009 MRSNE r0, psp ; [2]=1 ==> Z=0, ge t fault context fro m thread. 229 000000B4 230 000000B4 E920 0FF0 STMFD r0!, {r4 - r11} ; push r4 - r11 register 231 000000B8 IF {FPU} != "SoftVFP" 233 ENDIF 234 000000B8 F840 ED04 STMFD r0!, {lr} ; push exec_return register 235 000000BC 236 000000BC F01E 0F04 TST lr, #0x04 ; if(!EXC_RETURN[2] ) 237 000000C0 BF0C ITE EQ 238 000000C2 F380 8808 MSREQ msp, r0 ; [2]=0 ==> Z=1, up date stack pointer to MSP. 239 000000C6 F380 8809 MSRNE psp, r0 ; [2]=1 ==> Z=0, up date stack pointer to PSP. 240 000000CA 241 000000CA B500 PUSH {lr} 242 000000CC F7FF FFFE BL rt_hw_hard_fault_exception 243 000000D0 F85D EB04 POP {lr} 244 000000D4 245 000000D4 F04E 0E04 ORR lr, lr, #0x04 246 000000D8 4770 BX lr 247 000000DA ENDP 248 000000DA 249 000000DA 00 00 ALIGN 4 250 000000DC 251 000000DC END 00000000 00000000 ARM Macro Assembler Page 6 00000000 E000ED04 E000ED20 E000ED08 Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M4 --apcs=interw ork --depend=.\out\context_rvds.d -o.\out\context_rvds.o -ID:\Keil\ARM\Packs\Sy nwit\SWM32_DFP\2.0.6\CSL\SWM320\CMSIS\DeviceSupport -Id:\Keil\ARM\CMSIS\Include --predefine="__MICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 538" --lis t=.\out\context_rvds.lst APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S ARM Macro Assembler Page 1 Alphabetic symbol ordering Relocatable symbols .text 00000000 Symbol: .text Definitions At line 26 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses None Comment: .text unused HardFault_Handler 000000A6 Symbol: HardFault_Handler Definitions At line 222 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 221 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Comment: HardFault_Handler used once PendSV_Handler 0000002E Symbol: PendSV_Handler Definitions At line 88 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 89 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Comment: PendSV_Handler used once _reswitch 00000020 Symbol: _reswitch Definitions At line 75 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 68 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Comment: _reswitch used once pendsv_exit 00000060 Symbol: pendsv_exit Definitions At line 153 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 98 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Comment: pendsv_exit used once rt_hw_context_switch 0000000E Symbol: rt_hw_context_switch Definitions At line 61 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 62 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Comment: rt_hw_context_switch used once rt_hw_context_switch_interrupt 0000000E Symbol: rt_hw_context_switch_interrupt Definitions At line 59 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 60 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Comment: rt_hw_context_switch_interrupt used once rt_hw_context_switch_to 0000006A Symbol: rt_hw_context_switch_to ARM Macro Assembler Page 2 Alphabetic symbol ordering Relocatable symbols Definitions At line 166 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 167 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Comment: rt_hw_context_switch_to used once rt_hw_interrupt_disable 00000000 Symbol: rt_hw_interrupt_disable Definitions At line 38 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 39 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Comment: rt_hw_interrupt_disable used once rt_hw_interrupt_enable 00000008 Symbol: rt_hw_interrupt_enable Definitions At line 48 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 49 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Comment: rt_hw_interrupt_enable used once rt_hw_interrupt_thread_switch 000000A4 Symbol: rt_hw_interrupt_thread_switch Definitions At line 215 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 216 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Comment: rt_hw_interrupt_thread_switch used once switch_to_thread 00000052 Symbol: switch_to_thread Definitions At line 129 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 106 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Comment: switch_to_thread used once 12 symbols ARM Macro Assembler Page 1 Alphabetic symbol ordering Absolute symbols NVIC_INT_CTRL E000ED04 Symbol: NVIC_INT_CTRL Definitions At line 21 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 79 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S At line 197 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S NVIC_PENDSVSET 10000000 Symbol: NVIC_PENDSVSET Definitions At line 24 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 80 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S At line 198 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S NVIC_PENDSV_PRI 00FF0000 Symbol: NVIC_PENDSV_PRI Definitions At line 23 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 191 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Comment: NVIC_PENDSV_PRI used once NVIC_SYSPRI2 E000ED20 Symbol: NVIC_SYSPRI2 Definitions At line 22 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 190 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Comment: NVIC_SYSPRI2 used once SCB_VTOR E000ED08 Symbol: SCB_VTOR Definitions At line 20 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 202 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Comment: SCB_VTOR used once 5 symbols ARM Macro Assembler Page 1 Alphabetic symbol ordering External symbols rt_hw_hard_fault_exception 00000000 Symbol: rt_hw_hard_fault_exception Definitions At line 220 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 242 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Comment: rt_hw_hard_fault_exception used once rt_interrupt_from_thread 00000000 Symbol: rt_interrupt_from_thread Definitions At line 32 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 72 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S At line 104 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S At line 180 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S rt_interrupt_to_thread 00000000 Symbol: rt_interrupt_to_thread Definitions At line 33 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 76 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S At line 130 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S At line 169 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S rt_thread_switch_interrupt_flag 00000000 Symbol: rt_thread_switch_interrupt_flag Definitions At line 31 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S Uses At line 65 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S At line 96 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S At line 185 in file APP\rt-thread\libcpu\arm\cortex-m4\context_rvds.S 4 symbols 355 symbols in table