/*****************************************************************************************/
/* @file      : startup_cm4.arm                                                                */
/* @brief     : Startup Source File.                                                     */
/*              - Platform: Z20K14xM                                                     */
/*              - Autosar Version: 4.6.0                                                 */
/* @version   : 1.1.0                                                                    */
/* @author    : Xukaiming                                                                */
/* @note                                                                                 */
/*                                                                                       */
/* @copyright : Copyright (c) 2021-2023 Marelli  Semiconductor Ltd. All rights reserved.   */
/*****************************************************************************************/
 
                             
.set VTOR_REG, 0xE000ED08
.set CPACR_REG, 0xE000ED88
.set CPACR_VAL, 0x00F00000
.set WATER_MARK,0xDEADBEEF
    
.section ".zero_table", "a"
  .long 2
  .long INT_SRAM1_START
  .long INT_SRAM1_END
  .long INT_SRAM0_START
  .long INT_SRAM0_END
  
  
        .file "startup_cm4.arm"

;*******************************************************************************
;* Import symbols
        .import Watchdog_Disable
;*******************************************************************************
;*******************************************************************************
;* Export symbols
;*******************************************************************************
        .export Reset_Handler
        .export Cy_SaveIRQ
        .export Cy_RestoreIRQ
        .export __ramVectors
;*******************************************************************************
;* Helper functions
;*******************************************************************************
; Saves and disables the interrupts
        .text
Cy_SaveIRQ:
        MRS r0, PRIMASK
        CPSID I
        BX LR

        .endf Cy_SaveIRQ

;-----------------------------------------
 ;Restores the interrupts

        .text
Cy_RestoreIRQ:
        MSR PRIMASK, r0
        BX LR

        .endf Cy_RestoreIRQ
        
        
 ;*******************************************************************************		
 ;  .text (Program code) -- "ax"
 ;  .data (Initialized data) -- "aw"
 ;  .rodata (Read-only initialized data) -- "a" 
 ;  .data (Initialized data) -- "aw"
 ;  .bss (Uninitialized data) -- "awb"
 ;*******************************************************************************
 ; RAM interrupt vector
 
        .section ".intvec_ram", "awb"          
        .align 0x4
__ramVectors:
        .space  0x400

        .weak Reset_Handler
        .section ".startup", "ax"
        .thumb2

Reset_Handler:

; Disable global interrupts
        CPSID   I
; Disable Internal Watchdog
        BL Watchdog_Disable
;/******************************************************************/
;Zhixin Added
    ;Init the registers
    LDR     R1,=0
    LDR     R2,=0
    LDR     R3,=0
    LDR     R4,=0
    LDR     R5,=0
    LDR     R6,=0
    LDR     R7,=0
    MOV     R8,R7
    MOV     R9,R7
    MOV     R10,R7
    MOV     R11,R7
    MOV     R12,R7
;/******************************************************************/
;relocate vector table to RAM. 
;use c code implement
;/******************************************************************/
;/* Autosar Guidance 3 - The start-up code shall initialize the    */
;/* user stack pointer. The user stack pointer base address and    */
;/* the stack size are provided as configuration parameter or      */
;/* linker/locator setting.                                        */
;/******************************************************************/
 
SetVTOR:   ;set interrupt vector  to RAM
    ldr  r0, =VTOR_REG  
    ldr  r1, =__RAM_INTERRUPT_START
    str  r1,[r0]
/**************************************************/
/* set up stack; r13 SP. */
/**************************************************/
SetStack:
    ldr  r0, =__STACK_TOP
    msr  MSP, r0 
    ; Enable FPU. 
EnableFPU:
    LDR  R0, =CPACR_REG 
    LDR  R1, [R0]
    LDR  R2, =CPACR_VAL 
    ORR  R1, R1, R2
    STR  R1, [R0]
    DSB
    ISB    
StackWaterMark:
	//WATER_MARK 
	ldr  r0, =WATER_MARK
    ldr  r1, =__STACK_TOP
    ldr  r2, =__STACK_END
	subs r3,r1, r2  ;//save stack deepth
WATER_MARK_LOOP:
	stm r2!, {r0}
    subs r3, #4
    bge WATER_MARK_LOOP
WATER_MARK_END:
;/************************/
;/* Erase ".bss Section" */
;/************************/

;;/* Zero fill the bss segment */
;NT_INIT_RAM  zone
;Zhixin Added 
InitBss:
    ldr r0, =__ZERO_TABLE
    ldm r0!, {r1}      /* r1: major loop count */ 
	;//Data is continuously loaded into register R1,
	;//starting at the location indicated by memory address R0 
	;Exclamation point (!) Indicates that after loading is complete, 
	;the value of r0 is automatically increased to point to the next memory location. 
INIT_BSS_DATA_START:
    subs r1, #1              ;loop count -1
    blt INIT_BSS_DATA_END    ;when R1 lower than 0 jump to Label
    ldm r0!, {r3, r4}
    subs r2, r4, r3          ;/* r2: copy size */
    beq INIT_BSS_DATA_START  ;if R2 = 0 ,jump to  INIT_BSS_DATA_START
    movs r5, #0              
INIT_BSS_DATA_LOOP:
    ;store the value of register R4 to the memory location at address R3 
	;and automatically incerement the value of the R3 to point to the memory location
    stm r3!, {r5}            
    subs r2, #4
    bgt INIT_BSS_DATA_LOOP   ;if R2 greater than 0 ,jump to Label 
    b INIT_BSS_DATA_START    ;
INIT_BSS_DATA_END:

;Zhixin Added end
;  ldr  r2, =INT_SRAM1_START
;  ldr  r4, =INT_SRAM1_END

;  mov   r3, #0
;FillZerobss:
;  str   r3, [r2]
;  add   r2, r2, #4
;  cmp   r2, r4
;  bcc   FillZerobss
  
;/************************/
;/* Erase ".NT_NOINIT_RAM Section" */
;/************************/

;;/* Zero fill the bss segment */
  ldr  r2, =RC_NT_NO_INIT_SRC
  ldr  r4, =RC_NT_NO_INIT_END

  mov   r3, #0
NT_NOINIT_RAM:
  str   r3, [r2]
  add   r2, r2, #4
  cmp   r2, r4
  bcc   NT_NOINIT_RAM
  
;/************************/
;/* Erase ".sbss_no_cacheable Section" */
;/************************/

;/* Zero fill the bss segment */
  ldr  r2, =SBSS_SRAM_START
  ldr  r4, =SBSS_SRAM_SIZE

  mov   r3, #0
FillZeroSBssNoCacheable:
  str   r3, [r2]
  add   r2, r2, #4
  sub   r4, r4, #1
  cmp   r4, #0
  bgt   FillZeroSBssNoCacheable 
  
/************************/
/* Erase ".bss_no_cacheable Section" */
/************************/

;/* Zero fill the bss segment */
  ldr  r2, =BSS_SRAM_START
  ldr  r4, =BSS_SRAM_SIZE

  mov   r3, #0
FillZeroBssNoCacheable:
  str   r3, [r2]
  add   r2, r2, #4
  sub   r4, r4, #1
  cmp   r4, #0
  bgt   FillZeroBssNoCacheable  
    
;/******************************************************************/
;/* Copy  initialized data from Flash to SRAM                      */
;/******************************************************************/

;/**********/
;/* .sdata */
;/**********/
;/* nothing will be copied for linaro linker */
    ldr r3, = RC_SDATA_SIZE
    ldr r2, = RC_SDATA_SRC
    ldr r4, = RC_SDATA_DEST
sdata:    
    ldr   r5, [r2]
    str   r5, [r4]
    add   r2, r2, #4
    add   r4, r4, #4
    sub   r3, r3, #1
    cmp   r3, #0
    bgt sdata
;/************/
;/* .data */
;/************/
;/* nothing will be copied for linaro linker */ 
;// if SIZE = 0 there was a wrong action?
    ldr r3, = RC_DATA_SIZE
    ldr r2, = RC_DATA_SRC
    ldr r4, = RC_DATA_DEST
CopyRamData:    
    ldr   r5, [r2]
    str   r5, [r4]
    add   r2, r2, #4
    add   r4, r4, #4
    sub   r3, r3, #1
    cmp   r3, #0
    bgt CopyRamData
;
;/************/
;/* .ramcode */  
;/************/ 
; copy code from ROM to RAM for run application
    ldr r3, = RC_RAMCODE_SIZE
    ldr r2, = RC_RAMCODE_SRC
    ldr r4, = RC_RAMCODE_DEST
CopyRamCode:    
    ldr   r5, [r2]
    str   r5, [r4]
    add   r2, r2, #4
    add   r4, r4, #4
    sub   r3, r3, #1
    cmp   r3, #0
    bgt CopyRamCode
; /*************************/
;/* .RAM_INIT_UNSPECIFIED */
;/*************************/ 
;//Write what junk code, clearly a loop to fix things, really powerless to ridicule
    ldr r3, = RC_RAMINITUNSPECIFIED_SIZE
    ldr r2, = RC_RAMINITUNSPECIFIED_SRC
    ldr r4, = RC_RAMINITUNSPECIFIED_DEST
    cmp   r3, #0
    beq RAMINITUNSPECIFIEDEND
RAMINITUNSPECIFIED:    
    ldr   r5, [r2]
    str   r5, [r4]
    add   r2, r2, #4
    add   r4, r4, #4
    sub   r3, r3, #1
    cmp   r3, #0
    bgt RAMINITUNSPECIFIED
RAMINITUNSPECIFIEDEND:    
    ;
;;/******************/
;;/* .RAM_INIT_8BIT */
;;/******************/
    ldr r3, = RC_RAM_INIT8_SIZE
    ldr r2, = RC_RAM_INIT8_SRC
    ldr r4, = RC_RAM_INIT8_DEST
    cmp   r3, #0
    beq RAMINIT_8BITEND
RAMINIT_8BIT:    
    ldrb   r5, [r2]
    strb   r5, [r4]
    add   r2, r2, #1
    add   r4, r4, #1
    sub   r3, r3, #1
    cmp   r3, #0
    bgt RAMINIT_8BIT
RAMINIT_8BITEND:
;
;;/******************/
;;/* .RAM_INIT_8BIT */
;;/******************/
    ldr r3, = RC_RAMINIT8_SIZE
    ldr r2, = RC_RAMINIT8_SRC
    ldr r4, = RC_RAMINIT8_DEST
    cmp   r3, #0
    beq RAMINIT8BITEND
RAMINIT8BIT:    
    ldrb   r5, [r2]
    strb   r5, [r4]
    add   r2, r2, #1
    add   r4, r4, #1
    sub   r3, r3, #1
    cmp   r3, #0
    bgt RAMINIT8BIT
RAMINIT8BITEND:
;

;;/******************/
;;/* .RAM_INIT_16BIT */
;;/******************/
    ldr r3, = RC_RAMINIT16_SIZE
    ldr r2, = RC_RAMINIT16_SRC
    ldr r4, = RC_RAMINIT16_DEST
    cmp   r3, #0
    beq RAMINIT16BITEND
RAMINIT16BIT:    
    ldrh   r5, [r2]
    strh   r5, [r4]
    add   r2, r2, #2
    add   r4, r4, #2
    sub   r3, r3, #1
    cmp   r3, #0
    bgt RAMINIT16BIT
RAMINIT16BITEND:
;
;;/******************/
;;/* .RAM_INIT_32BIT */
;;/******************/
    ldr r3, = RC_RAMINIT32_SIZE
    ldr r2, = RC_RAMINIT32_SRC
    ldr r4, = RC_RAMINIT32_DEST
    cmp   r3, #0
    beq RAMINIT32BITEND
RAMINIT32BIT:    
    ldr   r5, [r2]
    str   r5, [r4]
    add   r2, r2, #4
    add   r4, r4, #4
    sub   r3, r3, #1
    cmp   r3, #0
    bgt RAMINIT32BIT
RAMINIT32BITEND:
;
;;/******************/
;;/* .RAM_INIT_BOOLEAN */
;;/******************/
    ldr r3, = RC_RAMINITBOOLEAN_SIZE
    ldr r2, = RC_RAMINITBOOLEAN_SRC
    ldr r4, = RC_RAMINITBOOLEAN_DEST
    cmp   r3, #0
    beq RAMINITBOOLEANEND
RAMINITBOOLEAN:    
    ldrb   r5, [r2]
    strb   r5, [r4]
    add   r2, r2, #1
    add   r4, r4, #1
    sub   r3, r3, #1
    cmp   r3, #0
    bgt RAMINITBOOLEAN
RAMINITBOOLEANEND:
;
;;/******************/
;;/* .RC_MCALDATA_SIZE */
;;/******************/
    ldr r3, = RC_MCALDATA_SIZE
    ldr r2, = RC_MCALDATA_SRC
    ldr r4, = RC_MCALDATA_DEST
    cmp   r3, #0
    beq MCALDATASIZEEND
MCALDATASIZE:    
    ldr   r5, [r2]
    str   r5, [r4]
    add   r2, r2, #4
    add   r4, r4, #4
    sub   r3, r3, #1
    cmp   r3, #0
    bgt MCALDATASIZE
MCALDATASIZEEND:
;    
;;/******************/
;;/* .RC_VARFASTINIT32 */
;;/******************/
    ldr r3, = RC_VARFASTINIT32_SIZE
    ldr r2, = RC_VARFASTINIT32_SRC
    ldr r4, = RC_VARFASTINIT32_DEST
    cmp   r3, #0
    beq VARFASTINIT32END
VARFASTINIT32:    
    ldr   r5, [r2]
    str   r5, [r4]
    add   r2, r2, #4
    add   r4, r4, #4
    sub   r3, r3, #1
    cmp   r3, #0
    bgt VARFASTINIT32
VARFASTINIT32END:
;
;;/******************/
;;/* .RC_VARFASTINIT64 */
;;/******************/
    ldr r3, = RC_VARFASTINIT64_SIZE
    ldr r2, = RC_VARFASTINIT64_SRC
    ldr r4, = RC_VARFASTINIT64_DEST
    cmp   r3, #0
    beq VARFASTINIT64END
VARFASTINIT64:    
    ldr   r5, [r2]
    str   r5, [r4]
    add   r2, r2, #4
    add   r4, r4, #4
    sub   r3, r3, #1
    cmp   r3, #0
    bgt VARFASTINIT64
VARFASTINIT64END:
;
;;/******************/
;;/* .RC_VARPOWERONINIT32 */
;;/******************/
    ldr r3, = RC_VARPOWERONINIT32_SIZE
    ldr r2, = RC_VARPOWERONINIT32_SRC
    ldr r4, = RC_VARPOWERONINIT32_DEST
    cmp   r3, #0
    beq VARPOWERONINIT32END
VARPOWERONINIT32:    
    ldr   r5, [r2]
    str   r5, [r4]
    add   r2, r2, #4
    add   r4, r4, #4
    sub   r3, r3, #1
    cmp   r3, #0
    bgt VARPOWERONINIT32
VARPOWERONINIT32END:
;
;;/******************/
;;/* .RC_VARPOWERONINIT16 */
;;/******************/
    ldr r3, = RC_VARPOWERONINIT16_SIZE
    ldr r2, = RC_VARPOWERONINIT16_SRC
    ldr r4, = RC_VARPOWERONINIT16_DEST
    cmp   r3, #0
    beq VARPOWERONINIT16END
VARPOWERONINIT16:    
    ldrh   r5, [r2]
    strh   r5, [r4]
    add   r2, r2, #2
    add   r4, r4, #2
    sub   r3, r3, #1
    cmp   r3, #0
    bgt VARPOWERONINIT16
VARPOWERONINIT16END:
;;/******************/
;;/* .RC_VARFASTINIT16 */
;;/******************/
    ldr r3, = RC_VARFASTINIT16_SIZE
    ldr r2, = RC_VARFASTINIT16_SRC
    ldr r4, = RC_VARFASTINIT16_DEST
    cmp   r3, #0
    beq VARFASTINIT16END
VARFASTINIT16:    
    ldrh   r5, [r2]
    strh   r5, [r4]
    add   r2, r2, #2
    add   r4, r4, #2
    sub   r3, r3, #1
    cmp   r3, #0
    bgt VARFASTINIT16
VARFASTINIT16END:
;
;;/******************/
;;/* .RC_VARPOWERONINIT8 */
;;/******************/
    ldr r3, = RC_VARPOWERONINIT8_SIZE
    ldr r2, = RC_VARPOWERONINIT8_SRC
    ldr r4, = RC_VARPOWERONINIT8_DEST
    cmp   r3, #0
    beq VARPOWERONINIT8END
VARPOWERONINIT8:    
    ldrb   r5, [r2]
    strb   r5, [r4]
    add   r2, r2, #1
    add   r4, r4, #1
    sub   r3, r3, #1
    cmp   r3, #0
    bgt VARPOWERONINIT8
VARPOWERONINIT8END:

;;/******************/
;;/* .T_VAR_POWER_ON_INIT_64 */
;;/******************/
    ldr r3, = RC_VARPOWERONINIT64_SIZE
    ldr r2, = RC_VARPOWERONINIT64_SRC
    ldr r4, = RC_VARPOWERONINIT64_DEST
    cmp   r3, #0
    beq VARPOWERONINIT64END
VARPOWERONINIT64:    
    ldr   r5, [r2]
    str   r5, [r4]
    add   r2, r2, #4
    add   r4, r4, #4
    sub   r3, r3, #1
    cmp   r3, #0
    bgt VARPOWERONINIT64
VARPOWERONINIT64END:
;
;;/******************/
;;/* .RC_VARFASTINIT8 */
;;/******************/
    ldr r3, = RC_VARFASTINIT8_SIZE
    ldr r2, = RC_VARFASTINIT8_SRC
    ldr r4, = RC_VARFASTINIT8_DEST
    cmp   r3, #0
    beq VARFASTINIT8END
VARFASTINIT8:    
    ldrb   r5, [r2]
    strb   r5, [r4]
    add   r2, r2, #1
    add   r4, r4, #1
    sub   r3, r3, #1
    cmp   r3, #0
    bgt VARFASTINIT8
VARFASTINIT8END:
;
;;/******************/
;;/* .RC_VARPOWERONINITBOOLEAN */
;;/******************/
    ldr r3, = RC_VARPOWERONINITBOOLEAN_SIZE
    ldr r2, = RC_VARPOWERONINITBOOLEAN_SRC
    ldr r4, = RC_VARPOWERONINITBOOLEAN_DEST
    cmp   r3, #0
    beq VARPOWERONINITBOOLEANEND
VARPOWERONINITBOOLEAN:    
    ldrb   r5, [r2]
    strb   r5, [r4]
    add   r2, r2, #1
    add   r4, r4, #1
    sub   r3, r3, #1
    cmp   r3, #0
    bgt VARPOWERONINITBOOLEAN 
VARPOWERONINITBOOLEANEND:
; 
;;/******************/
;;/* .RC_VARFASTINITBOOLEAN */
;;/******************/
    ldr r3, = RC_VARFASTINITBOOLEAN_SIZE
    ldr r2, = RC_VARFASTINITBOOLEAN_SRC
    ldr r4, = RC_VARFASTINITBOOLEAN_DEST
    cmp   r3, #0
    beq VARFASTINITBOOLEANEND
VARFASTINITBOOLEAN:    
    ldrb   r5, [r2]
    strb   r5, [r4]
    add   r2, r2, #1
    add   r4, r4, #1
    sub   r3, r3, #1
    cmp   r3, #0
    bgt VARFASTINITBOOLEAN	
VARFASTINITBOOLEANEND:
;
;;/******************/
;;/* .RC_VARPOWERONINITUNSPECIFIED */
;;/******************/
    ldr r3, = RC_VARPOWERONINITUNSPECIFIED_SIZE
    ldr r2, = RC_VARPOWERONINITUNSPECIFIED_SRC
    ldr r4, = RC_VARPOWERONINITUNSPECIFIED_DEST
    cmp   r3, #0
    beq VARPOWERONINITUNSPECIFIEDEND
VARPOWERONINITUNSPECIFIED:    
    ldr   r5, [r2]
    str   r5, [r4]
    add   r2, r2, #4
    add   r4, r4, #4
    sub   r3, r3, #1
    cmp   r3, #0
    bgt VARPOWERONINITUNSPECIFIED
VARPOWERONINITUNSPECIFIEDEND:
;
;;/******************/
;;/* .RC_VARINIT32 */
;;/******************/
    ldr r3, = RC_VARINIT32_SIZE
    ldr r2, = RC_VARINIT32_SRC
    ldr r4, = RC_VARINIT32_DEST
    cmp   r3, #0
    beq VARINIT32END
VARINIT32:    
    ldr   r5, [r2]
    str   r5, [r4]
    add   r2, r2, #4
    add   r4, r4, #4
    sub   r3, r3, #1
    cmp   r3, #0
    bgt VARINIT32
VARINIT32END:

;/******************/
;/* .RC_OS_INIT */
;/******************/
    ldr r3, = RC_OS_INIT_SIZE
    ldr r2, = RC_OS_INIT_SRC
    ldr r4, = RC_OS_INIT_DEST
    cmp   r3, #0
    beq OSINIT8END
OSINIT8:    
    ldrb   r5, [r2]
    strb   r5, [r4]
    add   r2, r2, #1
    add   r4, r4, #1
    sub   r3, r3, #1
    cmp   r3, #0
    bgt OSINIT8	
OSINIT8END:

;/******************/
;/* .RC_NT_INIT */
;/******************/
    ldr r3, = RC_NT_INIT_SIZE
    ldr r2, = RC_NT_INIT_SRC
    ldr r4, = RC_NT_INIT_DEST
    cmp   r3, #0
    beq NTINIT8END
NTINIT8:    
    ldrb   r5, [r2]
    strb   r5, [r4]
    add   r2, r2, #1
    add   r4, r4, #1
    sub   r3, r3, #1
    cmp   r3, #0
    bgt NTINIT8
NTINIT8END:

;;/******************/
;;/* .RAM_INIT_64BIT */
;;/******************/
    ldr r3, = RC_RAMINIT64_SIZE
    ldr r2, = RC_RAMINIT64_SRC
    ldr r4, = RC_RAMINIT64_DEST
    cmp   r3, #0
    beq RAMINIT64BITEND
RAMINIT64BIT:    
    ldr   r5, [r2]
    str   r5, [r4]
    add   r2, r2, #4
    add   r4, r4, #4
    sub   r3, r3, #1
    cmp   r3, #0
    bgt RAMINIT64BIT
RAMINIT64BITEND:
;
;;/******************/
;;/* .VAR_INIT_ASIL_D_8 */
;;/******************/
    ldr r3, = RC_RAMINITASILD8_SIZE
    ldr r2, = RC_RAMINITASILD8_SRC
    ldr r4, = RC_RAMINITASILD8_DEST
    cmp   r3, #0
    beq RAMINITASILD8BITEND
RAMINITASILD8BIT:    
    ldrb   r5, [r2]
    strb   r5, [r4]
    add   r2, r2, #1
    add   r4, r4, #1
    sub   r3, r3, #1
    cmp   r3, #0
    bgt RAMINITASILD8BIT
RAMINITASILD8BITEND:
;

;;/******************/
;;/* .T_VAR_INIT_ASIL_D_16 */
;;/******************/
    ldr r3, = RC_RAMINITASILD16_SIZE
    ldr r2, = RC_RAMINITASILD16_SRC
    ldr r4, = RC_RAMINITASILD16_DEST
    cmp   r3, #0
    beq TVARINITASILD16END
TVARINITASILD16:    
    ldrh   r5, [r2]
    strh   r5, [r4]
    add   r2, r2, #2
    add   r4, r4, #2
    sub   r3, r3, #1
    cmp   r3, #0
    bgt TVARINITASILD16
TVARINITASILD16END:
;
;;/******************/
;;/* .T_VAR_INIT_ASIL_D_32 */
;;/******************/
    ldr r3, = RC_RAMINITASILD32_SIZE
    ldr r2, = RC_RAMINITASILD32_SRC
    ldr r4, = RC_RAMINITASILD32_DEST
    cmp   r3, #0
    beq TVARINITASILD32END
TVARINITASILD32:    
    ldr   r5, [r2]
    str   r5, [r4]
    add   r2, r2, #4
    add   r4, r4, #4
    sub   r3, r3, #1
    cmp   r3, #0
    bgt TVARINITASILD32
TVARINITASILD32END:
;

;;/******************/
;;/* .T_VAR_INIT_ASIL_D_64 */
;;/******************/
    ldr r3, = RC_RAMINITASILD64_SIZE
    ldr r2, = RC_RAMINITASILD64_SRC
    ldr r4, = RC_RAMINITASILD64_DEST
    cmp   r3, #0
    beq TVARINITASILD64END
TVARINITASILD64:    
    ldr   r5, [r2]
    str   r5, [r4]
    add   r2, r2, #4
    add   r4, r4, #4
    sub   r3, r3, #1
    cmp   r3, #0
    bgt TVARINITASILD64
TVARINITASILD64END:
;

;;/******************/
;;/* .T_VAR_INIT_ASIL_D_BOOLEAN */
;;/******************/
    ldr r3, = RC_RAMINITASILDBOOLEAN_SIZE
    ldr r2, = RC_RAMINITASILDBOOLEAN_SRC
    ldr r4, = RC_RAMINITASILDBOOLEAN_DEST
    cmp   r3, #0
    beq TVARINITASILDBOOLEANEND
TVARINITASILDBOOLEAN:    
    ldrb   r5, [r2]
    strb   r5, [r4]
    add   r2, r2, #1
    add   r4, r4, #1
    sub   r3, r3, #1
    cmp   r3, #0
    bgt TVARINITASILDBOOLEAN 
TVARINITASILDBOOLEANEND:
;

;;/******************/
;;/* .T_VAR_INIT_ASIL_D_UNSPECIFIED */
;;/******************/
    ldr r3, = RC_RAMINITASILDUNSPECIFIED_SIZE
    ldr r2, = RC_RAMINITASILDUNSPECIFIED_SRC
    ldr r4, = RC_RAMINITASILDUNSPECIFIED_DEST
    cmp   r3, #0
    beq TVARINITASILDUNSPECIFIEDEND
TVARINITASILDUNSPECIFIED:    
    ldr   r5, [r2]
    str   r5, [r4]
    add   r2, r2, #4
    add   r4, r4, #4
    sub   r3, r3, #1
    cmp   r3, #0
    bgt TVARINITASILDUNSPECIFIED
TVARINITASILDUNSPECIFIEDEND:
;    

;;/******************/
;;/* .T_VAR_INIT_PTR */
;;/******************/
    ldr r3, = RC_T_VAR_INIT_PTR_SIZE
    ldr r2, = RC_T_VAR_INIT_PTR_SRC
    ldr r4, = RC_T_VAR_INIT_PTR_DEST
    cmp   r3, #0
    beq TVARINITPTREND
TVARINITPTR:    
    ldr   r5, [r2]
    str   r5, [r4]
    add   r2, r2, #4
    add   r4, r4, #4
    sub   r3, r3, #1
    cmp   r3, #0
    bgt TVARINITPTR
TVARINITPTREND:
;    
    
;;/******************************************************************/
;/* Go to user mode and Call Main Routine                          */
;/******************************************************************/

/*Start Up Initialisation*/
bl Startup_Init

;/*bl startup_go_to_user_mode*/
bl main

; Note: Control flow does not necessarily return here.
; On some tool-chains (e.g. IAR) control flow will never return from
; the system library.
Cy_Main_Exited:
        B Cy_Main_Exited

        .endf Reset_Handler

;*******************************************************************************
;* File end
;*******************************************************************************

        END