# 1 "../Generated/Src/Tmu_Drv_Cfg.c" # 1 "" 1 # 1 "" 3 # 387 "" 3 # 1 "" 1 # 1 "" 2 # 1 "../Generated/Src/Tmu_Drv_Cfg.c" 2 # 26 "../Generated/Src/Tmu_Drv_Cfg.c" # 1 "../../../mcal/Platform_ZX_K14xM/Inc\\Tmu_Drv.h" 1 # 28 "../../../mcal/Platform_ZX_K14xM/Inc\\Tmu_Drv.h" # 1 "../../../mcal/Platform_ZX_K14xM/Inc/Tmu_Drv_Types.h" 1 # 28 "../../../mcal/Platform_ZX_K14xM/Inc/Tmu_Drv_Types.h" # 1 "../Generated/inc\\Tmu_Drv_Cfg.h" 1 # 29 "../../../mcal/Platform_ZX_K14xM/Inc/Tmu_Drv_Types.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 1 # 30 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h" 1 # 86 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h" typedef unsigned char boolean; typedef unsigned char uint8; typedef unsigned short uint16; typedef unsigned int uint32; typedef unsigned long long uint64; typedef signed char sint8; typedef signed short sint16; typedef signed int sint32; typedef signed long long sint64; typedef unsigned long uint8_least; typedef unsigned long uint16_least; typedef unsigned long uint32_least; typedef signed long sint8_least; typedef signed long sint16_least; typedef signed long sint32_least; typedef float float32; typedef double float64; typedef void *VoidPtr; typedef const void *ConstVoidPtr; # 31 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 1 # 31 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler_Cfg.h" 1 # 32 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 2 # 32 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2 # 63 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" typedef unsigned char StatusType; # 104 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" typedef uint8 Std_ReturnType; typedef uint8 Std_TransformerClass; typedef uint8 Std_TransformerForwardCode; typedef uint8 Std_MessageTypeType; typedef uint8 Std_MessageResultType; typedef struct { uint16 vendorID; uint16 moduleID; uint8 sw_major_version; uint8 sw_minor_version; uint8 sw_patch_version; } Std_VersionInfoType; typedef struct { uint8 errorCode; Std_TransformerClass transformerClass; } Std_TransformerError; typedef struct { Std_TransformerForwardCode errorCode; Std_TransformerClass transformerClass; } Std_TransformerForward; typedef Std_ReturnType (*Std_ExtractProtocolHeaderFieldsType)(const uint8 *buffer, uint32 bufferLength, Std_MessageTypeType *messageType, Std_MessageResultType *messageResult); # 30 "../../../mcal/Platform_ZX_K14xM/Inc/Tmu_Drv_Types.h" 2 # 1 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 1 # 29 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" # 1 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 1 # 30 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" # 1 "../Generated/inc\\McalLib_Cfg.h" 1 # 31 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 2 # 273 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" static inline uint32 McalLib_ReadControlReg(void) { uint32 res; __asm("MRS %0,CONTROL" : "=r" (res)); return res; } # 290 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" static inline uint32 McalLib_ReadIpsrReg(void) { uint32 res; __asm("MRS %0,IPSR" : "=r" (res)); return res; } # 305 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" static inline uint32 McalLib_ReadPriMaskReg(void) { uint32 res; __asm("MRS %0,PRIMASK" : "=r" (res)); return res; } # 30 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 # 184 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" typedef enum { MCALLIB_COUNTER_SOFTWARE, MCALLIB_COUNTER_OS, } McalLib_CounterType; typedef struct { uint32 CounterId; uint32 CounterFreq; } McalLib_ConfigType; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 211 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 extern const McalLib_ConfigType *const McalLib_PreDefinedConfigPtr[(1U)]; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section rodata = "" # 216 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 # 230 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" extern void Sys_SystemReset(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section text = ".mcal_code" # 234 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 void McalLib_Init(void); # 254 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" Std_ReturnType McalLib_GetCounterValue(McalLib_CounterType Counter, uint32 *Value); # 270 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" Std_ReturnType McalLib_GetElapsedValue(McalLib_CounterType Counter, uint32 *const CounterValue, uint32 *ElapsedValue); # 282 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" uint32 McalLib_MicroSecToTicks(McalLib_CounterType Counter, uint32 MicroSecond); # 296 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" void McalLib_SetCounterFreq(McalLib_CounterType Counter, uint32 Freq); # 309 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" static inline void McalLib_Assert(const uint8 *File, uint32 Line) { (void)File; (void)Line; for (;;) { } } # 327 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" void McalLib_SuspendAllInterrupts(void); void McalLib_ResumeAllInterrupts(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section text = "" # 339 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 # 31 "../../../mcal/Platform_ZX_K14xM/Inc/Tmu_Drv_Types.h" 2 # 84 "../../../mcal/Platform_ZX_K14xM/Inc/Tmu_Drv_Types.h" typedef enum { TMU_DRV_INPUT_CHANNEL_VSS = 0U, TMU_DRV_INPUT_CHANNEL_VDD = 1U, TMU_DRV_INPUT_CHANNEL_IO_TMU_IN0 = 2U, TMU_DRV_INPUT_CHANNEL_IO_TMU_IN1 = 3U, TMU_DRV_INPUT_CHANNEL_IO_TMU_IN2 = 4U, TMU_DRV_INPUT_CHANNEL_IO_TMU_IN3 = 5U, TMU_DRV_INPUT_CHANNEL_IO_TMU_IN4 = 6U, TMU_DRV_INPUT_CHANNEL_IO_TMU_IN5 = 7U, TMU_DRV_INPUT_CHANNEL_IO_TMU_IN6 = 8U, TMU_DRV_INPUT_CHANNEL_IO_TMU_IN7 = 9U, TMU_DRV_INPUT_CHANNEL_IO_TMU_IN8 = 10U, TMU_DRV_INPUT_CHANNEL_IO_TMU_IN9 = 11U, TMU_DRV_INPUT_CHANNEL_IO_TMU_IN10 = 12U, TMU_DRV_INPUT_CHANNEL_IO_TMU_IN11 = 13U, TMU_DRV_INPUT_CHANNEL_RTC_SECOND = 14U, TMU_DRV_INPUT_CHANNEL_RTC_ALARM = 15U, TMU_DRV_INPUT_CHANNEL_STIM_TRIG_OUT0 = 16U, TMU_DRV_INPUT_CHANNEL_STIM_TRIG_OUT1 = 17U, TMU_DRV_INPUT_CHANNEL_STIM_TRIG_OUT2 = 18U, TMU_DRV_INPUT_CHANNEL_STIM_TRIG_OUT3 = 19U, TMU_DRV_INPUT_CHANNEL_TIM0_MATCH_TRIGGER = 20U, TMU_DRV_INPUT_CHANNEL_TIM0_INITIALIZATION_TRIGGER = 21U, TMU_DRV_INPUT_CHANNEL_TIM1_MATCH_TRIGGER = 22U, TMU_DRV_INPUT_CHANNEL_TIM1_INITIALIZATION_TRIGGER = 23U, TMU_DRV_INPUT_CHANNEL_TIM2_MATCH_TRIGGER = 24U, TMU_DRV_INPUT_CHANNEL_TIM2_INITIALIZATION_TRIGGER = 25U, TMU_DRV_INPUT_CHANNEL_TIM3_MATCH_TRIGGER = 26U, TMU_DRV_INPUT_CHANNEL_TIM3_INITIALIZATION_TRIGGER = 27U, TMU_DRV_INPUT_CHANNEL_ADC0_COCO = 28U, TMU_DRV_INPUT_CHANNEL_ADC1_COCO = 29U, TMU_DRV_INPUT_CHANNEL_CMP0_COUT = 30U, TMU_DRV_INPUT_CHANNEL_TDG0_CHANNEL0_TRIGGER_OUT = 31U, TMU_DRV_INPUT_CHANNEL_TDG0_CHANNEL1_TRIGGER_OUT = 32U, TMU_DRV_INPUT_CHANNEL_TDG0_CHANNEL2_TRIGGER_OUT = 33U, TMU_DRV_INPUT_CHANNEL_TDG0_CHANNEL3_TRIGGER_OUT = 34U, TMU_DRV_INPUT_CHANNEL_TDG0_CHANNEL4_TRIGGER_OUT = 35U, TMU_DRV_INPUT_CHANNEL_TDG0_CHANNEL5_TRIGGER_OUT = 36U, TMU_DRV_INPUT_CHANNEL_TDG1_CHANNEL0_TRIGGER_OUT = 37U, TMU_DRV_INPUT_CHANNEL_TDG1_CHANNEL1_TRIGGER_OUT = 38U, TMU_DRV_INPUT_CHANNEL_TDG1_CHANNEL2_TRIGGER_OUT = 39U, TMU_DRV_INPUT_CHANNEL_TDG1_CHANNEL3_TRIGGER_OUT = 40U, TMU_DRV_INPUT_CHANNEL_TDG1_CHANNEL4_TRIGGER_OUT = 41U, TMU_DRV_INPUT_CHANNEL_TDG1_CHANNEL5_TRIGGER_OUT = 42U, TMU_DRV_INPUT_CHANNEL_SPI0_RX_TRIG = 43U, TMU_DRV_INPUT_CHANNEL_SPI0_TX_TRIG = 44U, TMU_DRV_INPUT_CHANNEL_SPI1_RX_TRIG = 45U, TMU_DRV_INPUT_CHANNEL_SPI1_TX_TRIG = 46U, TMU_DRV_INPUT_CHANNEL_SPI2_RX_TRIG = 47U, TMU_DRV_INPUT_CHANNEL_SPI2_TX_TRIG = 48U, TMU_DRV_INPUT_CHANNEL_SPI3_RX_TRIG = 49U, TMU_DRV_INPUT_CHANNEL_SPI3_TX_TRIG = 50U, TMU_DRV_INPUT_CHANNEL_I2C0_RX_TRIG = 51U, TMU_DRV_INPUT_CHANNEL_I2C0_TX_TRIG = 52U, TMU_DRV_INPUT_CHANNEL_I2C1_RX_TRIG = 53U, TMU_DRV_INPUT_CHANNEL_I2C1_TX_TRIG = 54U, TMU_DRV_INPUT_CHANNEL_SCM_SW_TRIG0 = 55U, TMU_DRV_INPUT_CHANNEL_SCM_SW_TRIG1 = 56U, TMU_DRV_INPUT_CHANNEL_SCM_SW_TRIG2 = 57U, TMU_DRV_INPUT_CHANNEL_SCM_SW_TRIG3 = 58U, TMU_DRV_INPUT_CHANNEL_MCPWM0_EXT_TRIG0 = 59U, TMU_DRV_INPUT_CHANNEL_MCPWM0_EXT_TRIG1 = 60U, TMU_DRV_INPUT_CHANNEL_MCPWM0_EXT_TRIG2 = 61U, TMU_DRV_INPUT_CHANNEL_MCPWM0_EXT_TRIG3 = 62U, TMU_DRV_INPUT_CHANNEL_MCPWM0_EXT_TRIG4 = 63U, TMU_DRV_INPUT_CHANNEL_MCPWM0_EXT_TRIG5 = 64U, TMU_DRV_INPUT_CHANNEL_MCPWM0_EXT_TRIG6 = 65U, TMU_DRV_INPUT_CHANNEL_MCPWM0_EXT_TRIG7 = 66U, TMU_DRV_INPUT_CHANNEL_MCPWM0_INIT_TRIG0 = 67U, TMU_DRV_INPUT_CHANNEL_MCPWM0_INIT_TRIG1 = 68U, TMU_DRV_INPUT_CHANNEL_MCPWM0_INIT_TRIG2 = 69U, TMU_DRV_INPUT_CHANNEL_MCPWM0_INIT_TRIG3 = 70U, TMU_DRV_INPUT_CHANNEL_MCPWM1_EXT_TRIG0 = 71U, TMU_DRV_INPUT_CHANNEL_MCPWM1_EXT_TRIG1 = 72U, TMU_DRV_INPUT_CHANNEL_MCPWM1_EXT_TRIG2 = 73U, TMU_DRV_INPUT_CHANNEL_MCPWM1_EXT_TRIG3 = 74U, TMU_DRV_INPUT_CHANNEL_MCPWM1_EXT_TRIG4 = 75U, TMU_DRV_INPUT_CHANNEL_MCPWM1_EXT_TRIG5 = 76U, TMU_DRV_INPUT_CHANNEL_MCPWM1_EXT_TRIG6 = 77U, TMU_DRV_INPUT_CHANNEL_MCPWM1_EXT_TRIG7 = 78U, TMU_DRV_INPUT_CHANNEL_MCPWM1_INIT_TRIG0 = 79U, TMU_DRV_INPUT_CHANNEL_MCPWM1_INIT_TRIG1 = 80U, TMU_DRV_INPUT_CHANNEL_MCPWM1_INIT_TRIG2 = 81U, TMU_DRV_INPUT_CHANNEL_MCPWM1_INIT_TRIG3 = 82U } Tmu_Drv_InputChannelType; typedef enum { TMU_DRV_OUTPUT_CHANNEL_IO_TMU_OUT0 = 0U, TMU_DRV_OUTPUT_CHANNEL_IO_TMU_OUT1 = 1U, TMU_DRV_OUTPUT_CHANNEL_IO_TMU_OUT2 = 2U, TMU_DRV_OUTPUT_CHANNEL_IO_TMU_OUT3 = 3U, TMU_DRV_OUTPUT_CHANNEL_IO_TMU_OUT4 = 4U, TMU_DRV_OUTPUT_CHANNEL_IO_TMU_OUT5 = 5U, TMU_DRV_OUTPUT_CHANNEL_IO_TMU_OUT6 = 6U, TMU_DRV_OUTPUT_CHANNEL_IO_TMU_OUT7 = 7U, TMU_DRV_OUTPUT_CHANNEL_ADC0_HW_TRIG_OPT0 = 8U, TMU_DRV_OUTPUT_CHANNEL_ADC0_HW_TRIG_OPT1 = 9U, TMU_DRV_OUTPUT_CHANNEL_ADC0_HW_TRIG_OPT2 = 10U, TMU_DRV_OUTPUT_CHANNEL_ADC0_HW_TRIG_OPT3 = 11U, TMU_DRV_OUTPUT_CHANNEL_ADC1_HW_TRIG_OPT0 = 12U, TMU_DRV_OUTPUT_CHANNEL_ADC1_HW_TRIG_OPT1 = 13U, TMU_DRV_OUTPUT_CHANNEL_ADC1_HW_TRIG_OPT2 = 14U, TMU_DRV_OUTPUT_CHANNEL_ADC1_HW_TRIG_OPT3 = 15U, TMU_DRV_OUTPUT_CHANNEL_CMP0_SAMPLE = 16U, TMU_DRV_OUTPUT_CHANNEL_CMP0_EXTERNAL_ENABLE = 17U, TMU_DRV_OUTPUT_CHANNEL_TDG0_TRIG_IN = 18U, TMU_DRV_OUTPUT_CHANNEL_TDG1_TRIG_IN = 19U, TMU_DRV_OUTPUT_CHANNEL_TIM0_FAULT0 = 20U, TMU_DRV_OUTPUT_CHANNEL_TIM0_FAULT1 = 21U, TMU_DRV_OUTPUT_CHANNEL_TIM1_FAULT0 = 22U, TMU_DRV_OUTPUT_CHANNEL_TIM1_FAULT1 = 23U, TMU_DRV_OUTPUT_CHANNEL_TIM2_FAULT0 = 24U, TMU_DRV_OUTPUT_CHANNEL_TIM2_FAULT1 = 25U, TMU_DRV_OUTPUT_CHANNEL_TIM3_FAULT0 = 26U, TMU_DRV_OUTPUT_CHANNEL_TIM3_FAULT1 = 27U, TMU_DRV_OUTPUT_CHANNEL_MCPWM0_FAULT0 = 28U, TMU_DRV_OUTPUT_CHANNEL_MCPWM0_FAULT1 = 29U, TMU_DRV_OUTPUT_CHANNEL_MCPWM0_FAULT2 = 30U, TMU_DRV_OUTPUT_CHANNEL_MCPWM0_FAULT3 = 31U, TMU_DRV_OUTPUT_CHANNEL_MCPWM1_FAULT0 = 32U, TMU_DRV_OUTPUT_CHANNEL_MCPWM1_FAULT1 = 33U, TMU_DRV_OUTPUT_CHANNEL_MCPWM1_FAULT2 = 34U, TMU_DRV_OUTPUT_CHANNEL_MCPWM1_FAULT3 = 35U, TMU_DRV_OUTPUT_CHANNEL_STIM_TRIG_IN0 = 36U, TMU_DRV_OUTPUT_CHANNEL_STIM_TRIG_IN1 = 37U, TMU_DRV_OUTPUT_CHANNEL_STIM_TRIG_IN2 = 38U, TMU_DRV_OUTPUT_CHANNEL_STIM_TRIG_IN3 = 39U } Tmu_Drv_OutputChannelType; typedef struct { Tmu_Drv_InputChannelType InputChannel; Tmu_Drv_OutputChannelType OutputChannel; boolean OutputEnabled; } Tmu_Drv_ChannelConfigType; typedef struct { uint32 ConfigChannelCount; const Tmu_Drv_ChannelConfigType *ChannelConfigList; } Tmu_Drv_ConfigType; # 29 "../../../mcal/Platform_ZX_K14xM/Inc\\Tmu_Drv.h" 2 # 86 "../../../mcal/Platform_ZX_K14xM/Inc\\Tmu_Drv.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" #pragma clang section text = ".mcal_code" # 87 "../../../mcal/Platform_ZX_K14xM/Inc\\Tmu_Drv.h" 2 void Tmu_Drv_Init(const Tmu_Drv_ConfigType *ConfigPtr); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" #pragma clang section text = "" # 99 "../../../mcal/Platform_ZX_K14xM/Inc\\Tmu_Drv.h" 2 # 27 "../Generated/Src/Tmu_Drv_Cfg.c" 2