# 1 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" # 1 "" 1 # 1 "" 3 # 387 "" 3 # 1 "" 1 # 1 "" 2 # 1 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" 2 # 27 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" # 1 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" 1 # 29 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" # 1 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Drvw_Types.h" 1 # 29 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Drvw_Types.h" # 1 "../Generated/inc\\Pwm_Drvw_Cfg.h" 1 # 29 "../Generated/inc\\Pwm_Drvw_Cfg.h" # 1 "../Generated/inc/Pwm_Drvw_PBcfg.h" 1 # 30 "../Generated/inc\\Pwm_Drvw_Cfg.h" 2 # 30 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Drvw_Types.h" 2 # 1 "../../../mcal/Pwm_ZX_K14xM/Inc/Mcpwm_Pwm_Drv_Types.h" 1 # 29 "../../../mcal/Pwm_ZX_K14xM/Inc/Mcpwm_Pwm_Drv_Types.h" # 1 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 1 # 29 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" # 1 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 1 # 29 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 1 # 30 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h" 1 # 86 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h" typedef unsigned char boolean; typedef unsigned char uint8; typedef unsigned short uint16; typedef unsigned int uint32; typedef unsigned long long uint64; typedef signed char sint8; typedef signed short sint16; typedef signed int sint32; typedef signed long long sint64; typedef unsigned long uint8_least; typedef unsigned long uint16_least; typedef unsigned long uint32_least; typedef signed long sint8_least; typedef signed long sint16_least; typedef signed long sint32_least; typedef float float32; typedef double float64; typedef void *VoidPtr; typedef const void *ConstVoidPtr; # 31 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 1 # 31 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler_Cfg.h" 1 # 32 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 2 # 32 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2 # 63 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" typedef unsigned char StatusType; # 104 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" typedef uint8 Std_ReturnType; typedef uint8 Std_TransformerClass; typedef uint8 Std_TransformerForwardCode; typedef uint8 Std_MessageTypeType; typedef uint8 Std_MessageResultType; typedef struct { uint16 vendorID; uint16 moduleID; uint8 sw_major_version; uint8 sw_minor_version; uint8 sw_patch_version; } Std_VersionInfoType; typedef struct { uint8 errorCode; Std_TransformerClass transformerClass; } Std_TransformerError; typedef struct { Std_TransformerForwardCode errorCode; Std_TransformerClass transformerClass; } Std_TransformerForward; typedef Std_ReturnType (*Std_ExtractProtocolHeaderFieldsType)(const uint8 *buffer, uint32 bufferLength, Std_MessageTypeType *messageType, Std_MessageResultType *messageResult); # 30 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 2 # 1 "../Generated/inc\\McalLib_Cfg.h" 1 # 31 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 2 # 273 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" static inline uint32 McalLib_ReadControlReg(void) { uint32 res; __asm("MRS %0,CONTROL" : "=r" (res)); return res; } # 290 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" static inline uint32 McalLib_ReadIpsrReg(void) { uint32 res; __asm("MRS %0,IPSR" : "=r" (res)); return res; } # 305 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" static inline uint32 McalLib_ReadPriMaskReg(void) { uint32 res; __asm("MRS %0,PRIMASK" : "=r" (res)); return res; } # 30 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 # 184 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" typedef enum { MCALLIB_COUNTER_SOFTWARE, MCALLIB_COUNTER_OS, } McalLib_CounterType; typedef struct { uint32 CounterId; uint32 CounterFreq; } McalLib_ConfigType; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 211 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 extern const McalLib_ConfigType *const McalLib_PreDefinedConfigPtr[(1U)]; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section rodata = "" # 216 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 # 230 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" extern void Sys_SystemReset(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section text = ".mcal_code" # 234 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 void McalLib_Init(void); # 254 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" Std_ReturnType McalLib_GetCounterValue(McalLib_CounterType Counter, uint32 *Value); # 270 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" Std_ReturnType McalLib_GetElapsedValue(McalLib_CounterType Counter, uint32 *const CounterValue, uint32 *ElapsedValue); # 282 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" uint32 McalLib_MicroSecToTicks(McalLib_CounterType Counter, uint32 MicroSecond); # 296 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" void McalLib_SetCounterFreq(McalLib_CounterType Counter, uint32 Freq); # 309 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" static inline void McalLib_Assert(const uint8 *File, uint32 Line) { (void)File; (void)Line; for (;;) { } } # 327 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" void McalLib_SuspendAllInterrupts(void); void McalLib_ResumeAllInterrupts(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section text = "" # 339 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 # 30 "../../../mcal/Pwm_ZX_K14xM/Inc/Mcpwm_Pwm_Drv_Types.h" 2 # 1 "../Generated/inc\\Mcpwm_Pwm_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Mcpwm_Pwm_Drv_Cfg.h" # 1 "../Generated/inc/Mcpwm_Pwm_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Mcpwm_Pwm_Drv_Cfg.h" 2 # 31 "../../../mcal/Pwm_ZX_K14xM/Inc/Mcpwm_Pwm_Drv_Types.h" 2 # 108 "../../../mcal/Pwm_ZX_K14xM/Inc/Mcpwm_Pwm_Drv_Types.h" typedef enum { MCPWM_PWM_DRV_STATUS_SUCCESS = 0x00U, MCPWM_PWM_DRV_STATUS_ERROR = 0x01U, MCPWM_PWM_DRV_STATUS_BUSY = 0x002U, MCPWM_PWM_DRV_STATUS_TIMEOUT = 0x003U, MCPWM_PWM_DRV_STATUS_UNSUPPORTED = 0x004U } Mcpwm_Pwm_Drv_StatusType; typedef enum { MCPWM_PWM_DRV_CLK_DISABLE = 0U, MCPWM_PWM_DRV_CLK_SOURCE_SYSTEM = 1U, MCPWM_PWM_DRV_CLK_SOURCE_FUNCTION = 2U, MCPWM_PWM_DRV_CLK_SOURCE_EXTERNAL = 3U } Mcpwm_Pwm_Drv_ClkSourceType; typedef enum { MCPWM_PWM_DRV_CLK_DIVIDE_1 = 0U, MCPWM_PWM_DRV_CLK_DIVIDE_2, MCPWM_PWM_DRV_CLK_DIVIDE_4, MCPWM_PWM_DRV_CLK_DIVIDE_8, MCPWM_PWM_DRV_CLK_DIVIDE_16, MCPWM_PWM_DRV_CLK_DIVIDE_32, MCPWM_PWM_DRV_CLK_DIVIDE_64, MCPWM_PWM_DRV_CLK_DIVIDE_128 } Mcpwm_Pwm_Drv_ClkDivideType; typedef enum { MCPWM_PWM_DRV_COUNTING_UP = 0U, MCPWM_PWM_DRV_COUNTING_UP_AND_DOWN } Mcpwm_Pwm_Drv_CountingModeType; typedef enum { MCPWM_PWM_DRV_LOW_PULSE_POL = 0U, MCPWM_PWM_DRV_HIGH_PULSE_POL } Mcpwm_Pwm_Drv_PulsePolarityType; typedef enum { MCPWM_PWM_DRV_POL_HIGH = 0U, MCPWM_PWM_DRV_POL_LOW } Mcpwm_Pwm_Drv_PolarityType; typedef enum { MCPWM_PWM_DRV_SYMMETRIC = 0U, MCPWM_PWM_DRV_ASYMMETRIC } Mcpwm_Pwm_Drv_AsymType; typedef enum { MCPWM_PWM_DRV_CHANNEL_UNINIT = 0x00U, MCPWM_PWM_DRV_CHANNEL_RUNNING = 0x01U, MCPWM_PWM_DRV_CHANNEL_IDLE = 0x02U, MCPWM_PWM_DRV_CHANNEL_OUTPUT_FORCED = 0x03U } Mcpwm_Pwm_Drv_ChannelStateType; typedef enum { MCPWM_PWM_DRV_OUTPUT_STATE_LOW = 0x00U, MCPWM_PWM_DRV_OUTPUT_STATE_HIGH = 0x01U } Mcpwm_Pwm_Drv_OutputStateType; typedef enum { MCPWM_PWM_DRV_RISING_EDGE = 0U, MCPWM_PWM_DRV_FALLING_EDGE = 1U, MCPWM_PWM_DRV_BOTH_EDGES = 2U } Mcpwm_Pwm_Drv_EdgeNotifType; typedef enum { MCPWM_PWM_DRV_FULL_POWER = 0x00U, MCPWM_PWM_DRV_LOW_POWER = 0x01U, MCPWM_PWM_DRV_NODEFINE_POWER = 0x02U } Mcpwm_Pwm_Drv_PowerStateType; typedef enum { MCPWM_PWM_DRV_MODE_EDGE_ALIGNED = 0x01, MCPWM_PWM_DRV_MODE_CENTER_ALIGNED = 0x02, MCPWM_PWM_DRV_MODE_COMBINE_EDGE_ALIGNED = 0x03, MCPWM_PWM_DRV_MODE_COMBINE_SYM_CENTER_ALIGNED = 0x04, MCPWM_PWM_DRV_MODE_COMBINE_VARIABLE_EDGE_PLACEMENT = 0x06 } Mcpwm_Pwm_Drv_ChannelModeType; typedef uint8 Mcpwm_Pwm_Drv_EdgeInterruptType; typedef void (*Mcpwm_Pwm_Drv_CallbackType)(void); typedef struct { boolean DeadTimeEnable; uint16 PhaseShiftValue; } Mcpwm_Pwm_Drv_PairChannelCfgType; typedef struct { uint8 ChannelId; boolean ChIrqEn; Mcpwm_Pwm_Drv_CallbackType ChannelCb; boolean ChannelOutputEnable; Mcpwm_Pwm_Drv_PolarityType Polarity; Mcpwm_Pwm_Drv_ChannelModeType ChannelMode; uint8 ChannelDither; boolean ChannelMatchTrigEnable; boolean DmaEn; const Mcpwm_Pwm_Drv_PairChannelCfgType *PairCfg; } Mcpwm_Pwm_Drv_ChannelConfigType; typedef struct { uint8 CntId; uint16 PwmPeriod; uint16 PwmPeriodDither; uint16 DeadTimeVal; boolean OverflowIrqEn; Mcpwm_Pwm_Drv_CallbackType OverflowCb; } Mcpwm_Pwm_Drv_CounterType; typedef struct { Mcpwm_Pwm_Drv_ClkSourceType ClkSrc; Mcpwm_Pwm_Drv_ClkDivideType ClkDiv; # 303 "../../../mcal/Pwm_ZX_K14xM/Inc/Mcpwm_Pwm_Drv_Types.h" boolean GlobalCntEn; boolean InitTrigEn; uint8 CounterNum; const Mcpwm_Pwm_Drv_CounterType * const *CounterConfig; } Mcpwm_Pwm_Drv_ConfigType; typedef struct { const Mcpwm_Pwm_Drv_ConfigType *InstanceCfg; const Mcpwm_Pwm_Drv_ChannelConfigType * const *ConfiguredChArray; uint8 NoOfConfiguredCh; } Mcpwm_Pwm_Drv_UserCfgType; # 31 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Drvw_Types.h" 2 # 1 "../../../mcal/Pwm_ZX_K14xM/Inc/Tim_Pwm_Drv_Types.h" 1 # 30 "../../../mcal/Pwm_ZX_K14xM/Inc/Tim_Pwm_Drv_Types.h" # 1 "../Generated/inc\\Tim_Pwm_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Tim_Pwm_Drv_Cfg.h" # 1 "../Generated/inc/Tim_Pwm_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Tim_Pwm_Drv_Cfg.h" 2 # 31 "../../../mcal/Pwm_ZX_K14xM/Inc/Tim_Pwm_Drv_Types.h" 2 # 107 "../../../mcal/Pwm_ZX_K14xM/Inc/Tim_Pwm_Drv_Types.h" typedef enum { TIM_PWM_DRV_STATUS_SUCCESS = 0x00U, TIM_PWM_DRV_STATUS_ERROR = 0x01U, TIM_PWM_DRV_STATUS_BUSY = 0x002U, TIM_PWM_DRV_STATUS_TIMEOUT = 0x003U, TIM_PWM_DRV_STATUS_UNSUPPORTED = 0x004U } Tim_Pwm_Drv_StatusType; typedef enum { TIM_PWM_DRV_CLK_DISABLE = 0U, TIM_PWM_DRV_CLK_SOURCE_SYSTEM = 1U, TIM_PWM_DRV_CLK_SOURCE_FUNCTION = 2U, TIM_PWM_DRV_CLK_SOURCE_EXTERNAL = 3U } Tim_Pwm_Drv_ClkSourceType; typedef enum { TIM_PWM_DRV_CLK_DIVIDE_1 = 0U, TIM_PWM_DRV_CLK_DIVIDE_2, TIM_PWM_DRV_CLK_DIVIDE_4, TIM_PWM_DRV_CLK_DIVIDE_8, TIM_PWM_DRV_CLK_DIVIDE_16, TIM_PWM_DRV_CLK_DIVIDE_32, TIM_PWM_DRV_CLK_DIVIDE_64, TIM_PWM_DRV_CLK_DIVIDE_128 } Tim_Pwm_Drv_ClkDivideType; typedef enum { TIM_PWM_DRV_COUNTING_UP = 0U, TIM_PWM_DRV_COUNTING_UP_AND_DOWN } Tim_Pwm_Drv_CountingModeType; typedef enum { TIM_PWM_DRV_LOW_PULSE_POL = 1U, TIM_PWM_DRV_HIGH_PULSE_POL } Tim_Pwm_Drv_PulsePolarityType; typedef enum { TIM_PWM_DRV_POL_HIGH = 0U, TIM_PWM_DRV_POL_LOW } Tim_Pwm_Drv_PolarityType; typedef enum { TIM_PWM_DRV_CHANNEL_UNINIT = 0x00U, TIM_PWM_DRV_CHANNEL_RUNNING = 0x01U, TIM_PWM_DRV_CHANNEL_IDLE = 0x02U, TIM_PWM_DRV_CHANNEL_OUTPUT_FORCED = 0x03U } Tim_Pwm_Drv_ChannelStateType; typedef enum { TIM_PWM_DRV_OUTPUT_STATE_LOW = 0x00U, TIM_PWM_DRV_OUTPUT_STATE_HIGH = 0x01U } Tim_Pwm_Drv_OutputStateType; typedef enum { TIM_PWM_DRV_RISING_EDGE = 0U, TIM_PWM_DRV_FALLING_EDGE = 1U, TIM_PWM_DRV_BOTH_EDGES = 2U } Tim_Pwm_Drv_EdgeNotifType; typedef enum { TIM_PWM_DRV_FULL_POWER = 0x00U, TIM_PWM_DRV_LOW_POWER = 0x01U, TIM_PWM_DRV_NODEFINE_POWER = 0x02U } Tim_Pwm_Drv_PowerStateType; typedef enum { TIM_PWM_DRV_MODE_EDGE_ALIGNED = 0x01U, TIM_PWM_DRV_MODE_CENTER_ALIGNED = 0x02U, TIM_PWM_DRV_MODE_COMBINE_VARIABLE_EDGE_PLACEMENT = 0x03U } Tim_Pwm_Drv_ChannelModeType; typedef enum { TIM_PWM_DRV_CLK_DEADTIME_DIVIDE_1 = 0x01U, TIM_PWM_DRV_CLK_DEADTIME_DIVIDE_4 = 0x02U, TIM_PWM_DRV_CLK_DEADTIME_DIVIDE_16 = 0x03U } Tim_Pwm_Drv_DeadTimeDivider; typedef uint8 Tim_Pwm_Drv_EdgeInterruptType; typedef void (*Tim_Pwm_Drv_CallbackType)(void); typedef struct { boolean DeadTimeEnable; uint16 PhaseShiftValue; } Tim_Pwm_Drv_PairChannelCfgType; typedef struct { uint8 ChannelId; boolean ChIrqEn; Tim_Pwm_Drv_CallbackType ChannelCb; boolean ChannelOutputEnable; Tim_Pwm_Drv_PolarityType Polarity; Tim_Pwm_Drv_ChannelModeType ChannelMode; boolean ChannelMatchTrigEnable; boolean DmaEn; const Tim_Pwm_Drv_PairChannelCfgType *PairCfg; } Tim_Pwm_Drv_ChannelConfigType; typedef struct { Tim_Pwm_Drv_ClkSourceType ClkSrc; Tim_Pwm_Drv_ClkDivideType ClkDiv; # 290 "../../../mcal/Pwm_ZX_K14xM/Inc/Tim_Pwm_Drv_Types.h" uint16 PwmPeriod; Tim_Pwm_Drv_CountingModeType PwmCounterMode; Tim_Pwm_Drv_DeadTimeDivider DeadTimeDiv; uint16 DeadTimeVal; boolean InitTrigEn; boolean OverflowIrqEn; Tim_Pwm_Drv_CallbackType OverflowCb; } Tim_Pwm_Drv_ConfigType; typedef struct { const Tim_Pwm_Drv_ConfigType *InstanceCfg; const Tim_Pwm_Drv_ChannelConfigType * const *ConfiguredChArray; uint8 NoOfConfiguredCh; } Tim_Pwm_Drv_UserCfgType; # 32 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Drvw_Types.h" 2 # 104 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Drvw_Types.h" typedef uint8 Pwm_Drvw_ModuleType; typedef enum { PWM_DRVW_HW_NONE = 0x00U, PWM_DRVW_HW_MCPWM = 0x01U, PWM_DRVW_HW_TIM = 0x02U } Pwm_Drvw_HwType; typedef enum { PWM_DRVW_LOW = 0x00U, PWM_DRVW_HIGH } Pwm_Drvw_OutputStateType; typedef uint16 Pwm_Drvw_PeriodType; typedef enum { PWM_DRVW_RISING_EDGE = 0U, PWM_DRVW_FALLING_EDGE, PWM_DRVW_BOTH_EDGE } Pwm_Drvw_EdgeNotificationType; typedef enum { PWM_DRVW_FULL_POWER = 0x00U, PWM_DRVW_LOW_POWER, PWM_DRVW_NODEFINE_POWER } Pwm_Drvw_PowerStateType; typedef struct { const Pwm_Drvw_ModuleType ChnHwId; const Pwm_Drvw_HwType ChnHwType; const uint16 ChannelDutyCycle; const Mcpwm_Pwm_Drv_ChannelConfigType * McpwmChConfig; const Tim_Pwm_Drv_ChannelConfigType * TimChConfig; } Pwm_Drvw_ChannelConfigType; typedef struct { uint8 HwId; const Pwm_Drvw_HwType HwType; const Mcpwm_Pwm_Drv_UserCfgType * McpwmHwConfig; const Tim_Pwm_Drv_UserCfgType * TimHwConfig; } Pwm_Drvw_HwConfigType; # 30 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" 2 # 67 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 68 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" 2 extern const Pwm_Drvw_HwConfigType Pwm_Instances[((uint8)4U)]; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch0_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch1_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch2_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch3_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch4_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch9_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch10_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch11_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch12_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch5_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch6_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch7_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch8_Config; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section rodata = "" # 75 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section text = ".mcal_code" # 79 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" 2 # 91 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_Init(const Pwm_Drvw_HwConfigType * const HwCfgPtr); # 101 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_SetDefaultDutyCycle(uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 112 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_SyncDefaultDutyCycle(uint8 ModuleId, Pwm_Drvw_HwType HwType); # 121 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_StartInstance(const Pwm_Drvw_HwConfigType * const HwCfgPtr); # 131 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_InitIdleState(Pwm_Drvw_OutputStateType State, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 142 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_DeInit(const Pwm_Drvw_HwConfigType * const HwCfgPtr); # 157 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Std_ReturnType Pwm_Drvw_SetDutyCycle(uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 174 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Std_ReturnType Pwm_Drvw_SetPeriodAndDuty(Pwm_Drvw_PeriodType Period, uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 187 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_SetOutputToIdle(const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 201 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Pwm_Drvw_OutputStateType Pwm_Drvw_GetOutputState( const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 214 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_DisableNotification(const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 225 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_EnableNotification(Pwm_Drvw_EdgeNotificationType Notification, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 240 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Std_ReturnType Pwm_Drvw_CheckEdgeNotificationType(Pwm_Drvw_EdgeNotificationType Notification, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 253 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" uint16 Pwm_Drvw_GetChannelDutyCycle(const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 266 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_ForceOutputToLowLevel(boolean Force, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 282 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Std_ReturnType Pwm_Drvw_SetChannelDeadTimeTicks(uint16 DeadTimeTicks, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 300 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Std_ReturnType Pwm_Drvw_WriteDutyCycleToBuffer(uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 317 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Std_ReturnType Pwm_Drvw_WritePeriodAndDutyToBuffer(Pwm_Drvw_PeriodType Period, uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 333 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_WritePhaseShiftTicksToBuffer(uint16 Period, uint16 PhaseShiftTicks, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 347 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_SyncUpdate(const Pwm_Drvw_HwConfigType * HwCfgPtr); # 362 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_SetPhaseShiftTicks(uint16 Period, uint16 PhaseShiftTicks, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 380 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_SetDutyPhaseShiftTicks(uint16 DutyCyclePu, uint16 PhaseShiftTicks, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr, boolean SyncUpdate); # 396 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_EnableTriggerOutput(uint16 TrigMask, const Pwm_Drvw_HwConfigType * const HwCfgPtr); # 411 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_DisableTriggerOutput(uint16 TrigMask, const Pwm_Drvw_HwConfigType * const HwCfgPtr); # 425 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_MaskOutputs(uint8 ChannelMask, const Pwm_Drvw_HwConfigType * const HwCfgPtr); # 437 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_UnMaskOutputs(uint8 ChannelMask, const Pwm_Drvw_HwConfigType * const HwCfgPtr); # 450 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Std_ReturnType Pwm_Drvw_CheckIdleState(const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 462 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_SetPowerState(const Pwm_Drvw_HwConfigType * const HwCfgPtr, Pwm_Drvw_PowerStateType PowerState); # 479 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" uint32 Pwm_Drvw_GetMaxPeriodValue(const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 495 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Std_ReturnType Pwm_Drvw_CheckDeadTimeMode(const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 512 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Std_ReturnType Pwm_Drvw_CheckSetDutyPhaseShiftParams(uint16 PhaseShiftTicks, uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 522 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section text = "" # 523 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" 2 # 28 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" 2 # 1 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" 1 # 75 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 76 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" 2 extern const Mcpwm_Pwm_Drv_UserCfgType Mcpwm_Pwm_Drv_User0_Cfg; extern const Mcpwm_Pwm_Drv_ChannelConfigType Mcpwm_Pwm_Drv_I0_Ch0_Cfg; extern const Mcpwm_Pwm_Drv_UserCfgType Mcpwm_Pwm_Drv_User1_Cfg; extern const Mcpwm_Pwm_Drv_ChannelConfigType Mcpwm_Pwm_Drv_I1_Ch0_Cfg; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section rodata = "" # 83 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section text = ".mcal_code" # 88 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" 2 # 103 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_Init(uint8 McpwmId, const Mcpwm_Pwm_Drv_UserCfgType * userCfg); # 113 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_DeInit(uint8 McpwmId); # 126 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_SetDutyCycle(uint8 McpwmId, uint8 ChannelId, uint16 DutyCycle, boolean SwTrigger); # 141 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_SetPeriodAndDuty(uint8 McpwmId, uint8 ChannelId, uint16 Period, uint16 DutyCycle, boolean SwTrigger); # 155 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_SwOutputControl(uint8 McpwmId, uint8 ChannelId, Mcpwm_Pwm_Drv_OutputStateType State, boolean ActiveState); # 169 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" Mcpwm_Pwm_Drv_OutputStateType Mcpwm_Pwm_Drv_GetOutputState(uint8 McpwmId, uint8 ChannelId); # 180 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_DisableNotification(uint8 McpwmId, uint8 ChannelId); # 192 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_EnableNotification(uint8 McpwmId, uint8 ChannelId, Mcpwm_Pwm_Drv_EdgeNotifType Notification); # 208 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_SetPhaseShift(uint8 McpwmId, uint8 ChannelId, uint16 Period, uint16 PhaseShift, boolean SoftwareShift); # 224 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_SetDutyPhaseShift(uint8 McpwmId, uint8 ChannelId, uint16 DutyCycle, uint16 PhaseShift, boolean SotfwareTrigger); # 235 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" uint16 Mcpwm_Pwm_Drv_GetChannelDutyCycle(uint8 McpwmId, uint8 ChannelId); # 247 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_SetChannelDeadTime(uint8 McpwmId, uint8 ChannelId, uint16 DeadTimeVal); # 258 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_EnableTrigger(uint8 McpwmId, uint32 TriggerMask); # 269 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_DisableTrigger(uint8 McpwmId, uint32 TriggerMask); # 280 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_SyncUpdate(uint8 McpwmId); # 291 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_MaskOutputChannels(uint8 McpwmId, uint32 ChannelMask); # 302 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_UnMaskOutputChannels(uint8 McpwmId, uint32 ChannelMask); # 313 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_SetPowerState(uint8 McpwmId, Mcpwm_Pwm_Drv_PowerStateType PowerState); # 332 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" Mcpwm_Pwm_Drv_ChannelModeType Mcpwm_Pwm_Drv_GetChannelMode(uint8 McpwmId, uint8 ChannelId); # 347 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" Mcpwm_Pwm_Drv_ChannelStateType Mcpwm_Pwm_Drv_GetCurrentChannelState(uint8 McpwmId, uint8 ChannelId); # 359 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_SetCurrentChannelState(uint8 McpwmId, uint8 ChannelId, Mcpwm_Pwm_Drv_ChannelStateType State); # 371 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_RevertCurrentChannelState(uint8 McpwmId, uint8 ChannelId); # 382 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" Mcpwm_Pwm_Drv_EdgeInterruptType Mcpwm_Pwm_Drv_GetNotifFlag(uint8 McpwmId, uint8 ChannelId); # 393 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" uint16 Mcpwm_Pwm_Drv_GetPeriod(uint8 McpwmId, uint8 ChannelId); # 403 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_SoftwareUpdate(uint8 McpwmId); # 413 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_UpdateNow(uint8 McpwmId); # 425 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_InitIdleState(uint8 ModuleId, uint8 ChannelId, Mcpwm_Pwm_Drv_OutputStateType State); # 439 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" Mcpwm_Pwm_Drv_OutputStateType Mcpwm_Pwm_Drv_GetIdleState(uint8 McpwmId, uint8 ChannelId); # 451 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_InitOffValue(uint8 ModuleId, uint8 ChannelId, Mcpwm_Pwm_Drv_OutputStateType State); # 463 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_InitInstanceStart(uint8 McpwmId, const Mcpwm_Pwm_Drv_ConfigType * InstanceCfg); # 473 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_ProcessTofInterrupt(uint8 McpwmId); # 484 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" void Mcpwm_Pwm_Drv_ProcessCommonInterrupt(uint8 McpwmId); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section text = "" # 491 "../../../mcal/Pwm_ZX_K14xM/Inc\\Mcpwm_Pwm_Drv.h" 2 # 29 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" 2 # 1 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" 1 # 74 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 75 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" 2 extern const Tim_Pwm_Drv_UserCfgType Tim_Pwm_Drv_User2_Cfg; extern const Tim_Pwm_Drv_ChannelConfigType Tim_Pwm_Drv_I2_Ch0_Cfg; extern const Tim_Pwm_Drv_ChannelConfigType Tim_Pwm_Drv_I2_Ch1_Cfg; extern const Tim_Pwm_Drv_ChannelConfigType Tim_Pwm_Drv_I2_Ch2_Cfg; extern const Tim_Pwm_Drv_ChannelConfigType Tim_Pwm_Drv_I2_Ch3_Cfg; extern const Tim_Pwm_Drv_ChannelConfigType Tim_Pwm_Drv_I2_Ch4_Cfg; extern const Tim_Pwm_Drv_ChannelConfigType Tim_Pwm_Drv_I2_Ch5_Cfg; extern const Tim_Pwm_Drv_ChannelConfigType Tim_Pwm_Drv_I2_Ch6_Cfg; extern const Tim_Pwm_Drv_ChannelConfigType Tim_Pwm_Drv_I2_Ch7_Cfg; extern const Tim_Pwm_Drv_UserCfgType Tim_Pwm_Drv_User3_Cfg; extern const Tim_Pwm_Drv_ChannelConfigType Tim_Pwm_Drv_I3_Ch0_Cfg; extern const Tim_Pwm_Drv_ChannelConfigType Tim_Pwm_Drv_I3_Ch1_Cfg; extern const Tim_Pwm_Drv_ChannelConfigType Tim_Pwm_Drv_I3_Ch2_Cfg; extern const Tim_Pwm_Drv_ChannelConfigType Tim_Pwm_Drv_I3_Ch3_Cfg; extern const Tim_Pwm_Drv_ChannelConfigType Tim_Pwm_Drv_I3_Ch4_Cfg; extern const Tim_Pwm_Drv_ChannelConfigType Tim_Pwm_Drv_I3_Ch5_Cfg; extern const Tim_Pwm_Drv_ChannelConfigType Tim_Pwm_Drv_I3_Ch6_Cfg; extern const Tim_Pwm_Drv_ChannelConfigType Tim_Pwm_Drv_I3_Ch7_Cfg; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section rodata = "" # 82 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section text = ".mcal_code" # 87 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" 2 # 102 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_Init(uint8 TimId, const Tim_Pwm_Drv_UserCfgType * userCfg); # 112 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_DeInit(uint8 TimId); # 125 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_SetDutyCycle(uint8 TimId, uint8 ChannelId, uint16 DutyCycle, boolean SwTrigger); # 139 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_SetPeriodAndDuty(uint8 TimId, uint8 ChannelId, uint16 Period, uint16 DutyCycle, boolean SwTrigger); # 153 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_SwOutputControl(uint8 TimId, uint8 ChannelId, Tim_Pwm_Drv_OutputStateType State, boolean ActiveState); # 167 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" Tim_Pwm_Drv_OutputStateType Tim_Pwm_Drv_GetOutputState(uint8 TimId, uint8 ChannelId); # 178 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_DisableNotification(uint8 TimId, uint8 ChannelId); # 190 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_EnableNotification(uint8 TimId, uint8 ChannelId, Tim_Pwm_Drv_EdgeNotifType Notification); # 206 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_SetPhaseShift(uint8 TimId, uint8 ChannelId, uint16 Period, uint16 PhaseShift, boolean SoftwareShift); # 222 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_SetDutyPhaseShift(uint8 TimId, uint8 ChannelId, uint16 DutyCycle, uint16 PhaseShift, boolean SotfwareTrigger); # 233 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" uint16 Tim_Pwm_Drv_GetChannelDutyCycle(uint8 TimId, uint8 ChannelId); # 244 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_SetCounterDeadTime(uint8 TimId, uint16 DeadTimeVal); # 255 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_EnableTrigger(uint8 TimId, uint32 TriggerMask); # 266 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_DisableTrigger(uint8 TimId, uint32 TriggerMask); # 276 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_SyncUpdate(uint8 TimId); # 287 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_MaskOutputChannels(uint8 TimId, uint32 ChannelMask); # 298 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_UnMaskOutputChannels(uint8 TimId, uint32 ChannelMask); # 309 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_SetPowerState(uint8 TimId, Tim_Pwm_Drv_PowerStateType PowerState); # 324 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" Tim_Pwm_Drv_ChannelModeType Tim_Pwm_Drv_GetChannelMode(uint8 TimId, uint8 ChannelId); # 339 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" Tim_Pwm_Drv_ChannelStateType Tim_Pwm_Drv_GetCurrentChannelState(uint8 TimId, uint8 ChannelId); # 351 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_SetCurrentChannelState(uint8 TimId, uint8 ChannelId, Tim_Pwm_Drv_ChannelStateType State); # 363 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_RevertCurrentChannelState(uint8 TimId, uint8 ChannelId); # 374 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" Tim_Pwm_Drv_EdgeInterruptType Tim_Pwm_Drv_GetNotifFlag(uint8 TimId, uint8 ChannelId); # 384 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" uint16 Tim_Pwm_Drv_GetPeriod(uint8 TimId); # 394 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_SoftwareUpdate(uint8 TimId); # 404 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_UpdateNow(uint8 TimId); # 416 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_InitIdleState(uint8 ModuleId, uint8 ChannelId, Tim_Pwm_Drv_OutputStateType State); # 429 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" Tim_Pwm_Drv_OutputStateType Tim_Pwm_Drv_GetIdleState(uint8 TimId, uint8 ChannelId); # 440 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_InitInstanceStart(uint8 TimId, const Tim_Pwm_Drv_ConfigType * InstanceCfg); # 450 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_ProcessTofInterrupt(uint8 TimId); # 461 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" void Tim_Pwm_Drv_ProcessCommonInterrupt(uint8 TimId); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section text = "" # 467 "../../../mcal/Pwm_ZX_K14xM/Inc\\Tim_Pwm_Drv.h" 2 # 30 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" 2 # 119 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" static void Pwm_Drvw_ForceMcpwmOutputToLowLevel(boolean Force, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); static void Pwm_Drvw_ForceTimOutputToLowLevel(boolean Force, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); static void Pwm_Drvw_InitMcpwmIdleState(Pwm_Drvw_OutputStateType State, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); static void Pwm_Drvw_InitTimIdleState(Pwm_Drvw_OutputStateType State, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); static Std_ReturnType Pwm_Drvw_CheckMcpwmDefaultDutyPhaseShiftParams(uint16 DutyCycle, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); static Std_ReturnType Pwm_Drvw_CheckTimDefaultDutyPhaseShiftParams(uint16 DutyCycle, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 149 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" static Std_ReturnType Pwm_Drvw_CheckDefaultDutyPhaseShiftParams(uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 160 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section text = ".mcal_code" # 161 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" 2 # 174 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" static void Pwm_Drvw_ForceMcpwmOutputToLowLevel(boolean Force, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { boolean ForceEnable = Force; Mcpwm_Pwm_Drv_PolarityType PolCh = ChnConfigPtr->McpwmChConfig->Polarity; Mcpwm_Pwm_Drv_OutputStateType OutputState = (MCPWM_PWM_DRV_POL_LOW == PolCh)? MCPWM_PWM_DRV_OUTPUT_STATE_HIGH : MCPWM_PWM_DRV_OUTPUT_STATE_LOW; uint8 ModuleId = ChnConfigPtr->ChnHwId; uint8 ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; if (MCPWM_PWM_DRV_CHANNEL_OUTPUT_FORCED != Mcpwm_Pwm_Drv_GetCurrentChannelState(ModuleId,ChannelId)) { if(1U == ForceEnable) { Mcpwm_Pwm_Drv_SetCurrentChannelState(ModuleId, ChannelId,MCPWM_PWM_DRV_CHANNEL_OUTPUT_FORCED); } } else { if(0U == ForceEnable) { Mcpwm_Pwm_Drv_RevertCurrentChannelState(ModuleId, ChannelId); if (MCPWM_PWM_DRV_CHANNEL_IDLE == Mcpwm_Pwm_Drv_GetCurrentChannelState(ModuleId,ChannelId)) { OutputState = Mcpwm_Pwm_Drv_GetIdleState(ModuleId, ChannelId); ForceEnable = 1U; } } } Mcpwm_Pwm_Drv_SwOutputControl(ModuleId,ChannelId,OutputState,ForceEnable); } # 217 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" static void Pwm_Drvw_ForceTimOutputToLowLevel(boolean Force, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { boolean ForceEnable = Force; Tim_Pwm_Drv_PolarityType PolCh = ChnConfigPtr->TimChConfig->Polarity; Tim_Pwm_Drv_OutputStateType OutputState = (TIM_PWM_DRV_POL_LOW == PolCh)? TIM_PWM_DRV_OUTPUT_STATE_HIGH : TIM_PWM_DRV_OUTPUT_STATE_LOW; uint8 ModuleId = ChnConfigPtr->ChnHwId; uint8 ChannelId = ChnConfigPtr->TimChConfig->ChannelId; if (TIM_PWM_DRV_CHANNEL_OUTPUT_FORCED != Tim_Pwm_Drv_GetCurrentChannelState(ModuleId,ChannelId)) { if(1U == ForceEnable) { Tim_Pwm_Drv_SetCurrentChannelState(ModuleId, ChannelId,TIM_PWM_DRV_CHANNEL_OUTPUT_FORCED); } } else { if(0U == ForceEnable) { Tim_Pwm_Drv_RevertCurrentChannelState(ModuleId, ChannelId); if (TIM_PWM_DRV_CHANNEL_IDLE == Tim_Pwm_Drv_GetCurrentChannelState(ModuleId,ChannelId)) { OutputState = Tim_Pwm_Drv_GetIdleState(ModuleId, ChannelId);; ForceEnable = 1U; } } } Tim_Pwm_Drv_SwOutputControl(ModuleId,ChannelId,OutputState,ForceEnable); } # 261 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" static void Pwm_Drvw_InitMcpwmIdleState(Pwm_Drvw_OutputStateType State, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { uint8 ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; uint8 ModuleId = ChnConfigPtr->ChnHwId; Mcpwm_Pwm_Drv_PolarityType Polarity = ChnConfigPtr->McpwmChConfig->Polarity; Mcpwm_Pwm_Drv_InitOffValue(ModuleId, ChannelId, (Mcpwm_Pwm_Drv_OutputStateType)State); if(MCPWM_PWM_DRV_POL_HIGH == Polarity) { Mcpwm_Pwm_Drv_InitIdleState(ModuleId, ChannelId, (Mcpwm_Pwm_Drv_OutputStateType)State); } else { if(PWM_DRVW_LOW == State) { Mcpwm_Pwm_Drv_InitIdleState(ModuleId, ChannelId, MCPWM_PWM_DRV_OUTPUT_STATE_HIGH); } else { Mcpwm_Pwm_Drv_InitIdleState(ModuleId, ChannelId, MCPWM_PWM_DRV_OUTPUT_STATE_LOW); } } } # 297 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" static void Pwm_Drvw_InitTimIdleState(Pwm_Drvw_OutputStateType State, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { uint8 ChannelId = ChnConfigPtr->TimChConfig->ChannelId; uint8 ModuleId = ChnConfigPtr->ChnHwId; Tim_Pwm_Drv_PolarityType Polarity = ChnConfigPtr->TimChConfig->Polarity; if(TIM_PWM_DRV_POL_HIGH == Polarity) { Tim_Pwm_Drv_InitIdleState(ModuleId, ChannelId, (Tim_Pwm_Drv_OutputStateType)State); } else { if(PWM_DRVW_LOW == State) { Tim_Pwm_Drv_InitIdleState(ModuleId, ChannelId, TIM_PWM_DRV_OUTPUT_STATE_HIGH); } else { Tim_Pwm_Drv_InitIdleState(ModuleId, ChannelId, TIM_PWM_DRV_OUTPUT_STATE_LOW); } } } # 334 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" static Std_ReturnType Pwm_Drvw_CheckMcpwmDefaultDutyPhaseShiftParams(uint16 DutyCycle, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint8 ModuleId = ChnConfigPtr->ChnHwId; uint16 CnVValue = 0U; uint16 CurrentPeriod; uint16 DutyTicks; uint16 PhaseShiftTicks; uint8 ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; if(0U == (ChannelId % 2U)) { if(MCPWM_PWM_DRV_MODE_COMBINE_VARIABLE_EDGE_PLACEMENT == ChnConfigPtr->McpwmChConfig->ChannelMode) { PhaseShiftTicks = ChnConfigPtr->McpwmChConfig->PairCfg->PhaseShiftValue; CurrentPeriod = Mcpwm_Pwm_Drv_GetPeriod(ModuleId, ChannelId); DutyTicks = (uint16)((uint32)((uint32)CurrentPeriod * DutyCycle) / 0x8000U); if (((0x8000U) != DutyCycle) && (0U != DutyCycle)) { CnVValue = PhaseShiftTicks + DutyTicks; if ((CnVValue <= PhaseShiftTicks) || (CurrentPeriod <= CnVValue)) { RetVal = (Std_ReturnType)0x01U; } } } } return RetVal; } # 380 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" static Std_ReturnType Pwm_Drvw_CheckTimDefaultDutyPhaseShiftParams(uint16 DutyCycle, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint8 ModuleId = ChnConfigPtr->ChnHwId; uint16 CnVValue = 0U; uint16 CurrentPeriod; uint16 DutyTicks; uint16 PhaseShiftTicks; uint8 ChannelId = ChnConfigPtr->TimChConfig->ChannelId; if(0U == (ChannelId % 2U)) { if(TIM_PWM_DRV_MODE_COMBINE_VARIABLE_EDGE_PLACEMENT == ChnConfigPtr->TimChConfig->ChannelMode) { PhaseShiftTicks = ChnConfigPtr->TimChConfig->PairCfg->PhaseShiftValue; CurrentPeriod = Tim_Pwm_Drv_GetPeriod(ModuleId); DutyTicks = (uint16)((uint32)((uint32)CurrentPeriod * DutyCycle) / 0x8000U); if (((0x8000U) != DutyCycle) && (0U != DutyCycle)) { CnVValue = PhaseShiftTicks + DutyTicks; if ((CnVValue <= PhaseShiftTicks) || (CurrentPeriod <= CnVValue)) { RetVal = (Std_ReturnType)0x01U; } } } } return RetVal; } # 425 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" static Std_ReturnType Pwm_Drvw_CheckDefaultDutyPhaseShiftParams(uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; if(DutyCyclePu > 0x8000U) { RetVal = (Std_ReturnType)0x01U; } else { uint16 DutyCycle = 0x8000U - DutyCyclePu; switch (ChnConfigPtr->ChnHwType) { case PWM_DRVW_HW_MCPWM: RetVal = Pwm_Drvw_CheckMcpwmDefaultDutyPhaseShiftParams(DutyCycle,ChnConfigPtr); break; case PWM_DRVW_HW_TIM: RetVal = Pwm_Drvw_CheckTimDefaultDutyPhaseShiftParams(DutyCycle,ChnConfigPtr); break; default: RetVal = (Std_ReturnType)0x01U; break; } } return RetVal; } # 464 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_Init(const Pwm_Drvw_HwConfigType * const HwCfgPtr) { uint8 ModuleId = HwCfgPtr->HwId; if(PWM_DRVW_HW_MCPWM == HwCfgPtr->HwType) { if(((void *)0) != HwCfgPtr->McpwmHwConfig) { Mcpwm_Pwm_Drv_Init(ModuleId, HwCfgPtr->McpwmHwConfig); } } else if(PWM_DRVW_HW_TIM == HwCfgPtr->HwType) { if(((void *)0) != HwCfgPtr->TimHwConfig) { Tim_Pwm_Drv_Init(ModuleId, HwCfgPtr->TimHwConfig); } } else { } } # 496 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_SetDefaultDutyCycle(uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { uint32 DutyCycleTicks = 0U; uint8 ModuleId = ChnConfigPtr->ChnHwId; uint8 ChannelId; Std_ReturnType RetVal = Pwm_Drvw_CheckDefaultDutyPhaseShiftParams(DutyCyclePu, ChnConfigPtr); if((Std_ReturnType)0x00U == RetVal) { if (PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; DutyCycleTicks = (uint32)Mcpwm_Pwm_Drv_GetPeriod(ModuleId, ChannelId) * (uint32)DutyCyclePu; DutyCycleTicks = DutyCycleTicks / 0x8000U; Mcpwm_Pwm_Drv_SetDutyCycle (ModuleId, ChannelId, (uint16)DutyCycleTicks, 0U); } else if(PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { ChannelId = ChnConfigPtr->TimChConfig->ChannelId; DutyCycleTicks = (uint32)Tim_Pwm_Drv_GetPeriod(ModuleId) * (uint32)DutyCyclePu; DutyCycleTicks = DutyCycleTicks / 0x8000U; Tim_Pwm_Drv_SetDutyCycle (ModuleId, ChannelId, (uint16)DutyCycleTicks, 0U); } else { (void)DutyCycleTicks; (void)DutyCyclePu; } } } # 545 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_SyncDefaultDutyCycle(uint8 ModuleId, Pwm_Drvw_HwType HwType) { if(PWM_DRVW_HW_MCPWM == HwType) { Mcpwm_Pwm_Drv_SoftwareUpdate(ModuleId); } else if(PWM_DRVW_HW_TIM == HwType) { Tim_Pwm_Drv_SoftwareUpdate(ModuleId); } else { } } # 568 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_StartInstance(const Pwm_Drvw_HwConfigType * const HwCfgPtr) { uint8 ModuleId = HwCfgPtr->HwId; if(PWM_DRVW_HW_MCPWM == HwCfgPtr->HwType) { if(((void *)0) != HwCfgPtr->McpwmHwConfig) { Mcpwm_Pwm_Drv_InitInstanceStart(ModuleId, HwCfgPtr->McpwmHwConfig->InstanceCfg); } } else if(PWM_DRVW_HW_TIM == HwCfgPtr->HwType) { if(((void *)0) != HwCfgPtr->TimHwConfig) { Tim_Pwm_Drv_InitInstanceStart(ModuleId, HwCfgPtr->TimHwConfig->InstanceCfg); } } else { } } # 600 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_DeInit(const Pwm_Drvw_HwConfigType * const HwCfgPtr) { uint8 ModuleId = HwCfgPtr->HwId; if(PWM_DRVW_HW_MCPWM == HwCfgPtr->HwType) { Mcpwm_Pwm_Drv_DeInit(ModuleId); } else if(PWM_DRVW_HW_TIM == HwCfgPtr->HwType) { Tim_Pwm_Drv_DeInit(ModuleId); } else { } } # 632 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" Std_ReturnType Pwm_Drvw_SetDutyCycle(uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { uint8 ModuleId = ChnConfigPtr->ChnHwId; uint8 ChannelId = 0U; uint32 DutyCycleTicks = 0; Std_ReturnType RetVal = (Std_ReturnType)0x00U; if(PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { if (((void *)0) != ChnConfigPtr->McpwmChConfig) { ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; DutyCycleTicks = Mcpwm_Pwm_Drv_GetPeriod(ModuleId, ChannelId); DutyCycleTicks = (uint16)((uint32)DutyCycleTicks * DutyCyclePu / 0x8000U); Mcpwm_Pwm_Drv_SetDutyCycle(ModuleId, ChannelId,(uint16)DutyCycleTicks,1U); } } else if(PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { if (((void *)0) != ChnConfigPtr->TimChConfig) { ChannelId = ChnConfigPtr->TimChConfig->ChannelId; DutyCycleTicks = Tim_Pwm_Drv_GetPeriod(ModuleId); DutyCycleTicks = (uint16)((uint32)DutyCycleTicks * DutyCyclePu / 0x8000U); if((TIM_PWM_DRV_MODE_CENTER_ALIGNED == Tim_Pwm_Drv_GetChannelMode(ModuleId, ChannelId)) && (DutyCycleTicks >= 0x8000U)) { RetVal = (Std_ReturnType)0x01U; } else { Tim_Pwm_Drv_SetDutyCycle(ModuleId, ChannelId, (uint16)DutyCycleTicks, 1U); } } } else { } return RetVal; } # 702 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" Std_ReturnType Pwm_Drvw_SetPeriodAndDuty(Pwm_Drvw_PeriodType Period, uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { uint8 ModuleId = ChnConfigPtr->ChnHwId; uint8 ChannelId; Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint16 DutyCycleTicks = (uint16)(((uint32)Period * DutyCyclePu) / 0x8000U); if(PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { if (((void *)0) != ChnConfigPtr->McpwmChConfig) { ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; Mcpwm_Pwm_Drv_SetPeriodAndDuty(ModuleId, ChannelId, Period, DutyCycleTicks,1U); } } else if(PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { if (((void *)0) != ChnConfigPtr->TimChConfig) { ChannelId = ChnConfigPtr->TimChConfig->ChannelId; if((TIM_PWM_DRV_MODE_CENTER_ALIGNED == Tim_Pwm_Drv_GetChannelMode(ModuleId, ChannelId)) && (DutyCycleTicks >= 0x8000U)) { RetVal = (Std_ReturnType)0x01U; } else { Tim_Pwm_Drv_SetPeriodAndDuty(ModuleId, ChannelId, Period, DutyCycleTicks, 1U); } } } else { } return RetVal; } # 764 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_SetOutputToIdle(const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { uint8 ModuleId = ChnConfigPtr->ChnHwId; uint8 ChannelId; if(PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; if (MCPWM_PWM_DRV_CHANNEL_RUNNING == Mcpwm_Pwm_Drv_GetCurrentChannelState(ModuleId,ChannelId)) { Mcpwm_Pwm_Drv_OutputStateType SwCtrlValue = Mcpwm_Pwm_Drv_GetIdleState(ModuleId, ChannelId); Mcpwm_Pwm_Drv_SetCurrentChannelState(ModuleId,ChannelId,MCPWM_PWM_DRV_CHANNEL_IDLE); Mcpwm_Pwm_Drv_SwOutputControl(ModuleId,ChannelId,SwCtrlValue,1U); } } else if(PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { ChannelId = ChnConfigPtr->TimChConfig->ChannelId; if (TIM_PWM_DRV_CHANNEL_RUNNING == Tim_Pwm_Drv_GetCurrentChannelState(ModuleId,ChannelId)) { Tim_Pwm_Drv_OutputStateType SwCtrlValue = Tim_Pwm_Drv_GetIdleState(ModuleId, ChannelId); Tim_Pwm_Drv_SetCurrentChannelState(ModuleId,ChannelId,TIM_PWM_DRV_CHANNEL_IDLE); Tim_Pwm_Drv_SwOutputControl(ModuleId,ChannelId,SwCtrlValue,1U); } } else { } } # 807 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" Pwm_Drvw_OutputStateType Pwm_Drvw_GetOutputState( const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { Pwm_Drvw_OutputStateType RetVal = PWM_DRVW_LOW; uint8 ModuleId = ChnConfigPtr->ChnHwId; uint8 ChannelId = 0; if(PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { if (((void *)0) != ChnConfigPtr->McpwmChConfig) { ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; Mcpwm_Pwm_Drv_OutputStateType PwmOutputState = Mcpwm_Pwm_Drv_GetOutputState(ModuleId, ChannelId); RetVal = (MCPWM_PWM_DRV_OUTPUT_STATE_LOW == PwmOutputState)? PWM_DRVW_LOW : PWM_DRVW_HIGH; } } else if(PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { if (((void *)0) != ChnConfigPtr->TimChConfig) { ChannelId = ChnConfigPtr->TimChConfig->ChannelId; Tim_Pwm_Drv_OutputStateType PwmOutputState = Tim_Pwm_Drv_GetOutputState(ModuleId, ChannelId); RetVal = (TIM_PWM_DRV_OUTPUT_STATE_LOW == PwmOutputState)? PWM_DRVW_LOW : PWM_DRVW_HIGH; } } else { } return RetVal; } # 857 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_DisableNotification(const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { uint8 ModuleId = ChnConfigPtr->ChnHwId; uint8 ChannelId; if(PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { if (((void *)0) != ChnConfigPtr->McpwmChConfig) { ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; Mcpwm_Pwm_Drv_DisableNotification(ModuleId, ChannelId); } } else if(PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { if (((void *)0) != ChnConfigPtr->TimChConfig) { ChannelId = ChnConfigPtr->TimChConfig->ChannelId; Tim_Pwm_Drv_DisableNotification(ModuleId, ChannelId); } } else { } } # 893 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_EnableNotification(Pwm_Drvw_EdgeNotificationType Notification, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { uint8 ModuleId = ChnConfigPtr->ChnHwId; uint8 ChannelId; if(PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { if (((void *)0) != ChnConfigPtr->McpwmChConfig) { ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; Mcpwm_Pwm_Drv_EnableNotification(ModuleId,ChannelId,(Mcpwm_Pwm_Drv_EdgeNotifType)Notification); } } else if(PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { if (((void *)0) != ChnConfigPtr->TimChConfig) { ChannelId = ChnConfigPtr->TimChConfig->ChannelId; Tim_Pwm_Drv_EnableNotification(ModuleId,ChannelId,(Tim_Pwm_Drv_EdgeNotifType)Notification); } } else { } } # 933 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" Std_ReturnType Pwm_Drvw_CheckEdgeNotificationType(Pwm_Drvw_EdgeNotificationType Notification, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { Std_ReturnType RetVal = (Std_ReturnType)0x01U; uint8 ModuleId = ChnConfigPtr->ChnHwId; uint8 ChannelId; if(PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { if (((void *)0) != ChnConfigPtr->McpwmChConfig) { ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; Mcpwm_Pwm_Drv_ChannelModeType Mode = Mcpwm_Pwm_Drv_GetChannelMode(ModuleId, ChannelId); if(((MCPWM_PWM_DRV_MODE_CENTER_ALIGNED != Mode) && (MCPWM_PWM_DRV_MODE_COMBINE_SYM_CENTER_ALIGNED != Mode)) || (Notification == PWM_DRVW_BOTH_EDGE)) { RetVal = (Std_ReturnType)0x00U; } } } else if(PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { if (((void *)0) != ChnConfigPtr->TimChConfig) { ChannelId = ChnConfigPtr->TimChConfig->ChannelId; Tim_Pwm_Drv_ChannelModeType Mode = Tim_Pwm_Drv_GetChannelMode(ModuleId, ChannelId); if((Mode != TIM_PWM_DRV_MODE_CENTER_ALIGNED) || (Notification == PWM_DRVW_BOTH_EDGE)) { RetVal = (Std_ReturnType)0x00U; } } } else { } return RetVal; } # 983 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" uint16 Pwm_Drvw_GetChannelDutyCycle(const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { uint16 DutyCyclePu = (uint16)0U; uint8 ModuleId = ChnConfigPtr->ChnHwId; uint8 ChannelId; if(PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; DutyCyclePu = Mcpwm_Pwm_Drv_GetChannelDutyCycle(ModuleId,ChannelId); } else if(PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { ChannelId = ChnConfigPtr->TimChConfig->ChannelId; DutyCyclePu = Tim_Pwm_Drv_GetChannelDutyCycle(ModuleId,ChannelId); } else { } return DutyCyclePu; } # 1018 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_ForceOutputToLowLevel(boolean Force, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { if(PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { Pwm_Drvw_ForceMcpwmOutputToLowLevel(Force,ChnConfigPtr); } else if(PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { Pwm_Drvw_ForceTimOutputToLowLevel(Force,ChnConfigPtr); } else { } } # 1048 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" Std_ReturnType Pwm_Drvw_SetChannelDeadTimeTicks(uint16 DeadTimeTicks, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { Std_ReturnType RetVal = (Std_ReturnType)0x01U; uint8 ModuleId = ChnConfigPtr->ChnHwId; if (PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { if ((DeadTimeTicks > 0U) && (DeadTimeTicks < 4096U)) { RetVal = (Std_ReturnType)0x00U; uint8 ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; Mcpwm_Pwm_Drv_SetChannelDeadTime(ModuleId, ChannelId, DeadTimeTicks); } } else if (PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { if ((DeadTimeTicks > 0U) && (DeadTimeTicks < 64U)) { RetVal = (Std_ReturnType)0x00U; Tim_Pwm_Drv_SetCounterDeadTime(ModuleId,DeadTimeTicks); } } else { } return RetVal; } # 1094 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" Std_ReturnType Pwm_Drvw_WriteDutyCycleToBuffer(uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 DutyCycleTicks = 0U; uint8 ModuleId = ChnConfigPtr->ChnHwId; uint8 ChannelId; if (PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; DutyCycleTicks = (uint32)Mcpwm_Pwm_Drv_GetPeriod(ModuleId, ChannelId) * (uint32)DutyCyclePu; DutyCycleTicks = DutyCycleTicks / 0x8000U; Mcpwm_Pwm_Drv_SetDutyCycle(ModuleId, ChannelId, (uint16)DutyCycleTicks, 0U); } else if (PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { ChannelId = ChnConfigPtr->TimChConfig->ChannelId; DutyCycleTicks = (uint32)Tim_Pwm_Drv_GetPeriod(ModuleId) * (uint32)DutyCyclePu; DutyCycleTicks = DutyCycleTicks / 0x8000U; if((TIM_PWM_DRV_MODE_CENTER_ALIGNED == Tim_Pwm_Drv_GetChannelMode(ModuleId, ChannelId)) && (DutyCycleTicks >= 0x8000U)) { RetVal = (Std_ReturnType)0x01U; } else { Tim_Pwm_Drv_SetDutyCycle(ModuleId, ChannelId, (uint16)DutyCycleTicks, 0U); } } else { (void)DutyCycleTicks; (void)DutyCyclePu; } return RetVal; } # 1151 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" Std_ReturnType Pwm_Drvw_WritePeriodAndDutyToBuffer(Pwm_Drvw_PeriodType Period, uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { uint8 ModuleId = ChnConfigPtr->ChnHwId; uint8 ChannelId; Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint16 DutyCycleTicks = (uint16)(((uint32)Period * DutyCyclePu) / 0x8000U); if (PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; Mcpwm_Pwm_Drv_SetPeriodAndDuty(ModuleId, ChannelId, Period, DutyCycleTicks, 0U); } else if (PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { ChannelId = ChnConfigPtr->TimChConfig->ChannelId; if((TIM_PWM_DRV_MODE_CENTER_ALIGNED == Tim_Pwm_Drv_GetChannelMode(ModuleId, ChannelId)) && (DutyCycleTicks >= 0x8000U)) { RetVal = (Std_ReturnType)0x01U; } else { Tim_Pwm_Drv_SetPeriodAndDuty(ModuleId, ChannelId, Period, DutyCycleTicks, 0U); } } else { (void)DutyCycleTicks; (void)DutyCyclePu; (void)Period; } return RetVal; } # 1203 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_WritePhaseShiftTicksToBuffer(uint16 Period, uint16 PhaseShiftTicks, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { uint8 ModuleId = ChnConfigPtr->ChnHwId; uint8 ChannelId; if (PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; Mcpwm_Pwm_Drv_SetPhaseShift(ModuleId, ChannelId, Period, PhaseShiftTicks, 0U); } else if (PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { ChannelId = ChnConfigPtr->TimChConfig->ChannelId; Tim_Pwm_Drv_SetPhaseShift(ModuleId, ChannelId, Period, PhaseShiftTicks, 0U); } else { (void)PhaseShiftTicks; (void)Period; } } # 1237 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_SyncUpdate(const Pwm_Drvw_HwConfigType * HwCfgPtr) { uint8 ModuleId = HwCfgPtr->HwId; Pwm_Drvw_HwType HwType = HwCfgPtr->HwType; if(PWM_DRVW_HW_MCPWM == HwType) { Mcpwm_Pwm_Drv_SyncUpdate(ModuleId); } else if(PWM_DRVW_HW_TIM == HwType) { Tim_Pwm_Drv_SyncUpdate(ModuleId); } else { } } # 1269 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_SetPhaseShiftTicks(uint16 Period, uint16 PhaseShiftTicks, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { uint8 ModuleId = ChnConfigPtr->ChnHwId; uint8 ChannelId; if (PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; Mcpwm_Pwm_Drv_SetPhaseShift(ModuleId, ChannelId, Period, PhaseShiftTicks, 1U); } else if (PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { ChannelId = ChnConfigPtr->TimChConfig->ChannelId; Tim_Pwm_Drv_SetPhaseShift(ModuleId, ChannelId, Period, PhaseShiftTicks, 1U); } else { (void)Period; (void)PhaseShiftTicks; } } # 1309 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_SetDutyPhaseShiftTicks(uint16 DutyCyclePu, uint16 PhaseShiftTicks, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr, boolean SyncUpdate) { uint16 DutyCycleTicks = 0U; uint8 ModuleId = ChnConfigPtr->ChnHwId; uint8 ChannelId; if (PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; DutyCycleTicks = Mcpwm_Pwm_Drv_GetPeriod(ModuleId, ChannelId); DutyCycleTicks = (uint16)((uint32)DutyCycleTicks * DutyCyclePu / 0x8000U); Mcpwm_Pwm_Drv_SetDutyPhaseShift(ModuleId,ChannelId,DutyCycleTicks,PhaseShiftTicks,SyncUpdate); } else if (PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { ChannelId = ChnConfigPtr->TimChConfig->ChannelId; DutyCycleTicks = Tim_Pwm_Drv_GetPeriod(ModuleId); DutyCycleTicks = (uint16)((uint32)DutyCycleTicks * DutyCyclePu / 0x8000U); Tim_Pwm_Drv_SetDutyPhaseShift(ModuleId,ChannelId,DutyCycleTicks,PhaseShiftTicks,SyncUpdate); } else { (void)DutyCycleTicks; (void)DutyCyclePu; (void)PhaseShiftTicks; (void)SyncUpdate; } } # 1357 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_EnableTriggerOutput(uint16 TrigMask, const Pwm_Drvw_HwConfigType * const HwCfgPtr) { switch(HwCfgPtr->HwType) { case PWM_DRVW_HW_MCPWM: Mcpwm_Pwm_Drv_EnableTrigger(HwCfgPtr->HwId, (uint32)TrigMask); break; case PWM_DRVW_HW_TIM: Tim_Pwm_Drv_EnableTrigger(HwCfgPtr->HwId, (uint32)TrigMask); break; case PWM_DRVW_HW_NONE: break; default: break; } } # 1391 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_DisableTriggerOutput(uint16 TrigMask, const Pwm_Drvw_HwConfigType * const HwCfgPtr) { switch(HwCfgPtr->HwType) { case PWM_DRVW_HW_MCPWM: Mcpwm_Pwm_Drv_DisableTrigger(HwCfgPtr->HwId, (uint32)TrigMask); break; case PWM_DRVW_HW_TIM: Tim_Pwm_Drv_DisableTrigger(HwCfgPtr->HwId, (uint32)TrigMask); break; case PWM_DRVW_HW_NONE: break; default: break; } } # 1424 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_MaskOutputs(uint8 ChannelMask, const Pwm_Drvw_HwConfigType * const HwCfgPtr) { switch(HwCfgPtr->HwType) { case PWM_DRVW_HW_MCPWM: Mcpwm_Pwm_Drv_MaskOutputChannels(HwCfgPtr->HwId, (uint32)ChannelMask); break; case PWM_DRVW_HW_TIM: Tim_Pwm_Drv_MaskOutputChannels(HwCfgPtr->HwId, (uint32)ChannelMask); break; case PWM_DRVW_HW_NONE: break; default: break; } } # 1455 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_UnMaskOutputs(uint8 ChannelMask, const Pwm_Drvw_HwConfigType * const HwCfgPtr) { switch(HwCfgPtr->HwType) { case PWM_DRVW_HW_MCPWM: Mcpwm_Pwm_Drv_UnMaskOutputChannels(HwCfgPtr->HwId, (uint32)ChannelMask); break; case PWM_DRVW_HW_TIM: Tim_Pwm_Drv_UnMaskOutputChannels(HwCfgPtr->HwId, (uint32)ChannelMask); break; case PWM_DRVW_HW_NONE: break; default: break; } } # 1487 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" Std_ReturnType Pwm_Drvw_CheckIdleState(const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { uint8 ModuleId = ChnConfigPtr->ChnHwId; uint8 ChannelId; Std_ReturnType RetVal = (Std_ReturnType)0x00U; if (PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; Mcpwm_Pwm_Drv_ChannelStateType Pwm_State = Mcpwm_Pwm_Drv_GetCurrentChannelState(ModuleId,ChannelId); if(MCPWM_PWM_DRV_CHANNEL_RUNNING == Pwm_State) { RetVal = (Std_ReturnType)0x01U; } Mcpwm_Pwm_Drv_EdgeInterruptType Pwm_Notif = Mcpwm_Pwm_Drv_GetNotifFlag(ModuleId,ChannelId); if(((Mcpwm_Pwm_Drv_EdgeInterruptType)0U) != Pwm_Notif) { RetVal = (Std_ReturnType)0x01U; } } else if(PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { ChannelId = ChnConfigPtr->TimChConfig->ChannelId; Tim_Pwm_Drv_ChannelStateType Pwm_State = Tim_Pwm_Drv_GetCurrentChannelState(ModuleId,ChannelId); if(TIM_PWM_DRV_CHANNEL_RUNNING == Pwm_State) { RetVal = (Std_ReturnType)0x01U; } Tim_Pwm_Drv_EdgeInterruptType Pwm_Notif = Tim_Pwm_Drv_GetNotifFlag(ModuleId,ChannelId); if(((Tim_Pwm_Drv_EdgeInterruptType)0U) != Pwm_Notif) { RetVal = (Std_ReturnType)0x01U; } } else { RetVal = (Std_ReturnType)0x01U; } return RetVal; } # 1545 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_SetPowerState(const Pwm_Drvw_HwConfigType * const HwCfgPtr, Pwm_Drvw_PowerStateType PowerState) { switch(HwCfgPtr->HwType) { case PWM_DRVW_HW_MCPWM: if (((void *)0) != HwCfgPtr->McpwmHwConfig) { if (PWM_DRVW_FULL_POWER == PowerState) { Mcpwm_Pwm_Drv_SetPowerState(HwCfgPtr->HwId,MCPWM_PWM_DRV_FULL_POWER); } else { Mcpwm_Pwm_Drv_SetPowerState(HwCfgPtr->HwId,MCPWM_PWM_DRV_LOW_POWER); } } break; case PWM_DRVW_HW_TIM: if (((void *)0) != HwCfgPtr->TimHwConfig) { if (PWM_DRVW_FULL_POWER == PowerState) { Tim_Pwm_Drv_SetPowerState(HwCfgPtr->HwId,TIM_PWM_DRV_FULL_POWER); } else { Tim_Pwm_Drv_SetPowerState(HwCfgPtr->HwId,TIM_PWM_DRV_LOW_POWER); } } break; case PWM_DRVW_HW_NONE: default: (void)PowerState; break; } } # 1599 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" uint32 Pwm_Drvw_GetMaxPeriodValue(const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { uint32 RetVal; switch(ChnConfigPtr->ChnHwType) { case PWM_DRVW_HW_MCPWM: RetVal = (uint32)65534U; break; case PWM_DRVW_HW_TIM: RetVal = (uint32)65534U; break; case PWM_DRVW_HW_NONE: default: RetVal = (uint32)65535U; break; } return RetVal; } # 1638 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" Std_ReturnType Pwm_Drvw_CheckDeadTimeMode(const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { Std_ReturnType RetVal = (Std_ReturnType)0x01U; if(PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { const Mcpwm_Pwm_Drv_PairChannelCfgType* McpwmPairCfg = ((const Mcpwm_Pwm_Drv_ChannelConfigType*) ChnConfigPtr->McpwmChConfig)->PairCfg; if(((void *)0) != McpwmPairCfg) { if((1U == McpwmPairCfg->DeadTimeEnable)) { RetVal = (Std_ReturnType)0x00U; } } } else if(PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { const Tim_Pwm_Drv_PairChannelCfgType* TimPairCfg = ((const Tim_Pwm_Drv_ChannelConfigType*) ChnConfigPtr->TimChConfig)->PairCfg; if(((void *)0) != TimPairCfg) { if((1U == TimPairCfg->DeadTimeEnable)) { RetVal = (Std_ReturnType)0x00U; } } } else { } return RetVal; } # 1692 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" Std_ReturnType Pwm_Drvw_CheckSetDutyPhaseShiftParams(uint16 PhaseShiftTicks, uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { Std_ReturnType RetVal = (Std_ReturnType)0x01U; uint8 ModuleId = ChnConfigPtr->ChnHwId; uint16 CnVValue = 0U; uint16 CurrentPeriod; uint16 DutyTicks; uint16 DutyCycle = 0x8000U - DutyCyclePu; if(PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { uint8 ChannelId = ChnConfigPtr->McpwmChConfig->ChannelId; CurrentPeriod = Mcpwm_Pwm_Drv_GetPeriod(ModuleId, ChannelId); DutyTicks = (uint16)((uint32)((uint32)CurrentPeriod * DutyCycle) / 0x8000U); if (((0x8000U)!= DutyCyclePu) && (0U != DutyCyclePu)) { CnVValue = PhaseShiftTicks + DutyTicks; if ((CnVValue > PhaseShiftTicks) && (CurrentPeriod > CnVValue)) { RetVal = (Std_ReturnType)0x00U; } } } else { CurrentPeriod = Tim_Pwm_Drv_GetPeriod(ModuleId); DutyTicks = (uint16)((uint32)((uint32)CurrentPeriod * DutyCycle) / 0x8000U); if (((0x8000U)!= DutyCyclePu) && (0U != DutyCyclePu)) { CnVValue = PhaseShiftTicks + DutyTicks; if ((CnVValue > PhaseShiftTicks) && (CurrentPeriod > CnVValue)) { RetVal = (Std_ReturnType)0x00U; } } } return RetVal; } # 1745 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" void Pwm_Drvw_InitIdleState(Pwm_Drvw_OutputStateType State, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr) { if(PWM_DRVW_HW_MCPWM == ChnConfigPtr->ChnHwType) { Pwm_Drvw_InitMcpwmIdleState(State, ChnConfigPtr); } else if(PWM_DRVW_HW_TIM == ChnConfigPtr->ChnHwType) { Pwm_Drvw_InitTimIdleState(State, ChnConfigPtr); } else { } } # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section text = "" # 1766 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm_Drvw.c" 2