# 1 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" # 1 "" 1 # 1 "" 3 # 387 "" 3 # 1 "" 1 # 1 "" 2 # 1 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" 2 # 25 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" # 1 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" 1 # 29 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" # 1 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Types.h" 1 # 30 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Types.h" # 1 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Drvw_Types.h" 1 # 29 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Drvw_Types.h" # 1 "../Generated/inc\\Pwm_Drvw_Cfg.h" 1 # 29 "../Generated/inc\\Pwm_Drvw_Cfg.h" # 1 "../Generated/inc/Pwm_Drvw_PBcfg.h" 1 # 30 "../Generated/inc\\Pwm_Drvw_Cfg.h" 2 # 30 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Drvw_Types.h" 2 # 1 "../../../mcal/Pwm_ZX_K14xM/Inc/Mcpwm_Pwm_Drv_Types.h" 1 # 29 "../../../mcal/Pwm_ZX_K14xM/Inc/Mcpwm_Pwm_Drv_Types.h" # 1 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 1 # 29 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" # 1 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 1 # 29 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 1 # 30 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h" 1 # 86 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h" typedef unsigned char boolean; typedef unsigned char uint8; typedef unsigned short uint16; typedef unsigned int uint32; typedef unsigned long long uint64; typedef signed char sint8; typedef signed short sint16; typedef signed int sint32; typedef signed long long sint64; typedef unsigned long uint8_least; typedef unsigned long uint16_least; typedef unsigned long uint32_least; typedef signed long sint8_least; typedef signed long sint16_least; typedef signed long sint32_least; typedef float float32; typedef double float64; typedef void *VoidPtr; typedef const void *ConstVoidPtr; # 31 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 1 # 31 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler_Cfg.h" 1 # 32 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 2 # 32 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2 # 63 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" typedef unsigned char StatusType; # 104 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" typedef uint8 Std_ReturnType; typedef uint8 Std_TransformerClass; typedef uint8 Std_TransformerForwardCode; typedef uint8 Std_MessageTypeType; typedef uint8 Std_MessageResultType; typedef struct { uint16 vendorID; uint16 moduleID; uint8 sw_major_version; uint8 sw_minor_version; uint8 sw_patch_version; } Std_VersionInfoType; typedef struct { uint8 errorCode; Std_TransformerClass transformerClass; } Std_TransformerError; typedef struct { Std_TransformerForwardCode errorCode; Std_TransformerClass transformerClass; } Std_TransformerForward; typedef Std_ReturnType (*Std_ExtractProtocolHeaderFieldsType)(const uint8 *buffer, uint32 bufferLength, Std_MessageTypeType *messageType, Std_MessageResultType *messageResult); # 30 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 2 # 1 "../Generated/inc\\McalLib_Cfg.h" 1 # 31 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 2 # 273 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" static inline uint32 McalLib_ReadControlReg(void) { uint32 res; __asm("MRS %0,CONTROL" : "=r" (res)); return res; } # 290 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" static inline uint32 McalLib_ReadIpsrReg(void) { uint32 res; __asm("MRS %0,IPSR" : "=r" (res)); return res; } # 305 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" static inline uint32 McalLib_ReadPriMaskReg(void) { uint32 res; __asm("MRS %0,PRIMASK" : "=r" (res)); return res; } # 30 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 # 184 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" typedef enum { MCALLIB_COUNTER_SOFTWARE, MCALLIB_COUNTER_OS, } McalLib_CounterType; typedef struct { uint32 CounterId; uint32 CounterFreq; } McalLib_ConfigType; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 211 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 extern const McalLib_ConfigType *const McalLib_PreDefinedConfigPtr[(1U)]; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section rodata = "" # 216 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 # 230 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" extern void Sys_SystemReset(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section text = ".mcal_code" # 234 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 void McalLib_Init(void); # 254 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" Std_ReturnType McalLib_GetCounterValue(McalLib_CounterType Counter, uint32 *Value); # 270 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" Std_ReturnType McalLib_GetElapsedValue(McalLib_CounterType Counter, uint32 *const CounterValue, uint32 *ElapsedValue); # 282 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" uint32 McalLib_MicroSecToTicks(McalLib_CounterType Counter, uint32 MicroSecond); # 296 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" void McalLib_SetCounterFreq(McalLib_CounterType Counter, uint32 Freq); # 309 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" static inline void McalLib_Assert(const uint8 *File, uint32 Line) { (void)File; (void)Line; for (;;) { } } # 327 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" void McalLib_SuspendAllInterrupts(void); void McalLib_ResumeAllInterrupts(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section text = "" # 339 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 # 30 "../../../mcal/Pwm_ZX_K14xM/Inc/Mcpwm_Pwm_Drv_Types.h" 2 # 1 "../Generated/inc\\Mcpwm_Pwm_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Mcpwm_Pwm_Drv_Cfg.h" # 1 "../Generated/inc/Mcpwm_Pwm_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Mcpwm_Pwm_Drv_Cfg.h" 2 # 31 "../../../mcal/Pwm_ZX_K14xM/Inc/Mcpwm_Pwm_Drv_Types.h" 2 # 108 "../../../mcal/Pwm_ZX_K14xM/Inc/Mcpwm_Pwm_Drv_Types.h" typedef enum { MCPWM_PWM_DRV_STATUS_SUCCESS = 0x00U, MCPWM_PWM_DRV_STATUS_ERROR = 0x01U, MCPWM_PWM_DRV_STATUS_BUSY = 0x002U, MCPWM_PWM_DRV_STATUS_TIMEOUT = 0x003U, MCPWM_PWM_DRV_STATUS_UNSUPPORTED = 0x004U } Mcpwm_Pwm_Drv_StatusType; typedef enum { MCPWM_PWM_DRV_CLK_DISABLE = 0U, MCPWM_PWM_DRV_CLK_SOURCE_SYSTEM = 1U, MCPWM_PWM_DRV_CLK_SOURCE_FUNCTION = 2U, MCPWM_PWM_DRV_CLK_SOURCE_EXTERNAL = 3U } Mcpwm_Pwm_Drv_ClkSourceType; typedef enum { MCPWM_PWM_DRV_CLK_DIVIDE_1 = 0U, MCPWM_PWM_DRV_CLK_DIVIDE_2, MCPWM_PWM_DRV_CLK_DIVIDE_4, MCPWM_PWM_DRV_CLK_DIVIDE_8, MCPWM_PWM_DRV_CLK_DIVIDE_16, MCPWM_PWM_DRV_CLK_DIVIDE_32, MCPWM_PWM_DRV_CLK_DIVIDE_64, MCPWM_PWM_DRV_CLK_DIVIDE_128 } Mcpwm_Pwm_Drv_ClkDivideType; typedef enum { MCPWM_PWM_DRV_COUNTING_UP = 0U, MCPWM_PWM_DRV_COUNTING_UP_AND_DOWN } Mcpwm_Pwm_Drv_CountingModeType; typedef enum { MCPWM_PWM_DRV_LOW_PULSE_POL = 0U, MCPWM_PWM_DRV_HIGH_PULSE_POL } Mcpwm_Pwm_Drv_PulsePolarityType; typedef enum { MCPWM_PWM_DRV_POL_HIGH = 0U, MCPWM_PWM_DRV_POL_LOW } Mcpwm_Pwm_Drv_PolarityType; typedef enum { MCPWM_PWM_DRV_SYMMETRIC = 0U, MCPWM_PWM_DRV_ASYMMETRIC } Mcpwm_Pwm_Drv_AsymType; typedef enum { MCPWM_PWM_DRV_CHANNEL_UNINIT = 0x00U, MCPWM_PWM_DRV_CHANNEL_RUNNING = 0x01U, MCPWM_PWM_DRV_CHANNEL_IDLE = 0x02U, MCPWM_PWM_DRV_CHANNEL_OUTPUT_FORCED = 0x03U } Mcpwm_Pwm_Drv_ChannelStateType; typedef enum { MCPWM_PWM_DRV_OUTPUT_STATE_LOW = 0x00U, MCPWM_PWM_DRV_OUTPUT_STATE_HIGH = 0x01U } Mcpwm_Pwm_Drv_OutputStateType; typedef enum { MCPWM_PWM_DRV_RISING_EDGE = 0U, MCPWM_PWM_DRV_FALLING_EDGE = 1U, MCPWM_PWM_DRV_BOTH_EDGES = 2U } Mcpwm_Pwm_Drv_EdgeNotifType; typedef enum { MCPWM_PWM_DRV_FULL_POWER = 0x00U, MCPWM_PWM_DRV_LOW_POWER = 0x01U, MCPWM_PWM_DRV_NODEFINE_POWER = 0x02U } Mcpwm_Pwm_Drv_PowerStateType; typedef enum { MCPWM_PWM_DRV_MODE_EDGE_ALIGNED = 0x01, MCPWM_PWM_DRV_MODE_CENTER_ALIGNED = 0x02, MCPWM_PWM_DRV_MODE_COMBINE_EDGE_ALIGNED = 0x03, MCPWM_PWM_DRV_MODE_COMBINE_SYM_CENTER_ALIGNED = 0x04, MCPWM_PWM_DRV_MODE_COMBINE_VARIABLE_EDGE_PLACEMENT = 0x06 } Mcpwm_Pwm_Drv_ChannelModeType; typedef uint8 Mcpwm_Pwm_Drv_EdgeInterruptType; typedef void (*Mcpwm_Pwm_Drv_CallbackType)(void); typedef struct { boolean DeadTimeEnable; uint16 PhaseShiftValue; } Mcpwm_Pwm_Drv_PairChannelCfgType; typedef struct { uint8 ChannelId; boolean ChIrqEn; Mcpwm_Pwm_Drv_CallbackType ChannelCb; boolean ChannelOutputEnable; Mcpwm_Pwm_Drv_PolarityType Polarity; Mcpwm_Pwm_Drv_ChannelModeType ChannelMode; uint8 ChannelDither; boolean ChannelMatchTrigEnable; boolean DmaEn; const Mcpwm_Pwm_Drv_PairChannelCfgType *PairCfg; } Mcpwm_Pwm_Drv_ChannelConfigType; typedef struct { uint8 CntId; uint16 PwmPeriod; uint16 PwmPeriodDither; uint16 DeadTimeVal; boolean OverflowIrqEn; Mcpwm_Pwm_Drv_CallbackType OverflowCb; } Mcpwm_Pwm_Drv_CounterType; typedef struct { Mcpwm_Pwm_Drv_ClkSourceType ClkSrc; Mcpwm_Pwm_Drv_ClkDivideType ClkDiv; # 303 "../../../mcal/Pwm_ZX_K14xM/Inc/Mcpwm_Pwm_Drv_Types.h" boolean GlobalCntEn; boolean InitTrigEn; uint8 CounterNum; const Mcpwm_Pwm_Drv_CounterType * const *CounterConfig; } Mcpwm_Pwm_Drv_ConfigType; typedef struct { const Mcpwm_Pwm_Drv_ConfigType *InstanceCfg; const Mcpwm_Pwm_Drv_ChannelConfigType * const *ConfiguredChArray; uint8 NoOfConfiguredCh; } Mcpwm_Pwm_Drv_UserCfgType; # 31 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Drvw_Types.h" 2 # 1 "../../../mcal/Pwm_ZX_K14xM/Inc/Tim_Pwm_Drv_Types.h" 1 # 30 "../../../mcal/Pwm_ZX_K14xM/Inc/Tim_Pwm_Drv_Types.h" # 1 "../Generated/inc\\Tim_Pwm_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Tim_Pwm_Drv_Cfg.h" # 1 "../Generated/inc/Tim_Pwm_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Tim_Pwm_Drv_Cfg.h" 2 # 31 "../../../mcal/Pwm_ZX_K14xM/Inc/Tim_Pwm_Drv_Types.h" 2 # 107 "../../../mcal/Pwm_ZX_K14xM/Inc/Tim_Pwm_Drv_Types.h" typedef enum { TIM_PWM_DRV_STATUS_SUCCESS = 0x00U, TIM_PWM_DRV_STATUS_ERROR = 0x01U, TIM_PWM_DRV_STATUS_BUSY = 0x002U, TIM_PWM_DRV_STATUS_TIMEOUT = 0x003U, TIM_PWM_DRV_STATUS_UNSUPPORTED = 0x004U } Tim_Pwm_Drv_StatusType; typedef enum { TIM_PWM_DRV_CLK_DISABLE = 0U, TIM_PWM_DRV_CLK_SOURCE_SYSTEM = 1U, TIM_PWM_DRV_CLK_SOURCE_FUNCTION = 2U, TIM_PWM_DRV_CLK_SOURCE_EXTERNAL = 3U } Tim_Pwm_Drv_ClkSourceType; typedef enum { TIM_PWM_DRV_CLK_DIVIDE_1 = 0U, TIM_PWM_DRV_CLK_DIVIDE_2, TIM_PWM_DRV_CLK_DIVIDE_4, TIM_PWM_DRV_CLK_DIVIDE_8, TIM_PWM_DRV_CLK_DIVIDE_16, TIM_PWM_DRV_CLK_DIVIDE_32, TIM_PWM_DRV_CLK_DIVIDE_64, TIM_PWM_DRV_CLK_DIVIDE_128 } Tim_Pwm_Drv_ClkDivideType; typedef enum { TIM_PWM_DRV_COUNTING_UP = 0U, TIM_PWM_DRV_COUNTING_UP_AND_DOWN } Tim_Pwm_Drv_CountingModeType; typedef enum { TIM_PWM_DRV_LOW_PULSE_POL = 1U, TIM_PWM_DRV_HIGH_PULSE_POL } Tim_Pwm_Drv_PulsePolarityType; typedef enum { TIM_PWM_DRV_POL_HIGH = 0U, TIM_PWM_DRV_POL_LOW } Tim_Pwm_Drv_PolarityType; typedef enum { TIM_PWM_DRV_CHANNEL_UNINIT = 0x00U, TIM_PWM_DRV_CHANNEL_RUNNING = 0x01U, TIM_PWM_DRV_CHANNEL_IDLE = 0x02U, TIM_PWM_DRV_CHANNEL_OUTPUT_FORCED = 0x03U } Tim_Pwm_Drv_ChannelStateType; typedef enum { TIM_PWM_DRV_OUTPUT_STATE_LOW = 0x00U, TIM_PWM_DRV_OUTPUT_STATE_HIGH = 0x01U } Tim_Pwm_Drv_OutputStateType; typedef enum { TIM_PWM_DRV_RISING_EDGE = 0U, TIM_PWM_DRV_FALLING_EDGE = 1U, TIM_PWM_DRV_BOTH_EDGES = 2U } Tim_Pwm_Drv_EdgeNotifType; typedef enum { TIM_PWM_DRV_FULL_POWER = 0x00U, TIM_PWM_DRV_LOW_POWER = 0x01U, TIM_PWM_DRV_NODEFINE_POWER = 0x02U } Tim_Pwm_Drv_PowerStateType; typedef enum { TIM_PWM_DRV_MODE_EDGE_ALIGNED = 0x01U, TIM_PWM_DRV_MODE_CENTER_ALIGNED = 0x02U, TIM_PWM_DRV_MODE_COMBINE_VARIABLE_EDGE_PLACEMENT = 0x03U } Tim_Pwm_Drv_ChannelModeType; typedef enum { TIM_PWM_DRV_CLK_DEADTIME_DIVIDE_1 = 0x01U, TIM_PWM_DRV_CLK_DEADTIME_DIVIDE_4 = 0x02U, TIM_PWM_DRV_CLK_DEADTIME_DIVIDE_16 = 0x03U } Tim_Pwm_Drv_DeadTimeDivider; typedef uint8 Tim_Pwm_Drv_EdgeInterruptType; typedef void (*Tim_Pwm_Drv_CallbackType)(void); typedef struct { boolean DeadTimeEnable; uint16 PhaseShiftValue; } Tim_Pwm_Drv_PairChannelCfgType; typedef struct { uint8 ChannelId; boolean ChIrqEn; Tim_Pwm_Drv_CallbackType ChannelCb; boolean ChannelOutputEnable; Tim_Pwm_Drv_PolarityType Polarity; Tim_Pwm_Drv_ChannelModeType ChannelMode; boolean ChannelMatchTrigEnable; boolean DmaEn; const Tim_Pwm_Drv_PairChannelCfgType *PairCfg; } Tim_Pwm_Drv_ChannelConfigType; typedef struct { Tim_Pwm_Drv_ClkSourceType ClkSrc; Tim_Pwm_Drv_ClkDivideType ClkDiv; # 290 "../../../mcal/Pwm_ZX_K14xM/Inc/Tim_Pwm_Drv_Types.h" uint16 PwmPeriod; Tim_Pwm_Drv_CountingModeType PwmCounterMode; Tim_Pwm_Drv_DeadTimeDivider DeadTimeDiv; uint16 DeadTimeVal; boolean InitTrigEn; boolean OverflowIrqEn; Tim_Pwm_Drv_CallbackType OverflowCb; } Tim_Pwm_Drv_ConfigType; typedef struct { const Tim_Pwm_Drv_ConfigType *InstanceCfg; const Tim_Pwm_Drv_ChannelConfigType * const *ConfiguredChArray; uint8 NoOfConfiguredCh; } Tim_Pwm_Drv_UserCfgType; # 32 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Drvw_Types.h" 2 # 104 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Drvw_Types.h" typedef uint8 Pwm_Drvw_ModuleType; typedef enum { PWM_DRVW_HW_NONE = 0x00U, PWM_DRVW_HW_MCPWM = 0x01U, PWM_DRVW_HW_TIM = 0x02U } Pwm_Drvw_HwType; typedef enum { PWM_DRVW_LOW = 0x00U, PWM_DRVW_HIGH } Pwm_Drvw_OutputStateType; typedef uint16 Pwm_Drvw_PeriodType; typedef enum { PWM_DRVW_RISING_EDGE = 0U, PWM_DRVW_FALLING_EDGE, PWM_DRVW_BOTH_EDGE } Pwm_Drvw_EdgeNotificationType; typedef enum { PWM_DRVW_FULL_POWER = 0x00U, PWM_DRVW_LOW_POWER, PWM_DRVW_NODEFINE_POWER } Pwm_Drvw_PowerStateType; typedef struct { const Pwm_Drvw_ModuleType ChnHwId; const Pwm_Drvw_HwType ChnHwType; const uint16 ChannelDutyCycle; const Mcpwm_Pwm_Drv_ChannelConfigType * McpwmChConfig; const Tim_Pwm_Drv_ChannelConfigType * TimChConfig; } Pwm_Drvw_ChannelConfigType; typedef struct { uint8 HwId; const Pwm_Drvw_HwType HwType; const Mcpwm_Pwm_Drv_UserCfgType * McpwmHwConfig; const Tim_Pwm_Drv_UserCfgType * TimHwConfig; } Pwm_Drvw_HwConfigType; # 31 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Types.h" 2 # 1 "../Generated/inc\\Pwm_Cfg.h" 1 # 32 "../Generated/inc\\Pwm_Cfg.h" # 1 "../Generated/inc/Pwm_PBcfg.h" 1 # 52 "../Generated/inc/Pwm_PBcfg.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 53 "../Generated/inc/Pwm_PBcfg.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section rodata = "" # 57 "../Generated/inc/Pwm_PBcfg.h" 2 # 33 "../Generated/inc\\Pwm_Cfg.h" 2 # 32 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Types.h" 2 # 90 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Types.h" typedef uint8 Pwm_ChannelType; typedef uint8 Pwm_HwNumType; typedef Pwm_Drvw_PeriodType Pwm_PeriodType; typedef enum { PWM_LOW = 0x00U, PWM_HIGH } Pwm_OutputStateType; typedef enum { PWM_RISING_EDGE = 0U, PWM_FALLING_EDGE, PWM_BOTH_EDGE } Pwm_EdgeNotificationType; typedef enum { PWM_VARIABLE_PERIOD = 0x00U, PWM_FIXED_PERIOD, PWM_FIXED_PERIOD_SHIFTED } Pwm_ChannelClassType; typedef void (*Pwm_NotifyType)(void); typedef struct { const Pwm_ChannelType ChannelId; const Pwm_ChannelClassType PwmChnClass; const Pwm_Drvw_ChannelConfigType * DrvwChannelCfg; const Pwm_OutputStateType ChannelIdleState; const Pwm_NotifyType PwmChannelNotificationPtr; } Pwm_ChannelConfigType; typedef struct { const Pwm_ChannelType NumChannels; const Pwm_ChannelConfigType (*PwmChannelConfigs)[]; const Pwm_HwNumType NumModules; const Pwm_Drvw_HwConfigType (*PwmHwConfig)[]; } Pwm_ConfigType; typedef enum { PWM_SERVICE_ACCEPTED = 0x00U, PWM_NOT_INIT, PWM_SEQUENCE_ERROR, PWM_HW_FAILURE, PWM_POWER_STATE_NOT_SUPP, PWM_TRANS_NOT_POSSIBLE } Pwm_PowerStateRequestResultType; typedef enum { PWM_FULL_POWER = 0x00U, PWM_LOW_POWER, PWM_NODEFINE_POWER } Pwm_PowerStateType; typedef enum { PWM_STATE_UNINIT = 0x00U, PWM_STATE_IDLE = 0x01U } Pwm_GlobalStateType; typedef struct { Pwm_GlobalStateType PwmGlobalState; Pwm_PowerStateType PwmCurrentPowerState; Pwm_PowerStateType PwmTargetPowerState; } Pwm_DriverStateType; # 30 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" 2 # 320 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 848 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 321 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" 2 extern const Pwm_ConfigType * const Pwm_PreDefinedConfigPtr[(1U)]; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 864 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section rodata = "" # 324 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" 2 # 337 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section text = ".mcal_code" # 338 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" 2 # 350 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_Init(const Pwm_ConfigType * ConfigPtr); # 360 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_DeInit(void); # 372 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_SetDutyCycle(Pwm_ChannelType ChannelNumber, uint16 DutyCycle); # 385 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_SetPeriodAndDuty(Pwm_ChannelType ChannelNumber, Pwm_PeriodType Period, uint16 DutyCycle); # 398 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_SetOutputToIdle(Pwm_ChannelType ChannelNumber); # 411 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" Pwm_OutputStateType Pwm_GetOutputState(Pwm_ChannelType ChannelNumber); # 422 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_DisableNotification(Pwm_ChannelType ChannelNumber); # 435 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_EnableNotification(Pwm_ChannelType ChannelNumber, Pwm_EdgeNotificationType Notification); # 446 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_GetVersionInfo(Std_VersionInfoType * versioninfo); # 461 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" uint16 Pwm_GetChannelDutyCycle(Pwm_ChannelType ChannelNumber); # 473 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_ForceOutputToLowLevel(Pwm_ChannelType ChannelNumber, boolean ForceEnable); # 485 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_SetChannelDeadTimeTicks(Pwm_ChannelType ChannelNumber, uint16 DeadTimeTicks); # 501 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_WriteDutyCycleToBuffer(Pwm_ChannelType ChannelNumber, uint16 DutyCycle); # 517 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_WritePeriodAndDutyToBuffer(Pwm_ChannelType ChannelNumber, Pwm_PeriodType Period, uint16 DutyCycle); # 536 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_WritePhaseShiftTicksToBuffer(Pwm_ChannelType ChannelNumber, Pwm_PeriodType Period, uint16 PhaseShiftTicks); # 548 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_SyncUpdate(uint8 ModuleId); # 562 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_SetPhaseShiftTicks(Pwm_ChannelType ChannelNumber, Pwm_PeriodType Period, uint16 PhaseShiftTicks); # 580 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_SetDutyPhaseShiftTicks(Pwm_ChannelType ChannelNumber, uint16 DutyCycle, uint16 PhaseShiftTicks, boolean SyncUpdate); # 594 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_EnableTriggerOutput(uint8 ModuleId, uint16 TriggerMask); # 606 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_DisableTriggerOutput(uint8 ModuleId, uint16 TriggerMask); # 618 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_MaskOutputs(uint8 ModuleId, uint8 ChannelMask); # 628 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" void Pwm_UnMaskOutputs(uint8 ModuleId, uint8 ChannelMask); # 648 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" Std_ReturnType Pwm_SetPowerState(Pwm_PowerStateRequestResultType * Result); # 663 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" Std_ReturnType Pwm_GetCurrentPowerState(Pwm_PowerStateType * CurrentPowerState, Pwm_PowerStateRequestResultType * Result); # 679 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" Std_ReturnType Pwm_GetTargetPowerState(Pwm_PowerStateType * TargetPowerState, Pwm_PowerStateRequestResultType * Result); # 701 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" Std_ReturnType Pwm_PreparePowerState(Pwm_PowerStateType PowerState, Pwm_PowerStateRequestResultType * Result); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section text = "" # 707 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm.h" 2 # 26 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" 2 # 1 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" 1 # 67 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 68 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" 2 extern const Pwm_Drvw_HwConfigType Pwm_Instances[((uint8)4U)]; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch0_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch1_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch2_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch3_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch4_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch9_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch10_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch11_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch12_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch5_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch6_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch7_Config; extern const Pwm_Drvw_ChannelConfigType Pwm_Drvw_Ch8_Config; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section rodata = "" # 75 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section text = ".mcal_code" # 79 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" 2 # 91 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_Init(const Pwm_Drvw_HwConfigType * const HwCfgPtr); # 101 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_SetDefaultDutyCycle(uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 112 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_SyncDefaultDutyCycle(uint8 ModuleId, Pwm_Drvw_HwType HwType); # 121 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_StartInstance(const Pwm_Drvw_HwConfigType * const HwCfgPtr); # 131 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_InitIdleState(Pwm_Drvw_OutputStateType State, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 142 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_DeInit(const Pwm_Drvw_HwConfigType * const HwCfgPtr); # 157 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Std_ReturnType Pwm_Drvw_SetDutyCycle(uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 174 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Std_ReturnType Pwm_Drvw_SetPeriodAndDuty(Pwm_Drvw_PeriodType Period, uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 187 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_SetOutputToIdle(const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 201 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Pwm_Drvw_OutputStateType Pwm_Drvw_GetOutputState( const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 214 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_DisableNotification(const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 225 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_EnableNotification(Pwm_Drvw_EdgeNotificationType Notification, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 240 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Std_ReturnType Pwm_Drvw_CheckEdgeNotificationType(Pwm_Drvw_EdgeNotificationType Notification, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 253 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" uint16 Pwm_Drvw_GetChannelDutyCycle(const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 266 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_ForceOutputToLowLevel(boolean Force, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 282 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Std_ReturnType Pwm_Drvw_SetChannelDeadTimeTicks(uint16 DeadTimeTicks, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 300 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Std_ReturnType Pwm_Drvw_WriteDutyCycleToBuffer(uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 317 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Std_ReturnType Pwm_Drvw_WritePeriodAndDutyToBuffer(Pwm_Drvw_PeriodType Period, uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 333 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_WritePhaseShiftTicksToBuffer(uint16 Period, uint16 PhaseShiftTicks, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 347 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_SyncUpdate(const Pwm_Drvw_HwConfigType * HwCfgPtr); # 362 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_SetPhaseShiftTicks(uint16 Period, uint16 PhaseShiftTicks, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 380 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_SetDutyPhaseShiftTicks(uint16 DutyCyclePu, uint16 PhaseShiftTicks, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr, boolean SyncUpdate); # 396 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_EnableTriggerOutput(uint16 TrigMask, const Pwm_Drvw_HwConfigType * const HwCfgPtr); # 411 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_DisableTriggerOutput(uint16 TrigMask, const Pwm_Drvw_HwConfigType * const HwCfgPtr); # 425 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_MaskOutputs(uint8 ChannelMask, const Pwm_Drvw_HwConfigType * const HwCfgPtr); # 437 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_UnMaskOutputs(uint8 ChannelMask, const Pwm_Drvw_HwConfigType * const HwCfgPtr); # 450 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Std_ReturnType Pwm_Drvw_CheckIdleState(const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 462 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" void Pwm_Drvw_SetPowerState(const Pwm_Drvw_HwConfigType * const HwCfgPtr, Pwm_Drvw_PowerStateType PowerState); # 479 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" uint32 Pwm_Drvw_GetMaxPeriodValue(const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 495 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Std_ReturnType Pwm_Drvw_CheckDeadTimeMode(const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 512 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" Std_ReturnType Pwm_Drvw_CheckSetDutyPhaseShiftParams(uint16 PhaseShiftTicks, uint16 DutyCyclePu, const Pwm_Drvw_ChannelConfigType * const ChnConfigPtr); # 522 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section text = "" # 523 "../../../mcal/Pwm_ZX_K14xM/Inc\\Pwm_Drvw.h" 2 # 27 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" 2 # 1 "../../../mcal/Det_ZX_K14xM/Inc\\Det.h" 1 # 61 "../../../mcal/Det_ZX_K14xM/Inc\\Det.h" void Det_Init(void); Std_ReturnType Det_ReportError(uint16 ModuleId, uint8 InstanceId, uint8 ApiId, uint8 ErrorId); Std_ReturnType Det_ReportRuntimeError(uint16 ModuleId, uint8 InstanceId, uint8 ApiId, uint8 ErrorId); Std_ReturnType Det_ReportTransientFault(uint16 ModuleId, uint8 InstanceId, uint8 ApiId, uint8 FaultId); void Det_Start(void); # 30 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" 2 # 184 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1240 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section data = ".mcal_data" # 185 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" 2 static const Pwm_ConfigType * Pwm_ConfigPtr[(1U)] = {((void *)0)}; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1256 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section data = "" # 190 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1436 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section bss = ".mcal_bss" # 193 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" 2 static Pwm_DriverStateType Pwm_DrvState[(1U)]; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1452 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section bss = "" # 198 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section text = ".mcal_code" # 205 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" 2 static inline Std_ReturnType Pwm_CheckParamsPeriodClass(Pwm_ChannelType ChannelNumber, Pwm_ChannelClassType ChannelClass, Pwm_PeriodType Period, uint8 ServiceId); # 251 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" static Std_ReturnType Pwm_CheckHwInitCall(uint32 CoreId, uint8 ServiceId) { Std_ReturnType RetVal; if (PWM_STATE_UNINIT == Pwm_DrvState[CoreId].PwmGlobalState) { (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)(ServiceId),(uint8)(0x11U));; RetVal = (Std_ReturnType)0x01U; } else { RetVal = (Std_ReturnType)0x00U; } return RetVal; } # 279 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" static Std_ReturnType Pwm_CheckChnParamCall(Pwm_ChannelType ChannelNumber, uint8 ServiceId) { Std_ReturnType RetVal; if ((13U) <= ChannelNumber) { (void)Det_ReportError((uint16) 121U, (uint8)(0U), (uint8)(ServiceId), (uint8)(0x12U));; RetVal = (Std_ReturnType)0x01U; } else { RetVal = (Std_ReturnType)0x00U; } return RetVal; } # 306 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" static Std_ReturnType Pwm_CheckChnCfgCall(Pwm_ChannelType ChannelNumber, uint8 ServiceId) { Std_ReturnType RetVal; uint32 CoreId = (uint32)0U; if (ChannelNumber >= Pwm_ConfigPtr[CoreId]->NumChannels) { RetVal = (Std_ReturnType)0x01U; (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)(ServiceId), (uint8)(0x40U));; } else { RetVal = (Std_ReturnType)0x00U; } return RetVal; } # 335 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" static Std_ReturnType Pwm_CheckChnCfgStruct(Pwm_ChannelType ChannelNumber, uint8 ServiceId) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; const Pwm_Drvw_ChannelConfigType * DrvwChnCfgPtr = (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].DrvwChannelCfg; if(PWM_DRVW_HW_MCPWM == DrvwChnCfgPtr->ChnHwType) { if (((void *)0) == DrvwChnCfgPtr->McpwmChConfig) { RetVal = (Std_ReturnType)0x01U; (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)(ServiceId), (uint8)(0x34U));; } } else if(PWM_DRVW_HW_TIM == DrvwChnCfgPtr->ChnHwType) { if (((void *)0) == DrvwChnCfgPtr->TimChConfig) { RetVal = (Std_ReturnType)0x01U; (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)(ServiceId), (uint8)(0x34U));; } } else { RetVal = (Std_ReturnType)0x01U; (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)(ServiceId), (uint8)(0x34U));; } return RetVal; } # 378 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" static Std_ReturnType Pwm_CheckModuleCfgStruct(uint8 ModuleId, uint8 ServiceId) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; const Pwm_Drvw_HwConfigType * DrvwHwCfgPtr = &((*(Pwm_ConfigPtr[CoreId]->PwmHwConfig))[ModuleId]); if(PWM_DRVW_HW_MCPWM == DrvwHwCfgPtr->HwType) { if (((void *)0) == DrvwHwCfgPtr->McpwmHwConfig) { RetVal = (Std_ReturnType)0x01U; (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)(ServiceId), (uint8)(0x35U));; } } else if(PWM_DRVW_HW_TIM == DrvwHwCfgPtr->HwType) { if (((void *)0) == DrvwHwCfgPtr->TimHwConfig) { RetVal = (Std_ReturnType)0x01U; (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)(ServiceId), (uint8)(0x35U));; } } else { RetVal = (Std_ReturnType)0x01U; (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)(ServiceId), (uint8)(0x35U));; } return RetVal; } # 420 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" static Std_ReturnType Pwm_CheckPwmCfgStruct(uint8 ServiceId) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; uint8 Index; for(Index = 0U; Index < Pwm_ConfigPtr[CoreId]->NumChannels; Index++) { RetVal = Pwm_CheckChnCfgStruct(Index, ServiceId); if((Std_ReturnType)0x01U == RetVal) { break; } } if((Std_ReturnType)0x00U == RetVal) { for (Index = 0U; Index < Pwm_ConfigPtr[CoreId]->NumModules; Index++) { RetVal = Pwm_CheckModuleCfgStruct(Index, ServiceId); if((Std_ReturnType)0x01U == RetVal) { break; } } } return RetVal; } # 461 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" static Std_ReturnType Pwm_CheckHwAndChannel(Pwm_ChannelType ChannelNumber, uint8 ServiceId) { Std_ReturnType RetVal; uint32 CoreId = (uint32)0U; RetVal = Pwm_CheckHwInitCall(CoreId, ServiceId); if((Std_ReturnType)0x00U == RetVal) { RetVal = Pwm_CheckChnParamCall(ChannelNumber, ServiceId); if((Std_ReturnType)0x00U == RetVal) { RetVal = Pwm_CheckChnCfgCall(ChannelNumber, ServiceId); if((Std_ReturnType)0x00U == RetVal) { RetVal = Pwm_CheckChnCfgStruct(ChannelNumber, ServiceId); } } } return RetVal; } # 494 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" static Std_ReturnType Pwm_CheckInit(const Pwm_ConfigType * ConfigPtr, uint8 ServiceId) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; if (PWM_STATE_UNINIT != Pwm_DrvState[CoreId].PwmGlobalState) { RetVal = (Std_ReturnType)0x01U; (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)(ServiceId), (uint8)(0x14U));; } else { if (((void *)0) != ConfigPtr) { RetVal = (Std_ReturnType)0x01U; (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)(ServiceId), (uint8)(0x10U));; } else { Pwm_ConfigPtr[CoreId] = Pwm_PreDefinedConfigPtr[CoreId]; (void)ConfigPtr; RetVal = Pwm_CheckPwmCfgStruct(ServiceId); } } return RetVal; } # 544 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" static Std_ReturnType Pwm_CheckSetPowerState(Pwm_PowerStateRequestResultType * Result, uint8 ServiceId) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; if (PWM_STATE_UNINIT == Pwm_DrvState[CoreId].PwmGlobalState) { *Result = PWM_NOT_INIT; RetVal = (Std_ReturnType)0x01U; (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)(ServiceId),(uint8)(0x11U));; } else { RetVal = Pwm_CheckPwmCfgStruct(ServiceId); } return RetVal; } # 584 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" static inline Std_ReturnType Pwm_CheckParamsPeriodClass(Pwm_ChannelType ChannelNumber, Pwm_ChannelClassType ChannelClass, Pwm_PeriodType Period, uint8 ServiceId) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 PeriodMaxValue = (uint32)0U; uint32 CoreId = (uint32)0U; const Pwm_Drvw_ChannelConfigType * DrvwChnCfgPtr = (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].DrvwChannelCfg; if (PWM_VARIABLE_PERIOD == ChannelClass) { PeriodMaxValue = (uint32)Pwm_Drvw_GetMaxPeriodValue(DrvwChnCfgPtr); if ((uint32)Period > PeriodMaxValue) { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)(ServiceId), (uint8)(0x1AU));; RetVal = (Std_ReturnType)0x01U; } else { } } else { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)(ServiceId), (uint8)(0x13U));; RetVal = (Std_ReturnType)0x01U; } return RetVal; } # 639 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" static Std_ReturnType Pwm_CheckNotificationCallback(Pwm_NotifyType Callback, uint8 ServiceId) { Std_ReturnType RetVal; if (Callback == ((void *)0)) { RetVal = (Std_ReturnType)0x01U; (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)(ServiceId), (uint8)(0x31U));; } else { RetVal = (Std_ReturnType)0x00U; } return RetVal; } # 673 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_Init(const Pwm_ConfigType * ConfigPtr) { uint8 Index; uint32 CoreId = (uint32)0U; const Pwm_Drvw_ChannelConfigType * DrvwChnCfgPtr = ((void *)0); Pwm_OutputStateType State; Std_ReturnType RetVal = Pwm_CheckInit(ConfigPtr, (0x00U)); if ((Std_ReturnType)0x00U == RetVal) { # 693 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" for(Index = 0; Index < Pwm_ConfigPtr[CoreId]->NumChannels; Index++) { DrvwChnCfgPtr = (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[Index].DrvwChannelCfg; State = (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[Index].ChannelIdleState; if(PWM_LOW == State) { Pwm_Drvw_InitIdleState(PWM_DRVW_LOW, DrvwChnCfgPtr); } else if (PWM_HIGH == State) { Pwm_Drvw_InitIdleState(PWM_DRVW_HIGH, DrvwChnCfgPtr); } else { } } for (Index = 0; Index < Pwm_ConfigPtr[CoreId]->NumModules; Index++) { Pwm_Drvw_Init(&((*(Pwm_ConfigPtr[CoreId]->PwmHwConfig))[Index])); } for(Index = 0; Index < Pwm_ConfigPtr[CoreId]->NumChannels; Index++) { DrvwChnCfgPtr = (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[Index].DrvwChannelCfg; Pwm_Drvw_SetDefaultDutyCycle(DrvwChnCfgPtr->ChannelDutyCycle, DrvwChnCfgPtr); } for(Index = 0; Index < Pwm_ConfigPtr[CoreId]->NumModules; Index++) { Pwm_Drvw_SyncDefaultDutyCycle((*(Pwm_ConfigPtr[CoreId]->PwmHwConfig))[Index].HwId,(*(Pwm_ConfigPtr[CoreId]->PwmHwConfig))[Index].HwType); Pwm_Drvw_StartInstance(&((*(Pwm_ConfigPtr[CoreId]->PwmHwConfig))[Index])); } Pwm_DrvState[CoreId].PwmCurrentPowerState = PWM_FULL_POWER; Pwm_DrvState[CoreId].PwmTargetPowerState = PWM_NODEFINE_POWER; Pwm_DrvState[CoreId].PwmGlobalState = PWM_STATE_IDLE; } } # 746 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_DeInit(void) { uint8 Index; uint32 CoreId = (uint32)0U; const Pwm_Drvw_ChannelConfigType * DrvwChnCfgPtr = ((void *)0); Std_ReturnType RetVal = (Std_ReturnType)0x00U; if (PWM_STATE_UNINIT == Pwm_DrvState[CoreId].PwmGlobalState) { (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)((0x01U)),(uint8)(0x11U));; } else { RetVal = Pwm_CheckPwmCfgStruct((0x01U)); if ((Std_ReturnType)0x00U == RetVal) { for(Index = 0; Index < Pwm_ConfigPtr[CoreId]->NumChannels; Index++) { DrvwChnCfgPtr = (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[Index].DrvwChannelCfg; Pwm_Drvw_SetOutputToIdle(DrvwChnCfgPtr); } for (Index = 0; Index < Pwm_ConfigPtr[CoreId]->NumModules; Index++) { Pwm_Drvw_DeInit(&((*Pwm_ConfigPtr[CoreId]->PwmHwConfig)[Index])); } Pwm_ConfigPtr[CoreId] = ((void *)0); Pwm_DrvState[CoreId].PwmCurrentPowerState = PWM_NODEFINE_POWER; Pwm_DrvState[CoreId].PwmTargetPowerState = PWM_NODEFINE_POWER; Pwm_DrvState[CoreId].PwmGlobalState = PWM_STATE_UNINIT; } } } # 802 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_SetDutyCycle(Pwm_ChannelType ChannelNumber, uint16 DutyCycle) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; const Pwm_Drvw_ChannelConfigType * DrvwChnCfgPtr = ((void *)0); RetVal = Pwm_CheckHwAndChannel(ChannelNumber,(0x02U)); if ((Std_ReturnType)0x00U == RetVal) { if (DutyCycle <= ((uint16)0x8000U)) { DrvwChnCfgPtr = (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].DrvwChannelCfg; RetVal = Pwm_Drvw_SetDutyCycle(DutyCycle, DrvwChnCfgPtr); (void)RetVal; if ((Std_ReturnType)0x00U != RetVal) { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x02U)), (uint8)(0x32U));; } } else { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x02U)), (uint8)(0x32U));; } } } # 846 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_SetPeriodAndDuty(Pwm_ChannelType ChannelNumber, Pwm_PeriodType Period, uint16 DutyCycle) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; const Pwm_Drvw_ChannelConfigType * DrvwChnCfgPtr = ((void *)0); RetVal = Pwm_CheckHwAndChannel(ChannelNumber,(0x03U)); if ((Std_ReturnType)0x00U == RetVal) { if ((Std_ReturnType)0x00U == Pwm_CheckParamsPeriodClass(ChannelNumber, (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].PwmChnClass, Period,(0x03U))) { if (DutyCycle <= ((uint16)0x8000U)) { DrvwChnCfgPtr = (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].DrvwChannelCfg; RetVal = Pwm_Drvw_SetPeriodAndDuty(Period, DutyCycle, DrvwChnCfgPtr); (void)RetVal; if ((Std_ReturnType)0x00U != RetVal) { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x03U)), (uint8)(0x32U));; } } else { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x03U)), (uint8)(0x32U));; } } } } # 896 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_SetOutputToIdle(Pwm_ChannelType ChannelNumber) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; const Pwm_Drvw_ChannelConfigType * DrvwChnCfgPtr = ((void *)0); RetVal = Pwm_CheckHwAndChannel(ChannelNumber,(0x04U)); if ((Std_ReturnType)0x00U == RetVal) { DrvwChnCfgPtr = (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].DrvwChannelCfg; Pwm_Drvw_SetOutputToIdle(DrvwChnCfgPtr); (void)RetVal; } } # 932 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" Pwm_OutputStateType Pwm_GetOutputState(Pwm_ChannelType ChannelNumber) { Std_ReturnType CheckRetVal = (Std_ReturnType)0x00U; Pwm_OutputStateType RetVal = PWM_LOW; uint32 CoreId = (uint32)0U; const Pwm_Drvw_ChannelConfigType * DrvwChnCfgPtr = (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].DrvwChannelCfg; CheckRetVal = Pwm_CheckHwAndChannel(ChannelNumber,(0x05U)); if ((Std_ReturnType)0x00U == CheckRetVal) { if(PWM_DRVW_HIGH == Pwm_Drvw_GetOutputState(DrvwChnCfgPtr)) { RetVal = PWM_HIGH; } else { RetVal = PWM_LOW; } (void)CheckRetVal; } return RetVal; } # 974 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_DisableNotification(Pwm_ChannelType ChannelNumber) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; const Pwm_Drvw_ChannelConfigType * DrvwChnCfgPtr = (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].DrvwChannelCfg; RetVal = Pwm_CheckHwAndChannel(ChannelNumber,(0x06U)); if ((Std_ReturnType)0x00U == RetVal) { Pwm_Drvw_DisableNotification(DrvwChnCfgPtr); (void)RetVal; } } # 1009 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_EnableNotification(Pwm_ChannelType ChannelNumber, Pwm_EdgeNotificationType Notification) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; Pwm_Drvw_EdgeNotificationType PwmDrvwNotification = PWM_DRVW_RISING_EDGE; uint32 CoreId = (uint32)0U; const Pwm_Drvw_ChannelConfigType * DrvwChnCfgPtr = (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].DrvwChannelCfg; if(PWM_RISING_EDGE == Notification) { PwmDrvwNotification = PWM_DRVW_RISING_EDGE; } else if(PWM_FALLING_EDGE == Notification) { PwmDrvwNotification = PWM_DRVW_FALLING_EDGE; } else { PwmDrvwNotification = PWM_DRVW_BOTH_EDGE; } RetVal = Pwm_CheckHwAndChannel(ChannelNumber,(0x07U)); if ((Std_ReturnType)0x00U == RetVal) { RetVal = Pwm_CheckNotificationCallback( (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].PwmChannelNotificationPtr, (0x07U)); if((Std_ReturnType)0x00U == RetVal) { RetVal = Pwm_Drvw_CheckEdgeNotificationType(PwmDrvwNotification,DrvwChnCfgPtr); if ((Std_ReturnType)0x00U != RetVal) { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x07U)), (uint8)(0x30U));; } else { Pwm_Drvw_EnableNotification(PwmDrvwNotification,DrvwChnCfgPtr); (void)RetVal; } } } } # 1068 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_GetVersionInfo(Std_VersionInfoType * versioninfo) { if (((void *)0) == versioninfo) { (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)((0x08U)),(uint8)(0x15U));; } else { (versioninfo)->vendorID = (uint16)0x00B3U; (versioninfo)->moduleID = (uint16)121U; (versioninfo)->sw_major_version = (uint8)1U; (versioninfo)->sw_minor_version = (uint8)2U; (versioninfo)->sw_patch_version = (uint8)0U; } } # 1100 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" uint16 Pwm_GetChannelDutyCycle(Pwm_ChannelType ChannelNumber) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint16 DutyCycle = (uint16)0U; uint32 CoreId = (uint32)0U; const Pwm_Drvw_ChannelConfigType * DrvwChnCfgPtr = ((void *)0); RetVal = Pwm_CheckHwAndChannel(ChannelNumber,(0x20U)); if ((Std_ReturnType)0x00U == RetVal) { DrvwChnCfgPtr = (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].DrvwChannelCfg; DutyCycle = Pwm_Drvw_GetChannelDutyCycle(DrvwChnCfgPtr); (void)RetVal; } if(DutyCycle > ((uint16)0x8000U)) { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x20U)), (uint8)(0x32U));; } return DutyCycle; } # 1140 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_ForceOutputToLowLevel(Pwm_ChannelType ChannelNumber, boolean ForceEnable) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; const Pwm_Drvw_ChannelConfigType * DrvwChnCfgPtr = (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].DrvwChannelCfg; RetVal = Pwm_CheckHwAndChannel(ChannelNumber, (0x21U)); if ((Std_ReturnType)0x00U == RetVal) { Pwm_Drvw_ForceOutputToLowLevel(ForceEnable,DrvwChnCfgPtr); (void)RetVal; } } # 1173 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_SetChannelDeadTimeTicks(Pwm_ChannelType ChannelNumber, uint16 DeadTimeTicks) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; const Pwm_Drvw_ChannelConfigType * DrvwChnCfgPtr = (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].DrvwChannelCfg; RetVal = Pwm_CheckHwAndChannel(ChannelNumber,(0x2BU)); if ((Std_ReturnType)0x00U == RetVal) { RetVal = Pwm_Drvw_CheckDeadTimeMode(DrvwChnCfgPtr); if ((Std_ReturnType)0x00U != RetVal) { (void)Det_ReportError((uint16) 121U, (uint8)(0U), (uint8)((0x2BU)), (uint8)(0x12U));; } else { RetVal = Pwm_Drvw_SetChannelDeadTimeTicks(DeadTimeTicks, (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].DrvwChannelCfg); (void)RetVal; (void)DrvwChnCfgPtr; if((Std_ReturnType)0x00U != RetVal) { (void)Det_ReportRuntimeError((uint16)121U,(uint8)(0U), (uint8)(0x2BU),(uint8)(0x41U)); } } } } # 1224 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_WriteDutyCycleToBuffer(Pwm_ChannelType ChannelNumber, uint16 DutyCycle) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; const Pwm_Drvw_ChannelConfigType * DrvwChnCfgPtr = ((void *)0); RetVal = Pwm_CheckHwAndChannel(ChannelNumber,(0x2AU)); if ((Std_ReturnType)0x00U == RetVal) { DrvwChnCfgPtr = (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].DrvwChannelCfg; if (DutyCycle <= ((uint16)0x8000U)) { RetVal = Pwm_Drvw_WriteDutyCycleToBuffer(DutyCycle, DrvwChnCfgPtr); (void)RetVal; if ((Std_ReturnType)0x00U != RetVal) { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x2AU)), (uint8)(0x32U));; } } else { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x2AU)), (uint8)(0x32U));; } } } # 1274 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_WritePeriodAndDutyToBuffer(Pwm_ChannelType ChannelNumber, Pwm_PeriodType Period, uint16 DutyCycle) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; const Pwm_Drvw_ChannelConfigType * DrvwChnCfgPtr = ((void *)0); RetVal = Pwm_CheckHwAndChannel(ChannelNumber, (0x29U)); if ((Std_ReturnType)0x00U == RetVal) { DrvwChnCfgPtr = (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].DrvwChannelCfg; if ((Std_ReturnType)0x00U == Pwm_CheckParamsPeriodClass( ChannelNumber, (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].PwmChnClass, Period, (0x29U))) { if (DutyCycle > ((uint16)0x8000U)) { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x29U)), (uint8)(0x32U));; } else { RetVal = Pwm_Drvw_WritePeriodAndDutyToBuffer(Period, DutyCycle, DrvwChnCfgPtr); (void)RetVal; if ((Std_ReturnType)0x00U != RetVal) { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x29U)), (uint8)(0x32U));; } } } } } # 1332 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_WritePhaseShiftTicksToBuffer(Pwm_ChannelType ChannelNumber, Pwm_PeriodType Period, uint16 PhaseShiftTicks) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; RetVal = Pwm_CheckHwAndChannel(ChannelNumber, (0x2DU)); if ((Std_ReturnType)0x00U == RetVal) { if ((Std_ReturnType)0x00U == Pwm_CheckParamsPeriodClass(ChannelNumber, (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].PwmChnClass, Period,(0x2DU))) { if ((PhaseShiftTicks > (Period / 2U)) || (PhaseShiftTicks == 0U)) { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x2DU)), (uint8)(0x3AU));; } else { Pwm_Drvw_WritePhaseShiftTicksToBuffer(Period, PhaseShiftTicks, (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].DrvwChannelCfg); (void)RetVal; } } } } # 1376 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_SyncUpdate(uint8 ModuleId) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; if (PWM_STATE_UNINIT == Pwm_DrvState[CoreId].PwmGlobalState) { (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)((0x28U)),(uint8)(0x11U));; } else { if ((4U) > ModuleId) { RetVal = Pwm_CheckModuleCfgStruct(ModuleId, (0x28U)); if((Std_ReturnType)0x00U == RetVal) { Pwm_Drvw_SyncUpdate(&((*(Pwm_ConfigPtr[CoreId]->PwmHwConfig))[ModuleId])); (void)RetVal; } } else { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x28U)), (uint8)(0x36U));; } } } # 1419 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_SetPhaseShiftTicks(Pwm_ChannelType ChannelNumber, Pwm_PeriodType Period, uint16 PhaseShiftTicks) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; RetVal = Pwm_CheckHwAndChannel(ChannelNumber, (0x2CU)); if ((Std_ReturnType)0x00U == RetVal) { if ((Std_ReturnType)0x00U == Pwm_CheckParamsPeriodClass(ChannelNumber, (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].PwmChnClass, Period,(0x2CU))) { if ((PhaseShiftTicks > (Period / 2U)) || (PhaseShiftTicks == 0U)) { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x2CU)), (uint8)(0x3AU));; } else { Pwm_Drvw_SetPhaseShiftTicks(Period, PhaseShiftTicks, (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].DrvwChannelCfg); (void)RetVal; } } } } # 1467 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_SetDutyPhaseShiftTicks(Pwm_ChannelType ChannelNumber, uint16 DutyCycle, uint16 PhaseShiftTicks, boolean SyncUpdate) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; const Pwm_Drvw_ChannelConfigType * DrvwChnCfgPtr = ((void *)0); RetVal = Pwm_CheckHwAndChannel(ChannelNumber, (0x37U)); if ((Std_ReturnType)0x00U == RetVal) { DrvwChnCfgPtr = (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[ChannelNumber].DrvwChannelCfg; if (DutyCycle <= ((uint16)0x8000U)) { RetVal = Pwm_Drvw_CheckSetDutyPhaseShiftParams(PhaseShiftTicks,DutyCycle, DrvwChnCfgPtr); if((Std_ReturnType)0x00U != RetVal) { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x37U)), (uint8)(0x3AU));; } else { Pwm_Drvw_SetDutyPhaseShiftTicks(DutyCycle,PhaseShiftTicks,DrvwChnCfgPtr, SyncUpdate); (void)RetVal; } } else { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x37U)), (uint8)(0x32U));; } } } # 1523 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_EnableTriggerOutput(uint8 ModuleId, uint16 TriggerMask) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; if (PWM_STATE_UNINIT == Pwm_DrvState[CoreId].PwmGlobalState) { (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)((0x2EU)),(uint8)(0x11U));; } else { if ((4U) > ModuleId) { RetVal = Pwm_CheckModuleCfgStruct(ModuleId, (0x2EU)); if((Std_ReturnType)0x00U == RetVal) { if ((TriggerMask & ((uint32)(0x1FF))) != 0U) { Pwm_Drvw_EnableTriggerOutput(TriggerMask, &((*(Pwm_ConfigPtr[CoreId]->PwmHwConfig))[ModuleId])); (void)RetVal; } else { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x2EU)), (uint8)(0x3DU));; } } } else { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x2EU)), (uint8)(0x36U));; } } } # 1574 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_DisableTriggerOutput(uint8 ModuleId, uint16 TriggerMask) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; if (PWM_STATE_UNINIT == Pwm_DrvState[CoreId].PwmGlobalState) { (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)((0x2FU)),(uint8)(0x11U));; } else { if ((4U) > ModuleId) { RetVal = Pwm_CheckModuleCfgStruct(ModuleId, (0x2FU)); if((Std_ReturnType)0x00U == RetVal) { if ((TriggerMask & ((uint32)(0x1FF))) != 0U) { Pwm_Drvw_DisableTriggerOutput(TriggerMask, &((*(Pwm_ConfigPtr[CoreId]->PwmHwConfig))[ModuleId])); (void)RetVal; } else { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x2FU)), (uint8)(0x3DU));; } } } else { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x2FU)), (uint8)(0x36U));; } } } # 1625 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_MaskOutputs(uint8 ModuleId, uint8 ChannelMask) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; if (PWM_STATE_UNINIT == Pwm_DrvState[CoreId].PwmGlobalState) { (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)((0x32U)),(uint8)(0x11U));; } else { if ((4U) > ModuleId) { RetVal = Pwm_CheckModuleCfgStruct(ModuleId, (0x32U)); if((Std_ReturnType)0x00U == RetVal) { Pwm_Drvw_MaskOutputs(ChannelMask, &((*(Pwm_ConfigPtr[CoreId]->PwmHwConfig))[ModuleId])); (void)RetVal; } } else { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x32U)), (uint8)(0x36U));; } } } # 1666 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" void Pwm_UnMaskOutputs(uint8 ModuleId, uint8 ChannelMask) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; if (PWM_STATE_UNINIT == Pwm_DrvState[CoreId].PwmGlobalState) { (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)((0x33U)),(uint8)(0x11U));; } else { if ((4U) > ModuleId) { RetVal = Pwm_CheckModuleCfgStruct(ModuleId, (0x33U)); if((Std_ReturnType)0x00U == RetVal) { Pwm_Drvw_UnMaskOutputs(ChannelMask, &((*(Pwm_ConfigPtr[CoreId]->PwmHwConfig))[ModuleId])); (void)RetVal; } } else { (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x33U)), (uint8)(0x36U));; } } } # 1718 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" Std_ReturnType Pwm_SetPowerState(Pwm_PowerStateRequestResultType * Result) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; uint8 Index; Pwm_Drvw_PowerStateType PwmDrvwPowerState = (Pwm_Drvw_PowerStateType)Pwm_DrvState[CoreId].PwmTargetPowerState; if (((void *)0) != Result) { RetVal = Pwm_CheckSetPowerState(Result, (0x09U)); if((Std_ReturnType)0x00U == RetVal) { if (Pwm_DrvState[CoreId].PwmCurrentPowerState == Pwm_DrvState[CoreId].PwmTargetPowerState) { *Result = PWM_SERVICE_ACCEPTED; } else { switch(Pwm_DrvState[CoreId].PwmTargetPowerState) { case PWM_NODEFINE_POWER: *Result = PWM_SEQUENCE_ERROR; RetVal = (Std_ReturnType)0x01U; (void)Det_ReportError((uint16)121U, (uint8)(0U), (uint8)((0x09U)), (uint8)(0x19U));; break; case PWM_LOW_POWER: case PWM_FULL_POWER: for(Index = 0; Index < Pwm_ConfigPtr[CoreId]->NumChannels; Index++) { RetVal = Pwm_Drvw_CheckIdleState( (*(Pwm_ConfigPtr[CoreId]->PwmChannelConfigs))[Index].DrvwChannelCfg); if (RetVal == (Std_ReturnType)0x01U) { break; } } if((Std_ReturnType)0x00U == RetVal) { for (Index = 0; Index < Pwm_ConfigPtr[CoreId]->NumModules; Index++) { Pwm_Drvw_SetPowerState( &((*(Pwm_ConfigPtr[CoreId]->PwmHwConfig))[Index]), PwmDrvwPowerState); } *Result = PWM_SERVICE_ACCEPTED; Pwm_DrvState[CoreId].PwmCurrentPowerState = Pwm_DrvState[CoreId].PwmTargetPowerState; Pwm_DrvState[CoreId].PwmTargetPowerState = PWM_NODEFINE_POWER; } else { *Result = PWM_HW_FAILURE; (void)Det_ReportRuntimeError((uint16)121U,(uint8)(0U), (uint8)(0x09U),(uint8)(0x16U)); } break; default: *Result = PWM_POWER_STATE_NOT_SUPP; RetVal = (Std_ReturnType)0x01U; (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)((0x09U)),(uint8)(0x17U));; break; } } } } else { (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)((0x09U)),(uint8)(0x15U));; RetVal = (Std_ReturnType)0x01U; } return RetVal; } # 1823 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" Std_ReturnType Pwm_GetCurrentPowerState(Pwm_PowerStateType * CurrentPowerState, Pwm_PowerStateRequestResultType * Result) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; if ((((void *)0) != Result) && (((void *)0) != CurrentPowerState)) { if (PWM_STATE_UNINIT == Pwm_DrvState[CoreId].PwmGlobalState) { (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)((0x0AU)),(uint8)(0x11U));; *Result = PWM_NOT_INIT; RetVal = (Std_ReturnType)0x01U; } else { *CurrentPowerState = Pwm_DrvState[CoreId].PwmCurrentPowerState; *Result = PWM_SERVICE_ACCEPTED; } } else { RetVal = (Std_ReturnType)0x01U; (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)((0x0AU)),(uint8)(0x15U));; } return RetVal; } # 1875 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" Std_ReturnType Pwm_GetTargetPowerState(Pwm_PowerStateType * TargetPowerState, Pwm_PowerStateRequestResultType * Result) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; if ((((void *)0) != Result) && (((void *)0) != TargetPowerState)) { if (PWM_STATE_UNINIT == Pwm_DrvState[CoreId].PwmGlobalState) { (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)((0x0BU)),(uint8)(0x11U));; *Result = PWM_NOT_INIT; RetVal = (Std_ReturnType)0x01U; } else { *TargetPowerState = Pwm_DrvState[CoreId].PwmTargetPowerState; *Result = PWM_SERVICE_ACCEPTED; } } else { RetVal = (Std_ReturnType)0x01U; (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)((0x0BU)),(uint8)(0x15U));; } return RetVal; } # 1933 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" Std_ReturnType Pwm_PreparePowerState(Pwm_PowerStateType PowerState, Pwm_PowerStateRequestResultType * Result) { Std_ReturnType RetVal = (Std_ReturnType)0x00U; uint32 CoreId = (uint32)0U; if (((void *)0) != Result) { if (PWM_STATE_UNINIT == Pwm_DrvState[CoreId].PwmGlobalState) { (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)((0x0CU)),(uint8)(0x11U));; *Result = PWM_NOT_INIT; RetVal = (Std_ReturnType)0x01U; } else { if ( Pwm_DrvState[CoreId].PwmCurrentPowerState != PowerState) { if ((PWM_LOW_POWER != PowerState) && (PWM_FULL_POWER != PowerState)) { (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)((0x0CU)),(uint8)(0x17U));; *Result = PWM_POWER_STATE_NOT_SUPP; RetVal = (Std_ReturnType)0x01U; } else { *Result = PWM_SERVICE_ACCEPTED; Pwm_DrvState[CoreId].PwmTargetPowerState = PowerState; } } else { *Result = PWM_SEQUENCE_ERROR; RetVal = (Std_ReturnType)0x01U; } } } else { RetVal = (Std_ReturnType)0x01U; (void)Det_ReportError((uint16)121U,(uint8)(0U), (uint8)((0x0CU)),(uint8)(0x15U));; } return RetVal; } # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section text = "" # 1993 "../../../mcal/Pwm_ZX_K14xM/Src/Pwm.c" 2