# 1 "../Generated/Src/Port_Drvw_PBcfg.c" # 1 "" 1 # 1 "" 3 # 387 "" 3 # 1 "" 1 # 1 "" 2 # 1 "../Generated/Src/Port_Drvw_PBcfg.c" 2 # 27 "../Generated/Src/Port_Drvw_PBcfg.c" # 1 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drvw.h" 1 # 29 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drvw.h" # 1 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drvw_Types.h" 1 # 30 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drvw_Types.h" # 1 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drv_Types.h" 1 # 30 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drv_Types.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 1 # 30 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h" 1 # 86 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h" typedef unsigned char boolean; typedef unsigned char uint8; typedef unsigned short uint16; typedef unsigned int uint32; typedef unsigned long long uint64; typedef signed char sint8; typedef signed short sint16; typedef signed int sint32; typedef signed long long sint64; typedef unsigned long uint8_least; typedef unsigned long uint16_least; typedef unsigned long uint32_least; typedef signed long sint8_least; typedef signed long sint16_least; typedef signed long sint32_least; typedef float float32; typedef double float64; typedef void *VoidPtr; typedef const void *ConstVoidPtr; # 31 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 1 # 31 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler_Cfg.h" 1 # 32 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 2 # 32 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2 # 63 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" typedef unsigned char StatusType; # 104 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" typedef uint8 Std_ReturnType; typedef uint8 Std_TransformerClass; typedef uint8 Std_TransformerForwardCode; typedef uint8 Std_MessageTypeType; typedef uint8 Std_MessageResultType; typedef struct { uint16 vendorID; uint16 moduleID; uint8 sw_major_version; uint8 sw_minor_version; uint8 sw_patch_version; } Std_VersionInfoType; typedef struct { uint8 errorCode; Std_TransformerClass transformerClass; } Std_TransformerError; typedef struct { Std_TransformerForwardCode errorCode; Std_TransformerClass transformerClass; } Std_TransformerForward; typedef Std_ReturnType (*Std_ExtractProtocolHeaderFieldsType)(const uint8 *buffer, uint32 bufferLength, Std_MessageTypeType *messageType, Std_MessageResultType *messageResult); # 31 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drv_Types.h" 2 # 1 "../Generated/inc\\Port_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Port_Drv_Cfg.h" # 1 "../Generated/inc/Port_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Port_Drv_Cfg.h" 2 # 68 "../Generated/inc\\Port_Drv_Cfg.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 33 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" # 1 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib_Compiler.h" 1 # 30 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib_Compiler.h" # 1 "../Generated/inc\\McalLib_Cfg.h" 1 # 31 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib_Compiler.h" 2 # 273 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib_Compiler.h" static inline uint32 McalLib_ReadControlReg(void) { uint32 res; __asm("MRS %0,CONTROL" : "=r" (res)); return res; } # 290 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib_Compiler.h" static inline uint32 McalLib_ReadIpsrReg(void) { uint32 res; __asm("MRS %0,IPSR" : "=r" (res)); return res; } # 305 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib_Compiler.h" static inline uint32 McalLib_ReadPriMaskReg(void) { uint32 res; __asm("MRS %0,PRIMASK" : "=r" (res)); return res; } # 34 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 2 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 69 "../Generated/inc\\Port_Drv_Cfg.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section rodata = "" # 78 "../Generated/inc\\Port_Drv_Cfg.h" 2 # 32 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drv_Types.h" 2 # 77 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drv_Types.h" typedef enum { PORT_DRV_PULL_DISABLED = 0U, PORT_DRV_PULL_DOWN = 2U, PORT_DRV_PULL_UP = 3U, } Port_Drv_PullConfigType; typedef enum { PORT_DRV_PIN_MODE_ALT0 = 0U, PORT_DRV_PIN_MODE_GPIO = 1U, PORT_DRV_PIN_MODE_ALT2 = 2U, PORT_DRV_PIN_MODE_ALT3 = 3U, PORT_DRV_PIN_MODE_ALT4 = 4U, PORT_DRV_PIN_MODE_ALT5 = 5U, PORT_DRV_PIN_MODE_ALT6 = 6U, PORT_DRV_PIN_MODE_ALT7 = 7U } Port_Drv_PortMuxType; typedef enum { PORT_DRV_PIN_IN = 0U, PORT_DRV_PIN_OUT = 1U, } Port_Drv_DirectionType; typedef enum { PORT_DRV_PORT_A = 0U, PORT_DRV_PORT_B, PORT_DRV_PORT_C, PORT_DRV_PORT_D, PORT_DRV_PORT_E } Port_Drv_PortIdType; typedef enum { PORT_DRV_FAST_RATE = 0U, PORT_DRV_SLOW_RATE } Port_Drv_SlewRateType; typedef enum { PORT_DRV_LEVEL_LOW = 0U, PORT_DRV_LEVEL_HIGH } Port_Drv_GpioLvlType; typedef enum { PORT_DRV_GPIO_0 = 0U, PORT_DRV_GPIO_1, PORT_DRV_GPIO_2, PORT_DRV_GPIO_3, PORT_DRV_GPIO_4, PORT_DRV_GPIO_5, PORT_DRV_GPIO_6, PORT_DRV_GPIO_7, PORT_DRV_GPIO_8, PORT_DRV_GPIO_9, PORT_DRV_GPIO_10, PORT_DRV_GPIO_11, PORT_DRV_GPIO_12, PORT_DRV_GPIO_13, PORT_DRV_GPIO_14, PORT_DRV_GPIO_15, PORT_DRV_GPIO_16, PORT_DRV_GPIO_17, PORT_DRV_GPIO_18, PORT_DRV_GPIO_19, PORT_DRV_GPIO_20, PORT_DRV_GPIO_21, PORT_DRV_GPIO_22, PORT_DRV_GPIO_23, PORT_DRV_GPIO_24, PORT_DRV_GPIO_25, PORT_DRV_GPIO_26, PORT_DRV_GPIO_27, PORT_DRV_GPIO_28, PORT_DRV_GPIO_29, PORT_DRV_GPIO_30, PORT_DRV_GPIO_31 } Port_Drv_GpioNoType; typedef struct { Port_Drv_PortIdType PortId; Port_Drv_GpioNoType GpioNo; Port_Drv_PullConfigType PullConfig; Port_Drv_PortMuxType PinMode; Port_Drv_DirectionType Direction; Port_Drv_SlewRateType SlewRate; boolean PassiveFilter; boolean FilterEnable; uint8 FilterConfig; boolean OpenDrainConfig; Port_Drv_GpioLvlType InitValue; } Port_Drv_ConfigType; # 31 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drvw_Types.h" 2 # 1 "../Generated/inc\\Port_Drvw_Cfg.h" 1 # 31 "../Generated/inc\\Port_Drvw_Cfg.h" # 1 "../Generated/inc/Port_Drvw_PBcfg.h" 1 # 32 "../Generated/inc\\Port_Drvw_Cfg.h" 2 # 82 "../Generated/inc\\Port_Drvw_Cfg.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 83 "../Generated/inc\\Port_Drvw_Cfg.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section rodata = "" # 89 "../Generated/inc\\Port_Drvw_Cfg.h" 2 # 32 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drvw_Types.h" 2 # 77 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drvw_Types.h" typedef uint32 Port_Drvw_PinType; typedef uint8 Port_Drvw_PinModeType; # 97 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drvw_Types.h" typedef enum { PORT_DRVW_PORT_A = 0U, PORT_DRVW_PORT_B, PORT_DRVW_PORT_C, PORT_DRVW_PORT_D, PORT_DRVW_PORT_E } Port_Drvw_PortIdType; typedef enum { PORT_DRVW_GPIO_0 = 0U, PORT_DRVW_GPIO_1, PORT_DRVW_GPIO_2, PORT_DRVW_GPIO_3, PORT_DRVW_GPIO_4, PORT_DRVW_GPIO_5, PORT_DRVW_GPIO_6, PORT_DRVW_GPIO_7, PORT_DRVW_GPIO_8, PORT_DRVW_GPIO_9, PORT_DRVW_GPIO_10, PORT_DRVW_GPIO_11, PORT_DRVW_GPIO_12, PORT_DRVW_GPIO_13, PORT_DRVW_GPIO_14, PORT_DRVW_GPIO_15, PORT_DRVW_GPIO_16, PORT_DRVW_GPIO_17, PORT_DRVW_GPIO_18, PORT_DRVW_GPIO_19, PORT_DRVW_GPIO_20, PORT_DRVW_GPIO_21, PORT_DRVW_GPIO_22, PORT_DRVW_GPIO_23, PORT_DRVW_GPIO_24, PORT_DRVW_GPIO_25, PORT_DRVW_GPIO_26, PORT_DRVW_GPIO_27, PORT_DRVW_GPIO_28, PORT_DRVW_GPIO_29, PORT_DRVW_GPIO_30, PORT_DRVW_GPIO_31 } Port_Drvw_GpioNoType; typedef enum { PORT_DRVW_PIN_IN = 0U, PORT_DRVW_PIN_OUT, } Port_Drvw_DirectionType; typedef enum { PORT_DRVW_LEVEL_LOW = 0U, PORT_DRVW_LEVEL_HIGH } Port_Drvw_GpioLvlType; typedef enum { PORT_DRVW_FAST_RATE = 0U, PORT_DRVW_SLOW_RATE } Port_Drvw_SlewRateType; typedef enum { PORT_DRVW_PULL_DISABLED = 0U, PORT_DRVW_PULL_DOWN = 2U, PORT_DRVW_PULL_UP = 3U, } Port_Drvw_PullConfigType; typedef struct { Port_Drvw_DirectionType PinDirection; uint8 PinOutputLevel; Port_Drvw_SlewRateType PinSlewRate; Port_Drvw_PullConfigType PinPullConfig; } Port_Drvw_UnconfigPinAttrType; typedef struct { uint16 Pin; uint8 PinOutputLevel; Port_Drvw_DirectionType PinDirection; boolean GPIO; boolean DirectionChangebility; boolean ModeChangebility; } Port_Drvw_ConfigPinAttrType; typedef struct { uint16 NumConfigPins; uint16 NumUnconfigPins; const uint16 *UnconfigPinList; const Port_Drvw_UnconfigPinAttrType *UnconfigPinConfigAttr; const Port_Drvw_ConfigPinAttrType *ConfigPinAttr; const Port_Drv_ConfigType *DrvConfigPtr; } Port_Drvw_ConfigType; # 30 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drvw.h" 2 # 79 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drvw.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 80 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drvw.h" 2 extern const Port_Drvw_ConfigType Port_DrvwConfig; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section rodata = "" # 87 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drvw.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section text = ".mcal_code" # 95 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drvw.h" 2 void Port_Drvw_Init(const Port_Drvw_ConfigType *DrvwConfigPtr); # 118 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drvw.h" Std_ReturnType Port_Drvw_CheckPinDirectionChangeable(Port_Drvw_PinType PinIndex, const Port_Drvw_ConfigType *DrvwConfigPtr); # 133 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drvw.h" Std_ReturnType Port_Drvw_CheckPinModeChangeable(Port_Drvw_PinType PinIndex, const Port_Drvw_ConfigType *DrvwConfigPtr); # 149 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drvw.h" void Port_Drvw_SetPinDirection(Port_Drvw_PinType PinIndex, Port_Drvw_DirectionType Direction, const Port_Drvw_ConfigType *DrvwConfigPtr); # 164 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drvw.h" void Port_Drvw_SetPinMode(Port_Drvw_PinType PinIndex, Port_Drvw_PinModeType PinMode, const Port_Drvw_ConfigType *DrvwConfigPtr); # 175 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drvw.h" void Port_Drvw_RefreshPortDirection(const Port_Drvw_ConfigType *DrvwConfigPtr); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section text = "" # 179 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drvw.h" 2 # 28 "../Generated/Src/Port_Drvw_PBcfg.c" 2 # 1 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drv.h" 1 # 72 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drv.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 73 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drv.h" 2 extern const Port_Drv_ConfigType Port_DrvConfig[70]; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section rodata = "" # 80 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drv.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section text = ".mcal_code" # 89 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drv.h" 2 # 99 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drv.h" void Port_Drv_SetPinOutput(Port_Drv_PortIdType PortId, Port_Drv_GpioNoType GpioNo); # 110 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drv.h" void Port_Drv_ClearPinOutput(Port_Drv_PortIdType PortId, Port_Drv_GpioNoType GpioNo); # 122 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drv.h" void Port_Drv_SetPinDirection(Port_Drv_PortIdType PortId, Port_Drv_GpioNoType GpioNo, Port_Drv_DirectionType Direction); # 133 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drv.h" void Port_Drv_Init(uint32 PinCount, const Port_Drv_ConfigType Config[]); # 145 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drv.h" void Port_Drv_SetPinMode(Port_Drv_PortIdType PortId, Port_Drv_GpioNoType GpioNo, Port_Drv_PortMuxType PinMode); # 158 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drv.h" void Port_Drv_SetSlewRate(Port_Drv_PortIdType PortId, Port_Drv_GpioNoType GpioNo, Port_Drv_SlewRateType SlewRateConfig); # 171 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drv.h" void Port_Drv_SetPullConfig(Port_Drv_PortIdType PortId, Port_Drv_GpioNoType GpioNo, Port_Drv_PullConfigType PullConfig); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section text = "" # 176 "../../../mcal/Port_ZX_K14xM/Inc\\Port_Drv.h" 2 # 29 "../Generated/Src/Port_Drvw_PBcfg.c" 2 # 93 "../Generated/Src/Port_Drvw_PBcfg.c" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 94 "../Generated/Src/Port_Drvw_PBcfg.c" 2 static const Port_Drvw_UnconfigPinAttrType Port_DrvwUnconfigPinAttr = { PORT_DRVW_PIN_OUT, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_SLOW_RATE, PORT_DRVW_PULL_DISABLED }; static const Port_Drvw_ConfigPinAttrType Port_DrvwConfigPinAttr[((uint16)70)]= { {(uint16)144, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)143, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)97, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)96, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)141, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)75, (uint8)PORT_DRVW_LEVEL_HIGH, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)43, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)42, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)40, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)108, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)106, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)77, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)76, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)66, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)65, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)64, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)81, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)80, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)79, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)78, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)35, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)34, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)33, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)7, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)45, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)44, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)100, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)99, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)98, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)3, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)2, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)1, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)71, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)0, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)70, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)16, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)15, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)134, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)13, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)12, (uint8)PORT_DRVW_LEVEL_HIGH, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)131, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)74, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)135, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)17, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)41, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)11, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)10, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)69, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)9, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)8, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)103, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)102, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)101, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)107, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)37, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)32, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)130, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)129, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)128, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)6, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)49, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)48, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)47, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)46, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)140, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)113, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)110, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_OUT, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)109, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)0U, (boolean)0U, (boolean)1U}, {(uint16)142, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)1U, (boolean)1U, (boolean)1U}, {(uint16)73, (uint8)PORT_DRVW_LEVEL_LOW, PORT_DRVW_PIN_IN, (boolean)1U, (boolean)1U, (boolean)1U} }; static const uint16 Port_DrvwUnconfigPinList[(16U)]= { (uint16)4, (uint16)5, (uint16)14, (uint16)36, (uint16)38, (uint16)39, (uint16)67, (uint16)68, (uint16)72, (uint16)104, (uint16)105, (uint16)111, (uint16)112, (uint16)136, (uint16)137, (uint16)139 }; const Port_Drvw_ConfigType Port_DrvwConfig = { ((uint16)70), (16U), Port_DrvwUnconfigPinList, &Port_DrvwUnconfigPinAttr, Port_DrvwConfigPinAttr, Port_DrvConfig, }; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section rodata = "" # 296 "../Generated/Src/Port_Drvw_PBcfg.c" 2