# 1 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" # 1 "" 1 # 1 "" 3 # 387 "" 3 # 1 "" 1 # 1 "" 2 # 1 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 # 26 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" # 1 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" 1 # 29 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" # 1 "../../../mcal/Fls_ZX_K14xM/Inc/Flash_Drv_Types.h" 1 # 29 "../../../mcal/Fls_ZX_K14xM/Inc/Flash_Drv_Types.h" # 1 "../Generated/inc\\Flash_Drv_Cfg.h" 1 # 30 "../../../mcal/Fls_ZX_K14xM/Inc/Flash_Drv_Types.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 1 # 30 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h" 1 # 86 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h" typedef unsigned char boolean; typedef unsigned char uint8; typedef unsigned short uint16; typedef unsigned int uint32; typedef unsigned long long uint64; typedef signed char sint8; typedef signed short sint16; typedef signed int sint32; typedef signed long long sint64; typedef unsigned long uint8_least; typedef unsigned long uint16_least; typedef unsigned long uint32_least; typedef signed long sint8_least; typedef signed long sint16_least; typedef signed long sint32_least; typedef float float32; typedef double float64; typedef void *VoidPtr; typedef const void *ConstVoidPtr; # 31 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 1 # 31 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler_Cfg.h" 1 # 32 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 2 # 32 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2 # 63 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" typedef unsigned char StatusType; # 104 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" typedef uint8 Std_ReturnType; typedef uint8 Std_TransformerClass; typedef uint8 Std_TransformerForwardCode; typedef uint8 Std_MessageTypeType; typedef uint8 Std_MessageResultType; typedef struct { uint16 vendorID; uint16 moduleID; uint8 sw_major_version; uint8 sw_minor_version; uint8 sw_patch_version; } Std_VersionInfoType; typedef struct { uint8 errorCode; Std_TransformerClass transformerClass; } Std_TransformerError; typedef struct { Std_TransformerForwardCode errorCode; Std_TransformerClass transformerClass; } Std_TransformerForward; typedef Std_ReturnType (*Std_ExtractProtocolHeaderFieldsType)(const uint8 *buffer, uint32 bufferLength, Std_MessageTypeType *messageType, Std_MessageResultType *messageResult); # 31 "../../../mcal/Fls_ZX_K14xM/Inc/Flash_Drv_Types.h" 2 # 1 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 1 # 29 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" # 1 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 1 # 30 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" # 1 "../Generated/inc\\McalLib_Cfg.h" 1 # 31 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 2 # 273 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" static inline uint32 McalLib_ReadControlReg(void) { uint32 res; __asm("MRS %0,CONTROL" : "=r" (res)); return res; } # 290 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" static inline uint32 McalLib_ReadIpsrReg(void) { uint32 res; __asm("MRS %0,IPSR" : "=r" (res)); return res; } # 305 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" static inline uint32 McalLib_ReadPriMaskReg(void) { uint32 res; __asm("MRS %0,PRIMASK" : "=r" (res)); return res; } # 30 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 # 184 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" typedef enum { MCALLIB_COUNTER_SOFTWARE, MCALLIB_COUNTER_OS, } McalLib_CounterType; typedef struct { uint32 CounterId; uint32 CounterFreq; } McalLib_ConfigType; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 211 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 extern const McalLib_ConfigType *const McalLib_PreDefinedConfigPtr[(1U)]; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section rodata = "" # 216 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 # 230 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" extern void Sys_SystemReset(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section text = ".mcal_code" # 234 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 void McalLib_Init(void); # 254 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" Std_ReturnType McalLib_GetCounterValue(McalLib_CounterType Counter, uint32 *Value); # 270 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" Std_ReturnType McalLib_GetElapsedValue(McalLib_CounterType Counter, uint32 *const CounterValue, uint32 *ElapsedValue); # 282 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" uint32 McalLib_MicroSecToTicks(McalLib_CounterType Counter, uint32 MicroSecond); # 296 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" void McalLib_SetCounterFreq(McalLib_CounterType Counter, uint32 Freq); # 309 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" static inline void McalLib_Assert(const uint8 *File, uint32 Line) { (void)File; (void)Line; for (;;) { } } # 327 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" void McalLib_SuspendAllInterrupts(void); void McalLib_ResumeAllInterrupts(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section text = "" # 339 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 # 32 "../../../mcal/Fls_ZX_K14xM/Inc/Flash_Drv_Types.h" 2 # 1 "../../../mcal/MemIf_ZX_K14xM/Inc\\MemIf.h" 1 # 46 "../../../mcal/MemIf_ZX_K14xM/Inc\\MemIf.h" typedef enum { MEMIF_UNINIT = 0U, MEMIF_IDLE, MEMIF_BUSY, MEMIF_BUSY_INTERNAL }MemIf_StatusType; typedef enum { MEMIF_JOB_OK = 0U, MEMIF_JOB_FAILED, MEMIF_JOB_PENDING, MEMIF_JOB_CANCELED, MEMIF_BLOCK_INCONSISTENT, MEMIF_BLOCK_INVALID }MemIf_JobResultType; typedef enum { MEMIF_MODE_SLOW = 0U, MEMIF_MODE_FAST }MemIf_ModeType; # 33 "../../../mcal/Fls_ZX_K14xM/Inc/Flash_Drv_Types.h" 2 # 87 "../../../mcal/Fls_ZX_K14xM/Inc/Flash_Drv_Types.h" typedef void (*Flash_Drv_StartAccessNotifType)(void); typedef void (*Flash_Drv_FinishAccessNotifType)(void); typedef void (*Flash_Drv_AcPtrType)(void (*CallBack)(void)); typedef void (*Flash_Drv_CallBackType)(void); typedef enum { FLASH_DRV_SUCCESS = 0U, FLASH_DRV_BUSY = 1U, FLASH_DRV_CMD_ABORTED = 2U, FLASH_DRV_ERR = 3U, FLASH_DRV_ERR_TIMEOUT = 4U, FLASH_DRV_ERR_INPUT_PARAM = 5U, FLASH_DRV_ERR_BLANK_CHECK = 6U, FLASH_DRV_ERR_COMPARE = 7U, FLASH_DRV_ERR_ECC_S = 8U, FLASH_DRV_ERR_ECC_M = 9U, FLASH_DRV_ERR_HW_FAIL = 10U, } Flash_Drv_ReturnType; typedef enum { FLASH_DRV_STATUS_FAIL = 0x00000001U, FLASH_DRV_STATUS_CMDABT = 0x00000004U, FLASH_DRV_STATUS_ACCERR = 0x00000020U, FLASH_DRV_STATUS_PREABT = 0x00000040U, FLASH_DRV_STATUS_CCIF = 0x00000080U, FLASH_DRV_STATUS_CMDWRF = 0x00000800U, FLASH_DRV_STATUS_DFDIF = 0x00010000U, FLASH_DRV_STATUS_SFDIF = 0x00020000U, FLASH_DRV_STATUS_DBG_ERSALL_DIS = 0x40000000U }Flash_Drv_StatusType; typedef enum { FLASH_DRV_READ_IDLE = 0U, FLASH_DRV_READ_BUSY = 1U, FLASH_DRV_READ_ERROR = 2U, } Flash_Drv_ReadStatusType; typedef struct { Flash_Drv_ReadStatusType Status; uint32 Address; } Flash_Drv_ReadStateType; typedef struct { Flash_Drv_StartAccessNotifType StartNotifPtr; Flash_Drv_FinishAccessNotifType FinishNotifPtr; uint32 IgnoreBusErrStartAddr; uint32 IgnoreBusErrEndAddr; } Flash_Drv_ConfigType; typedef struct { boolean AsyncFlag; Flash_Drv_CallBackType CallBack; Flash_Drv_AcPtrType AcFunc; } Flash_Drv_CmdActionType; # 30 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" 2 # 79 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 904 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 80 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" 2 extern const Flash_Drv_ConfigType Flash_DrvConfig; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 920 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section rodata = "" # 83 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1436 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section bss = ".mcal_bss" # 86 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1452 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section bss = "" # 94 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1492 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section bss = ".mcal_bss" # 97 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" 2 extern Flash_Drv_ReadStateType Flash_Drv_ReadState; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1508 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section bss = "" # 100 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1100 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section text = ".mcal_code" # 107 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" 2 # 118 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" Flash_Drv_ReturnType Flash_Drv_Init(const Flash_Drv_ConfigType* ConfigPtr); # 131 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" Flash_Drv_ReturnType Flash_Drv_Abort(void); # 146 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" Flash_Drv_ReturnType Flash_Drv_EraseSector(const uint32 Addr, const Flash_Drv_CmdActionType * CmdActPtr); # 166 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" Flash_Drv_ReturnType Flash_Drv_Write(const uint32 FlashAddr, const uint32 Len, const uint8 *SourceAddrPtr, const Flash_Drv_CmdActionType * CmdActPtr); # 183 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" Flash_Drv_ReturnType Flash_Drv_Read(uint32 SrcAddr, uint8 const *DestAddrPtr, uint32 Length); # 198 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" Flash_Drv_ReturnType Flash_Drv_Compare(uint32 SrcAddr, const uint8 *CompareBufPtr, uint32 Length); # 212 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" Flash_Drv_ReturnType Flash_Drv_CheckBlank(uint32 SrcAddr, uint32 Length); # 228 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" Flash_Drv_ReturnType Flash_Drv_PollEraseWriteStatus(void); # 241 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" uint32 Flash_Drv_GetBlockNumFromAddr(uint32 Address); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1116 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section text = "" # 245 "../../../mcal/Fls_ZX_K14xM/Inc\\Flash_Drv.h" 2 # 27 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 # 1 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Fls.h" 1 # 57 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Fls.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Rte_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Rte_MemMap.h" #pragma clang section text = ".mcal_code" # 58 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Fls.h" 2 void SchM_Enter_Fls_TransferStatus(void); void SchM_Exit_Fls_TransferStatus(void); void SchM_Enter_Fls_FCMD(void); void SchM_Exit_Fls_FCMD(void); void SchM_Enter_Fls_FCTRL(void); void SchM_Exit_Fls_FCTRL(void); void SchM_Enter_Fls_BEDStartAddr(void); void SchM_Exit_Fls_BEDStartAddr(void); void SchM_Enter_Fls_BEDEndAddr(void); void SchM_Exit_Fls_BEDEndAddr(void); void SchM_Enter_Fls_MBEState(void); void SchM_Exit_Fls_MBEState(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Rte_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Rte_MemMap.h" #pragma clang section text = "" # 79 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Fls.h" 2 # 28 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 # 1 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices\\Device_Regs.h" 1 # 17 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices\\Device_Regs.h" # 1 "../Generated/inc\\Device_Cfg.h" 1 # 18 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices\\Device_Regs.h" 2 # 1 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices/Z20K148M.h" 1 # 43 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices/Z20K148M.h" typedef enum IRQn { NMI_IRQn = -14, HardFalut_IRQn = -13, MemManageFault_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, DMA_Ch0_IRQn = 0, DMA_Ch1_IRQn = 1, DMA_Ch2_IRQn = 2, DMA_Ch3_IRQn = 3, DMA_Ch4_IRQn = 4, DMA_Ch5_IRQn = 5, DMA_Ch6_IRQn = 6, DMA_Ch7_IRQn = 7, DMA_Ch8_IRQn = 8, DMA_Ch9_IRQn = 9, DMA_Ch10_IRQn = 10, DMA_Ch11_IRQn = 11, DMA_Ch12_IRQn = 12, DMA_Ch13_IRQn = 13, DMA_Ch14_IRQn = 14, DMA_Ch15_IRQn = 15, DMA_Err_IRQn = 16, FLASH_CmdComplete_IRQn = 17, FLASH_Ecc_IRQn = 18, PMU_IRQn = 19, WDOG_IRQn = 20, EWDT_IRQn = 21, SRMC_IRQn = 22, I2C0_IRQn = 23, I2C1_IRQn = 24, SPI0_Txe_IRQn = 25, SPI0_Txo_IRQn = 26, SPI0_Rxf_IRQn = 27, SPI0_Rxo_IRQn = 28, SPI0_Rxu_IRQn = 29, Reserved30_IRQn = 30, SPI1_Txe_IRQn = 31, SPI1_Txo_IRQn = 32, SPI1_Rxf_IRQn = 33, SPI1_Rxo_IRQn = 34, SPI1_Rxu_IRQn = 35, Reserved36_IRQn = 36, SPI2_Txe_IRQn = 37, SPI2_Txo_IRQn = 38, SPI2_Rxf_IRQn = 39, SPI2_Rxo_IRQn = 40, SPI2_Rxu_IRQn = 41, Reserved42_IRQn = 42, SPI3_Txe_IRQn = 43, SPI3_Txo_IRQn = 44, SPI3_Rxf_IRQn = 45, SPI3_Rxo_IRQn = 46, SPI3_Rxu_IRQn = 47, Reserved48_IRQn = 48, UART0_IRQn = 49, UART1_IRQn = 50, UART2_IRQn = 51, UART3_IRQn = 52, UART4_IRQn = 53, UART5_IRQn = 54, CAN0_BusOff_IRQn = 55, CAN0_TxWarn_IRQn = 56, CAN0_RxWarn_IRQn = 57, CAN0_Err_IRQn = 58, CAN0_ErrFd_IRQn = 59, CAN0_PnWake_IRQn = 60, CAN0_SelfWakeup_IRQn = 61, CAN0_Ecc_IRQn = 62, CAN0_Mb0To15_IRQn = 63, CAN0_Mb16To31_IRQn = 64, CAN0_Mb32To47_IRQn = 65, CAN0_Mb48To63_IRQn = 66, CAN1_BusOff_IRQn = 67, CAN1_TxWarn_IRQn = 68, CAN1_RxWarn_IRQn = 69, CAN1_Err_IRQn = 70, CAN1_ErrFd_IRQn = 71, CAN1_PnWake_IRQn = 72, CAN1_SelfWakeup_IRQn = 73, CAN1_Ecc_IRQn = 74, CAN1_Mb0To15_IRQn = 75, CAN1_Mb16To31_IRQn = 76, CAN1_Mb32To47_IRQn = 77, CAN1_Mb48To63_IRQn = 78, CAN2_BusOff_IRQn = 79, CAN2_TxWarn_IRQn = 80, CAN2_RxWarn_IRQn = 81, CAN2_Err_IRQn = 82, CAN2_ErrFd_IRQn = 83, CAN2_PnWake_IRQn = 84, CAN2_SelfWakeup_IRQn = 85, CAN2_Ecc_IRQn = 86, CAN2_Mb0To15_IRQn = 87, CAN2_Mb16To31_IRQn = 88, CAN2_Mb32To47_IRQn = 89, CAN2_Mb48To63_IRQn = 90, CAN3_BusOff_IRQn = 91, CAN3_TxWarn_IRQn = 92, CAN3_RxWarn_IRQn = 93, CAN3_Err_IRQn = 94, CAN3_ErrFd_IRQn = 95, CAN3_PnWake_IRQn = 96, CAN3_SelfWakeup_IRQn = 97, CAN3_Ecc_IRQn = 98, CAN3_Mb0To15_IRQn = 99, CAN3_Mb16To31_IRQn = 100, CAN3_Mb32To47_IRQn = 101, CAN3_Mb48To63_IRQn = 102, CAN4_BusOff_IRQn = 103, CAN4_TxWarn_IRQn = 104, CAN4_RxWarn_IRQn = 105, CAN4_Err_IRQn = 106, CAN4_ErrFd_IRQn = 107, CAN4_PnWake_IRQn = 108, CAN4_SelfWakeup_IRQn = 109, CAN4_Ecc_IRQn = 110, CAN4_Mb0To15_IRQn = 111, CAN4_Mb16To31_IRQn = 112, CAN4_Mb32To47_IRQn = 113, CAN4_Mb48To63_IRQn = 114, CAN5_BusOff_IRQn = 115, CAN5_TxWarn_IRQn = 116, CAN5_RxWarn_IRQn = 117, CAN5_Err_IRQn = 118, CAN5_ErrFd_IRQn = 119, CAN5_PnWake_IRQn = 120, CAN5_SelfWakeup_IRQn = 121, CAN5_Ecc_IRQn = 122, CAN5_Mb0To15_IRQn = 123, CAN5_Mb16To31_IRQn = 124, CAN5_Mb32To47_IRQn = 125, CAN5_Mb48To63_IRQn = 126, CAN6_BusOff_IRQn = 127, CAN6_TxWarn_IRQn = 128, CAN6_RxWarn_IRQn = 129, CAN6_Err_IRQn = 130, CAN6_ErrFd_IRQn = 131, CAN6_PnWake_IRQn = 132, CAN6_SelfWakeup_IRQn = 133, CAN6_Ecc_IRQn = 134, CAN6_Mb0To31_IRQn = 135, CAN6_Mb32To63_IRQn = 136, CAN6_Mb64To95_IRQn = 137, CAN6_Mb96To127_IRQn = 138, CAN7_BusOff_IRQn = 139, CAN7_TxWarn_IRQn = 140, CAN7_RxWarn_IRQn = 141, CAN7_Err_IRQn = 142, CAN7_ErrFd_IRQn = 143, CAN7_PnWake_IRQn = 144, CAN7_SelfWakeup_IRQn = 145, CAN7_Ecc_IRQn = 146, CAN7_Mb0To31_IRQn = 147, CAN7_Mb32To63_IRQn = 148, CAN7_Mb64To95_IRQn = 149, CAN7_Mb96To127_IRQn = 150, Reserved151_IRQn = 151, Reserved152_IRQn = 152, Reserved153_IRQn = 153, TIM0_Ch_IRQn = 154, TIM0_Fault_IRQn = 155, TIM0_Overflow_IRQn = 156, TIM0_Rlfl_IRQn = 157, TIM1_Ch_IRQn = 158, TIM1_Fault_IRQn = 159, TIM1_Overflow_IRQn = 160, TIM1_Rlfl_IRQn = 161, TIM2_Ch_IRQn = 162, TIM2_Fault_IRQn = 163, TIM2_Overflow_IRQn = 164, TIM2_Rlfl_IRQn = 165, TIM3_Ch_IRQn = 166, TIM3_Fault_IRQn = 167, TIM3_Overflow_IRQn = 168, TIM3_Rlfl_IRQn = 169, TDG0_Tco_IRQn = 170, TDG0_Err_IRQn = 171, TDG1_Tco_IRQn = 172, TDG1_Err_IRQn = 173, I2S0_IRQn = 174, I2S1_IRQn = 175, PORTA_IRQn = 176, PORTB_IRQn = 177, PORTC_IRQn = 178, PORTD_IRQn = 179, PORTE_IRQn = 180, STIM_IRQn = 181, RTC_Alarm_IRQn = 182, RTC_Second_IRQn = 183, AES_IRQn = 184, TRNG_IRQn = 185, CMU0_IRQn = 186, CMU1_IRQn = 187, CMU2_IRQn = 188, SERU_ParityErr_IRQn = 189, SERU_ChErr_IRQn = 190, SCC_IRQn = 191, MCPWM0_Ch_IRQn = 192, MCPWM0_Fault_IRQn = 193, MCPWM0_Overflow_IRQn = 194, MCPWM0_Rlfl_IRQn = 195, MCPWM1_Ch_IRQn = 196, MCPWM1_Fault_IRQn = 197, MCPWM1_Overflow_IRQn = 198, MCPWM1_Rlfl_IRQn = 199, ADC0_IRQn = 200, ADC1_IRQn = 201, CMP_IRQn = 202, FPU_Err_IRQn = 203, CACHE_Err_IRQn = 204, } IRQn_Type; # 352 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices/Z20K148M.h" typedef struct { uint32 RESERVED0[1U]; volatile const uint32 ICTR; volatile uint32 ACTLR; } Z20_SCnSCBType; typedef struct { volatile const uint32 CPUID; volatile uint32 ICSR; volatile uint32 VTOR; volatile uint32 AIRCR; volatile uint32 SCR; volatile uint32 CCR; volatile uint8 SHP[12U]; volatile uint32 SHCSR; volatile uint32 CFSR; volatile uint32 HFSR; volatile uint32 DFSR; volatile uint32 MMFAR; volatile uint32 BFAR; volatile uint32 AFSR; volatile const uint32 PFR[2U]; volatile const uint32 DFR; volatile const uint32 ADR; volatile const uint32 MMFR[4U]; volatile const uint32 ISAR[5U]; uint32 RESERVED0[5U]; volatile uint32 CPACR; } Z20_SCBType; typedef struct { volatile uint32 CTRL; volatile uint32 LOAD; volatile uint32 VAL; volatile const uint32 CALIB; } Z20_SysTickType; typedef struct { volatile uint32 ISER[8U]; uint32 RESERVED0[24U]; volatile uint32 ICER[8U]; uint32 RSERVED1[24U]; volatile uint32 ISPR[8U]; uint32 RESERVED2[24U]; volatile uint32 ICPR[8U]; uint32 RESERVED3[24U]; volatile uint32 IABR[8U]; uint32 RESERVED4[56U]; volatile uint8 IP[240U]; uint32 RESERVED5[644U]; volatile uint32 STIR; } Z20_NVICType; typedef struct { volatile uint32 CTRL; volatile uint32 CYCCNT; volatile uint32 CPICNT; volatile uint32 EXCCNT; volatile uint32 SLEEPCNT; volatile uint32 LSUCNT; volatile uint32 FOLDCNT; volatile const uint32 PCSR; volatile uint32 COMP0; volatile uint32 MASK0; volatile uint32 FUNCTION0; uint32 RESERVED0[1U]; volatile uint32 COMP1; volatile uint32 MASK1; volatile uint32 FUNCTION1; uint32 RESERVED1[1U]; volatile uint32 COMP2; volatile uint32 MASK2; volatile uint32 FUNCTION2; uint32 RESERVED2[1U]; volatile uint32 COMP3; volatile uint32 MASK3; volatile uint32 FUNCTION3; } Z20_DWTType; typedef struct { volatile uint32 DHCSR; volatile uint32 DCRSR; volatile uint32 DCRDR; volatile uint32 DEMCR; } Z20_CoreDebugType; typedef struct { uint32 RESERVED0[1U]; volatile uint32 FPCCR; volatile uint32 FPCAR; volatile uint32 FPDSCR; volatile const uint32 MVFR0; volatile const uint32 MVFR1; } Z20_FPUType; # 496 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices/Z20K148M.h" struct Reg_Adc_Bf { uint32 zResverd0x000; struct { uint32 RSVD_7_0 : 8; uint32 FIFO_SIZE : 8; uint32 RSVD_31_16 : 16; } ADC_PARAM; struct { uint32 ADC_EN : 1; uint32 CAL_REQ : 1; uint32 RST : 1; uint32 DOZEN : 1; uint32 TRIG_MODE_ENABLE : 1; uint32 TRIG_MODE : 1; uint32 MODE1_RST : 1; uint32 LMD : 3; uint32 IREF_SEL : 1; uint32 STABLE_T : 11; uint32 RSVD_31_22 : 10; } ADC_CTRL; struct { uint32 FWM_INT : 1; uint32 FOF : 1; uint32 TCOMP_INT : 1; uint32 CMP_INT : 1; uint32 DMA_REQ : 1; uint32 RDY : 1; uint32 CAL_RDY : 1; uint32 ADC_ACTIVE : 1; uint32 LSI : 1; uint32 TC_ERR : 1; uint32 RSVD_31_10 : 22; } ADC_STAT; struct { uint32 FWM_IE : 1; uint32 FOF_IE : 1; uint32 TCOM_IE : 1; uint32 CMP_IE : 1; uint32 FWMDE : 1; uint32 ERR_INT_IE : 1; uint32 RSVD_31_6 : 26; } ADC_IE; struct { uint32 DIFF_MODE : 1; uint32 CHSELP : 5; uint32 CHSELN : 2; uint32 RSVD_10_8 : 3; uint32 CTYPE : 1; uint32 CMPS : 3; uint32 HWT_EN : 1; uint32 REF_SEL : 1; uint32 RES : 2; uint32 AVGS : 3; uint32 STS : 10; } ADC_CFG; struct { uint32 CVL : 12; uint32 RSVD_15_12 : 4; uint32 CVH : 12; uint32 RSVD_31_28 : 4; } ADC_CV; uint8 zResverd0x01C[4]; struct { uint32 ADC_DATA_RD : 17; uint32 RSVD_31_17 : 15; } ADC_DATA_RD; struct { uint32 FCOUNT : 5; uint32 RSVD_15_5 : 11; uint32 FWMARK : 4; uint32 FDRD : 5; uint32 RSVD_31_25 : 7; } ADC_FCTRL; struct { uint32 ADC_SWTRIG : 1; uint32 RSVD_31_1 : 31; } ADC_SWTRIG; struct { uint32 ADC_CAL_VAL : 13; uint32 RSVD_31_13 : 19; } ADC_CAL_VAL; struct { uint32 CMD0 : 5; uint32 CMD0_INT_EN : 1; uint32 RSVD_7_6 : 2; uint32 CMD1 : 5; uint32 CMD1_INT_EN : 1; uint32 RSVD_15_14 : 2; uint32 CMD2 : 5; uint32 CMD2_INT_EN : 1; uint32 RSVD_23_22 : 2; uint32 CMD3 : 5; uint32 CMD3_INT_EN : 1; uint32 RSVD_31_30 : 2; } ADC_CMD_BUFF0; struct { uint32 CMD4 : 5; uint32 CMD4_INT_EN : 1; uint32 RSVD_7_6 : 2; uint32 CMD5 : 5; uint32 CMD5_INT_EN : 1; uint32 RSVD_31_14 : 18; } ADC_CMD_BUFF1; }; struct Reg_Adc_W { uint32 zResverd0x000; uint32 ADC_PARAM; uint32 ADC_CTRL; uint32 ADC_STAT; uint32 ADC_IE; uint32 ADC_CFG; uint32 ADC_CV; uint8 zResverd0x01C[4]; uint32 ADC_DATA_RD; uint32 ADC_FCTRL; uint32 ADC_SWTRIG; uint32 ADC_CAL_VAL; uint32 ADC_CMD_BUFF0; uint32 ADC_CMD_BUFF1; }; typedef volatile struct Reg_Adc_Bf Reg_Adc_BfType; typedef volatile struct Reg_Adc_W Reg_Adc_WType; struct Reg_Aes_Bf { uint32 zResverd0x0000; struct { uint32 R : 1; uint32 ERR : 8; uint32 RSVD_31_9 : 23; } AES_STATUS; struct { uint32 S : 1; uint32 RND : 4; uint32 RSVD_31_5 : 27; } AES_CONTROL; struct { uint32 CD : 1; uint32 KSS : 2; uint32 RSVD_3 : 1; uint32 RSVD_7_4 : 4; uint32 MODE : 8; uint32 BS : 8; uint32 ALGO : 8; } AES_CONFIG; uint8 zResverd0x010[12]; struct { uint32 DATA_I : 32; } AES_DATA_I0; struct { uint32 DATA_I : 32; } AES_DATA_I1; struct { uint32 DATA_I : 32; } AES_DATA_I2; struct { uint32 DATA_I : 32; } AES_DATA_I3; struct { uint32 DATA_O : 32; } AES_DATA_O0; struct { uint32 DATA_O : 32; } AES_DATA_O1; struct { uint32 DATA_O : 32; } AES_DATA_O2; struct { uint32 DATA_O : 32; } AES_DATA_O3; struct { uint32 KEY0 : 32; } AES_KEY0; struct { uint32 KEY1 : 32; } AES_KEY1; struct { uint32 KEY2 : 32; } AES_KEY2; struct { uint32 KEY3 : 32; } AES_KEY3; uint8 zResverd0x04C[16]; struct { uint32 IV0 : 32; } AES_IV0; struct { uint32 IV1 : 32; } AES_IV1; struct { uint32 IV2 : 32; } AES_IV2; struct { uint32 IV3 : 32; } AES_IV3; }; struct Reg_Aes_W { uint32 zResverd0x0000; uint32 AES_STATUS; uint32 AES_CONTROL; uint32 AES_CONFIG; uint8 zResverd0x010[12]; uint32 AES_DATA_I0; uint32 AES_DATA_I1; uint32 AES_DATA_I2; uint32 AES_DATA_I3; uint32 AES_DATA_O0; uint32 AES_DATA_O1; uint32 AES_DATA_O2; uint32 AES_DATA_O3; uint32 AES_KEY0; uint32 AES_KEY1; uint32 AES_KEY2; uint32 AES_KEY3; uint8 zResverd0x04C[16]; uint32 AES_IV0; uint32 AES_IV1; uint32 AES_IV2; uint32 AES_IV3; }; typedef volatile struct Reg_Aes_Bf Reg_Aes_BfType; typedef volatile struct Reg_Aes_W Reg_Aes_WType; struct Reg_Can_Bf { struct { uint32 MAXMB : 7; uint32 RSVD_7 : 1; uint32 IDAM : 2; uint32 RSVD_10 : 1; uint32 FDEN : 1; uint32 AEN : 1; uint32 LPRIOEN : 1; uint32 PNET_EN : 1; uint32 DMAE : 1; uint32 IRMQ : 1; uint32 SRXDIS : 1; uint32 DOZE : 1; uint32 WAKSRC : 1; uint32 LPMACK : 1; uint32 WRNEN : 1; uint32 SLFWAK : 1; uint32 SUPV : 1; uint32 FRZACK : 1; uint32 SOFTRST : 1; uint32 WAKMSK : 1; uint32 NOTRDY : 1; uint32 HALT : 1; uint32 RFEN : 1; uint32 FRZ : 1; uint32 MDIS : 1; } CAN_MCR; struct { uint32 PROPSEG : 3; uint32 LOM : 1; uint32 LBUF : 1; uint32 TSYC : 1; uint32 BOFFREC : 1; uint32 SMP : 1; uint32 RSVD_9_8 : 2; uint32 RWRNMSK : 1; uint32 TWRNMSK : 1; uint32 LPB : 1; uint32 RSVD_13 : 1; uint32 ERRMSK : 1; uint32 BOFFMSK : 1; uint32 PSEG2 : 3; uint32 PSEG1 : 3; uint32 RJW : 2; uint32 PRESDIV : 8; } CAN_CTRL1; struct { uint32 TIMER : 16; uint32 RSVD_31_16 : 16; } CAN_TIMER; uint8 zResverd0x0C[4]; struct { uint32 MG : 32; } CAN_RXMGMSK; struct { uint32 RX14M : 32; } CAN_RX14MASK; struct { uint32 RX15M : 32; } CAN_RX15MASK; struct { uint32 TXERRCNT : 8; uint32 RXERRCNT : 8; uint32 TX_ERRCNT_FAST : 8; uint32 RX_ERRCNT_FAST : 8; } CAN_ECR; struct { uint32 WAKINT : 1; uint32 ERRINT : 1; uint32 BOFFINT : 1; uint32 RX : 1; uint32 FLTCONF : 2; uint32 TX : 1; uint32 IDLE : 1; uint32 RXWRN : 1; uint32 TXWRN : 1; uint32 STFERR : 1; uint32 FRAMERR : 1; uint32 CRCERR : 1; uint32 ACKERR : 1; uint32 BIT0ERR : 1; uint32 BIT1ERR : 1; uint32 RWRNINT : 1; uint32 TWRNINT : 1; uint32 SYNCH : 1; uint32 BUSOFFDONEINT : 1; uint32 ERRINT_FAST : 1; uint32 ERROVR : 1; uint32 RSVD_25_22 : 4; uint32 STFERR_FAST : 1; uint32 FRAMERR_FAST : 1; uint32 CRCERR_FAST : 1; uint32 RSVD_29 : 1; uint32 BIT0ERR_FAST : 1; uint32 BIT1ERR_FAST : 1; } CAN_ESR1; struct { uint32 BUF63TO32M : 32; } CAN_IMASK2; struct { uint32 BUF31TO0M : 32; } CAN_IMASK1; struct { uint32 BUF63TO32I : 32; } CAN_IFLAG2; struct { uint32 BUF0I : 1; uint32 BUF4TO1I : 4; uint32 BUF5I : 1; uint32 BUF6I : 1; uint32 BUF7I : 1; uint32 BUF31TO8I : 24; } CAN_IFLAG1; struct { uint32 RSVD_10_0 : 11; uint32 EDFLTDIS : 1; uint32 ISOCANFDEN : 1; uint32 RSVD_13 : 1; uint32 PREXCEN : 1; uint32 TIMER_SRC : 1; uint32 EACEN : 1; uint32 RRS : 1; uint32 MRP : 1; uint32 TASD : 5; uint32 RFFN : 4; uint32 WRMFRZ : 1; uint32 ECRWRE : 1; uint32 BOFFDONEMSK : 1; uint32 ERRMASK_FAST : 1; } CAN_CTRL2; struct { uint32 RSVD_12_0 : 13; uint32 IMB : 1; uint32 VPS : 1; uint32 RSVD_15 : 1; uint32 LPTM : 7; uint32 RSVD_31_23 : 9; } CAN_ESR2; uint8 zResverd0x03C[8]; struct { uint32 TXCRC : 15; uint32 RSVD_15 : 1; uint32 MBCRC : 7; uint32 RSVD_31_23 : 9; } CAN_CRCR; struct { uint32 FGM : 32; } CAN_RXFGMASK; struct { uint32 IDHIT : 9; uint32 RSVD_31_9 : 23; } CAN_RXFIR; struct { uint32 EPSEG2 : 5; uint32 EPSEG1 : 5; uint32 EPROPSEG : 6; uint32 ERJW : 5; uint32 EPRESDIV : 10; uint32 BTF : 1; } CAN_CBT; uint8 zResverd0x054[20]; struct { uint32 BUF127TO96M : 32; } CAN_IMASK4; struct { uint32 BUF95TO64M : 32; } CAN_IMASK3; struct { uint32 BUF127TO96I : 32; } CAN_IFLAG4; struct { uint32 BUF95TO64I : 32; } CAN_IFLAG3; uint8 zResverd0x078[8]; struct { struct { uint32 TIME_STAMP : 16; uint32 DLC : 4; uint32 RTR : 1; uint32 IDE : 1; uint32 SRR : 1; uint32 RSVD_23 : 1; uint32 CODE : 4; uint32 RSVD_28 : 1; uint32 ESI : 1; uint32 BRS : 1; uint32 EDL : 1; } CAN_MB_CS; struct { uint32 ID_EXTEND : 18; uint32 ID_STD_EXD : 11; uint32 PRIO : 3; } CAN_MB_ID; struct { uint32 DATA_BYTE03 : 32; } CAN_MB_DATA03; struct { uint32 DATA_BYTE47 : 32; } CAN_MB_DATA47; } CAN_MB[128]; struct { uint32 MI : 32; } CAN_RXIMRn[128]; uint8 zResverd0x0A80[96]; struct { uint32 RSVD_6_0 : 7; uint32 NCEFAFRZ : 1; uint32 ECCDIS : 1; uint32 RERRDIS : 1; uint32 RSVD_12_10 : 3; uint32 EXTERRIE : 1; uint32 FAERRIE : 1; uint32 HAERRI : 1; uint32 CEI_MSK : 1; uint32 RSVD_17 : 1; uint32 FANCEI_MSK : 1; uint32 HANCEI_MSK : 1; uint32 RSVD_30_20 : 11; uint32 ECRWRDIS : 1; } CAN_MECR; struct { uint32 INJADDR_L : 2; uint32 INJADDR_H : 12; uint32 RSVD_31_14 : 18; } CAN_ERRIAR; struct { uint32 DFLIP : 32; } CAN_ERRIDPR; struct { uint32 PFLIP0 : 5; uint32 RSVD_7_5 : 3; uint32 PFLIP1 : 5; uint32 RSVD_15_13 : 3; uint32 PFLIP2 : 5; uint32 RSVD_23_21 : 3; uint32 PFLIP3 : 5; uint32 RSVD_31_29 : 3; } CAN_ERRIPPR; struct { uint32 ERRADDR : 14; uint32 RSVD_15_14 : 2; uint32 SAID : 3; uint32 RSVD_23_19 : 5; uint32 NCE : 1; uint32 RSVD_31_25 : 7; } CAN_RERRAR; struct { uint32 RDATA : 32; } CAN_RERRDR; struct { uint32 SYND0 : 5; uint32 RSVD_6_5 : 2; uint32 BE0 : 1; uint32 SYND1 : 5; uint32 RSVD_14_13 : 2; uint32 BE1 : 1; uint32 SYND2 : 5; uint32 RSVD_22_21 : 2; uint32 BE2 : 1; uint32 SYND3 : 5; uint32 RSVD_30_29 : 2; uint32 BE3 : 1; } CAN_RERRSYNR; struct { uint32 CEIOF : 1; uint32 RSVD_1 : 1; uint32 FANCEIOF : 1; uint32 HANCEIOF : 1; uint32 RSVD_15_4 : 12; uint32 CEIF : 1; uint32 RSVD_17 : 1; uint32 FANCEIF : 1; uint32 HANCEIF : 1; uint32 RSVD_31_20 : 12; } CAN_ERRSR; struct { uint32 FCS : 2; uint32 IDFS : 2; uint32 PLFS : 2; uint32 RSVD_7_6 : 2; uint32 NMATCH : 8; uint32 WUMF_MSK : 1; uint32 WTOF_MSK : 1; uint32 RSVD_31_18 : 14; } CAN_CTRL1_PN; struct { uint32 MATCHTO : 16; uint32 RSVD_31_16 : 16; } CAN_CTRL2_PN; struct { uint32 RSVD_7_0 : 8; uint32 MCOUNTER : 8; uint32 WUMF : 1; uint32 WTOF : 1; uint32 RSVD_31_18 : 14; } CAN_WU_MTC; struct { uint32 FLT_ID1 : 29; uint32 FLT_RTR : 1; uint32 FLT_IDE : 1; uint32 RSVD_31 : 1; } CAN_FLT_ID1; struct { uint32 FLT_DLC_HI : 4; uint32 RSVD_15_4 : 12; uint32 FLT_DLC_LO : 4; uint32 RSVD_31_20 : 12; } CAN_FLT_DLC; struct { uint32 DATA_BYTE_3 : 8; uint32 DATA_BYTE_2 : 8; uint32 DATA_BYTE_1 : 8; uint32 DATA_BYTE_0 : 8; } CAN_PL1_LO; struct { uint32 DATA_BYTE_7 : 8; uint32 DATA_BYTE_6 : 8; uint32 DATA_BYTE_5 : 8; uint32 DATA_BYTE_4 : 8; } CAN_PL1_HI; struct { uint32 FLT_ID2_IDMASK : 29; uint32 RTR_MSK : 1; uint32 IDE_MSK : 1; uint32 RSVD_31 : 1; } CAN_FLT_ID2_IDMASK; struct { uint32 DATA_BYTE_3 : 8; uint32 DATA_BYTE_2 : 8; uint32 DATA_BYTE_1 : 8; uint32 DATA_BYTE_0 : 8; } CAN_PL2_PLMASK_LO; struct { uint32 DATA_BYTE_7 : 8; uint32 DATA_BYTE_6 : 8; uint32 DATA_BYTE_5 : 8; uint32 DATA_BYTE_4 : 8; } CAN_PL2_PLMASK_HI; uint8 zResverd0x0B28[24]; struct { struct { uint32 RSVD_15_0 : 16; uint32 DLC : 4; uint32 RTR : 1; uint32 IDE : 1; uint32 SRR : 1; uint32 RSVD_31_23 : 9; } CAN_WMB_CS; struct { uint32 ID : 29; uint32 RSVD_31_29 : 3; } CAN_WMB_ID; struct { uint32 DATA_BYTE_3 : 8; uint32 DATA_BYTE_2 : 8; uint32 DATA_BYTE_1 : 8; uint32 DATA_BYTE_0 : 8; } CAN_WMB_D03; struct { uint32 DATA_BYTE_7 : 8; uint32 DATA_BYTE_6 : 8; uint32 DATA_BYTE_5 : 8; uint32 DATA_BYTE_4 : 8; } CAN_WMB_D47; } CAN_WMB[4]; uint8 zResverd0x0B80[128]; struct { uint32 TDCVAL : 6; uint32 RSVD_7_6 : 2; uint32 TDCOFF : 5; uint32 RSVD_13 : 1; uint32 TDCFAIL : 1; uint32 TDCEN : 1; uint32 MBDSR0 : 2; uint32 RSVD_18 : 1; uint32 MBDSR1 : 2; uint32 RSVD_21 : 1; uint32 MBDSR2 : 2; uint32 RSVD_24 : 1; uint32 MBDSR3 : 2; uint32 RSVD_30_27 : 4; uint32 FD_RATE : 1; } CAN_FDCTRL; struct { uint32 FPSEG2 : 3; uint32 RSVD_4_3 : 2; uint32 FPSEG1 : 3; uint32 RSVD_9_8 : 2; uint32 FPROPSEG : 5; uint32 RSVD_15 : 1; uint32 FRJW : 3; uint32 RSVD_19 : 1; uint32 FPRESDIV : 10; uint32 RSVD_31_30 : 2; } CAN_FDCBT; struct { uint32 FD_TXCRC : 21; uint32 RSVD_23_21 : 3; uint32 FD_MBCRC : 7; uint32 RSVD_31 : 1; } CAN_FDCRC; }; struct Reg_Can_W { uint32 CAN_MCR; uint32 CAN_CTRL1; uint32 CAN_TIMER; uint8 zResverd0x0C[4]; uint32 CAN_RXMGMSK; uint32 CAN_RX14MASK; uint32 CAN_RX15MASK; uint32 CAN_ECR; uint32 CAN_ESR1; uint32 CAN_IMASK2; uint32 CAN_IMASK1; uint32 CAN_IFLAG2; uint32 CAN_IFLAG1; uint32 CAN_CTRL2; uint32 CAN_ESR2; uint8 zResverd0x03C[8]; uint32 CAN_CRCR; uint32 CAN_RXFGMASK; uint32 CAN_RXFIR; uint32 CAN_CBT; uint8 zResverd0x054[20]; uint32 CAN_IMASK4; uint32 CAN_IMASK3; uint32 CAN_IFLAG4; uint32 CAN_IFLAG3; uint8 zResverd0x078[8]; struct { uint32 MB0; uint32 MB1; uint32 MB2; uint32 MB3; } CAN_MB[128]; uint32 CAN_RXIMR[128]; uint8 zResverd0x0A80[96]; uint32 CAN_MECR; uint32 CAN_ERRIAR; uint32 CAN_ERRIDPR; uint32 CAN_ERRIPPR; uint32 CAN_RERRAR; uint32 CAN_RERRDR; uint32 CAN_RERRSYNR; uint32 CAN_ERRSR; uint32 CAN_CTRL1_PN; uint32 CAN_CTRL2_PN; uint32 CAN_WU_MTC; uint32 CAN_FLT_ID1; uint32 CAN_FLT_DLC; uint32 CAN_PL1_LO; uint32 CAN_PL1_HI; uint32 CAN_FLT_ID2_IDMASK; uint32 CAN_PL2_PLMASK_LO; uint32 CAN_PL2_PLMASK_HI; uint8 zResverd0x0B28[24]; struct { uint32 CAN_WMB_CS; uint32 CAN_WMB_ID; uint32 CAN_WMB_D03; uint32 CAN_WMB_D47; } CAN_WMB[4]; uint8 zResverd0x0B80[128]; uint32 CAN_FDCTRL; uint32 CAN_FDCBT; uint32 CAN_FDCRC; }; typedef volatile struct Reg_Can_Bf Reg_Can_BfType; typedef volatile struct Reg_Can_W Reg_Can_WType; struct Reg_Cmp_Bf { uint32 zResverd0x0; struct { uint32 DAC_RES : 4; uint32 RSVD_31_4 : 28; } CMP_PARAM; struct { uint32 CMP_SEL : 1; uint32 CMP_EN : 1; uint32 SOC_TRG_EN : 1; uint32 STOP_EN : 1; uint32 RSVD_31_4 : 28; } CMP_CCR0; struct { uint32 WINDOW_EN : 1; uint32 SAMPLE_EN : 1; uint32 DMA_EN : 1; uint32 COUT_INV : 1; uint32 COUT_SEL : 1; uint32 COUT_PEN : 1; uint32 COUT_OWE : 1; uint32 COUT_OW : 1; uint32 RSVD_15_8 : 8; uint32 FILT_CNT : 3; uint32 RSVD_23_19 : 5; uint32 FILT_PER : 8; } CMP_CCR1; struct { uint32 HS_HSTCTR : 2; uint32 RSVD_3_2 : 2; uint32 LS_HSTCTR : 2; uint32 RSVD_15_6 : 10; uint32 HS_PSEL : 4; uint32 HS_MSEL : 4; uint32 LS_PSEL : 4; uint32 LS_MSEL : 4; } CMP_CCR2; struct { uint32 DAC_EN : 1; uint32 DAC_BUFF_EN : 1; uint32 RSVD_7_2 : 6; uint32 VREF_SEL : 1; uint32 RSVD_15_9 : 7; uint32 DAC_SEL : 8; uint32 RSVD_31_24 : 8; } CMP_DCR; struct { uint32 CFR_IE : 1; uint32 CFF_IE : 1; uint32 RSVD_31_2 : 30; } CMP_IER; struct { uint32 CFR : 1; uint32 CFF : 1; uint32 RSVD_7_2 : 6; uint32 COUT : 1; uint32 RSVD_31_9 : 23; } CMP_CSR; }; struct Reg_Cmp_W { uint32 zResverd0x0; uint32 CMP_PARAM; uint32 CMP_CCR0; uint32 CMP_CCR1; uint32 CMP_CCR2; uint32 CMP_DCR; uint32 CMP_IER; uint32 CMP_CSR; }; typedef volatile struct Reg_Cmp_Bf Reg_Cmp_BfType; typedef volatile struct Reg_Cmp_W Reg_Cmp_WType; struct Reg_Cmu_Bf { uint32 zResverd0x0; struct { uint32 RST_IMP : 1; uint32 RSVD_31_1 : 31; } CMU_PARAM; struct { uint32 CME : 1; uint32 RSVD_3_1 : 3; uint32 CMMD : 1; uint32 RSVD_7_5 : 3; uint32 FAHTRSTE : 1; uint32 FBLTRSTE : 1; uint32 RSVD_15_10 : 6; uint32 FAHTIE : 1; uint32 FBLTIE : 1; uint32 RSVD_30_18 : 13; uint32 LOCK : 1; } CMU_CTRL; struct { uint32 MONST : 2; uint32 RSVD_3_2 : 2; uint32 STARTMEA : 1; uint32 RSVD_15_5 : 11; uint32 FAHTIF : 1; uint32 FBLTIF : 1; uint32 RSVD_31_18 : 14; } CMU_STAT; struct { uint32 MONWIN : 32; } CMU_MONWIN; struct { uint32 HCT4INT : 32; } CMU_CUMHCT4INT; struct { uint32 LCT4INT : 32; } CMU_CUMLCT4INT; struct { uint32 HCT4RST : 32; } CMU_CUMHCT4RST; struct { uint32 LCT4RST : 32; } CMU_CUMLCT4RST; struct { uint32 MEARSLT : 32; } CMU_CUMMEARSLT; }; struct Reg_Cmu_W { uint32 zResverd0x0; uint32 CMU_PARAM; uint32 CMU_CTRL; uint32 CMU_STAT; uint32 CMU_MONWIN; uint32 CMU_CUMHCT4INT; uint32 CMU_CUMLCT4INT; uint32 CMU_CUMHCT4RST; uint32 CMU_CUMLCT4RST; uint32 CMU_CUMMEARSLT; }; typedef volatile struct Reg_Cmu_Bf Reg_Cmu_BfType; typedef volatile struct Reg_Cmu_W Reg_Cmu_WType; struct Reg_Crc_Bf { uint32 zResverd0x0; struct { uint32 RSVD_31_0 : 32; } CRC_PARAM; struct { uint32 BYTE0 : 8; uint32 BYTE1 : 8; uint32 BYTE2 : 8; uint32 BYTE3 : 8; } CRC_DATA; struct { uint32 LPHW : 16; uint32 HPHW : 16; } CRC_POLY; struct { uint32 MODE : 1; uint32 WS : 1; uint32 CR : 1; uint32 RSVD_3 : 1; uint32 RT : 2; uint32 WT : 2; uint32 RSVD_31_8 : 24; } CRC_CTRL; }; struct Reg_Crc_W { uint32 zResverd0x0; uint32 CRC_PARAM; uint32 CRC_DATA; uint32 CRC_POLY; uint32 CRC_CTRL; }; typedef volatile struct Reg_Crc_Bf Reg_Crc_BfType; typedef volatile struct Reg_Crc_W Reg_Crc_WType; struct Reg_Dmamux_Bf { struct { uint32 ENABLE : 1; uint32 SRC_MUX : 7; uint32 RSVD_31_8 : 24; } DMA_MUX_CH_CFG[16]; }; struct Reg_Dmamux_W { uint32 DMA_MUX_CH_CFG[16]; }; struct Reg_Dma_Bf { struct { uint32 HALT : 1; uint32 HOEE : 1; uint32 RRCAE : 1; uint32 DBGE : 1; uint32 RSVD_5_4 : 2; uint32 BUSY : 1; uint32 RSVD_31_7 : 25; } DMA_CONF; struct { uint32 DMAE0 : 1; uint32 DMAE1 : 1; uint32 DMAE2 : 1; uint32 DMAE3 : 1; uint32 DMAE4 : 1; uint32 DMAE5 : 1; uint32 DMAE6 : 1; uint32 DMAE7 : 1; uint32 DMAE8 : 1; uint32 DMAE9 : 1; uint32 DMAE10 : 1; uint32 DMAE11 : 1; uint32 DMAE12 : 1; uint32 DMAE13 : 1; uint32 DMAE14 : 1; uint32 DMAE15 : 1; uint32 RSVD_31_16 : 16; } DMA_DMAE; uint8 zResverd0x08[4]; struct { uint32 EIE0 : 1; uint32 EIE1 : 1; uint32 EIE2 : 1; uint32 EIE3 : 1; uint32 EIE4 : 1; uint32 EIE5 : 1; uint32 EIE6 : 1; uint32 EIE7 : 1; uint32 EIE8 : 1; uint32 EIE9 : 1; uint32 EIE10 : 1; uint32 EIE11 : 1; uint32 EIE12 : 1; uint32 EIE13 : 1; uint32 EIE14 : 1; uint32 EIE15 : 1; uint32 RSVD_31_16 : 16; } DMA_EIE; uint8 zResverd0x010[4]; struct { uint32 CCDONE : 4; uint32 RSVD_5_4 : 2; uint32 CACDONE : 1; uint32 WPEN0 : 1; uint32 SCSTART : 4; uint32 RSVD_13_12 : 2; uint32 SACSTART : 1; uint32 WPEN1 : 1; uint32 CCES : 4; uint32 RSVD_21_20 : 2; uint32 CACES : 1; uint32 WPEN2 : 1; uint32 CCIS : 4; uint32 RSVD_29_28 : 2; uint32 CACIS : 1; uint32 WPEN3 : 1; } DMA_GCC; struct { uint32 DBEF : 1; uint32 SBEF : 1; uint32 RSVD_2 : 1; uint32 NUMEF : 1; uint32 DOEF : 1; uint32 DAEF : 1; uint32 SOEF : 1; uint32 SAEF : 1; uint32 CHEF : 4; uint32 RSVD_12 : 1; uint32 PRIEF : 1; uint32 RSVD_14 : 1; uint32 ERRF : 1; uint32 RSVD_31_16 : 16; } DMA_ES; struct { uint32 ERR0 : 1; uint32 ERR1 : 1; uint32 ERR2 : 1; uint32 ERR3 : 1; uint32 ERR4 : 1; uint32 ERR5 : 1; uint32 ERR6 : 1; uint32 ERR7 : 1; uint32 ERR8 : 1; uint32 ERR9 : 1; uint32 ERR10 : 1; uint32 ERR11 : 1; uint32 ERR12 : 1; uint32 ERR13 : 1; uint32 ERR14 : 1; uint32 ERR15 : 1; uint32 RSVD_31_16 : 16; } DMA_CES; struct { uint32 INT0 : 1; uint32 INT1 : 1; uint32 INT2 : 1; uint32 INT3 : 1; uint32 INT4 : 1; uint32 INT5 : 1; uint32 INT6 : 1; uint32 INT7 : 1; uint32 INT8 : 1; uint32 INT9 : 1; uint32 INT10 : 1; uint32 INT11 : 1; uint32 INT12 : 1; uint32 INT13 : 1; uint32 INT14 : 1; uint32 INT15 : 1; uint32 RSVD_31_16 : 16; } DMA_CIS; struct { uint32 HRS0 : 1; uint32 HRS1 : 1; uint32 HRS2 : 1; uint32 HRS3 : 1; uint32 HRS4 : 1; uint32 HRS5 : 1; uint32 HRS6 : 1; uint32 HRS7 : 1; uint32 HRS8 : 1; uint32 HRS9 : 1; uint32 HRS10 : 1; uint32 HRS11 : 1; uint32 HRS12 : 1; uint32 HRS13 : 1; uint32 HRS14 : 1; uint32 HRS15 : 1; uint32 RSVD_31_16 : 16; } DMA_CHRS; struct { uint32 CPRI3 : 4; uint32 RSVD_5_4 : 2; uint32 CPDIS3 : 1; uint32 CSE3 : 1; uint32 CPRI2 : 4; uint32 RSVD_13_12 : 2; uint32 CPDIS2 : 1; uint32 CSE2 : 1; uint32 CPRI1 : 4; uint32 RSVD_21_20 : 2; uint32 CPDIS1 : 1; uint32 CSE1 : 1; uint32 CPRI0 : 4; uint32 RSVD_29_28 : 2; uint32 CPDIS0 : 1; uint32 CSE0 : 1; } DMA_CPRI0; struct { uint32 CPRI7 : 4; uint32 RSVD_5_4 : 2; uint32 CPDIS7 : 1; uint32 CSE7 : 1; uint32 CPRI6 : 4; uint32 RSVD_13_12 : 2; uint32 CPDIS6 : 1; uint32 CSE6 : 1; uint32 CPRI5 : 4; uint32 RSVD_21_20 : 2; uint32 CPDIS5 : 1; uint32 CSE5 : 1; uint32 CPRI4 : 4; uint32 RSVD_29_28 : 2; uint32 CPDIS4 : 1; uint32 CSE4 : 1; } DMA_CPRI1; struct { uint32 CPRI11 : 4; uint32 RSVD_5_4 : 2; uint32 CPDIS11 : 1; uint32 CSE11 : 1; uint32 CPRI10 : 4; uint32 RSVD_13_12 : 2; uint32 CPDIS10 : 1; uint32 CSE10 : 1; uint32 CPRI9 : 4; uint32 RSVD_21_20 : 2; uint32 CPDIS9 : 1; uint32 CSE9 : 1; uint32 CPRI8 : 4; uint32 RSVD_29_28 : 2; uint32 CPDIS8 : 1; uint32 CSE8 : 1; } DMA_CPRI2; struct { uint32 CPRI15 : 4; uint32 RSVD_5_4 : 2; uint32 CPDIS15 : 1; uint32 CSE15 : 1; uint32 CPRI14 : 4; uint32 RSVD_13_12 : 2; uint32 CPDIS14 : 1; uint32 CSE14 : 1; uint32 CPRI13 : 4; uint32 RSVD_21_20 : 2; uint32 CPDIS13 : 1; uint32 CSE13 : 1; uint32 CPRI12 : 4; uint32 RSVD_29_28 : 2; uint32 CPDIS12 : 1; uint32 CSE12 : 1; } DMA_CPRI3; uint8 zResverd0x038[456]; struct { struct { uint32 SADDR : 32; } DMA_SADDR; struct { uint32 DADDR : 32; } DMA_DADDR; struct { sint32 SAOFF : 16; sint32 DAOFF : 16; } DMA_AOFF; struct { sint32 MLSAOFF : 16; sint32 MLDAOFF : 16; } DMA_MLAOFF; struct { uint32 NUM : 32; } DMA_NUM; struct { uint32 MLITER : 16; uint32 MLSTA : 16; } DMA_ITER; struct { uint32 START : 1; uint32 INTE : 1; uint32 RSVD_2 : 1; uint32 REQDIS : 1; uint32 RSVD_5_4 : 2; uint32 BUSY : 1; uint32 DONE : 1; uint32 RSVD_15_8 : 8; uint32 DSIZE : 2; uint32 RSVD_23_18 : 6; uint32 SSIZE : 2; uint32 RSVD_31_26 : 6; } DMA_CS; uint8 zResverd[4]; } DMA_CH_CONFIG[16]; }; struct Reg_Dma_W { uint32 DMA_CONF; uint32 DMA_DMAE; uint8 zResverd0x08[4]; uint32 DMA_EIE; uint8 zResverd0x010[4]; uint32 DMA_GCC; uint32 DMA_ES; uint32 DMA_CES; uint32 DMA_CIS; uint32 DMA_CHRS; uint32 DMA_CPRI0; uint32 DMA_CPRI1; uint32 DMA_CPRI2; uint32 DMA_CPRI3; uint8 zResverd0x038[456]; struct { uint32 DMA_SADDR; uint32 DMA_DADDR; uint32 DMA_AOFF; uint32 DMA_MLAOFF; uint32 DMA_NUM; uint32 DMA_ITER; uint32 DMA_CS; uint8 zResverd[4]; } DMA_CH_CONFIG[16]; }; typedef volatile struct Reg_Dmamux_Bf Reg_Dmamux_BfType; typedef volatile struct Reg_Dmamux_W Reg_Dmamux_WType; typedef volatile struct Reg_Dma_Bf Reg_Dma_BfType; typedef volatile struct Reg_Dma_W Reg_Dma_WType; struct Reg_Eiru_Bf { struct { uint32 SRAM0_ER_DIS : 1; uint32 SRAM0_EW_DIS : 1; uint32 SRAM0_ESB_DIS : 1; uint32 SRAM0_EMB_DIS : 1; uint32 SRAM0_EEI_EN : 1; uint32 RSVD_7_5 : 3; uint32 SRAM1_ER_DIS : 1; uint32 SRAM1_EW_DIS : 1; uint32 SRAM1_ESB_DIS : 1; uint32 SRAM1_EMB_DIS : 1; uint32 SRAM1_EEI_EN : 1; uint32 RSVD_30_13 : 18; uint32 LOCK : 1; } EIRU_CR; struct { uint32 RSVD_1_0 : 2; uint32 EEIADDR : 30; } EIRU_EEIADDR; uint8 zResverd0x08[8]; struct { struct { uint32 EFPROT : 4; uint32 EFSIZE : 3; uint32 RSVD_7 : 1; uint32 EFMST : 8; uint32 RSVD_28_16 : 13; uint32 SBERR : 1; uint32 MBERR : 1; uint32 OVERRUN : 1; } EIRU_SRAMn_EESR; struct { uint32 EFADDR : 32; } EIRU_SRAMn_FADDR; struct { uint32 EFDATA : 32; } EIRU_SRAMn_FDATA; struct { uint32 ECCMASK : 7; uint32 RSVD_31_7 : 25; } EIRU_SRAMn_ECCMASK; struct { uint32 DATAMASK : 32; } EIRU_SRAMn_DATAMASK; uint8 zResverd0x024[12]; } EIRU_SRAMn_SC[2]; }; struct Reg_Eiru_W { uint32 EIRU_CR; uint32 EIRU_EEIADDR; uint8 zResverd0x08[8]; struct { uint32 EIRU_SRAMn_EESR; uint32 EIRU_SRAMn_FADDR; uint32 EIRU_SRAMn_FDATA; uint32 EIRU_SRAMn_ECCMASK; uint32 EIRU_SRAMn_DATAMASK; uint8 zResverd0x024[12]; } EIRU_SRAMn_SC[2]; }; typedef volatile struct Reg_Eiru_Bf Reg_Eiru_BfType; typedef volatile struct Reg_Eiru_W Reg_Eiru_WType; struct Reg_Ewdt_Bf { uint32 zResverd0x0; struct { uint32 RSVD_31_0 : 32; } EWDT_PARAM; struct { uint32 EWDTE : 1; uint32 DEBUGE : 1; uint32 WAITE : 1; uint32 RSVD_3 : 1; uint32 INTE : 1; uint32 INPE : 1; uint32 INPP : 1; uint32 RSVD_23_7 : 17; uint32 INTF : 1; uint32 RSVD_31_25 : 7; } EWDT_CS; struct { uint32 COMPH : 32; } EWDT_COMPH; struct { uint32 COMPL : 32; } EWDT_COMPL; struct { uint32 CNT : 32; } EWDT_CNT; }; struct Reg_Ewdt_W { uint32 zResverd0x0; uint32 EWDT_PARAM; uint32 EWDT_CS; uint32 EWDT_COMPH; uint32 EWDT_COMPL; uint32 EWDT_CNT; }; typedef volatile struct Reg_Ewdt_Bf Reg_Ewdt_BfType; typedef volatile struct Reg_Ewdt_W Reg_Ewdt_WType; struct Reg_Flash_Bf { struct { uint32 FAIL : 1; uint32 RSVD_1 : 1; uint32 CMDABT : 1; uint32 RSVD_4_3 : 2; uint32 ACCERR : 1; uint32 PREABT : 1; uint32 CCIF : 1; uint32 RSVD_10_8 : 3; uint32 CMDWRF : 1; uint32 RSVD_15_12 : 4; uint32 DFDIF : 1; uint32 SFDIF : 1; uint32 RSVD_29_18 : 12; uint32 DBG_ERSALL_DIS : 1; uint32 FSEC : 1; } FLASH_FSTAT; struct { uint32 BK_QUERY : 1; uint32 RSVD_6_1 : 6; uint32 CCIE : 1; uint32 DBG_ERS_FLG : 1; uint32 RSVD_15_9 : 7; uint32 DFDIE : 1; uint32 SFDIE : 1; uint32 RSVD_31_18 : 14; } FLASH_FCNFG; struct { uint32 RWSC : 4; uint32 RSVD_7_4 : 4; uint32 LSMODE : 1; uint32 RSVD_15_9 : 7; uint32 FECCF : 1; uint32 RSVD_23_17 : 7; uint32 ABTREQ : 1; uint32 RSVD_31_25 : 7; } FLASH_FCTRL; uint8 zResverd0x0C[4]; struct { uint32 CMDCODE : 8; uint32 RSVD_31_8 : 24; } FLASH_FCMD; uint8 zResverd0x14[4]; struct { uint32 CMDADDR : 32; } FLASH_FADDR; struct { uint32 CMDADDRE : 32; } FLASH_FADDR_END; struct { uint32 CMDDATA0 : 32; } FLASH_FDATA0; struct { uint32 CMDDATA1 : 32; } FLASH_FDATA1; struct { uint32 CMDDATA2 : 32; } FLASH_FDATA2; struct { uint32 CMDDATA3 : 32; } FLASH_FDATA3; struct { uint32 RSVD_3_0 : 4; uint32 BED_ADDR_STRT : 28; } FLASH_BED_ADDR_STRT; struct { uint32 RSVD_3_0 : 4; uint32 BED_ADDR_END : 28; } FLASH_BED_ADDR_END; struct { uint32 RSVD_3_0 : 4; uint32 ECC_IN_ADDR : 28; } FLASH_ECC_IN_ADDR; struct { uint32 ECC_9BIT : 9; uint32 ECC_IN_EN : 1; uint32 RSVD_30_10 : 21; uint32 LOCK : 1; } FLASH_ECC_IN_CTRL; struct { uint32 MBE_FLAG : 1; uint32 MBE_OVERRUN : 1; uint32 RSVD_3_2 : 2; uint32 MBE_ADDR : 28; } FLASH_MBE_STATE; struct { uint32 SBE_FLAG : 1; uint32 SBE_OVERRUN : 1; uint32 RSVD_3_2 : 2; uint32 SBE_ADDR : 28; } FLASH_SBE_STATE; }; struct Reg_Flash_W { uint32 FLASH_FSTAT; uint32 FLASH_FCNFG; uint32 FLASH_FCTRL; uint8 zResverd0x0C[4]; uint32 FLASH_FCMD; uint8 zResverd0x14[4]; uint32 FLASH_FADDR; uint32 FLASH_FADDR_END; uint32 FLASH_FDATA0; uint32 FLASH_FDATA1; uint32 FLASH_FDATA2; uint32 FLASH_FDATA3; uint32 FLASH_BED_ADDR_STRT; uint32 FLASH_BED_ADDR_END; uint32 FLASH_ECC_IN_ADDR; uint32 FLASH_ECC_IN_CTRL; uint32 FLASH_MBE_STATE; uint32 FLASH_SBE_STATE; }; typedef volatile struct Reg_Flash_Bf Reg_Flash_BfType; typedef volatile struct Reg_Flash_W Reg_Flash_WType; struct Reg_Gpio_Bf { struct { uint32 PDO : 32; } GPIOx_PDOR; struct { uint32 PSO : 32; } GPIOx_PSOR; struct { uint32 PCO : 32; } GPIOx_PCOR; struct { uint32 PTO : 32; } GPIOx_PTOR; struct { uint32 PDI : 32; } GPIOx_PDIR; struct { uint32 PDD : 32; } GPIOx_PDDR; }; struct Reg_Gpio_W { uint32 GPIOx_PDOR; uint32 GPIOx_PSOR; uint32 GPIOx_PCOR; uint32 GPIOx_PTOR; uint32 GPIOx_PDIR; uint32 GPIOx_PDDR; }; typedef volatile struct Reg_Gpio_Bf Reg_Gpio_BfType; typedef volatile struct Reg_Gpio_W Reg_Gpio_WType; struct Reg_I2c_Bf { uint32 zResverd0x00; struct { uint32 I2C_SUPPORT_SPEED : 2; uint32 DMA_SUPPORT : 1; uint32 TXFIFO_DEPTH : 4; uint32 RXFIFO_DEPTH : 4; uint32 RSVD_31_11 : 21; } I2C_PARAMETER; struct { uint32 MODULE_EN : 1; uint32 SLAVE_ACK_GENCALL : 1; uint32 SLAVE_NACK : 1; uint32 SDA_RECOVER_EN : 1; uint32 MASTER_ABORT : 1; uint32 MASTER_BUS_RECOVER_EN : 1; uint32 MASTER_BLK_TXFIFO : 1; uint32 H_MCODE : 3; uint32 RSVD_31_10 : 22; } I2C_CONFIG0; struct { uint32 SLAVE_MODE_DIS : 1; uint32 MASTER_MODE_EN : 1; uint32 MASTER_RESTART_EN : 1; uint32 SLAVE_STOP_DET_EN : 1; uint32 MASTER_STOP_DET_EN : 1; uint32 TXFIFO_EMPTY_EN : 1; uint32 SPEED_SEL : 2; uint32 HOLD_EN_RXFIFO_FULL : 1; uint32 SLAVE_10BIT_ADDR_SEL : 1; uint32 MASTER_10BIT_ADDR_SEL : 1; uint32 RSVD_31_11 : 21; } I2C_CONFIG1; struct { uint32 SDA_SETUP_TIMING : 8; uint32 RSVD_31_8 : 24; } I2C_SDA_SETUP_TIMING; struct { uint32 SDA_TX_HOLD_TIMING : 16; uint32 SDA_RX_HOLD_TIMING : 8; uint32 RSVD_31_24 : 8; } I2C_SDA_HOLD_TIMING; struct { uint32 RXFIFO_DMA_EN : 1; uint32 TXFIFO_DMA_EN : 1; uint32 DMA_TXFIFO_WATERMARK : 2; uint32 DMA_RXFIFO_WATERMARK : 2; uint32 RSVD_31_6 : 26; } I2C_DMA_CTRL; struct { uint32 I2C_CALL_IE : 1; uint32 I2C_TX_OVF_IE : 1; uint32 I2C_ERROR_ABORT_IE : 1; uint32 I2C_ACTIVITY_DET_IE : 1; uint32 I2C_STOP_DET_IE : 1; uint32 I2C_START_DET_IE : 1; uint32 RSVD_21_6 : 16; uint32 SLAVE_RD_REQ_IE : 1; uint32 RX_DONE_IE : 1; uint32 RX_UNDER_IE : 1; uint32 RX_OVF_IE : 1; uint32 RESTART_DET_IE : 1; uint32 SCL_STUCK_AT_LOW_IE : 1; uint32 RSVD_29_28 : 2; uint32 RX_FULL_IE : 1; uint32 TX_EMPTY_IE : 1; } I2C_INT_ENABLE; struct { uint32 DATA : 8; uint32 CMD_MASTER_DIRECTION : 1; uint32 CMD_STOP : 1; uint32 CMD_RESTART : 1; uint32 RSVD_31_11 : 21; } I2C_COMMAND_DATA; struct { uint32 DEST_ADDR : 10; uint32 MASTER_CMD_SEL : 2; uint32 RSVD_31_12 : 20; } I2C_DEST_ADDR; struct { uint32 SLV_ADDR : 10; uint32 RSVD_31_10 : 22; } I2C_SLAVE_ADDR; struct { uint32 STD_SCL_HCNT : 16; uint32 RSVD_31_16 : 16; } I2C_STD_SCL_HCNT; struct { uint32 STD_SCL_LCNT : 16; uint32 RSVD_31_16 : 16; } I2C_STD_SCL_LCNT; struct { uint32 FST_SCL_HCNT : 16; uint32 RSVD_31_16 : 16; } I2C_FST_SCL_HCNT; struct { uint32 FST_SCL_LCNT : 16; uint32 RSVD_31_16 : 16; } I2C_FST_SCL_LCNT; struct { uint32 HS_SCL_HCNT : 16; uint32 RSVD_31_16 : 16; } I2C_HS_SCL_HCNT; struct { uint32 HS_SCL_LCNT : 16; uint32 RSVD_31_16 : 16; } I2C_HS_SCL_LCNT; struct { uint32 RXFIFO_WATER_MARK : 2; uint32 RSVD_31_2 : 30; } I2C_RXFIFO_WATER_MARK; struct { uint32 TXFIFO_WATER_MARK : 2; uint32 RSVD_31_2 : 30; } I2C_TXFIFO_WATER_MARK; struct { uint32 TX_FIFO_CNT : 3; uint32 RSVD_31_3 : 29; } I2C_TX_FIFO_CNT; struct { uint32 RX_FIFO_CNT : 3; uint32 RSVD_31_3 : 29; } I2C_RX_FIFO_CNT; struct { uint32 FSTD_SPKLEN : 8; uint32 RSVD_31_8 : 24; } I2C_FSTD_SPKCNT; struct { uint32 HS_SPKLEN : 8; uint32 RSVD_31_8 : 24; } I2C_HS_SPKCNT; struct { uint32 GENERAL_CALL : 1; uint32 TXFIFO_OVERUN : 1; uint32 ERROR_ABORT : 1; uint32 ACTIVITY : 1; uint32 STOP_DETECT : 1; uint32 START_DETECT : 1; uint32 RSVD_21_6 : 16; uint32 SLAVE_READ_REQ : 1; uint32 RXFIFO_DONE : 1; uint32 RXFIFO_UNDERUN : 1; uint32 RXFIFO_OVERUN : 1; uint32 RESTART_DET : 1; uint32 SCL_STUCK_AT_LOW : 1; uint32 RSVD_29_28 : 2; uint32 RXFIFO_FULL : 1; uint32 TXFIFO_EMPTY : 1; } I2C_STATUS0; struct { uint32 MASTER_IS_ACTIVE : 1; uint32 SLAVE_IS_ACTIVE : 1; uint32 TXFIFO_EMPTY_MASTER_HOLD : 1; uint32 TXFIFO_EMPTY_SLAVE_HOLD : 1; uint32 RXFIFO_FULL_MASTER_HOLD : 1; uint32 RXFIFO_FULL_SLAVE_HOLD : 1; uint32 TXFIO_IS_NOT_FULL : 1; uint32 TXFIFO_IS_EMPTY : 1; uint32 RXFIFO_IS_NOT_EMPTY : 1; uint32 RXFIO_IS_FULL : 1; uint32 SDA_ERR_RECOVER_STUCK_LOW : 1; uint32 SLAVE_IS_DISABLED_UNDER_ACT : 1; uint32 SLAVE_RX_DATA_DISCARD : 1; uint32 I2C_IS_ENABLE : 1; uint32 RSVD_31_14 : 18; } I2C_STATUS1; struct { uint32 ERR_GEN_CALL_NO_ACK : 1; uint32 ERR_GEN_CALL_READ : 1; uint32 ERR_START_BYTE_ACK_DET : 1; uint32 ERR_SBYTE_NORSTRT : 1; uint32 ERR_H_NO_RSTRT : 1; uint32 ERR_H_MCODE_ACK_DET : 1; uint32 ERR_7BIT_ADDR_NO_ACK : 1; uint32 ERR_10BIT_ADDR1_NO_ACK : 1; uint32 ERR_10BIT_ADDR2_NO_ACK : 1; uint32 ERR_10BIT_READ_NO_RSTRT : 1; uint32 ERR_DATA_NO_ACK : 1; uint32 ERR_MASTER_ABRT : 1; uint32 ERR_MASTER_DIS : 1; uint32 ERR_SLAVE_ARBLOST : 1; uint32 ERR_MASTER_LOST : 1; uint32 ERR_SLAVE_READ_REQ : 1; uint32 ERR_SLAVE_FLUSH_TXFIFO : 1; uint32 ERR_SDA_LOW_TIMEOUT : 1; uint32 ERR_TXFIFO_FLUSH_CNT : 3; uint32 RSVD_31_21 : 11; } I2C_ERROR_STATUS; struct { uint32 SCL_LOW_TIMEOUT : 32; } I2C_SCL_LOW_TIMEOUT; struct { uint32 SDA_LOW_TIMEOUT : 32; } I2C_SDA_LOW_TIMEOUT; struct { uint32 CLR_ERR : 1; uint32 RSVD_31_1 : 31; } I2C_RD_CLR_ERR_STATUS; }; struct Reg_I2c_W { uint32 zResverd0x00; uint32 I2C_PARAMETER; uint32 I2C_CONFIG0; uint32 I2C_CONFIG1; uint32 I2C_SDA_SETUP_TIMING; uint32 I2C_SDA_HOLD_TIMING; uint32 I2C_DMA_CTRL; uint32 I2C_INT_ENABLE; uint32 I2C_COMMAND_DATA; uint32 I2C_DEST_ADDR; uint32 I2C_SLAVE_ADDR; uint32 I2C_STD_SCL_HCNT; uint32 I2C_STD_SCL_LCNT; uint32 I2C_FST_SCL_HCNT; uint32 I2C_FST_SCL_LCNT; uint32 I2C_HS_SCL_HCNT; uint32 I2C_HS_SCL_LCNT; uint32 I2C_RXFIFO_WATER_MARK; uint32 I2C_TXFIFO_WATER_MARK; uint32 I2C_TX_FIFO_CNT; uint32 I2C_RX_FIFO_CNT; uint32 I2C_FSTD_SPKCNT; uint32 I2C_HS_SPKCNT; uint32 I2C_STATUS0; uint32 I2C_STATUS1; uint32 I2C_ERROR_STATUS; uint32 I2C_SCL_LOW_TIMEOUT; uint32 I2C_SDA_LOW_TIMEOUT; uint32 I2C_RD_CLR_ERR_STATUS; }; typedef volatile struct Reg_I2c_Bf Reg_I2c_BfType; typedef volatile struct Reg_I2c_W Reg_I2c_WType; struct Reg_I2s_Bf { struct { uint32 I2S_MODULE_EN : 1; uint32 I2S_TE : 1; uint32 I2S_RE : 1; uint32 I2S_TXFIFO_RESET : 1; uint32 I2S_RXFIFO_RESET : 1; uint32 RSVD_31_5 : 27; } I2S_CONTROL; struct { uint32 I2S_MASTER_EN : 1; uint32 I2S_NUM_BCLK : 2; uint32 RSVD_4_3 : 2; uint32 I2S_NUM_BCLK_GATE : 3; uint32 MCK_DIV : 8; uint32 RSVD_31_16 : 16; } I2S_MASTER_CONFIG; struct { struct { uint32 LEFT_DATA : 32; } I2S_CHn_LEFT_DATA; struct { uint32 RIGHT_DATA : 32; } I2S_CHn_RIGHT_DATA; struct { uint32 TX_EN : 1; uint32 RX_EN : 1; uint32 TX_AUDIO_RESOLUTION : 3; uint32 RX_AUDIO_RESOLUTION : 3; uint32 RSVD_31_8 : 24; } I2S_CHn_CFG; struct { uint32 RXFIFO_AVAILABLE_IE : 1; uint32 RXFIFO_OVERUN_IE : 1; uint32 TXFIFO_EMPTY_IE : 1; uint32 TXFIFO_OVERUN_IE : 1; uint32 RXFIFO_DAF : 1; uint32 RXFIFO_ORF : 1; uint32 TXFIFO_EMPTYF : 1; uint32 TXFIFO_ORF : 1; uint32 RSVD_31_8 : 24; } I2S_CHn_INT_CFG; struct { uint32 RXFIFO_FULL_TRIG_LEV : 4; uint32 TXFIFO_EMPTY_TRIG_LEV : 4; uint32 CH_TXFIFO_RESET : 1; uint32 CH_RXFIFO_RESET : 1; uint32 RSVD_31_10 : 22; } I2S_CHn_TRIGGER_LEVEL_CFG; } I2S_CHANNEL_REG[4]; struct { uint32 CYCLE_TX_DATA : 32; } I2S_CYCLE_TX_DATA; struct { uint32 CYCLE_TX_RESET : 1; uint32 RSVD_31_1 : 31; } I2S_CYCLE_TX_RESET; struct { uint32 CYCLE_RX_DATA : 32; } I2S_CYCLE_RX_DATA; struct { uint32 CYCLE_RX_RESET : 1; uint32 RSVD_31_1 : 31; } I2S_CYCLE_RX_RESET; }; struct Reg_I2s_W { uint32 I2S_CONTROL; uint32 I2S_MASTER_CONFIG; struct { uint32 I2S_CHn_LEFT_DATA; uint32 I2S_CHn_RIGHT_DATA; uint32 I2S_CHn_CFG; uint32 I2S_CHn_INT_CFG; uint32 I2S_CHn_TRIGGER_LEVEL_CFG; } I2S_CHANNEL_REG[4]; uint32 I2S_CYCLE_TX_DATA; uint32 I2S_CYCLE_TX_RESET; uint32 I2S_CYCLE_RX_DATA; uint32 I2S_CYCLE_RX_RESET; }; typedef volatile struct Reg_I2s_Bf Reg_I2s_BfType; typedef volatile struct Reg_I2s_W Reg_I2s_WType; struct Reg_Mcpwm_Bf { struct { uint32 CKSRC : 2; uint32 PSDIV : 3; uint32 DBGM : 2; uint32 RSVD_31_7 : 25; } MCPWM_TIMEBASE; struct { uint32 CNT : 16; uint32 RSVD_31_16 : 16; } MCPWM_CNTn[4]; struct { uint32 MOD : 16; uint32 RSVD_31_16 : 16; } MCPWM_MODn[4]; struct { uint32 DTVAL : 12; uint32 RSVD_31_12 : 20; } MCPWM_DTVALn[4]; struct { uint32 CHOE0 : 1; uint32 CHOE1 : 1; uint32 CHOE2 : 1; uint32 CHOE3 : 1; uint32 CHOE4 : 1; uint32 CHOE5 : 1; uint32 CHOE6 : 1; uint32 CHOE7 : 1; uint32 CNTM0 : 1; uint32 CNTM1 : 1; uint32 CNTM2 : 1; uint32 CNTM3 : 1; uint32 CNTEN0 : 1; uint32 CNTEN1 : 1; uint32 CNTEN2 : 1; uint32 CNTEN3 : 1; uint32 RLDIE0 : 1; uint32 RLDIE1 : 1; uint32 RLDIE2 : 1; uint32 RLDIE3 : 1; uint32 TOIE0 : 1; uint32 TOIE1 : 1; uint32 TOIE2 : 1; uint32 TOIE3 : 1; uint32 RSVD_29_24 : 6; uint32 WPEN : 1; uint32 GLBCNTEN : 1; } MCPWM_GLBCR; struct { uint32 CH0F : 1; uint32 CH1F : 1; uint32 CH2F : 1; uint32 CH3F : 1; uint32 CH4F : 1; uint32 CH5F : 1; uint32 CH6F : 1; uint32 CH7F : 1; uint32 RLDF0 : 1; uint32 RLDF1 : 1; uint32 RLDF2 : 1; uint32 RLDF3 : 1; uint32 TOF0 : 1; uint32 TOF1 : 1; uint32 TOF2 : 1; uint32 TOF3 : 1; uint32 WPDIS : 1; uint32 RSVD_31_17 : 15; } MCPWM_GLBSR; struct { uint32 CPP : 1; uint32 RSVD_3_1 : 3; uint32 CHIE : 1; uint32 CHF : 1; uint32 DMA : 1; uint32 RSVD_31_7 : 25; } MCPWM_CFGn[8]; struct { uint32 CV : 16; uint32 RSVD_31_16 : 16; } MCPWM_CVn[8]; struct { uint32 POL0 : 1; uint32 POL1 : 1; uint32 POL2 : 1; uint32 POL3 : 1; uint32 POL4 : 1; uint32 POL5 : 1; uint32 POL6 : 1; uint32 POL7 : 1; uint32 OFFVAL0 : 1; uint32 OFFVAL1 : 1; uint32 OFFVAL2 : 1; uint32 OFFVAL3 : 1; uint32 OFFVAL4 : 1; uint32 OFFVAL5 : 1; uint32 OFFVAL6 : 1; uint32 OFFVAL7 : 1; uint32 RSVD_31_16 : 16; } MCPWM_OUTCR; struct { uint32 TRIGE0 : 1; uint32 TRIGE1 : 1; uint32 TRIGE2 : 1; uint32 TRIGE3 : 1; uint32 TRIGE4 : 1; uint32 TRIGE5 : 1; uint32 TRIGE6 : 1; uint32 TRIGE7 : 1; uint32 INITRIGE : 1; uint32 TRIGF : 1; uint32 RSVD_31_10 : 22; } MCPWM_OUTTRIG; struct { uint32 CH0OC : 1; uint32 CH1OC : 1; uint32 CH2OC : 1; uint32 CH3OC : 1; uint32 CH4OC : 1; uint32 CH5OC : 1; uint32 CH6OC : 1; uint32 CH7OC : 1; uint32 CH0OCV : 1; uint32 CH1OCV : 1; uint32 CH2OCV : 1; uint32 CH3OCV : 1; uint32 CH4OCV : 1; uint32 CH5OCV : 1; uint32 CH6OCV : 1; uint32 CH7OCV : 1; uint32 RSVD_31_16 : 16; } MCPWM_OUTSWCR; struct { uint32 FCTLEN0 : 1; uint32 DTEN0 : 1; uint32 SYNCEN0 : 1; uint32 ASYMEN0 : 1; uint32 CVSEL0 : 1; uint32 PEC0 : 1; uint32 COMB0 : 1; uint32 RSVD_7 : 1; uint32 FCTLEN1 : 1; uint32 DTEN1 : 1; uint32 SYNCEN1 : 1; uint32 ASYMEN1 : 1; uint32 CVSEL1 : 1; uint32 PEC1 : 1; uint32 COMB1 : 1; uint32 RSVD_15 : 1; uint32 FCTLEN2 : 1; uint32 DTEN2 : 1; uint32 SYNCEN2 : 1; uint32 ASYMEN2 : 1; uint32 CVSEL2 : 1; uint32 PEC2 : 1; uint32 COMB2 : 1; uint32 RSVD_23 : 1; uint32 FCTLEN3 : 1; uint32 DTEN3 : 1; uint32 SYNCEN3 : 1; uint32 ASYMEN3 : 1; uint32 CVSEL3 : 1; uint32 PEC3 : 1; uint32 COMB3 : 1; uint32 RSVD_31 : 1; } MCPWM_PCR; struct { uint32 FIFEN0 : 1; uint32 FIFEN1 : 1; uint32 FIFEN2 : 1; uint32 FIFEN3 : 1; uint32 FLTEN0 : 1; uint32 FLTEN1 : 1; uint32 FLTEN2 : 1; uint32 FLTEN3 : 1; uint32 FLTPOL0 : 1; uint32 FLTPOL1 : 1; uint32 FLTPOL2 : 1; uint32 FLTPOL3 : 1; uint32 FLTIE : 1; uint32 FLTCM : 1; uint32 RSVD_15_14 : 2; uint32 FIFVAL : 4; uint32 FSTATE : 1; uint32 RSVD_31_21 : 11; } MCPWM_FLTCR; struct { uint32 FAULTF0 : 1; uint32 FAULTF1 : 1; uint32 FAULTF2 : 1; uint32 FAULTF3 : 1; uint32 FAULTFA : 1; uint32 FAULTFB : 1; uint32 FAULTINA : 1; uint32 FAULTINB : 1; uint32 RSVD_31_8 : 24; } MCPWM_FLTSR; struct { uint32 FLTASS0 : 1; uint32 FLTASS1 : 1; uint32 FLTASS2 : 1; uint32 FLTASS3 : 1; uint32 FLTASS4 : 1; uint32 FLTASS5 : 1; uint32 FLTASS6 : 1; uint32 FLTASS7 : 1; uint32 RSVD_31_8 : 24; } MCPWM_FLTASS; struct { uint32 FLTBSS0 : 1; uint32 FLTBSS1 : 1; uint32 FLTBSS2 : 1; uint32 FLTBSS3 : 1; uint32 FLTBSS4 : 1; uint32 FLTBSS5 : 1; uint32 FLTBSS6 : 1; uint32 FLTBSS7 : 1; uint32 RSVD_31_8 : 24; } MCPWM_FLTBSS; struct { uint32 SWTRIG : 1; uint32 SYNCOSWC : 1; uint32 SWWRBUF : 1; uint32 SWRSTCNT : 1; uint32 RSVD_31_4 : 28; } MCPWM_SYNC; struct { uint32 CPWMFCR0 : 1; uint32 CPWMFCR1 : 1; uint32 CPWMFCR2 : 1; uint32 CPWMFCR3 : 1; uint32 CPWMHCR0 : 1; uint32 CPWMHCR1 : 1; uint32 CPWMHCR2 : 1; uint32 CPWMHCR3 : 1; uint32 LOADEN0 : 1; uint32 LOADEN1 : 1; uint32 LOADEN2 : 1; uint32 LOADEN3 : 1; uint32 RSVD_31_12 : 20; } MCPWM_RELOAD; struct { uint32 LDFREQ0 : 5; uint32 RSVD_7_5 : 3; uint32 LDFREQ1 : 5; uint32 RSVD_15_13 : 3; uint32 LDFREQ2 : 5; uint32 RSVD_23_21 : 3; uint32 LDFREQ3 : 5; uint32 RSVD_31_29 : 3; } MCPWM_LDFREQ; uint8 zResverd0x0A8[88]; struct { uint32 MOD_DITHER : 5; uint32 RSVD_31_5 : 27; } MCPWM_MODn_DITHER[4]; struct { uint32 CV_DITHER : 5; uint32 RSVD_31_5 : 27; } MCPWM_CVn_DITHER[8]; }; struct Reg_Mcpwm_W { uint32 MCPWM_TIMEBASE; uint32 MCPWM_CNTn[4]; uint32 MCPWM_MODn[4]; uint32 MCPWM_DTVALn[4]; uint32 MCPWM_GLBCR; uint32 MCPWM_GLBSR; uint32 MCPWM_CFGn[8]; uint32 MCPWM_CVn[8]; uint32 MCPWM_OUTCR; uint32 MCPWM_OUTTRIG; uint32 MCPWM_OUTSWCR; uint32 MCPWM_PCR; uint32 MCPWM_FLTCR; uint32 MCPWM_FLTSR; uint32 MCPWM_FLTASS; uint32 MCPWM_FLTBSS; uint32 MCPWM_SYNC; uint32 MCPWM_RELOAD; uint32 MCPWM_LDFREQ; uint8 zResverd0x0A8[88]; uint32 MCPWM_MODn_DITHER[4]; uint32 MCPWM_CVn_DITHER[8]; }; typedef volatile struct Reg_Mcpwm_Bf Reg_Mcpwm_BfType; typedef volatile struct Reg_Mcpwm_W Reg_Mcpwm_WType; struct Reg_Parcc_Bf { struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_WDOG; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_EWDT; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_STIM; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_TIM0; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_TIM1; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_TIM2; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_TIM3; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_MCPWM0; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_MCPWM1; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_TDG0; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_TDG1; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CAN0; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CAN1; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CAN2; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CAN3; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CAN4; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CAN5; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CAN6; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CAN7; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_UART0; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_UART1; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_UART2; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_UART3; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_UART4; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_UART5; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_SPI0; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_SPI1; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_SPI2; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_SPI3; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_I2C0; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_I2C1; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_I2S0; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_I2S1; uint32 zResverd0x84; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_ADC0; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_ADC1; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CMP0; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CRC; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_AES; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_TRNG; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 RSVD_16 : 1; uint32 RSVD_19_17 : 3; uint32 RSVD_20 : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_FLASH; uint32 zResverd0xA4; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_DMA; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_DMAMUX; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_PORTA; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_PORTB; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_PORTC; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_PORTD; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_PORTE; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_TMU; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_REGFILE; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_SMPU; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_GPIO; }; struct Reg_Parcc_W { uint32 PARCC_WDOG; uint32 PARCC_EWDT; uint32 PARCC_STIM; uint32 PARCC_TIM0; uint32 PARCC_TIM1; uint32 PARCC_TIM2; uint32 PARCC_TIM3; uint32 PARCC_MCPWM0; uint32 PARCC_MCPWM1; uint32 PARCC_TDG0; uint32 PARCC_TDG1; uint32 PARCC_CAN0; uint32 PARCC_CAN1; uint32 PARCC_CAN2; uint32 PARCC_CAN3; uint32 PARCC_CAN4; uint32 PARCC_CAN5; uint32 PARCC_CAN6; uint32 PARCC_CAN7; uint32 PARCC_UART0; uint32 PARCC_UART1; uint32 PARCC_UART2; uint32 PARCC_UART3; uint32 PARCC_UART4; uint32 PARCC_UART5; uint32 PARCC_SPI0; uint32 PARCC_SPI1; uint32 PARCC_SPI2; uint32 PARCC_SPI3; uint32 PARCC_I2C0; uint32 PARCC_I2C1; uint32 PARCC_I2S0; uint32 PARCC_I2S1; uint32 zResverd0x84; uint32 PARCC_ADC0; uint32 PARCC_ADC1; uint32 PARCC_CMP0; uint32 PARCC_CRC; uint32 PARCC_AES; uint32 PARCC_TRNG; uint32 PARCC_FLASH; uint32 zResverd0xA4; uint32 PARCC_DMA; uint32 PARCC_DMAMUX; uint32 PARCC_PORTA; uint32 PARCC_PORTB; uint32 PARCC_PORTC; uint32 PARCC_PORTD; uint32 PARCC_PORTE; uint32 PARCC_TMU; uint32 PARCC_REGFILE; uint32 PARCC_SMPU; uint32 PARCC_GPIO; }; typedef volatile struct Reg_Parcc_Bf Reg_Parcc_BfType; typedef volatile struct Reg_Parcc_W Reg_Parcc_WType; struct Reg_Pmu_Bf { struct { uint32 RSVD_30_0 : 31; uint32 LOCK : 1; } PMU_LOCK; struct { uint32 LPO_CLK_DIS : 1; uint32 RSVD_1 : 1; uint32 LPO_CLK_READY : 1; uint32 RSVD_31_3 : 29; } PMU_LPO_32K_CFG; uint8 zResverd0x08[4]; struct { uint32 ISO_CLR : 1; uint32 RSVD_31_1 : 31; } PMU_ISO_CLR; struct { uint32 VDD_LVD_LP_EN : 1; uint32 VDD_LVD_ACT_EN : 1; uint32 VDD_LVD_IE : 1; uint32 VDD_LVD_RE : 1; uint32 VDD_LVW_EN : 1; uint32 VDD_LVW_IE : 1; uint32 LVWF_VDD : 1; uint32 LVDF_VDD : 1; uint32 REF_BUF_1V_EN : 1; uint32 RSVD_31_9 : 23; } PMU_CSR; struct { uint32 LDO_CORE_EN : 1; uint32 LDO_CLOCK_EN : 1; uint32 LDO_FLASH_EN : 1; uint32 RSVD_3 : 1; uint32 LDO_CORE_LPEN : 1; uint32 LDO_CLOCK_LPEN : 1; uint32 LDO_FLASH_LPEN : 1; uint32 RSVD_31_7 : 25; } PMU_LDO_EN_CFG; struct { uint32 LVD_CORE_FLAG : 1; uint32 LVD_CLOCK_FLAG : 1; uint32 LVD_FLASH_FLAG : 1; uint32 RSVD_3 : 1; uint32 LVD_AOA_FLAG : 1; uint32 RSVD_31_5 : 27; } PMU_LDO_LVD_STATUS; struct { uint32 LVD_CORE_RE : 1; uint32 LVD_CLOCK_RE : 1; uint32 LVD_FLASH_RE : 1; uint32 RSVD_3 : 1; uint32 LVD_AOA_RE : 1; uint32 ACT_CORE_LVDE : 1; uint32 ACT_CLOCK_LVDE : 1; uint32 RSVD_8_7 : 2; uint32 ACT_AOA_LVDE : 1; uint32 LP_CORE_LVDE : 1; uint32 LP_CLOCK_LVDE : 1; uint32 RSVD_13_12 : 2; uint32 LP_AOA_LVDE : 1; uint32 RSVD_31_15 : 17; } PMU_LDO_LVD_CFG; }; struct Reg_Pmu_W { uint32 PMU_LOCK; uint32 PMU_LPO_32K_CFG; uint8 zResverd0x08[4]; uint32 PMU_ISO_CLR; uint32 PMU_CSR; uint32 PMU_LDO_EN_CFG; uint32 PMU_LDO_LVD_STATUS; uint32 PMU_LDO_LVD_CFG; }; typedef volatile struct Reg_Pmu_Bf Reg_Pmu_BfType; typedef volatile struct Reg_Pmu_W Reg_Pmu_WType; struct Reg_Port_Bf { uint8 zResverd0x0[8]; struct { uint32 GPWD : 32; } PORTx_GLBDAT; struct { uint32 GPWE : 32; } PORTx_GLBCTL; struct { uint32 PS : 1; uint32 PE : 1; uint32 RSVD_2 : 1; uint32 SRE : 1; uint32 PFE : 1; uint32 ODE : 1; uint32 RSVD_7_6 : 2; uint32 MUX : 3; uint32 RSVD_14_11 : 4; uint32 LK : 1; uint32 IRQC : 4; uint32 RSVD_22_20 : 3; uint32 ISF : 1; uint32 FLT : 5; uint32 RSVD_30_29 : 2; uint32 FLTEN : 1; } PORTx_PCRn[32]; struct { uint32 ISF : 32; } PORTx_IRQFLG; }; struct Reg_Port_W { uint8 zResverd0x0[8]; uint32 PORTx_GLBDAT; uint32 PORTx_GLBCTL; uint32 PORTx_PCRn[32]; uint32 PORTx_IRQFLG; }; typedef volatile struct Reg_Port_Bf Reg_Port_BfType; typedef volatile struct Reg_Port_W Reg_Port_WType; struct Reg_Regfile_Bf { struct { uint32 DATA : 32; } REGFILE_REGn[32]; }; struct Reg_Regfile_W { uint32 REGFILE_REGn[32]; }; typedef volatile struct Reg_Regfile_Bf Reg_Regfile_BfType; typedef volatile struct Reg_Regfile_W Reg_Regfile_WType; struct Reg_Rtc_Bf { struct { uint32 CRYSTAL_EN : 1; uint32 CNT_CLK_SEL : 1; uint32 CLKOUT_SEL : 1; uint32 CLKOUT_PIN_EN : 1; uint32 SUP_EN : 1; uint32 SW_RST : 1; uint32 COUNT_EN : 1; uint32 OVF : 1; uint32 ALARM_MATCHF : 1; uint32 OSC_RDY : 1; uint32 EXTAL_32K_EN : 1; uint32 SECONDS_INT_FLAG : 1; uint32 PERIODIC_CNT_EN : 1; uint32 PERIODIC_MATCH_FLG : 1; uint32 RSVD_31_14 : 18; } RTC_CSR; struct { uint32 SECOND_INT_MUX_SEL : 3; uint32 OVFLOW_IE : 1; uint32 ALARM_IE : 1; uint32 SECONDS_IE : 1; uint32 PERIODIC_IE : 1; uint32 RSVD_31_7 : 25; } RTC_IER; struct { uint32 ALARM_CNT : 32; } RTC_ALARM_CNTR; struct { uint32 ONE_SECOND_CNT : 16; uint32 RSVD_31_16 : 16; } RTC_ONE_SECOND_CNTR; struct { uint32 MATCH_CNT : 32; } RTC_MATCH_CNTR; struct { uint32 COMP_CNT : 7; uint32 COMP_DIRECTION : 1; uint32 DLY : 8; uint32 CCOMP_CNT : 8; uint32 CDLY : 8; } RTC_COMPENSATIONR; struct { uint32 RSVD_30_0 : 31; uint32 LOCK : 1; } RTC_LOCKR; uint8 zResverd0x01C[4]; struct { uint32 PERIODIC_TMR_CNT : 32; } RTC_PERIODIC_TMR_CNT; struct { uint32 PERIODIC_MATCH_CNT : 32; } RTC_PERIODIC_TMR_MATCH_CNT; }; struct Reg_Rtc_W { uint32 RTC_CSR; uint32 RTC_IER; uint32 RTC_ALARM_CNTR; uint32 RTC_ONE_SECOND_CNTR; uint32 RTC_MATCH_CNTR; uint32 RTC_COMPENSATIONR; uint32 RTC_LOCKR; uint8 zResverd0x01C[4]; uint32 RTC_PERIODIC_TMR_CNT; uint32 RTC_PERIODIC_TMR_MATCH_CNT; }; typedef volatile struct Reg_Rtc_Bf Reg_Rtc_BfType; typedef volatile struct Reg_Rtc_W Reg_Rtc_WType; struct Reg_Scc_Bf { uint32 zResverd0x0; struct { uint32 CLKSPRES : 5; uint32 RSVD_27_5 : 23; uint32 DIVPRES : 3; uint32 RSVD_31 : 1; } SCC_PARAM; struct { uint32 DIVSLOW : 4; uint32 DIVBUS : 4; uint32 DIVCORE : 4; uint32 RSVD_15_12 : 4; uint32 SCS : 3; uint32 RSVD_31_19 : 13; } SCC_CST; struct { uint32 DIVSLOW : 4; uint32 DIVBUS : 4; uint32 DIVCORE : 4; uint32 RSVD_15_12 : 4; uint32 SCS : 3; uint32 RSVD_30_19 : 12; uint32 LOCK : 1; } SCC_CFG; struct { uint32 RSVD_15_0 : 16; uint32 CLKOUTSEL : 4; uint32 RSVD_31_20 : 12; } SCC_CLKOUTCFG; struct { uint32 OSCEN : 1; uint32 OSCSTOPEN : 1; uint32 RSVD_3_2 : 2; uint32 OSCLOCINTEN : 1; uint32 RSVD_8_5 : 4; uint32 OSCCME : 1; uint32 OSCCMRE : 1; uint32 RSVD_15_11 : 5; uint32 OSCRDY : 1; uint32 OSCSELD : 1; uint32 OSCLOC : 1; uint32 RSVD_30_19 : 12; uint32 LOCK : 1; } SCC_OSCCS; struct { uint32 EXCLKS : 1; uint32 OLMEN : 1; uint32 HFREQ : 1; uint32 RSVD_7_3 : 5; uint32 ITRIM : 2; uint32 RSVD_30_10 : 21; uint32 LOCK : 1; } SCC_OSCCFG; struct { uint32 FIRCEN : 1; uint32 FIRCSTOPEN : 1; uint32 RSVD_3_2 : 2; uint32 FIRCLOCINTEN : 1; uint32 RSVD_8_5 : 4; uint32 FIRCCME : 1; uint32 FIRCCMRE : 1; uint32 RSVD_11 : 1; uint32 RSVD_12 : 1; uint32 RSVD_15_13 : 3; uint32 FIRCRDY : 1; uint32 FIRCSELD : 1; uint32 FIRCLOC : 1; uint32 RSVD_30_19 : 12; uint32 LOCK : 1; } SCC_FIRCCS; uint8 zResverd0x020[8]; struct { uint32 SPLLEN : 1; uint32 SPLLSTOPEN : 1; uint32 RSVD_3_2 : 2; uint32 RSVD_4 : 1; uint32 RSVD_8_5 : 4; uint32 RDYEN : 1; uint32 RSVD_10 : 1; uint32 RSVD_11 : 1; uint32 LOCKWIN : 2; uint32 RSVD_15_14 : 2; uint32 SPLLRDY : 1; uint32 SPLLSELD : 1; uint32 RSVD_18 : 1; uint32 RSVD_24_19 : 6; uint32 OUTEN : 1; uint32 RSVD_30_26 : 5; uint32 LOCK : 1; } SCC_SPLLCS; struct { uint32 PREDIV : 2; uint32 RSVD_3_2 : 2; uint32 FBPRESEN : 1; uint32 REFCKS : 1; uint32 RSVD_7_6 : 2; uint32 MULT : 8; uint32 POSTDIV : 3; uint32 RSVD_30_19 : 12; uint32 LOCK : 1; } SCC_SPLLCFG1; struct { uint32 CPIR : 2; uint32 CPIC : 2; uint32 CS : 2; uint32 CAP : 2; uint32 RES : 3; uint32 KVCO : 1; uint32 VCODIV : 1; uint32 PFDDIEN : 1; uint32 CPISEL : 1; uint32 RSVD_15 : 1; uint32 RSVD_23_16 : 8; uint32 LDOODEN : 1; uint32 RSVD_30_25 : 6; uint32 LOCK : 1; } SCC_SPLLCFG2; }; struct Reg_Scc_W { uint32 zResverd0x0; uint32 SCC_PARAM; uint32 SCC_CST; uint32 SCC_CFG; uint32 SCC_CLKOUTCFG; uint32 SCC_OSCCS; uint32 SCC_OSCCFG; uint32 SCC_FIRCCS; uint8 zResverd0x020[8]; uint32 SCC_SPLLCS; uint32 SCC_SPLLCFG1; uint32 SCC_SPLLCFG2; }; typedef volatile struct Reg_Scc_Bf Reg_Scc_BfType; typedef volatile struct Reg_Scc_W Reg_Scc_WType; struct Reg_Scm_Bf { struct { uint32 RSVD_3_0 : 4; uint32 CLKOUTSEL : 2; uint32 RSVD_7_6 : 2; uint32 CLKOUTDIV : 3; uint32 CLKOUTEN : 1; uint32 RSVD_31_12 : 20; } SCM_CHIPCTL; struct { uint32 SWTRIG0 : 1; uint32 SWTRIG1 : 1; uint32 SWTRIG2 : 1; uint32 SWTRIG3 : 1; uint32 SRAML_READ_BUFF_EN : 1; uint32 SRAMU_READ_BUFF_EN : 1; uint32 XBAR_ROUND_ROBIN : 1; uint32 RSVD_7 : 1; uint32 RSVD_8 : 1; uint32 RSVD_9 : 1; uint32 RSVD_10 : 1; uint32 CCACHE_CLR : 1; uint32 CCACHE_PARITY_MISS_EN : 1; uint32 CCACHE_PARITY_FAULT_EN : 1; uint32 CACHE_DIS : 1; uint32 RSVD_15 : 1; uint32 CCACHE_BE_INT_EN : 1; uint32 RSVD_23_17 : 7; uint32 FPU_INEXACT_INT_EN : 1; uint32 FPU_OVERFLOW_INT_EN : 1; uint32 FPU_UNDERFLOW_INT_EN : 1; uint32 FPU_INVALIDOP_INT_EN : 1; uint32 FPU_DIVZERO_INT_EN : 1; uint32 FPU_DENORMALIN_INT_EN : 1; uint32 RSVD_31_30 : 2; } SCM_MISCCTL1; uint8 zResverd0x08[32]; struct { uint32 RSVD_7_0 : 8; uint32 MCPWM0_TCLK_SEL : 2; uint32 MCPWM1_TCLK_SEL : 2; uint32 TIM0_TCLK_SEL : 2; uint32 TIM1_TCLK_SEL : 2; uint32 TIM2_TCLK_SEL : 2; uint32 TIM3_TCLK_SEL : 2; uint32 RSVD_23_20 : 4; uint32 ADC0_CH8_SEL : 1; uint32 ADC0_CH9_SEL : 1; uint32 ADC1_CH14_SEL : 1; uint32 ADC1_CH15_SEL : 1; uint32 RSVD_31_28 : 4; } SCM_MISCCTL2; uint8 zResverd0x02C[20]; struct { uint32 RSVD_14_0 : 15; uint32 RSVD_15 : 1; uint32 CCACHE_BE_FLAG : 8; uint32 FPU_INEXACT_FLAG : 1; uint32 FPU_OVERFLOW_FLAG : 1; uint32 FPU_UNDERFLOW_FLAG : 1; uint32 FPU_INVALIDOP_FLAG : 1; uint32 FPU_DIVZERO_FLAG : 1; uint32 FPU_DENORMALIN_FLAG : 1; uint32 RSVD_31_30 : 2; } SCM_MISCSTAT1; struct { uint32 CACHE_BE_ADDR : 32; } SCM_MISCDATA1; struct { uint32 CACHE_BE_DATA : 32; } SCM_MISCDATA2; uint8 zResverd0x04C[180]; struct { uint32 CCACHE_DIS_IFR : 1; uint32 FPU_DIS : 1; uint32 RSVD_31_2 : 30; } SCM_CHIPOPT; struct { uint32 RSVD_23_0 : 24; uint32 PFSIZE : 4; uint32 DFSIZE : 4; } SCM_FLSCFG; struct { uint32 CACHESIZE : 4; uint32 RSVD_27_4 : 24; uint32 RAMSIZE : 4; } SCM_RAMCFG; uint8 zResverd0x010C[16]; struct { uint32 MEMSIZE_ID : 4; uint32 SERIES_ID : 3; uint32 SUBFAMILY_ID : 5; uint32 FAMILY_ID : 4; uint32 REV_ID : 4; uint32 FEATURE_ID : 7; uint32 PACKAGE_ID : 5; } SCM_DEVID; struct { uint32 UID_31_0 : 32; } SCM_UNIQUE0; struct { uint32 UID_63_32 : 32; } SCM_UNIQUE1; struct { uint32 UID_95_64 : 32; } SCM_UNIQUE2; struct { uint32 UID_127_96 : 32; } SCM_UNIQUE3; }; struct Reg_Scm_W { uint32 SCM_CHIPCTL; uint32 SCM_MISCCTL1; uint8 zResverd0x08[32]; uint32 SCM_MISCCTL2; uint8 zResverd0x02C[20]; uint32 SCM_MISCSTAT1; uint32 SCM_MISCDATA1; uint32 SCM_MISCDATA2; uint8 zResverd0x04C[180]; uint32 SCM_CHIPOPT; uint32 SCM_FLSCFG; uint32 SCM_RAMCFG; uint8 zResverd0x010C[16]; uint32 SCM_DEVID; uint32 SCM_UNIQUE0; uint32 SCM_UNIQUE1; uint32 SCM_UNIQUE2; uint32 SCM_UNIQUE3; }; typedef volatile struct Reg_Scm_Bf Reg_Scm_BfType; typedef volatile struct Reg_Scm_W Reg_Scm_WType; struct Reg_Seru_Bf { uint32 zResverd0x0; struct { uint32 PARAM : 32; } SERU_PARAM; struct { uint32 CRPAR_INT_EN : 1; uint32 RSVD_3_1 : 3; uint32 EOUT_PS : 1; uint32 EOUT0_IO_EN : 1; uint32 EOUT1_IO_EN : 1; uint32 FFI_EN : 1; uint32 CFG_MODE : 1; uint32 RSVD_31_9 : 23; } SERU_CSR; struct { uint32 S_CRPAR_ERR : 1; uint32 RSVD_31_1 : 31; } SERU_INTF; struct { uint32 KEY : 32; } SERU_CFG_KEY; struct { uint32 CH_FFI_6_0 : 7; uint32 RSVD_7 : 1; uint32 CH_FFI_14_8 : 7; uint32 RSVD_15 : 1; uint32 CH_FFI_16 : 1; uint32 RSVD_31_17 : 15; } SERU_CH_FFI; struct { uint32 SWERR_CH0 : 1; uint32 SWERR_CH1 : 1; uint32 SWERR_CH2 : 1; uint32 RSVD_31_3 : 29; } SERU_SWERR_GNT; struct { uint32 CH_FLAG_6_0 : 7; uint32 RSVD_7 : 1; uint32 CH_FLAG_14_8 : 7; uint32 RSVD_15 : 1; uint32 CH_FLAG_16 : 1; uint32 RSVD_31_17 : 15; } SERU_CH_FLAG; struct { uint32 CH_EN : 1; uint32 CH_INT_CFG : 1; uint32 CH_INT_TYP : 1; uint32 CH_EOUT_CFG : 1; uint32 CH_RESET_CFG : 1; uint32 CH_RESET_TYP : 1; uint32 CH_RESET_DLY : 2; uint32 CH_FLAG : 1; uint32 RSVD_31_9 : 23; } SERU_CFG_CHn[17]; }; struct Reg_Seru_W { uint32 zResverd0x0; uint32 SERU_PARAM; uint32 SERU_CSR; uint32 SERU_INTF; uint32 SERU_CFG_KEY; uint32 SERU_CH_FFI; uint32 SERU_SWERR_GNT; uint32 SERU_CH_FLAG; uint32 SERU_CFG_CHn[17]; }; typedef volatile struct Reg_Seru_Bf Reg_Seru_BfType; typedef volatile struct Reg_Seru_W Reg_Seru_WType; struct Reg_Smpu_Bf { uint32 zResverd0x00; struct { uint32 S0ERR : 1; uint32 S1ERR : 1; uint32 S2ERR : 1; uint32 RSVD_3 : 1; uint32 RSVD_7_4 : 4; uint32 GLBEN : 1; uint32 RSVD_31_9 : 23; } SMPU_CS; uint8 zResverd0x08[8]; struct { uint32 EADDR : 32; } SMPU_Sn_EA[3]; uint8 zResverd0x01C[20]; struct { uint32 EMRC : 16; uint32 RSVD_23_16 : 8; uint32 EMN : 4; uint32 EATTR : 1; uint32 EUS : 1; uint32 RSVD_30 : 1; uint32 ERW : 1; } SMPU_Sn_ES[3]; uint8 zResverd0x03C[196]; struct { struct { uint32 RSVD_4_0 : 5; uint32 SADDR : 27; } SMPU_MRCn_W0; struct { uint32 RSVD_4_0 : 5; uint32 EADDR : 27; } SMPU_MRCn_W1; struct { uint32 M0UX : 1; uint32 M0UW : 1; uint32 M0UR : 1; uint32 M0SM : 2; uint32 RSVD_5 : 1; uint32 M1UX : 1; uint32 M1UW : 1; uint32 M1UR : 1; uint32 M1SM : 2; uint32 RSVD_11 : 1; uint32 M2UX : 1; uint32 M2UW : 1; uint32 M2UR : 1; uint32 M2SM : 2; uint32 RSVD_31_17 : 15; } SMPU_MRCn_W2; struct { uint32 RSVD_15_0 : 16; uint32 EN : 1; uint32 RSVD_31_17 : 15; } SMPU_MRCn_W3; } SMPU_MRCn_W[16]; }; struct Reg_Smpu_W { uint32 zResverd0x00; uint32 SMPU_CS; uint8 zResverd0x08[8]; uint32 SMPU_Sn_EA[3]; uint8 zResverd0x01C[20]; uint32 SMPU_Sn_ES[3]; uint8 zResverd0x03C[196]; struct { uint32 SMPU_MRCn_W0; uint32 SMPU_MRCn_W1; uint32 SMPU_MRCn_W2; uint32 SMPU_MRCn_W3; } SMPU_MRCn_W[16]; }; typedef volatile struct Reg_Smpu_Bf Reg_Smpu_BfType; typedef volatile struct Reg_Smpu_W Reg_Smpu_WType; struct Reg_Spi_Bf { struct { uint32 RSVD_5_0 : 6; uint32 SCPH : 1; uint32 SCPOL : 1; uint32 TMOD : 2; uint32 RSVD_10 : 1; uint32 RSVD_11 : 1; uint32 RSVD_15_12 : 4; uint32 DFS_32 : 5; uint32 MST_MODE : 1; uint32 RSVD_22 : 1; uint32 RSVD_23 : 1; uint32 RSVD_24 : 1; uint32 RSVD_31_25 : 7; } SPI_CTRLR0; struct { uint32 NDF : 16; uint32 RSVD_31_16 : 16; } SPI_CTRLR1; struct { uint32 SPI_EN : 1; uint32 RSVD_15_1 : 15; uint32 SER : 2; uint32 RSVD_31_18 : 14; } SPI_SSENR; struct { uint32 SCKDV : 16; uint32 RSVD_31_16 : 16; } SPI_BAUDR; struct { uint32 TFT : 2; uint32 RSVD_15_2 : 14; uint32 RFT : 2; uint32 RSVD_31_18 : 14; } SPI_FTLR; struct { uint32 TXTFL : 3; uint32 RSVD_15_3 : 13; uint32 RXTFL : 3; uint32 RSVD_31_19 : 13; } SPI_FLR; struct { uint32 BUSY : 1; uint32 TFNF : 1; uint32 TFE : 1; uint32 RFNE : 1; uint32 RFF : 1; uint32 TXE : 1; uint32 RSVD_31_6 : 26; } SPI_SR; struct { uint32 TXEIE : 1; uint32 TXOIE : 1; uint32 RXUIE : 1; uint32 RXOIE : 1; uint32 RXFIE : 1; uint32 RSVD_31_5 : 27; } SPI_IER; struct { uint32 TXEIS : 1; uint32 TXOIS : 1; uint32 RXUIS : 1; uint32 RXOIS : 1; uint32 RXFIS : 1; uint32 RSVD_15_5 : 11; uint32 TXEIR : 1; uint32 TXOIR : 1; uint32 RXUIR : 1; uint32 RXOIR : 1; uint32 RXFIR : 1; uint32 RSVD_31_21 : 11; } SPI_ISR; struct { uint32 TXOICR : 1; uint32 RSVD_31_1 : 31; } SPI_TXOICR; struct { uint32 RXOICR : 1; uint32 RSVD_31_1 : 31; } SPI_RXOICR; struct { uint32 RXUICR : 1; uint32 RSVD_31_1 : 31; } SPI_RXUICR; uint8 zResverd0x030[4]; struct { uint32 ICR : 1; uint32 RSVD_31_1 : 31; } SPI_ICR; struct { uint32 RDMAE : 1; uint32 TDMAE : 1; uint32 RSVD_31_2 : 30; } SPI_DMACR; struct { uint32 DMATDL : 2; uint32 RSVD_31_2 : 30; } SPI_DMATDLR; struct { uint32 DMARDL : 2; uint32 RSVD_31_2 : 30; } SPI_DMARDLR; uint8 zResverd0x044[28]; struct { uint32 DR : 32; } SPI_DR_LOW; uint8 zResverd0x064[136]; struct { uint32 DR : 32; } SPI_DR_HIGH; }; struct Reg_Spi_W { uint32 SPI_CTRLR0; uint32 SPI_CTRLR1; uint32 SPI_SSENR; uint32 SPI_BAUDR; uint32 SPI_FTLR; uint32 SPI_FLR; uint32 SPI_SR; uint32 SPI_IER; uint32 SPI_ISR; uint32 SPI_TXOICR; uint32 SPI_RXOICR; uint32 SPI_RXUICR; uint8 zResverd0x030[4]; uint32 SPI_ICR; uint32 SPI_DMACR; uint32 SPI_DMATDLR; uint32 SPI_DMARDLR; uint8 zResverd0x044[28]; uint32 SPI_DR_LOW; uint8 zResverd0x064[136]; uint32 SPI_DR_HIGH; }; typedef volatile struct Reg_Spi_Bf Reg_Spi_BfType; typedef volatile struct Reg_Spi_W Reg_Spi_WType; struct Reg_Srmc_Bf { uint32 zResverd0x00; struct { uint32 EWAKEUP : 1; uint32 ELVD : 1; uint32 ELOC : 1; uint32 RSVD_3 : 1; uint32 RSVD_4 : 1; uint32 EWDOG : 1; uint32 EPIN : 1; uint32 EPOR : 1; uint32 RSVD_8 : 1; uint32 ELOCKUP : 1; uint32 ESW : 1; uint32 EADM_AP : 1; uint32 RSVD_12 : 1; uint32 ESACKERR : 1; uint32 RSVD_15_14 : 2; uint32 ESTB : 1; uint32 RSVD_31_17 : 15; } SRMC_PARAM; struct { uint32 WAKEUP : 1; uint32 LVD : 1; uint32 LOC : 1; uint32 RSVD_4_3 : 2; uint32 WDOG : 1; uint32 PIN : 1; uint32 POR : 1; uint32 RSVD_8 : 1; uint32 LOCKUP : 1; uint32 SW : 1; uint32 ADM_AP : 1; uint32 SERU_COLD : 1; uint32 SERU_SYS : 1; uint32 RSVD_14 : 1; uint32 SACKERR : 1; uint32 RSVD_31_16 : 16; } SRMC_SRS; struct { uint32 RSTFLTSRW : 2; uint32 RSTFLTSS : 1; uint32 RSVD_7_3 : 5; uint32 RSTFLTSEL : 5; uint32 RSVD_30_13 : 18; uint32 LOCKUP_RST_EN : 1; } SRMC_CTRL; uint8 zResverd0x010[8]; struct { uint32 SWAKEUP : 1; uint32 SLVD : 1; uint32 SLOC : 1; uint32 RSVD_4_3 : 2; uint32 SWDOG : 1; uint32 SPIN : 1; uint32 SPOR : 1; uint32 RSVD_8 : 1; uint32 SLOCKUP : 1; uint32 SSW : 1; uint32 SADM_AP : 1; uint32 SSERU_COLD : 1; uint32 SSERU_SYS : 1; uint32 RSVD_14 : 1; uint32 SSACKERR : 1; uint32 RSVD_31_16 : 16; } SRMC_SSRS; struct { uint32 DELAY : 2; uint32 LOC : 1; uint32 RSVD_4_3 : 2; uint32 WDOG : 1; uint32 PIN : 1; uint32 GIE : 1; uint32 RSVD_8 : 1; uint32 LOCKUP : 1; uint32 SW : 1; uint32 RSVD_11 : 1; uint32 SERU_COLD : 1; uint32 SERU_SYS : 1; uint32 RSVD_14 : 1; uint32 SACKERR : 1; uint32 RSVD_31_16 : 16; } SRMC_SRIE; struct { uint32 APD : 1; uint32 RSVD_31_1 : 31; } SRMC_PMPORT; struct { uint32 DSMC : 2; uint32 RSVD_7_2 : 6; uint32 DSMACKTMO : 8; uint32 RSVD_31_16 : 16; } SRMC_PMCTRL; struct { uint32 PMSTAT : 4; uint32 RSVD_7_4 : 4; uint32 DSMABORT : 1; uint32 RSVD_31_9 : 23; } SRMC_PMSTAT; struct { uint32 WUPSRC_EN2_0 : 3; uint32 RSVD_3 : 1; uint32 WUPSRC_EN15_4 : 12; uint32 WUPSRC_PL2_0 : 3; uint32 RSVD_19 : 1; uint32 WUPSRC_PL14_4 : 11; uint32 RSVD_31 : 1; } SRMC_DSMWUPC1; struct { uint32 WUPSRC_EN16 : 1; uint32 RSVD_31_1 : 31; } SRMC_DSMWUPC2; struct { uint32 WUPS_2_0 : 3; uint32 RSVD_3 : 1; uint32 WUPS_16_4 : 13; uint32 RSVD_31_17 : 15; } SRMC_DSMWUPS; }; struct Reg_Srmc_W { uint32 zResverd0x00; uint32 SRMC_PARAM; uint32 SRMC_SRS; uint32 SRMC_CTRL; uint8 zResverd0x010[8]; uint32 SRMC_SSRS; uint32 SRMC_SRIE; uint32 SRMC_PMPORT; uint32 SRMC_PMCTRL; uint32 SRMC_PMSTAT; uint32 SRMC_DSMWUPC1; uint32 SRMC_DSMWUPC2; uint32 SRMC_DSMWUPS; }; typedef volatile struct Reg_Srmc_Bf Reg_Srmc_BfType; typedef volatile struct Reg_Srmc_W Reg_Srmc_WType; struct Reg_Stim_Bf { uint32 zResverd0x00; struct { uint32 CNT : 32; } STIM_CNTn[4]; struct { uint32 CV : 32; } STIM_CVn[4]; struct { uint32 CLKS : 2; uint32 PSDIV : 4; uint32 PSEN : 1; uint32 POL : 1; uint32 PSRC : 2; uint32 MODE : 1; uint32 RSTDIS : 1; uint32 DMAE : 1; uint32 IE : 1; uint32 EN : 1; uint32 FLAG : 1; uint32 RSVD_31_16 : 16; } STIM_SCn[4]; }; struct Reg_Stim_W { uint32 zResverd0x00; uint32 STIM_CNTn[4]; uint32 STIM_CVn[4]; uint32 STIM_SCn[4]; }; typedef volatile struct Reg_Stim_Bf Reg_Stim_BfType; typedef volatile struct Reg_Stim_W Reg_Stim_WType; struct Reg_Tdg_Bf { uint32 zResverd0x0; struct { uint32 DOPNUM : 4; uint32 CHNUM : 4; uint32 RSVD_31_8 : 24; } TDG_PARAM; struct { uint32 TDGEN : 1; uint32 RSVD_3_1 : 3; uint32 TRIGS : 1; uint32 CNTMD : 1; uint32 CLRMD : 1; uint32 RSVD_7 : 1; uint32 PRES : 3; uint32 RSVD_15_11 : 5; uint32 CFGUP : 1; uint32 SWTRG : 1; uint32 RSVD_19_18 : 2; uint32 UPMD : 2; uint32 RSVD_31_22 : 10; } TDG_CTRL1; struct { uint32 CDO0IE : 1; uint32 CDO1IE : 1; uint32 CDO2IE : 1; uint32 CDO3IE : 1; uint32 CDO4IE : 1; uint32 CDO5IE : 1; uint32 RSVD_7_6 : 2; uint32 ERRIE : 1; uint32 RSVD_15_9 : 7; uint32 CH0E : 1; uint32 CH1E : 1; uint32 CH2E : 1; uint32 CH3E : 1; uint32 CH4E : 1; uint32 CH5E : 1; uint32 RSVD_31_22 : 10; } TDG_CTRL2; struct { uint32 CDO0IF : 1; uint32 CDO1IF : 1; uint32 CDO2IF : 1; uint32 CDO3IF : 1; uint32 CDO4IF : 1; uint32 CDO5IF : 1; uint32 RSVD_7_6 : 2; uint32 ERRIF : 1; uint32 RSVD_31_9 : 23; } TDG_STAT; struct { uint32 MOD : 16; uint32 RSVD_31_16 : 16; } TDG_MOD; struct { uint32 CNT : 16; uint32 RSVD_31_16 : 16; } TDG_CNT; struct { struct { uint32 RSVD_7_0 : 8; uint32 DO0E : 1; uint32 DO1E : 1; uint32 DO2E : 1; uint32 DO3E : 1; uint32 DO4E : 1; uint32 DO5E : 1; uint32 DO6E : 1; uint32 DO7E : 1; uint32 RSVD_31_16 : 16; } TDG_CHCTRL; struct { uint32 DO0OFS : 16; uint32 RSVD_31_16 : 16; } TDG_CHDOOFS[8]; struct { uint32 CDOINTDLY : 10; uint32 RSVD_15_10 : 6; uint32 LDCO : 1; uint32 RSVD_31_17 : 15; } TDG_CHCDOINTDLY; } TDG_CHCFG[6]; }; struct Reg_Tdg_W { uint32 zResverd0x0; uint32 TDG_PARAM; uint32 TDG_CTRL1; uint32 TDG_CTRL2; uint32 TDG_STAT; uint32 TDG_MOD; uint32 TDG_CNT; struct { uint32 TDG_CHCTRL; uint32 TDG_CHDOOFS[8]; uint32 TDG_CHCDOINTDLY; } TDG_CHCFG[6]; }; typedef volatile struct Reg_Tdg_Bf Reg_Tdg_BfType; typedef volatile struct Reg_Tdg_W Reg_Tdg_WType; struct Reg_Tim_Bf { struct { uint32 CKSRC : 2; uint32 PSDIV : 3; uint32 DBGM : 2; uint32 RSVD_31_7 : 25; } TIM_TIMEBASE; struct { uint32 CNT : 16; uint32 RSVD_31_16 : 16; } TIM_CNT; struct { uint32 CNTINIT : 16; uint32 RSVD_31_16 : 16; } TIM_CNTINIT; struct { uint32 MOD : 16; uint32 RSVD_31_16 : 16; } TIM_MOD; struct { uint32 CHOE0 : 1; uint32 CHOE1 : 1; uint32 CHOE2 : 1; uint32 CHOE3 : 1; uint32 CHOE4 : 1; uint32 CHOE5 : 1; uint32 CHOE6 : 1; uint32 CHOE7 : 1; uint32 RLDIE : 1; uint32 TOIE : 1; uint32 CNTMODE : 1; uint32 INIT : 1; uint32 RSVD_31_12 : 20; } TIM_GLBCR; struct { uint32 CH0F : 1; uint32 CH1F : 1; uint32 CH2F : 1; uint32 CH3F : 1; uint32 CH4F : 1; uint32 CH5F : 1; uint32 CH6F : 1; uint32 CH7F : 1; uint32 RLDF : 1; uint32 TOF : 1; uint32 WPDIS : 1; uint32 RSVD_31_11 : 21; } TIM_GLBSR; struct { uint32 ELS : 2; uint32 CMS : 2; uint32 CHIE : 1; uint32 CHF : 1; uint32 DMAEN : 1; uint32 ICRST : 1; uint32 RSVD_31_8 : 24; } TIM_CMCn[8]; struct { uint32 CCV : 16; uint32 RSVD_31_16 : 16; } TIM_CCVn[8]; struct { uint32 INIT0 : 1; uint32 INIT1 : 1; uint32 INIT2 : 1; uint32 INIT3 : 1; uint32 INIT4 : 1; uint32 INIT5 : 1; uint32 INIT6 : 1; uint32 INIT7 : 1; uint32 POL0 : 1; uint32 POL1 : 1; uint32 POL2 : 1; uint32 POL3 : 1; uint32 POL4 : 1; uint32 POL5 : 1; uint32 POL6 : 1; uint32 POL7 : 1; uint32 TRIGE0 : 1; uint32 TRIGE1 : 1; uint32 TRIGE2 : 1; uint32 TRIGE3 : 1; uint32 TRIGE4 : 1; uint32 TRIGE5 : 1; uint32 TRIGE6 : 1; uint32 TRIGE7 : 1; uint32 INITRIGE : 1; uint32 TRIGF : 1; uint32 RSVD_31_26 : 6; } TIM_OUTCR; struct { uint32 CH0OC : 1; uint32 CH1OC : 1; uint32 CH2OC : 1; uint32 CH3OC : 1; uint32 CH4OC : 1; uint32 CH5OC : 1; uint32 CH6OC : 1; uint32 CH7OC : 1; uint32 CH0OCV : 1; uint32 CH1OCV : 1; uint32 CH2OCV : 1; uint32 CH3OCV : 1; uint32 CH4OCV : 1; uint32 CH5OCV : 1; uint32 CH6OCV : 1; uint32 CH7OCV : 1; uint32 RSVD_31_16 : 16; } TIM_OUTSWCR; struct { uint32 FCTLEN0 : 1; uint32 DTEN0 : 1; uint32 COMB0 : 1; uint32 SYNCEN0 : 1; uint32 DECAPEN0 : 1; uint32 DECAP0 : 1; uint32 RSVD_7_6 : 2; uint32 FCTLEN1 : 1; uint32 DTEN1 : 1; uint32 COMB1 : 1; uint32 SYNCEN1 : 1; uint32 DECAPEN1 : 1; uint32 DECAP1 : 1; uint32 RSVD_15_14 : 2; uint32 FCTLEN2 : 1; uint32 DTEN2 : 1; uint32 COMB2 : 1; uint32 SYNCEN2 : 1; uint32 DECAPEN2 : 1; uint32 DECAP2 : 1; uint32 RSVD_23_22 : 2; uint32 FCTLEN3 : 1; uint32 DTEN3 : 1; uint32 COMB3 : 1; uint32 SYNCEN3 : 1; uint32 DECAPEN3 : 1; uint32 DECAP3 : 1; uint32 RSVD_31_30 : 2; } TIM_PCR; struct { uint32 FILVAL0 : 4; uint32 FILVAL1 : 4; uint32 FILVAL2 : 4; uint32 FILVAL3 : 4; uint32 DTPS : 2; uint32 DTVAL : 6; uint32 RSVD_31_24 : 8; } TIM_FILTER; struct { uint32 FAULTEN0 : 1; uint32 FIFEN0 : 1; uint32 FLTPOL0 : 1; uint32 FAULTEN1 : 1; uint32 FIFEN1 : 1; uint32 FLTPOL1 : 1; uint32 FLTIE : 1; uint32 FLTCEN : 1; uint32 FLTCM : 1; uint32 RSVD_10_9 : 2; uint32 FIFVAL : 4; uint32 FSTATE : 1; uint32 RSVD_31_16 : 16; } TIM_FLTCR; struct { uint32 FAULTF0 : 1; uint32 FAULTF1 : 1; uint32 RSVD_3_2 : 2; uint32 FAULTF : 1; uint32 FAULTIN : 1; uint32 WPEN : 1; uint32 RSVD_31_7 : 25; } TIM_FLTSR; struct { uint32 SWTRIG : 1; uint32 RSVD_7_1 : 7; uint32 SYNCINIT : 1; uint32 SYNCOSWC : 1; uint32 RSVD_17_10 : 8; uint32 SWWRBUF : 1; uint32 SWRSTCNT : 1; uint32 RSVD_31_20 : 12; } TIM_SYNC; struct { uint32 CH0SEL : 1; uint32 CH1SEL : 1; uint32 CH2SEL : 1; uint32 CH3SEL : 1; uint32 CH4SEL : 1; uint32 CH5SEL : 1; uint32 CH6SEL : 1; uint32 CH7SEL : 1; uint32 LOADEN : 1; uint32 RSVD_10_9 : 2; uint32 HCSEL : 1; uint32 RSVD_15_12 : 4; uint32 LDFREQ : 5; uint32 RSVD_31_21 : 11; } TIM_RELOAD; struct { uint32 HCV : 16; uint32 RSVD_31_16 : 16; } TIM_HCV; }; struct Reg_Tim_W { uint32 TIM_TIMEBASE; uint32 TIM_CNT; uint32 TIM_CNTINIT; uint32 TIM_MOD; uint32 TIM_GLBCR; uint32 TIM_GLBSR; uint32 TIM_CMCn[8]; uint32 TIM_CCVn[8]; uint32 TIM_OUTCR; uint32 TIM_OUTSWCR; uint32 TIM_PCR; uint32 TIM_FILTER; uint32 TIM_FLTCR; uint32 TIM_FLTSR; uint32 TIM_SYNC; uint32 TIM_RELOAD; uint32 TIM_HCV; }; typedef volatile struct Reg_Tim_Bf Reg_Tim_BfType; typedef volatile struct Reg_Tim_W Reg_Tim_WType; struct Reg_Tmu_Bf { struct { uint32 SEL : 16; uint32 EN : 1; uint32 RSVD_30_17 : 14; uint32 LOCK : 1; } TMU_CFGn[40]; }; struct Reg_Tmu_W { uint32 TMU_CFGn[40]; }; typedef volatile struct Reg_Tmu_Bf Reg_Tmu_BfType; typedef volatile struct Reg_Tmu_W Reg_Tmu_WType; struct Reg_Trng_Bf { uint32 zResverd0x0000; uint32 zResverd0x0004; struct { uint32 RD : 1; uint32 IN : 1; uint32 TA : 1; uint32 CA : 1; uint32 RSVD_31_4 : 28; } TRNG_STATUS; struct { uint32 EN : 1; uint32 SM : 1; uint32 RSVD_3_2 : 2; uint32 DEC : 10; uint32 LP : 5; uint32 RSVD_31_19 : 13; } TRNG_CONFIG; struct { uint32 GE : 1; uint32 IN : 1; uint32 HT : 1; uint32 UN : 1; uint32 RS : 1; uint32 AK : 1; uint32 RSVD_31_6 : 26; } CTR_DRBG_CONTROL; struct { uint32 RS : 12; uint32 RP : 20; } CTR_DRBG_REQUEST_SIZE; struct { uint32 RP : 32; } CTR_DRBG_CONFIG_1; struct { uint32 HTP : 32; } CTR_DRBG_CONFIG_2; struct { uint32 AL0 : 1; uint32 AL1 : 1; uint32 AL2 : 1; uint32 AL3 : 1; uint32 VA : 1; uint32 RSVD_31_5 : 27; } TRNG_ALARM; struct { uint32 AL0 : 1; uint32 AL1 : 1; uint32 AL2 : 1; uint32 VA : 1; uint32 RSVD_31_4 : 28; } CTR_DRBG_ALARM; struct { uint32 FL : 1; uint32 RSVD_31_1 : 31; } TRNG_RAW_RANDOM_CONTROL; struct { uint32 DATA : 16; uint32 VA : 1; uint32 RSVD_31_17 : 15; } TRNG_RAW_RANDOM_DATA; struct { uint32 DATA : 16; uint32 VA : 1; uint32 RSVD_31_17 : 15; } CTR_DRBG_RANDOM_DATA; struct { uint32 I0 : 1; uint32 I1 : 1; uint32 I2 : 1; uint32 I3 : 1; uint32 MC : 1; uint32 RE : 1; uint32 E0 : 1; uint32 E1 : 1; uint32 E2 : 1; uint32 E3 : 1; uint32 SE : 1; uint32 RSVD_31_11 : 21; } ADDITIONAL_CONFIG_0; struct { uint32 AC1 : 11; uint32 RSVD_31_11 : 21; } ADDITIONAL_CONFIG_1; struct { uint32 AC2 : 32; } ADDITIONAL_CONFIG_2; struct { uint32 NS : 1; uint32 RSVD_31_1 : 31; } ADDITIONAL_MEAS_CONTROL; struct { uint32 TIME : 30; uint32 SEL : 2; } ADDITIONAL_MEAS_CONFIG; struct { uint32 RD : 1; uint32 OV : 1; uint32 RSVD_31_2 : 30; } ADDITIONAL_MEAS_STATUS; struct { uint32 D0 : 32; } ADDITIONAL_MEAS_DATA_0; struct { uint32 D1 : 32; } ADDITIONAL_MEAS_DATA_1; struct { uint32 IS0 : 1; uint32 IS1 : 1; uint32 IS2 : 1; uint32 IS3 : 1; uint32 RSVD_31_4 : 28; } IRQ_STATUS; struct { uint32 CL0 : 1; uint32 CL1 : 1; uint32 CL2 : 1; uint32 CL3 : 1; uint32 RSVD_31_4 : 28; } IRQ_CLEAR; struct { uint32 E0 : 1; uint32 E1 : 1; uint32 E2 : 1; uint32 E3 : 1; uint32 RSVD_31_4 : 28; } IRQ_CONFIG; struct { uint32 TIMEOUT : 32; } ERROR_CONFIG; struct { uint32 ST : 1; uint32 RSVD_31_1 : 31; } ERROR_CONTROL; struct { uint32 RD : 1; uint32 OV : 1; uint32 TR : 1; uint32 RSVD_31_3 : 29; } ERROR_STATUS; struct { uint32 MO : 1; uint32 RSVD_31_1 : 31; } STATS_CONFIG; struct { uint32 CL : 1; uint32 RSVD_31_1 : 31; } STATS_CONTROL; struct { uint32 EV : 16; uint32 PA : 16; } STATS_DATA; }; struct Reg_Trng_W { uint32 zResverd0x0000; uint32 zResverd0x0004; uint32 TRNG_STATUS; uint32 TRNG_CONFIG; uint32 CTR_DRBG_CONTROL; uint32 CTR_DRBG_REQUEST_SIZE; uint32 CTR_DRBG_CONFIG_1; uint32 CTR_DRBG_CONFIG_2; uint32 TRNG_ALARM; uint32 CTR_DRBG_ALARM; uint32 TRNG_RAW_RANDOM_CONTROL; uint32 TRNG_RAW_RANDOM_DATA; uint32 CTR_DRBG_RANDOM_DATA; uint32 ADDITIONAL_CONFIG_0; uint32 ADDITIONAL_CONFIG_1; uint32 ADDITIONAL_CONFIG_2; uint32 ADDITIONAL_MEAS_CONTROL; uint32 ADDITIONAL_MEAS_CONFIG; uint32 ADDITIONAL_MEAS_STATUS; uint32 ADDITIONAL_MEAS_DATA_0; uint32 ADDITIONAL_MEAS_DATA_1; uint32 IRQ_STATUS; uint32 IRQ_CLEAR; uint32 IRQ_CONFIG; uint32 ERROR_CONFIG; uint32 ERROR_CONTROL; uint32 ERROR_STATUS; uint32 STATS_CONFIG; uint32 STATS_CONTROL; uint32 STATS_DATA; }; typedef volatile struct Reg_Trng_Bf Reg_Trng_BfType; typedef volatile struct Reg_Trng_W Reg_Trng_WType; struct Reg_Uart_Bf { union { struct { uint32 RBR_LSB : 8; uint32 RBR_MSB : 1; uint32 RSVD_31_9 : 23; } UART_RBR; struct { uint32 THR_LSB : 8; uint32 THR_MSB : 1; uint32 RSVD_31_9 : 23; } UART_THR; struct { uint32 DL_L : 8; uint32 RSVD_31_8 : 24; } UART_DLL; } UART_RBR_THR_DLL; union { struct { uint32 DL_H : 8; uint32 RSVD_31_8 : 24; } UART_DLH; struct { uint32 ERBFI : 1; uint32 ETBEI : 1; uint32 ELSI : 1; uint32 EDSSI : 1; uint32 RSVD_6_4 : 3; uint32 PTIME : 1; uint32 HEADER_DONE_INT_EN : 1; uint32 RSP_DONE_INT_EN : 1; uint32 ASYNC_INT_EN : 1; uint32 RSVD_31_11 : 21; } UART_IER; } UART_DLH_IER; union { struct { uint32 IID : 4; uint32 RSVD_5_4 : 2; uint32 FIFOSE : 2; uint32 RSVD_31_8 : 24; } UART_IIR; struct { uint32 FIFOE : 1; uint32 RFIFOR : 1; uint32 XFIFOR : 1; uint32 RSVD_3 : 1; uint32 TET : 2; uint32 RCVR : 2; uint32 RSVD_31_8 : 24; } UART_FCR; } UART_IIR_FCR; struct { uint32 DLS : 2; uint32 STOP : 1; uint32 PEN : 1; uint32 EPS : 1; uint32 RSVD_5 : 1; uint32 BC : 1; uint32 DLAB : 1; uint32 LBKEN : 1; uint32 LBKM : 5; uint32 IDLE_DET_LENGTH : 3; uint32 IDLE_DET_EN : 1; uint32 AUTO_SYNC_EN : 1; uint32 DEBUG_EN : 1; uint32 RSVD_31_20 : 12; } UART_LCR; struct { uint32 RSVD_0 : 1; uint32 RTS : 1; uint32 RSVD_2 : 1; uint32 RSVD_3 : 1; uint32 LB : 1; uint32 AFCE : 1; uint32 RSVD_6 : 1; uint32 RSVD_31_7 : 25; } UART_AFCR; struct { uint32 DR : 1; uint32 OE : 1; uint32 PE : 1; uint32 FE : 1; uint32 BI : 1; uint32 THRE : 1; uint32 TEMT : 1; uint32 RFE : 1; uint32 ADDR_RCVD : 1; uint32 ASYNC_INT : 1; uint32 SYNC_FIELD_ERROR : 1; uint32 PID_ERR : 1; uint32 CHECKSUM_ERROR : 1; uint32 TO_ERROR : 1; uint32 HEADER_OP_DONE : 1; uint32 RSP_OP_DONE : 1; uint32 RSVD_31_16 : 16; } UART_LSR; struct { uint32 RSVD_3_0 : 4; uint32 CTS : 1; uint32 RSVD_31_5 : 27; } UART_MSR; uint8 zResverd0x01C[96]; struct { uint32 BUSY : 1; uint32 RSVD_31_1 : 31; } UART_USR; uint8 zResverd0x080[40]; struct { uint32 RSVD_0 : 1; uint32 RSVD_31_1 : 31; } UART_DMA_SA; uint8 zResverd0x0AC[20]; struct { uint32 FD : 4; uint32 RSVD_31_4 : 28; } UART_FD; struct { uint32 RAR : 8; uint32 RSVD_31_8 : 24; } UART_RAR; struct { uint32 TAR : 8; uint32 RSVD_31_8 : 24; } UART_TAR; struct { uint32 DLS_E : 1; uint32 ADDR_MATCH : 1; uint32 SEND_ADDR : 1; uint32 TRANSMIST_MODE : 1; uint32 RSVD_31_4 : 28; } UART_LCR_EXT; uint8 zResverd0x0D0[48]; struct { uint32 LIN_MODE : 1; uint32 MASTER_MODE : 1; uint32 HEADER_OP_START : 1; uint32 RSP_OP_START : 1; uint32 RSP_DIR : 1; uint32 RSVD_31_5 : 27; } UART_LIN_CTL; struct { uint32 RSP_LENGTH : 4; uint32 RSVD_31_4 : 28; } UART_LIN_RSP_LENGTH; struct { uint32 PID : 8; uint32 RSVD_31_8 : 24; } UART_LIN_PID_VALUE; struct { uint32 CHECKSUM_TYPE : 1; uint32 RSVD_7_1 : 7; uint32 RSVD_31_8 : 24; } UART_LIN_CHECKSUM; struct { uint32 LIN_DEL_LENGTH : 3; uint32 RSVD_31_3 : 29; } UART_LIN_DEL_LENGTH; struct { uint32 FID0 : 6; uint32 RSVD_7_6 : 2; uint32 FID1 : 6; uint32 RSVD_15_14 : 2; uint32 FID2 : 6; uint32 RSVD_23_22 : 2; uint32 FID3 : 6; uint32 RSVD_31_30 : 2; } UART_LIN_PID_FILTER_0; struct { uint32 FID4 : 6; uint32 RSVD_7_6 : 2; uint32 FID5 : 6; uint32 RSVD_15_14 : 2; uint32 FID6 : 6; uint32 RSVD_23_22 : 2; uint32 FID7 : 6; uint32 RSVD_31_30 : 2; } UART_LIN_PID_FILTER_1; struct { uint32 FID8 : 6; uint32 RSVD_7_6 : 2; uint32 FID9 : 6; uint32 RSVD_15_14 : 2; uint32 FID10 : 6; uint32 RSVD_23_22 : 2; uint32 FID11 : 6; uint32 RSVD_31_30 : 2; } UART_LIN_PID_FILTER_2; struct { uint32 FID12 : 6; uint32 RSVD_7_6 : 2; uint32 FID13 : 6; uint32 RSVD_15_14 : 2; uint32 FID14 : 6; uint32 RSVD_23_22 : 2; uint32 FID15 : 6; uint32 RSVD_31_30 : 2; } UART_LIN_PID_FILTER_3; struct { uint32 FID_VAGUE : 6; uint32 RSVD_31_6 : 26; } UART_LIN_PID_FILTER_VAGUE; struct { uint32 FID_MASK : 17; uint32 FID_VAGUE_MASK : 6; uint32 LIN_FILTER_EN : 1; uint32 RSVD_31_24 : 8; } UART_LIN_PID_FILTER_CTRL; }; struct Reg_Uart_W { union { uint32 UART_RBR; uint32 UART_THR; uint32 UART_DLL; } UART_RBR_THR_DLL; union { uint32 UART_DLH; uint32 UART_IER; } UART_DLH_IER; union { uint32 UART_IIR; uint32 UART_FCR; } UART_IIR_FCR; uint32 UART_LCR; uint32 UART_AFCR; uint32 UART_LSR; uint32 UART_MSR; uint8 zResverd0x01C[96]; uint32 UART_USR; uint8 zResverd0x080[40]; uint32 UART_DMA_SA; uint8 zResverd0x0AC[20]; uint32 UART_FD; uint32 UART_RAR; uint32 UART_TAR; uint32 UART_LCR_EXT; uint8 zResverd0x0D0[48]; uint32 UART_LIN_CTL; uint32 UART_LIN_RSP_LENGTH; uint32 UART_LIN_PID_VALUE; uint32 UART_LIN_CHECKSUM; uint32 UART_LIN_DEL_LENGTH; uint32 UART_LIN_PID_FILTER_0; uint32 UART_LIN_PID_FILTER_1; uint32 UART_LIN_PID_FILTER_2; uint32 UART_LIN_PID_FILTER_3; uint32 UART_LIN_PID_FILTER_VAGUE; uint32 UART_LIN_PID_FILTER_CTRL; }; typedef volatile struct Reg_Uart_Bf Reg_Uart_BfType; typedef volatile struct Reg_Uart_W Reg_Uart_WType; struct Reg_Wdog_Bf { uint32 zResverd0x0; struct { uint32 INT_PRESENT : 1; uint32 RSVD_31_1 : 31; } WDOG_PARAM; struct { uint32 WDOGE : 1; uint32 DEBUGE : 1; uint32 WAITE : 1; uint32 STOPE : 1; uint32 INTE : 1; uint32 WINE : 1; uint32 CFGUA : 1; uint32 RSVD_7 : 1; uint32 CLKS : 2; uint32 RSVD_15_10 : 6; uint32 TSTM : 3; uint32 RSVD_23_19 : 5; uint32 CFGUF : 1; uint32 UNLKF : 1; uint32 INTF : 1; uint32 RSVD_31_27 : 5; } WDOG_CS; struct { uint32 TMO : 32; } WDOG_TMO; struct { uint32 WIN : 32; } WDOG_WIN; struct { uint32 CNT : 32; } WDOG_CNT; }; struct Reg_Wdog_W { uint32 zResverd0x0; uint32 WDOG_PARAM; uint32 WDOG_CS; uint32 WDOG_TMO; uint32 WDOG_WIN; uint32 WDOG_CNT; }; typedef volatile struct Reg_Wdog_Bf Reg_Wdog_BfType; typedef volatile struct Reg_Wdog_W Reg_Wdog_WType; # 20 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices\\Device_Regs.h" 2 # 29 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 # 98 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" typedef enum { FLASH_DRV_CMD_PGMPHR = 0x24U, FLASH_DRV_CMD_ERSSCR = 0x42U }Flash_Drv_CmdType; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1436 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section bss = ".mcal_bss" # 110 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1452 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section bss = "" # 116 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1492 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section bss = ".mcal_bss" # 119 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 Flash_Drv_ReadStateType Flash_Drv_ReadState; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1508 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section bss = "" # 122 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1436 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section bss = ".mcal_bss" # 129 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1452 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section bss = "" # 134 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1464 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section bss = ".mcal_bss" # 137 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 static const Flash_Drv_ConfigType * Flash_Drv_ConfigPtr; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1480 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section bss = "" # 143 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1044 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section rodata = ".mcal_const" # 146 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 static Reg_Flash_BfType *const Fls_Drv_FlsRegBfPtr = (Reg_Flash_BfType *) (((uint32)0x40000000U) + 0x20000UL); static Reg_Flash_WType *const Fls_Drv_FlsRegWPtr = (Reg_Flash_WType *) (((uint32)0x40000000U) + 0x20000UL); static Reg_Scm_BfType *const Fls_Drv_ScmRegBfPtr = (Reg_Scm_BfType *)(((uint32)0x40000000U) + 0x48000UL); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1060 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section rodata = "" # 163 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1100 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section text = ".mcal_code" # 170 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 void Flash_Drv_EccIrqHandler(void); static boolean Flash_Drv_CheckAddr(const uint32 Addr); static boolean Flash_Drv_CheckValidRange(const uint32 StartAddr, const uint32 Length); static Flash_Drv_ReturnType Flash_Drv_CheckReadParam(const uint32 SrcAddress, const uint8 *DestPtr, const uint32 Length); static uint32 Flash_Drv_ComputeReadSize(uint32 SrcAddr, uint32 DesAddr, uint32 Len); static void Flash_Drv_ReadData(uint32 ReadSize, const uint32 * ReadAddr, uint32 * DesAddr); static Flash_Drv_ReturnType Flash_Drv_CompareData(uint32 ReadSize, const uint32 * ReadAddr, const uint32 * CompareAddr); static Flash_Drv_ReturnType Flash_Drv_BlankCheckData(uint32 ReadSize, const uint32 * ReadAddr); static void Flash_Drv_ConfigCommand(Flash_Drv_CmdType Cmd, uint32 DestAddr, const uint8 * SrcAddrPtr); static void Flash_Drv_CallStartNotif(void); static void Flash_Drv_CallFinishNotif(void); static void Flash_Drv_StartCmd(void); static Flash_Drv_ReturnType Flash_Drv_ExecuteCmd(void (*CallBack)(void), void (*AcFunc)(void (*CallBack)(void))); static void Flash_Drv_ClearCache(void); static void Flash_Drv_IgnoreBusErrorConfig(uint32 StartAddr, uint32 EndAddr); static Flash_Drv_ReturnType Flash_Drv_WritePhrase(const uint32 FlashAddr,const uint8 *SourceAddrPtr, const Flash_Drv_CmdActionType * CmdActPtr); static uint8 Flash_Drv_GetStatus(Flash_Drv_StatusType Stat); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1116 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section text = "" # 199 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1100 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section text = ".mcal_code" # 206 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 # 215 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" static boolean Flash_Drv_CheckAddr(const uint32 Addr) { boolean Ret; if((((Addr) <= ((0U) + (0x00200000U) - 1U)) || (((Addr) >= (0x02000000U)) && ((Addr) <= ((0x02000000U) + (0x00008000U) - 1U))) || (((Addr) >= (0x01000000U)) && ((Addr) <= ((0x01000000U) + (0x00020000U) - 1U))))) { Ret = (boolean)1U; } else { Ret = (boolean)0U; } return Ret; } # 240 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" static boolean Flash_Drv_CheckValidRange(const uint32 StartAddr, const uint32 Length) { boolean Ret; uint32 EndAddr = StartAddr + Length - 1UL; Ret = Flash_Drv_CheckAddr(StartAddr); Ret &= Flash_Drv_CheckAddr(EndAddr); if(((boolean)1U == Ret) && (Length > 0U)) { Ret = (boolean)1U; } else { Ret = (boolean)0U; } return Ret; } # 272 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" static Flash_Drv_ReturnType Flash_Drv_CheckReadParam(const uint32 SrcAddress, const uint8 *DestPtr, const uint32 Length) { Flash_Drv_ReturnType Ret; if((((void *)0) == DestPtr) || ((boolean)0U == Flash_Drv_CheckValidRange(SrcAddress, Length))) { Ret = FLASH_DRV_ERR_INPUT_PARAM; } else { Ret = FLASH_DRV_SUCCESS; } return Ret; } # 301 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" static uint32 Flash_Drv_ComputeReadSize(uint32 SrcAddr, uint32 DesAddr, uint32 Len) { uint32 ReadSize = 1U; uint32 CombinedAddr = SrcAddr | DesAddr; if(0UL == (CombinedAddr & 0x03U)) { if (Len >= 4U) { ReadSize = 4U; } else if(Len >= 2U) { ReadSize = 2U; } else { } } else if((0UL == (CombinedAddr & 0x01UL)) && (Len >= 2U)) { ReadSize = 2U; } else { } return ReadSize; } # 342 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" static void Flash_Drv_ReadData(uint32 ReadSize, const uint32 * ReadAddr, uint32 * DesAddr) { uint32 ReadData = *ReadAddr; switch (ReadSize) { case 4U: *DesAddr = ReadData; break; case 2U: *DesAddr = (*DesAddr & 0xFFFF0000U) | (ReadData & 0xFFFFU); break; case 1U: *(uint8 *)DesAddr = (uint8)(ReadData & 0xFFU); break; default: break; } } # 377 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" static Flash_Drv_ReturnType Flash_Drv_CompareData(uint32 ReadSize, const uint32 * ReadAddr, const uint32 * CompareAddr) { Flash_Drv_ReturnType Ret = FLASH_DRV_ERR_COMPARE; uint32 ReadData = *ReadAddr; uint32 CompareData = *CompareAddr; switch (ReadSize) { case 4U: if(CompareData == ReadData) { Ret = FLASH_DRV_SUCCESS; } break; case 2U: if((CompareData & 0xFFFFU) == (ReadData & 0xFFFFU)) { Ret = FLASH_DRV_SUCCESS; } break; case 1U: if((CompareData & 0xFFU) == (ReadData & 0xFFU)) { Ret = FLASH_DRV_SUCCESS; } break; default: break; } return Ret; } # 425 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" static Flash_Drv_ReturnType Flash_Drv_BlankCheckData(uint32 ReadSize, const uint32 * ReadAddr) { Flash_Drv_ReturnType Ret = FLASH_DRV_ERR_BLANK_CHECK; uint32 ReadData = *ReadAddr; switch (ReadSize) { case 4U: if((0xFFFFFFFFU) == ReadData) { Ret = FLASH_DRV_SUCCESS; } break; case 2U: if((uint16)(0xFFFFFFFFU) == (ReadData & 0xFFFFU)) { Ret = FLASH_DRV_SUCCESS; } break; case 1U: if((uint8)(0xFFFFFFFFU) == (ReadData & 0xFFU)) { Ret = FLASH_DRV_SUCCESS; } break; default: break; } return Ret; } # 470 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" static void Flash_Drv_ConfigCommand(Flash_Drv_CmdType Cmd, uint32 DestAddr, const uint8 * SrcAddrPtr) { volatile uint8 *FlashData = (volatile uint8 *)&(Fls_Drv_FlsRegWPtr->FLASH_FDATA0); Fls_Drv_FlsRegWPtr->FLASH_FADDR = DestAddr; SchM_Enter_Fls_FCMD(); Fls_Drv_FlsRegBfPtr->FLASH_FCMD.CMDCODE = (uint32)Cmd; SchM_Exit_Fls_FCMD(); if(SrcAddrPtr != ((void *)0)) { for(uint8 i = 0U; i < 0x10U; i++) { FlashData[i] = SrcAddrPtr[i]; } } SchM_Enter_Fls_FCTRL(); Fls_Drv_FlsRegBfPtr->FLASH_FCTRL.ABTREQ = 0U; SchM_Exit_Fls_FCTRL(); Fls_Drv_FlsRegWPtr->FLASH_FSTAT = (0x00000004U) | (0x00000020U) | (0x00000040U); } # 504 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" static void Flash_Drv_CallStartNotif(void) { if (((void *)0) != Flash_Drv_ConfigPtr->StartNotifPtr) { (Flash_Drv_ConfigPtr->StartNotifPtr)(); } } # 519 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" static void Flash_Drv_CallFinishNotif(void) { if (((void *)0) != Flash_Drv_ConfigPtr->FinishNotifPtr) { (Flash_Drv_ConfigPtr->FinishNotifPtr)(); } } # 534 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" static void Flash_Drv_StartCmd(void) { uint32 PriMaskReg = 0U; Fls_Drv_ScmRegBfPtr->SCM_MISCCTL1.CACHE_DIS = 1U; Flash_Drv_ClearCache(); PriMaskReg = McalLib_ReadPriMaskReg(); if (0U == PriMaskReg) { McalLib_SuspendAllInterrupts(); } __asm volatile ( "PUSH {R0, R1, R2}\n" "LDR R0, =0x40020000\n" "LDR R1, =0x80\n" "NOP\n" "NOP\n" "NOP\n" "NOP\n" "NOP\n" "NOP\n" "NOP\n" "NOP\n" "STR R1, [R0]\n" "LDR R2, [R0]\n" "NOP\n" "NOP\n" "NOP\n" "NOP\n" "NOP\n" "NOP\n" "NOP\n" "NOP\n" "POP {R0, R1, R2}\n" ); if (0U == PriMaskReg) { McalLib_ResumeAllInterrupts(); } Fls_Drv_ScmRegBfPtr->SCM_MISCCTL1.CACHE_DIS = 0U; } # 607 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" static Flash_Drv_ReturnType Flash_Drv_ExecuteCmd(void (*CallBack)(void), void (*AcFunc)(void (*CallBack)(void))) { Flash_Drv_ReturnType Ret; if(AcFunc != ((void *)0)) { Flash_Drv_CallStartNotif(); ((Flash_Drv_AcPtrType)(((uint32)(AcFunc)) | 0x00000001U))(CallBack); Flash_Drv_CallFinishNotif(); } else { Flash_Drv_StartCmd(); # 641 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" while(Fls_Drv_FlsRegBfPtr->FLASH_FSTAT.CCIF == 0U) { if(CallBack != ((void *)0)) { CallBack(); } } } SchM_Enter_Fls_TransferStatus(); if(Fls_Drv_FlsRegBfPtr->FLASH_FSTAT.CCIF != 0U) { if(((Fls_Drv_FlsRegWPtr->FLASH_FSTAT) & (((uint32)0x00000020U | (uint32)0x00000001U))) != 0U) { Ret = FLASH_DRV_ERR; Fls_Drv_FlsRegWPtr->FLASH_FSTAT = 0x00000020U; } else { Ret = FLASH_DRV_SUCCESS; } } else { Ret = FLASH_DRV_ERR_TIMEOUT; } SchM_Exit_Fls_TransferStatus(); return Ret; } # 684 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" static void Flash_Drv_ClearCache(void) { Fls_Drv_ScmRegBfPtr->SCM_MISCCTL1.CCACHE_CLR = 1U; Fls_Drv_ScmRegBfPtr->SCM_MISCCTL1.CCACHE_CLR = 0U; } # 707 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" static void Flash_Drv_IgnoreBusErrorConfig(uint32 StartAddr, uint32 EndAddr) { SchM_Enter_Fls_BEDStartAddr(); Fls_Drv_FlsRegBfPtr->FLASH_BED_ADDR_STRT.BED_ADDR_STRT = StartAddr >> 4U; SchM_Exit_Fls_BEDStartAddr(); SchM_Enter_Fls_BEDEndAddr(); Fls_Drv_FlsRegBfPtr->FLASH_BED_ADDR_END.BED_ADDR_END = EndAddr >> 4U; SchM_Exit_Fls_BEDEndAddr(); } # 734 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" static Flash_Drv_ReturnType Flash_Drv_WritePhrase(const uint32 FlashAddr,const uint8 *SourceAddrPtr, const Flash_Drv_CmdActionType * CmdActPtr) { boolean AddrValid = Flash_Drv_CheckAddr(FlashAddr) & (boolean)(((FlashAddr) & (0x10U - 1U)) == 0U); Flash_Drv_ReturnType Ret = FLASH_DRV_SUCCESS; while (1U) {; if ((boolean)(AddrValid) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c", 746); break; }; if(Fls_Drv_FlsRegBfPtr->FLASH_FSTAT.CCIF == 0U) { Ret = FLASH_DRV_BUSY; } else { # 770 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" Flash_Drv_ConfigCommand(FLASH_DRV_CMD_PGMPHR, FlashAddr, SourceAddrPtr); if((CmdActPtr->AsyncFlag) == 0U) { Ret = Flash_Drv_ExecuteCmd(CmdActPtr->CallBack, CmdActPtr->AcFunc); Flash_Drv_ClearCache(); } else { Flash_Drv_StartCmd(); } } break; }; return Ret; } # 800 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" static uint8 Flash_Drv_GetStatus(Flash_Drv_StatusType Stat) { uint8 Status; Status = (((Fls_Drv_FlsRegWPtr->FLASH_FSTAT) & (uint32)Stat) == 0U)? 0x00U: 0x01U; return Status; } # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1116 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section text = "" # 811 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1100 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section text = ".mcal_code" # 818 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2 # 830 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" Flash_Drv_ReturnType Flash_Drv_Init(const Flash_Drv_ConfigType* ConfigPtr) { Flash_Drv_ReturnType Ret = FLASH_DRV_SUCCESS; while (1U) {; if ((boolean)(((void *)0) != ConfigPtr) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c", 838); break; }; Flash_Drv_ConfigPtr = ConfigPtr; if(Flash_Drv_GetStatus(FLASH_DRV_STATUS_FAIL) == 0x01U) { Ret = FLASH_DRV_ERR_HW_FAIL; } else { if(Flash_Drv_GetStatus(FLASH_DRV_STATUS_CCIF) == 0x00U) { Ret = FLASH_DRV_BUSY; } else { Fls_Drv_FlsRegWPtr->FLASH_FSTAT = ((uint32)0x00000004U | (uint32)0x00000020U | (uint32)0x00000040U | (uint32)0x00010000U | (uint32)0x00020000U); Flash_Drv_IgnoreBusErrorConfig(ConfigPtr->IgnoreBusErrStartAddr, ConfigPtr->IgnoreBusErrEndAddr); Fls_Drv_FlsRegBfPtr->FLASH_FCNFG.DFDIE = 1U; } } break; }; return Ret; } # 885 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" Flash_Drv_ReturnType Flash_Drv_Abort(void) { volatile uint32 LocalCnt = 0U; Flash_Drv_ReturnType Ret = FLASH_DRV_SUCCESS; volatile uint32 LoopFlag = 1U; if (Fls_Drv_FlsRegBfPtr->FLASH_FSTAT.CCIF == 1U) { Ret = FLASH_DRV_SUCCESS; } else { SchM_Enter_Fls_FCTRL(); Fls_Drv_FlsRegBfPtr->FLASH_FCTRL.ABTREQ = 1U; SchM_Exit_Fls_FCTRL(); while(LoopFlag != 0U) { SchM_Enter_Fls_TransferStatus(); if(Fls_Drv_FlsRegBfPtr->FLASH_FSTAT.CCIF == 1U) { if(Fls_Drv_FlsRegBfPtr->FLASH_FSTAT.CMDABT == 1U) { Fls_Drv_FlsRegWPtr->FLASH_FSTAT = 0x00000004U; SchM_Exit_Fls_TransferStatus(); Ret = FLASH_DRV_CMD_ABORTED; LoopFlag = 0U; } else { Fls_Drv_FlsRegWPtr->FLASH_FSTAT = 0x00000040U; SchM_Exit_Fls_TransferStatus(); Ret = FLASH_DRV_SUCCESS; LoopFlag = 0U; } } else { SchM_Exit_Fls_TransferStatus(); if(LocalCnt > 300U) { Ret = FLASH_DRV_ERR_TIMEOUT; LoopFlag = 0U; } else { LocalCnt++; } } } } return Ret; } # 957 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" Flash_Drv_ReturnType Flash_Drv_EraseSector(const uint32 Addr, const Flash_Drv_CmdActionType * CmdActPtr) { boolean AddrValid = Flash_Drv_CheckAddr(Addr) & (boolean)(((Addr) & (0x2000U - 1U)) == 0U); Flash_Drv_ReturnType Ret = FLASH_DRV_SUCCESS; while (1U) {; if ((boolean)(AddrValid) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c", 969); break; }; if(Fls_Drv_FlsRegBfPtr->FLASH_FSTAT.CCIF == 0U) { Ret = FLASH_DRV_BUSY; } else { # 993 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" Flash_Drv_ConfigCommand(FLASH_DRV_CMD_ERSSCR, Addr, ((void *)0)); if((CmdActPtr->AsyncFlag) == 0U) { Ret = Flash_Drv_ExecuteCmd(CmdActPtr->CallBack, CmdActPtr->AcFunc); Flash_Drv_ClearCache(); } else { Flash_Drv_StartCmd(); } } break; }; return Ret; } # 1032 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" Flash_Drv_ReturnType Flash_Drv_Write(const uint32 FlashAddr, const uint32 Len, const uint8 *SourceAddrPtr, const Flash_Drv_CmdActionType * CmdActPtr) { boolean ParaValid = (Flash_Drv_CheckAddr(FlashAddr)) & (boolean)((((FlashAddr) & (0x10U - 1U)) == 0U) && (((Len) & (0x10U - 1U)) == 0U)); Flash_Drv_ReturnType Ret = FLASH_DRV_SUCCESS; uint32 Count; while (1U) {; if ((boolean)(ParaValid) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c", 1046); break; }; for(Count = 0U; Count < Len; Count += 16U) { Ret = Flash_Drv_WritePhrase((FlashAddr + Count), &(SourceAddrPtr[Count]), CmdActPtr); if(Ret != FLASH_DRV_SUCCESS) { break; } } break; }; return Ret; } # 1079 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" Flash_Drv_ReturnType Flash_Drv_Read(uint32 SrcAddr, uint8 const *DestAddrPtr, uint32 Length) { Flash_Drv_ReturnType Ret = Flash_Drv_CheckReadParam(SrcAddr, DestAddrPtr, Length); uint32 RemainBytes = Length; uint32 ReadAddr = SrcAddr; uint32 CurDesAddr = (uint32)DestAddrPtr; uint32 ReadSize = 1U; while (1U) {; if ((boolean)(FLASH_DRV_SUCCESS == Ret) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c", 1094); break; }; Flash_Drv_ReadState.Status = FLASH_DRV_READ_BUSY; Flash_Drv_ClearCache(); while((RemainBytes > 0U) && (Flash_Drv_ReadState.Status != FLASH_DRV_READ_ERROR)) { Flash_Drv_ReadState.Address = ReadAddr; Fls_Drv_FlsRegWPtr->FLASH_FSTAT = 0x00010000U; SchM_Enter_Fls_MBEState(); Fls_Drv_FlsRegBfPtr->FLASH_MBE_STATE.MBE_FLAG = 1U; SchM_Exit_Fls_MBEState(); ReadSize = Flash_Drv_ComputeReadSize(ReadAddr, CurDesAddr, RemainBytes); Flash_Drv_ReadData(ReadSize, (uint32 *)ReadAddr, (uint32 *)CurDesAddr); # 1128 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" ReadAddr += ReadSize; CurDesAddr += ReadSize; RemainBytes -= ReadSize; } if (FLASH_DRV_READ_ERROR == Flash_Drv_ReadState.Status) { Ret = FLASH_DRV_ERR_ECC_M; } Flash_Drv_ReadState.Status = FLASH_DRV_READ_IDLE; break; }; return Ret; } # 1160 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" Flash_Drv_ReturnType Flash_Drv_Compare(uint32 SrcAddr, const uint8 *CompareBufPtr, uint32 Length) { Flash_Drv_ReturnType Ret = Flash_Drv_CheckReadParam(SrcAddr, CompareBufPtr, Length); uint32 RemainBytes = Length; uint32 ReadAddr = SrcAddr; uint32 CurCompareAddr = (uint32)CompareBufPtr; uint32 ReadSize = 1U; while (1U) {; if ((boolean)(FLASH_DRV_SUCCESS == Ret) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c", 1175); break; }; Flash_Drv_ReadState.Status = FLASH_DRV_READ_BUSY; Flash_Drv_ClearCache(); while((RemainBytes > 0U) && (Flash_Drv_ReadState.Status != FLASH_DRV_READ_ERROR) && (Ret == FLASH_DRV_SUCCESS)) { Flash_Drv_ReadState.Address = ReadAddr; Fls_Drv_FlsRegWPtr->FLASH_FSTAT = 0x00010000U; SchM_Enter_Fls_MBEState(); Fls_Drv_FlsRegBfPtr->FLASH_MBE_STATE.MBE_FLAG = 1U; SchM_Exit_Fls_MBEState(); ReadSize = Flash_Drv_ComputeReadSize(ReadAddr, CurCompareAddr, RemainBytes); Ret = Flash_Drv_CompareData(ReadSize, (uint32 *)ReadAddr, (uint32 *)CurCompareAddr); # 1210 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" ReadAddr += ReadSize; CurCompareAddr += ReadSize; RemainBytes -= ReadSize; } if((FLASH_DRV_READ_ERROR == Flash_Drv_ReadState.Status) && (FLASH_DRV_SUCCESS == Ret)) { Ret = FLASH_DRV_ERR_ECC_M; } else { } Flash_Drv_ReadState.Status = FLASH_DRV_READ_IDLE; break; }; return Ret; } # 1246 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" Flash_Drv_ReturnType Flash_Drv_CheckBlank(uint32 SrcAddr, uint32 Length) { Flash_Drv_ReturnType Ret = FLASH_DRV_SUCCESS; boolean ParamCheck = Flash_Drv_CheckValidRange(SrcAddr, Length); uint32 RemainBytes = Length; uint32 ReadAddr = SrcAddr; uint32 ReadSize = 1U; while (1U) {; if ((boolean)(1U == ParamCheck) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c", 1259); break; }; Flash_Drv_ReadState.Status = FLASH_DRV_READ_BUSY; Flash_Drv_ClearCache(); while((RemainBytes > 0U) && (Flash_Drv_ReadState.Status != FLASH_DRV_READ_ERROR) && (Ret == FLASH_DRV_SUCCESS)) { Flash_Drv_ReadState.Address = ReadAddr; Fls_Drv_FlsRegWPtr->FLASH_FSTAT = 0x00010000U; SchM_Enter_Fls_MBEState(); Fls_Drv_FlsRegBfPtr->FLASH_MBE_STATE.MBE_FLAG = 1U; SchM_Exit_Fls_MBEState(); ReadSize = Flash_Drv_ComputeReadSize(ReadAddr, 0U, RemainBytes); Ret = Flash_Drv_BlankCheckData(ReadSize, (uint32 *)ReadAddr); # 1294 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" ReadAddr += ReadSize; RemainBytes -= ReadSize; } if((FLASH_DRV_READ_ERROR == Flash_Drv_ReadState.Status) && (FLASH_DRV_SUCCESS == Ret)) { Ret = FLASH_DRV_ERR_ECC_M; } else { } Flash_Drv_ReadState.Status = FLASH_DRV_READ_IDLE; break; }; return Ret; } # 1331 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" Flash_Drv_ReturnType Flash_Drv_PollEraseWriteStatus(void) { Flash_Drv_ReturnType Ret; SchM_Enter_Fls_TransferStatus(); if(Fls_Drv_FlsRegBfPtr->FLASH_FSTAT.CCIF == 1U) { if(((Fls_Drv_FlsRegWPtr->FLASH_FSTAT) & (((uint32)0x00000020U | (uint32)0x00000001U))) != 0U) { Ret = FLASH_DRV_ERR; Fls_Drv_FlsRegWPtr->FLASH_FSTAT = 0x00000020U; SchM_Exit_Fls_TransferStatus(); } else { SchM_Exit_Fls_TransferStatus(); Ret = FLASH_DRV_SUCCESS; } Flash_Drv_ClearCache(); } else { SchM_Exit_Fls_TransferStatus(); # 1371 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" { Ret = FLASH_DRV_BUSY; } } return Ret; } # 1391 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" uint32 Flash_Drv_GetBlockNumFromAddr(uint32 Address) { uint32 BlockNum; if((Address >= (0x01000000U)) && (Address <= ((0x01000000U) + (0x00020000U) - 1U))) { BlockNum = 2U; } else if(Address <= ((0U) + (0x00200000U) - 1U)) { BlockNum = 1U; } else if((Address >= (0x02000000U)) && (Address <= ((0x02000000U) + (0x00008000U) - 1U))) { BlockNum = 1U; } else { BlockNum = 0U; } return BlockNum; } # 1427 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" void Flash_Drv_EccIrqHandler(void) { if((Fls_Drv_FlsRegBfPtr->FLASH_FSTAT.DFDIF == 1U) && (Fls_Drv_FlsRegBfPtr->FLASH_FCNFG.DFDIE == 1U) && (Flash_Drv_ReadState.Status == FLASH_DRV_READ_BUSY) && ((Flash_Drv_ReadState.Address >> 4) == Fls_Drv_FlsRegBfPtr->FLASH_MBE_STATE.MBE_ADDR)) { Flash_Drv_ReadState.Status = FLASH_DRV_READ_ERROR; } Fls_Drv_FlsRegWPtr->FLASH_FSTAT = 0x00010000U; __asm("DSB"); } # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" 1 # 1116 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Fls_MemMap.h" #pragma clang section text = "" # 1445 "../../../mcal/Fls_ZX_K14xM/Src/Flash_Drv.c" 2