# 1 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" # 1 "" 1 # 1 "" 3 # 387 "" 3 # 1 "" 1 # 1 "" 2 # 1 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 # 24 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" # 1 "../../../Package/Cdd\\AL_Helper.h" 1 # 1 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 1 # 30 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h" 1 # 86 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h" typedef unsigned char boolean; typedef unsigned char uint8; typedef unsigned short uint16; typedef unsigned int uint32; typedef unsigned long long uint64; typedef signed char sint8; typedef signed short sint16; typedef signed int sint32; typedef signed long long sint64; typedef unsigned long uint8_least; typedef unsigned long uint16_least; typedef unsigned long uint32_least; typedef signed long sint8_least; typedef signed long sint16_least; typedef signed long sint32_least; typedef float float32; typedef double float64; typedef void *VoidPtr; typedef const void *ConstVoidPtr; # 31 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 1 # 31 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler_Cfg.h" 1 # 32 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 2 # 32 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2 # 63 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" typedef unsigned char StatusType; # 104 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" typedef uint8 Std_ReturnType; typedef uint8 Std_TransformerClass; typedef uint8 Std_TransformerForwardCode; typedef uint8 Std_MessageTypeType; typedef uint8 Std_MessageResultType; typedef struct { uint16 vendorID; uint16 moduleID; uint8 sw_major_version; uint8 sw_minor_version; uint8 sw_patch_version; } Std_VersionInfoType; typedef struct { uint8 errorCode; Std_TransformerClass transformerClass; } Std_TransformerError; typedef struct { Std_TransformerForwardCode errorCode; Std_TransformerClass transformerClass; } Std_TransformerForward; typedef Std_ReturnType (*Std_ExtractProtocolHeaderFieldsType)(const uint8 *buffer, uint32 bufferLength, Std_MessageTypeType *messageType, Std_MessageResultType *messageResult); # 5 "../../../Package/Cdd\\AL_Helper.h" 2 # 20 "../../../Package/Cdd\\AL_Helper.h" void AL_Helper_Dummy(const uint32 ulDummyParam); # 25 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 # 1 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" 1 # 29 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" # 1 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Types.h" 1 # 28 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Types.h" # 1 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drvw_Types.h" 1 # 28 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drvw_Types.h" # 1 "../Generated/inc\\Spi_Drvw_Cfg.h" 1 # 28 "../Generated/inc\\Spi_Drvw_Cfg.h" # 1 "../Generated/inc/Spi_Drvw_PBcfg.h" 1 # 29 "../Generated/inc\\Spi_Drvw_Cfg.h" 2 # 29 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drvw_Types.h" 2 # 1 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drv_Types.h" 1 # 29 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drv_Types.h" # 1 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 1 # 29 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" # 1 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 1 # 30 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" # 1 "../Generated/inc\\McalLib_Cfg.h" 1 # 31 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 2 # 273 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" static inline uint32 McalLib_ReadControlReg(void) { uint32 res; __asm("MRS %0,CONTROL" : "=r" (res)); return res; } # 290 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" static inline uint32 McalLib_ReadIpsrReg(void) { uint32 res; __asm("MRS %0,IPSR" : "=r" (res)); return res; } # 305 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" static inline uint32 McalLib_ReadPriMaskReg(void) { uint32 res; __asm("MRS %0,PRIMASK" : "=r" (res)); return res; } # 30 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 # 184 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" typedef enum { MCALLIB_COUNTER_SOFTWARE, MCALLIB_COUNTER_OS, } McalLib_CounterType; typedef struct { uint32 CounterId; uint32 CounterFreq; } McalLib_ConfigType; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 211 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 extern const McalLib_ConfigType *const McalLib_PreDefinedConfigPtr[(1U)]; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section rodata = "" # 216 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 # 230 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" extern void Sys_SystemReset(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section text = ".mcal_code" # 234 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 void McalLib_Init(void); # 254 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" Std_ReturnType McalLib_GetCounterValue(McalLib_CounterType Counter, uint32 *Value); # 270 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" Std_ReturnType McalLib_GetElapsedValue(McalLib_CounterType Counter, uint32 *const CounterValue, uint32 *ElapsedValue); # 282 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" uint32 McalLib_MicroSecToTicks(McalLib_CounterType Counter, uint32 MicroSecond); # 296 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" void McalLib_SetCounterFreq(McalLib_CounterType Counter, uint32 Freq); # 309 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" static inline void McalLib_Assert(const uint8 *File, uint32 Line) { (void)File; (void)Line; for (;;) { } } # 327 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" void McalLib_SuspendAllInterrupts(void); void McalLib_ResumeAllInterrupts(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section text = "" # 339 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 # 30 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drv_Types.h" 2 # 1 "../Generated/inc\\Spi_Drv_Cfg.h" 1 # 28 "../Generated/inc\\Spi_Drv_Cfg.h" # 1 "../Generated/inc/Spi_Drv_PBcfg.h" 1 # 29 "../Generated/inc\\Spi_Drv_Cfg.h" 2 # 31 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drv_Types.h" 2 # 84 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drv_Types.h" typedef enum { SPI_DRV_EVENT_SUCCESS = 0U, SPI_DRV_EVENT_FAULT } Spi_Drv_EventType; typedef void (*Spi_Drv_CallbackType)(uint8 Instance, Spi_Drv_EventType Event); typedef enum { SPI_DRV_POLLING = 0U, SPI_DRV_INTERRUPT } Spi_Drv_AsyncModeType; typedef enum { SPI_DRV_UNINIT = 0U, SPI_DRV_IDLE, SPI_DRV_BUSY, SPI_DRV_FAULT } Spi_Drv_StatusType; typedef struct { uint8 FrameSize; boolean Lsb; uint32 DefaultData; } Spi_Drv_DeviceParamType; typedef struct { uint8 Instance; uint8 CsIdentifier; uint8 ClockPhase; uint8 ClockPolarity; uint32 ClockDivider; Spi_Drv_DeviceParamType *DeviceParamPtr; } Spi_Drv_ExternalDeviceType; typedef struct { uint8 Instance; boolean DmaUsed; uint8 TxDmaChannel; uint8 RxDmaChannel; Spi_Drv_AsyncModeType AsyncMode; } Spi_Drv_PhyUnitConfigType; typedef struct { Spi_Drv_AsyncModeType AsyncMode; Spi_Drv_StatusType Status; uint8 *RxBuffer; uint8 *TxBuffer; Spi_Drv_CallbackType Callback; uint16 RxIndex; uint16 TxIndex; uint16 ExpectReadNum; uint16 ExpectWriteNum; boolean ContinueTransferFlag; boolean FirstTransferFlag; const Spi_Drv_PhyUnitConfigType *PhyUnitConfig; const Spi_Drv_ExternalDeviceType *ExternalDevice; uint8 FrameSize; boolean TxLsb; boolean NextTransferConfigAvailable; uint8 CurrentTxFifoSlot; boolean TxDoneFlag; } Spi_Drv_TransferConfigType; # 30 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drvw_Types.h" 2 # 88 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drvw_Types.h" typedef enum { IB = 0, EB } Spi_Drvw_BufferType; typedef enum { SPI_DRVW_POLLING_MODE = 0, SPI_DRVW_INTERRUPT_MODE } Spi_Drvw_AsyncModeType; typedef uint8 Spi_Drvw_HWUnitType; typedef uint16 Spi_Drvw_NumberOfDataType; typedef uint8 Spi_Drvw_DataBufferType; typedef struct { uint8 Instance; uint32 IsSync; uint32 SpiCoreUse; const Spi_Drv_PhyUnitConfigType *PhyUnitConfigPtr; } Spi_Drvw_HWUnitConfigType; typedef struct { const Spi_Drvw_HWUnitConfigType *DrvwHWUnitConfig; } Spi_Drvw_HWUnitConfigListType; typedef struct { uint8 Instance; uint32 SpiCoreUse; const Spi_Drv_ExternalDeviceType *DrvExternalDeviceConfigPtr; } Spi_Drvw_ExternalDeviceConfigType; typedef struct { const Spi_Drvw_ExternalDeviceConfigType *DrvwExternalDeviceConfigPtr; } Spi_Drvw_ExternalDeviceListType; typedef struct { Spi_Drvw_DataBufferType *TxBuffer; Spi_Drvw_DataBufferType *RxBuffer; } Spi_Drvw_BufferDescriptorType; typedef struct { uint8 Flags; Spi_Drvw_NumberOfDataType Length; } Spi_Drvw_ChannelStateType; typedef struct { Spi_Drvw_BufferType BufferType; uint8 FrameSize; boolean Lsb; uint32 DefaultTransmitValue; Spi_Drvw_NumberOfDataType Length; Spi_Drvw_BufferDescriptorType *BufferDescriptor; uint32 SpiCoreUse; Spi_Drvw_ChannelStateType *ChannelState; } Spi_Drvw_ChannelConfigType; # 29 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Types.h" 2 # 1 "../Generated/inc\\Spi_Cfg.h" 1 # 28 "../Generated/inc\\Spi_Cfg.h" # 1 "../Generated/inc/Spi_PBcfg.h" 1 # 66 "../Generated/inc/Spi_PBcfg.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" #pragma clang section text = ".mcal_code" # 67 "../Generated/inc/Spi_PBcfg.h" 2 extern void Ex_Spi_StpJobStartNotification(void); extern void Ex_Spi_SbcJobStartNotification(void); extern void Ex_Spi_BuckJobStartNotification(void); extern void Ex_Spi_BoostJobStartNotification(void); extern void Ex_Spi_StpJobEndNotification(void); extern void Ex_Spi_SbcJobEndNotification(void); extern void Ex_Spi_BuckJobEndNotification(void); extern void Ex_Spi_BoostJobEndNotification(void); extern void Ex_Spi_StpSequenceEndNotification(void); extern void Ex_Spi_SbcSequenceEndNotification(void); extern void Ex_Spi_BuckSequenceEndNotification(void); extern void Ex_Spi_BoostSequenceEndNotification(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" #pragma clang section text = "" # 132 "../Generated/inc/Spi_PBcfg.h" 2 # 29 "../Generated/inc\\Spi_Cfg.h" 2 # 30 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Types.h" 2 # 99 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Types.h" typedef enum { SPI_UNINIT = 0, SPI_IDLE, SPI_BUSY } Spi_StatusType; typedef enum { SPI_JOB_OK = 0, SPI_JOB_PENDING, SPI_JOB_FAILED, SPI_JOB_QUEUED } Spi_JobResultType; typedef enum { SPI_SEQ_OK = 0, SPI_SEQ_PENDING, SPI_SEQ_FAILED, SPI_SEQ_CANCELLED } Spi_SeqResultType; typedef enum { SPI_POLLING_MODE = 0, SPI_INTERRUPT_MODE } Spi_AsyncModeType; typedef Spi_Drvw_DataBufferType Spi_DataBufferType; typedef Spi_Drvw_NumberOfDataType Spi_NumberOfDataType; typedef uint8 Spi_ChannelType; typedef uint16 Spi_JobType; typedef uint8 Spi_SequenceType; typedef Spi_Drvw_HWUnitType Spi_HWUnitType; typedef uint8 Spi_ExternalDeviceType; typedef void(Spi_NotifyType)(void); typedef struct { Spi_JobType JobNum; uint32 SpiCoreUse; const Spi_JobType *JobIndexList; Spi_NotifyType(*EndNotification); uint8 Interruptible; } Spi_SequenceConfigType; typedef struct { const Spi_SequenceConfigType *SeqConfig; } Spi_SequenceConfigListType; typedef struct { Spi_SeqResultType Result; const Spi_SequenceConfigType *Sequence; const Spi_JobType *CurrentJobIndexPointer; Spi_JobType RemainingJobs; } Spi_SequenceStateType; typedef struct { Spi_JobResultType Result; Spi_SequenceStateType *AsyncSequenceState; Spi_JobType AsyncNextJob; } Spi_JobStateType; typedef struct { Spi_ChannelType ChannelNum; const Spi_ChannelType *ChannelIndexList; Spi_NotifyType(*EndNotification); Spi_NotifyType(*StartNotification); sint8 Priority; uint32 SpiCoreUse; Spi_JobStateType *JobState; Spi_HWUnitType HWUnit; Spi_ExternalDeviceType ExternalDevice; const Spi_Drvw_ExternalDeviceListType *ExternalDeviceConfig; } Spi_JobConfigType; typedef struct { const Spi_JobConfigType *JobConfig; } Spi_JobConfigListType; typedef struct { Spi_JobType ScheduledJobsListHead[(4U)]; Spi_JobType ScheduledJobsListTail[(4U)]; sint8 MaxScheduledPriority; Spi_StatusType Status; Spi_ChannelType Channel; Spi_JobType Job; } Spi_HWUnitQueue; typedef struct { const Spi_Drvw_ChannelConfigType *ChannelConfig; } Spi_ChannelConfigListType; typedef struct { uint16 MaxExternalDevice; Spi_ChannelType SpiMaxChannel; Spi_JobType SpiMaxJob; Spi_SequenceType SpiMaxSequence; uint32 SpiCoreUse; const Spi_ChannelConfigListType *ChannelConfigList; const Spi_JobConfigListType *JobConfigList; const Spi_SequenceConfigListType *SequenceConfigList; const Spi_Drvw_ExternalDeviceListType *ExternalDeviceConfigList; const Spi_Drvw_HWUnitConfigListType *HWUnitConfigList; } Spi_ConfigType; # 30 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" 2 # 296 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 297 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" 2 extern const Spi_ConfigType Spi_Config; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" #pragma clang section rodata = "" # 304 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" 1 # 1436 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" #pragma clang section bss = ".mcal_bss" # 308 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" 2 extern Spi_JobStateType Spi_JobStateArray[(4U)]; extern Spi_Drvw_ChannelStateType Spi_ChannelStateArray[(4U)]; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" 1 # 1452 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" #pragma clang section bss = "" # 315 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" #pragma clang section text = ".mcal_code" # 324 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" 2 # 335 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" void Spi_Init(const Spi_ConfigType *ConfigPtr); # 348 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" Std_ReturnType Spi_DeInit(void); # 368 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" Std_ReturnType Spi_WriteIB(Spi_ChannelType Channel, const Spi_DataBufferType *DataBufferPtr); # 385 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" Std_ReturnType Spi_AsyncTransmit(Spi_SequenceType Sequence); # 408 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" Std_ReturnType Spi_ReadIB(Spi_ChannelType Channel, Spi_DataBufferType *DataBufferPtr); # 431 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" Std_ReturnType Spi_SetupEB(Spi_ChannelType Channel, Spi_DataBufferType *SrcDataBufferPtr, Spi_DataBufferType *DesDataBufferPtr, Spi_NumberOfDataType Length); # 448 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" Spi_StatusType Spi_GetStatus(void); # 464 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" Spi_JobResultType Spi_GetJobResult(Spi_JobType Job); # 480 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" Spi_SeqResultType Spi_GetSequenceResult(Spi_SequenceType Sequence); # 494 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" void Spi_GetVersionInfo(Std_VersionInfoType *versioninfo); # 511 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" Std_ReturnType Spi_SyncTransmit(Spi_SequenceType Sequence); # 530 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" Spi_StatusType Spi_GetHWUnitStatus(Spi_HWUnitType HWUnit); # 547 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" void Spi_Cancel(Spi_SequenceType Sequence); # 564 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" Std_ReturnType Spi_SetAsyncMode(Spi_AsyncModeType Mode); # 579 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" Std_ReturnType Spi_SetHWUnitAsyncMode(Spi_HWUnitType HWUnit, Spi_AsyncModeType Mode); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" #pragma clang section text = "" # 584 "../../../mcal/Spi_ZX_K14xM/Inc\\Spi.h" 2 # 26 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 # 1 "../../../Package/Cdd/CddSbc/Cfg\\CddSbc_Cfg.h" 1 # 1 "../../../Package/Cdd\\CddTle94x1\\Gen\\CddTle94x1_Types.h" 1 # 43 "../../../Package/Cdd\\CddTle94x1\\Gen\\CddTle94x1_Types.h" typedef struct { boolean boInitStatRead; boolean boInitCtrlWrite; boolean boGoToStop_Failure; boolean boGotoStop_SpiFailure; boolean boGoToSleep_Failure; boolean boGotoSleep_SpiFailure; boolean boCyclic_SPI_Communication; boolean boCyclic_CanMode; boolean boReadWKStat_Failure; boolean boReadSUPStat_Failure; boolean boScheduleTableFull; boolean boCanModeError; boolean boCanChannelError; boolean boSpiWdgFailure; boolean boReadWdgStat_Failure; boolean boErrorReset; }tisSbcErrorState; typedef enum teDefaultMsgType { eNoMsg = 0, eBUS_CTRL_0, eBUS_STAT, eWK_LVL_STAT, eSUP_STAT_0, eTHERM_STAT }teDefaultMsgType; # 6 "../../../Package/Cdd/CddSbc/Cfg\\CddSbc_Cfg.h" 2 # 1 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 1 # 30 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" # 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h" 1 # 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h" # 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 1 # 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" # 1 "../Generated/inc\\Mcu_Drvw_Cfg.h" 1 # 30 "../Generated/inc\\Mcu_Drvw_Cfg.h" # 1 "../Generated/inc/Mcu_Drvw_PBcfg.h" 1 # 31 "../Generated/inc\\Mcu_Drvw_Cfg.h" 2 # 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2 # 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Scc_Drv_Types.h" 1 # 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Scc_Drv_Types.h" # 1 "../Generated/inc\\Scc_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Scc_Drv_Cfg.h" # 1 "../Generated/inc/Scc_Drv_PBcfg.h" 1 # 65 "../Generated/inc/Scc_Drv_PBcfg.h" extern void FOSCClkLossCallbackFunc(void); # 31 "../Generated/inc\\Scc_Drv_Cfg.h" 2 # 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Scc_Drv_Types.h" 2 # 90 "../../../mcal/Mcu_ZX_K14xM/Inc/Scc_Drv_Types.h" typedef enum { SCC_DRV_CLOCK_SRC_NO = 0U, SCC_DRV_CLOCK_SRC_LPO32K, SCC_DRV_CLOCK_SRC_SOSC, SCC_DRV_CLOCK_SRC_FIRC64M, SCC_DRV_CLOCK_SRC_FOSC, SCC_DRV_CLOCK_SRC_PLL } Scc_Drv_ClockSrcType; typedef enum { SCC_DRV_SYS_CLOCK_FIRC64M = 1U, SCC_DRV_SYS_CLOCK_FOSC = 2U, SCC_DRV_SYS_CLOCK_PLL = 3U } Scc_Drv_SystemClockType; typedef enum { SCC_DRV_OSC_XTAL = 0U, SCC_DRV_OSC_EXT_SRC } Scc_Drv_OscModeType; typedef enum { SCC_DRV_FOSC_FREQ_MODE_LOW = 0U, SCC_DRV_FOSC_FREQ_MODE_HIGH } Scc_Drv_FOscFreqModeType; typedef enum { SCC_DRV_OSC_CLOCK_LOSS_INT = 0U, SCC_DRV_OSC_CLOCK_LOSS_RST } Scc_Drv_OscClockLossActType; typedef enum { SCC_DRV_FIRC64M_CLOCK_LOSS_INT = 0U, SCC_DRV_FIRC64M_CLOCK_LOSS_RST } Scc_Drv_Firc64MClockLossActType; # 167 "../../../mcal/Mcu_ZX_K14xM/Inc/Scc_Drv_Types.h" typedef enum { SCC_DRV_PLL_REF_FIRC64M = 0U, SCC_DRV_PLL_REF_FOSC } Scc_Drv_PllRefClockType; typedef enum { SCC_DRV_PLL_PRE_DIV_1 = 0U, SCC_DRV_PLL_PRE_DIV_2 = 1U, SCC_DRV_PLL_PRE_DIV_4 = 2U } Scc_Drv_PllPreDivType; typedef enum { SCC_DRV_PLL_POST_DIV_6 = 3U, SCC_DRV_PLL_POST_DIV_8 = 4U, SCC_DRV_PLL_POST_DIV_10 = 5U, SCC_DRV_PLL_POST_DIV_12 = 6U, SCC_DRV_PLL_POST_DIV_14 = 7U } Scc_Drv_PllPostDivType; typedef enum { SCC_DRV_PLL_SCALER_1 = 0U, SCC_DRV_PLL_SCALER_2 = 1U } Scc_Drv_PllPreScalerType; typedef enum { SCC_DRV_SYS_CLOCK_CORE = 0x85U, SCC_DRV_SYS_CLOCK_BUS = 0x86U, SCC_DRV_SYS_CLOCK_SLOW = 0x87U } Scc_Drv_SysClockType; typedef enum { SCC_DRV_SYS_CLOCK_DIV_1 = 0U, SCC_DRV_SYS_CLOCK_DIV_2, SCC_DRV_SYS_CLOCK_DIV_3, SCC_DRV_SYS_CLOCK_DIV_4, SCC_DRV_SYS_CLOCK_DIV_5, SCC_DRV_SYS_CLOCK_DIV_6, SCC_DRV_SYS_CLOCK_DIV_7, SCC_DRV_SYS_CLOCK_DIV_8, SCC_DRV_SYS_CLOCK_DIV_9, SCC_DRV_SYS_CLOCK_DIV_10, SCC_DRV_SYS_CLOCK_DIV_11, SCC_DRV_SYS_CLOCK_DIV_12, SCC_DRV_SYS_CLOCK_DIV_13, SCC_DRV_SYS_CLOCK_DIV_14, SCC_DRV_SYS_CLOCK_DIV_15, SCC_DRV_SYS_CLOCK_DIV_16 } Scc_Drv_SysClockDividerType; typedef struct { Scc_Drv_PllPreDivType PllPreDivider; Scc_Drv_PllPostDivType PllPostDivider; uint32 PllMultiplier; Scc_Drv_PllRefClockType PllRefClock; Scc_Drv_PllPreScalerType PllPreScaler; uint32 PllFreq; } Scc_Drv_PllParamConfigType; typedef struct { Scc_Drv_PllParamConfigType SccPllClockParamConfig; boolean SccPllEnableUnderStop; boolean Enable; } Scc_Drv_PllClockConfigType; typedef void (*Scc_Drv_LocCallbackFunc)(void); typedef struct { boolean Firc64MStopEn; boolean Enable; Scc_Drv_LocCallbackFunc Firc64MLocCallbackFunc; } Scc_Drv_Firc64MClockConfigType; typedef struct { Scc_Drv_FOscFreqModeType SccOscHfreq; boolean SccOscEnableUnderStop; Scc_Drv_OscModeType Mode; boolean Enable; Scc_Drv_LocCallbackFunc LocCallbackFunc; } Scc_Drv_FOscClockConfigType; typedef struct { Scc_Drv_OscModeType Mode; boolean Enable; } Scc_Drv_SOscClockConfigType; typedef struct { uint32 Enable; } Scc_Drv_LpoClockConfigType; typedef struct { Scc_Drv_SystemClockType SccSystemClockSource; uint32 SccSystemClockFreq; Scc_Drv_SysClockDividerType SccCoreClockDivider; Scc_Drv_SysClockDividerType SccBusClockDivider; Scc_Drv_SysClockDividerType SccSlowClockDivider; } Scc_Drv_SystemClockConfigType; typedef struct { Scc_Drv_SystemClockConfigType SccSystemClockConfig; Scc_Drv_Firc64MClockConfigType SccFircClockConfig; Scc_Drv_FOscClockConfigType SccFOscClockConfig; Scc_Drv_PllClockConfigType SccPllClockConfig; Scc_Drv_SOscClockConfigType SccSOscClockConfig; Scc_Drv_LpoClockConfigType SccLpoClockConfig; } Scc_Drv_ClockConfigType; # 32 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2 # 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Parcc_Drv_Types.h" 1 # 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Parcc_Drv_Types.h" # 1 "../Generated/inc\\Parcc_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Parcc_Drv_Cfg.h" # 1 "../Generated/inc/Parcc_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Parcc_Drv_Cfg.h" 2 # 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Parcc_Drv_Types.h" 2 # 91 "../../../mcal/Mcu_ZX_K14xM/Inc/Parcc_Drv_Types.h" typedef enum { PARCC_DRV_WDOG = 0x00U, PARCC_DRV_EWDT, PARCC_DRV_STIM, PARCC_DRV_TIM0, PARCC_DRV_TIM1, PARCC_DRV_TIM2, PARCC_DRV_TIM3, PARCC_DRV_MCPWM0, PARCC_DRV_MCPWM1, PARCC_DRV_TDG0, PARCC_DRV_TDG1, PARCC_DRV_CAN0, PARCC_DRV_CAN1, PARCC_DRV_CAN2, PARCC_DRV_CAN3, PARCC_DRV_CAN4, PARCC_DRV_CAN5, PARCC_DRV_CAN6, PARCC_DRV_CAN7, PARCC_DRV_UART0, PARCC_DRV_UART1, PARCC_DRV_UART2, PARCC_DRV_UART3, PARCC_DRV_UART4, PARCC_DRV_UART5, PARCC_DRV_SPI0, PARCC_DRV_SPI1, PARCC_DRV_SPI2, PARCC_DRV_SPI3, PARCC_DRV_I2C0, PARCC_DRV_I2C1, PARCC_DRV_I2S0, PARCC_DRV_I2S1, PARCC_DRV_RESERVED1, PARCC_DRV_ADC0, PARCC_DRV_ADC1, PARCC_DRV_CMP0, PARCC_DRV_CRC, PARCC_DRV_AES, PARCC_DRV_TRNG, PARCC_DRV_FLASH, PARCC_DRV_RESERVED2, PARCC_DRV_DMA, PARCC_DRV_DMAMUX, PARCC_DRV_PORTA, PARCC_DRV_PORTB, PARCC_DRV_PORTC, PARCC_DRV_PORTD, PARCC_DRV_PORTE, PARCC_DRV_TMU, PARCC_DRV_REGFILE, PARCC_DRV_SMPU, PARCC_DRV_GPIO } Parcc_Drv_ModuleType; typedef enum { PARCC_DRV_CLOCK_SRC_NO = 0U, PARCC_DRV_CLOCK_SRC_LPO32K = 1U, PARCC_DRV_CLOCK_SRC_SOSC = 2U, PARCC_DRV_CLOCK_SRC_FIRC64M = 3U, PARCC_DRV_CLOCK_SRC_FOSC = 4U, PARCC_DRV_CLOCK_SRC_PLL = 5U, PARCC_DRV_CLOCK_SRC_SLOW = 6U, PARCC_DRV_CLOCK_SRC_BUS = 7U, PARCC_DRV_CLOCK_SRC_CORE = 8U } Parcc_Drv_ClockSrcType; typedef enum { PARCC_DRV_CLOCK_DIV_1 = 0U, PARCC_DRV_CLOCK_DIV_2, PARCC_DRV_CLOCK_DIV_3, PARCC_DRV_CLOCK_DIV_4, PARCC_DRV_CLOCK_DIV_5, PARCC_DRV_CLOCK_DIV_6, PARCC_DRV_CLOCK_DIV_7, PARCC_DRV_CLOCK_DIV_8, PARCC_DRV_CLOCK_DIV_9, PARCC_DRV_CLOCK_DIV_10, PARCC_DRV_CLOCK_DIV_11, PARCC_DRV_CLOCK_DIV_12, PARCC_DRV_CLOCK_DIV_13, PARCC_DRV_CLOCK_DIV_14, PARCC_DRV_CLOCK_DIV_15, PARCC_DRV_CLOCK_DIV_16 } Parcc_Drv_ClockDividerType; typedef enum { PARCC_DRV_STATUS_OK = 0x00U, PARCC_DRV_STATUS_NOT_OK = 0x01U, PARCC_DRV_STATUS_UNDEFINED = 0x02U } Parcc_Drv_StatusType; typedef struct { Parcc_Drv_ModuleType ParccModule; Parcc_Drv_ClockSrcType ParccModuleSrc; Parcc_Drv_ClockDividerType ParccModuleDivider; boolean Enable; boolean SupervisorAccessEnable; boolean WriteLockEnable; } Parcc_Drv_ModuleConfigType; typedef struct { uint32 NumberOfModule; const Parcc_Drv_ModuleConfigType *SystemParccConfigPtr; } Parcc_Drv_SystemParccConfigType; # 33 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2 # 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Pmu_Drv_Types.h" 1 # 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Pmu_Drv_Types.h" # 1 "../Generated/inc\\Pmu_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Pmu_Drv_Cfg.h" # 1 "../Generated/inc/Pmu_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Pmu_Drv_Cfg.h" 2 # 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Pmu_Drv_Types.h" 2 # 90 "../../../mcal/Mcu_ZX_K14xM/Inc/Pmu_Drv_Types.h" typedef enum { PMU_DRV_VDD_LVD_LP = 0U, PMU_DRV_VDD_LVD_ACT = 1U, PMU_DRV_VDD_LVD_RE = 3U, PMU_DRV_VDD_LVW = 4U, PMU_DRV_REF_BUF_1V = 8U } Pmu_Drv_CtrlType; typedef enum { PMU_DRV_VDD_LVW_INT = 0U, PMU_DRV_VDD_LVD_INT } Pmu_Drv_IntType; typedef void (*Pmu_Drv_CallbackFunc)(void); typedef struct { boolean PmuCtrlLVDLowPowerEnable; boolean PmuCtrlLVDActiveEnable; boolean PmuCtrlLVDResetEnable; boolean PmuCtrlLVWEnable; boolean PmuCtrlRef1VEnable; boolean PmuLVDInterruptEnable; Pmu_Drv_CallbackFunc PmuLVDInterruptCallbackFunc; boolean PmuLVWInterruptEnable; Pmu_Drv_CallbackFunc PmuLVWInterruptCallbackFunc; } Pmu_Drv_ConfigType; # 34 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2 # 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Scm_Mcu_Drv_Types.h" 1 # 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Scm_Mcu_Drv_Types.h" # 1 "../Generated/inc\\Scm_Mcu_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Scm_Mcu_Drv_Cfg.h" # 1 "../Generated/inc/Scm_Mcu_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Scm_Mcu_Drv_Cfg.h" 2 # 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Scm_Mcu_Drv_Types.h" 2 # 93 "../../../mcal/Mcu_ZX_K14xM/Inc/Scm_Mcu_Drv_Types.h" typedef enum { SCM_MCU_DRV_CLOCK_OUT_DIV_1 = 0U, SCM_MCU_DRV_CLOCK_OUT_DIV_2 = 1U, SCM_MCU_DRV_CLOCK_OUT_DIV_4 = 2U, SCM_MCU_DRV_CLOCK_OUT_DIV_8 = 3U } Scm_Mcu_Drv_ClockOutDivType; typedef enum { SCM_MCU_DRV_CLOCK_OUT_DISABLED = 0U, SCM_MCU_DRV_CLOCK_OUT_FIRC64M = 1U, SCM_MCU_DRV_CLOCK_OUT_FOSC = 2U, SCM_MCU_DRV_CLOCK_OUT_PLL = 3U, SCM_MCU_DRV_CLOCK_OUT_SLOW = 8U, SCM_MCU_DRV_CLOCK_OUT_BUS = 9U, SCM_MCU_DRV_CLOCK_OUT_CORE = 10U, SCM_MCU_DRV_CLOCK_OUT_SOSC = 11U, SCM_MCU_DRV_CLOCK_OUT_LPO32K = 12U } Scm_Mcu_Drv_ClockOutSrcType; typedef enum { SCM_MCU_DRV_SRAML = 0U, SCM_MCU_DRV_SRAMU = 1U } Scm_Mcu_Drv_SramType; typedef enum { SCM_MCU_DRV_TIM0 = 3U, SCM_MCU_DRV_TIM1 = 4U, SCM_MCU_DRV_TIM2 = 5U, SCM_MCU_DRV_TIM3 = 6U, SCM_MCU_DRV_MCPWM0 = 7U, SCM_MCU_DRV_MCPWM1 = 8U } Scm_Mcu_Drv_TimerType; typedef enum { SCM_MCU_DRV_TCLK0 = 0U, SCM_MCU_DRV_TCLK1 = 1U, SCM_MCU_DRV_TCLK2 = 2U } Scm_Mcu_Drv_TimerExtClockInputType; typedef enum { SCM_MCU_DRV_ADC1CH15 = 0U, SCM_MCU_DRV_ADC1CH14 = 1U, SCM_MCU_DRV_ADC0CH9 = 2U, SCM_MCU_DRV_ADC0CH8 = 3U } Scm_Mcu_Drv_AdcChannelSelectType; typedef enum { SCM_MCU_DRV_ADCMUX0 = 0U, SCM_MCU_DRV_ADCMUX1 = 1U } Scm_Mcu_Drv_AdcMuxSelectType; typedef enum { SCM_MCU_DRV_CCACHE_BE_INT = 0U, SCM_MCU_DRV_FPU_INEXACT_INT = 1U, SCM_MCU_DRV_FPU_OVERFLOW_INT = 2U, SCM_MCU_DRV_FPU_UNDERFLOW_INT = 3U, SCM_MCU_DRV_FPU_INVALIDOP_INT = 4U, SCM_MCU_DRV_FPU_DIVZERO_INT = 5U, SCM_MCU_DRV_FPU_DENORMALIN_INT = 6U } Scm_Mcu_Drv_IntType; typedef struct { Scm_Mcu_Drv_ClockOutSrcType ScmClockOutputSrc; Scm_Mcu_Drv_ClockOutDivType ScmClockOutputDivider; boolean Enable; } Scm_Mcu_Drv_ClockOutputConfigType; typedef struct { Scm_Mcu_Drv_ClockOutputConfigType ScmClockOutputConfig; } Scm_Mcu_Drv_ClockConfigType; typedef struct { boolean CacheBEInterruptEnable; boolean FpuInExactInterruptEnable; boolean FpuOverflowInterruptEnable; boolean FpuUnderflowInterruptEnable; boolean FpuInvalidOPInterruptEnable; boolean FpuDivzeroInterruptEnable; boolean FpuDenormalInterruptEnable; boolean SramLReadBufferEnable; boolean SramUReadBufferEnable; boolean CacheEnable; boolean CacheParityFaultEnable; boolean CacheParityMissEnable; Scm_Mcu_Drv_TimerExtClockInputType Mcpwm0Select; Scm_Mcu_Drv_TimerExtClockInputType Mcpwm1Select; Scm_Mcu_Drv_TimerExtClockInputType Tim0Select; Scm_Mcu_Drv_TimerExtClockInputType Tim1Select; Scm_Mcu_Drv_TimerExtClockInputType Tim2Select; Scm_Mcu_Drv_TimerExtClockInputType Tim3Select; Scm_Mcu_Drv_AdcMuxSelectType Adc0Ch8Select; Scm_Mcu_Drv_AdcMuxSelectType Adc0Ch9Select; Scm_Mcu_Drv_AdcMuxSelectType Adc1Ch14Select; Scm_Mcu_Drv_AdcMuxSelectType Adc1Ch15Select; } Scm_Mcu_Drv_ConfigType; # 35 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2 # 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Srmc_Drv_Types.h" 1 # 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Srmc_Drv_Types.h" # 1 "../Generated/inc\\Srmc_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Srmc_Drv_Cfg.h" # 1 "../Generated/inc/Srmc_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Srmc_Drv_Cfg.h" 2 # 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Srmc_Drv_Types.h" 2 # 119 "../../../mcal/Mcu_ZX_K14xM/Inc/Srmc_Drv_Types.h" typedef enum { SRMC_DRV_RESET_PIN_DISABLE_FILTER = 0U, SRMC_DRV_RESET_PIN_BUS_CLOCK_FILTER, SRMC_DRV_RESET_PIN_LPO_CLOCK_FILTER } Srmc_Drv_ResetPinFilterType; typedef enum { SRMC_DRV_DELAY_8_LPO_CYCLES = 0U, SRMC_DRV_DELAY_32_LPO_CYCLES, SRMC_DRV_DELAY_128_LPO_CYCLES, SRMC_DRV_DELAY_512_LPO_CYCLES } Srmc_Drv_DelayType; typedef enum { SRMC_DRV_MODE_RUN = 0U, SRMC_DRV_MODE_WAIT, SRMC_DRV_MODE_STOP, SRMC_DRV_MODE_STANDBY } Srmc_Drv_PowerModeType; typedef enum { SRMC_DRV_WUPSRC_PTD0 = 0x0U, SRMC_DRV_WUPSRC_PTD1 = 0x1U, SRMC_DRV_WUPSRC_PTA4 = 0x2U, SRMC_DRV_WUPSRC_PTC4 = 0x4U, SRMC_DRV_WUPSRC_PTC5 = 0x5U, SRMC_DRV_WUPSRC_PTE0 = 0x6U, SRMC_DRV_WUPSRC_PTE1 = 0x7U, SRMC_DRV_WUPSRC_PTE11 = 0x8U, SRMC_DRV_WUPSRC_PTE13 = 0x9U, SRMC_DRV_WUPSRC_PTE15 = 0xAU, SRMC_DRV_WUPSRC_PTE16 = 0xBU, SRMC_DRV_WUPSRC_PTA8 = 0xCU, SRMC_DRV_WUPSRC_PTA9 = 0xDU, SRMC_DRV_WUPSRC_PTA25 = 0xEU, SRMC_DRV_WUPSRC_PMU = 0xFU, SRMC_DRV_WUPSRC_RTC = 0x10U } Srmc_Drv_WakeupSourceType; typedef enum { SRMC_DRV_WUPSRC_POLARITY_LOW = 0x0U, SRMC_DRV_WUPSRC_POLARITY_HIGH = 0x1U } Srmc_Drv_WupPolarityType; # 298 "../../../mcal/Mcu_ZX_K14xM/Inc/Srmc_Drv_Types.h" typedef struct { Srmc_Drv_ResetPinFilterType ResetPinFilterInNormal; Srmc_Drv_ResetPinFilterType ResetPinFilterInStop; uint32 ResetPinFilterBusClock; boolean CoreLockupResetEnable; Srmc_Drv_DelayType ResetDelayTime; uint32 ResetInterruptEnable; } Srmc_Drv_ResetConfigType; typedef struct { boolean AllowStandbyMode; uint32 StopModeAckTimeout; uint32 WakeupControl1; uint32 WakeupControl2; } Srmc_Drv_PowerModeConfigType; # 36 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2 # 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Ram_Drv_Types.h" 1 # 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Ram_Drv_Types.h" # 1 "../Generated/inc\\Ram_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Ram_Drv_Cfg.h" # 1 "../Generated/inc/Ram_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Ram_Drv_Cfg.h" 2 # 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Ram_Drv_Types.h" 2 # 90 "../../../mcal/Mcu_ZX_K14xM/Inc/Ram_Drv_Types.h" typedef enum { RAM_DRV_STATUS_OK = 0x00U, RAM_DRV_STATUS_NOT_OK = 0x01U, RAM_DRV_STATUS_UNDEFINED = 0x02U } Ram_Drv_StatusType; typedef uint32 Ram_Drv_SectorSizeType; typedef uint32 Ram_Drv_WriteSizeType; typedef uint32 Ram_Drv_IndexType; typedef struct { uint32 RamBaseAddr; uint32 RamSize; uint64 RamDefaultValue; uint32 RamWriteSize; } Ram_Drv_ConfigType; # 37 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2 # 202 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" typedef enum { MCU_DRVW_OSC_CLOCK_LOSS_INT = 0U, MCU_DRVW_OSC_CLOCK_LOSS_RST } Mcu_Drvw_OscClockLossActType; typedef enum { MCU_DRVW_FIRC64M_CLOCK_LOSS_INT = 0U, MCU_DRVW_FIRC64M_CLOCK_LOSS_RST } Mcu_Drvw_Firc64MClockLossActType; typedef enum { MCU_DRVW_WUPSRC_PTD0 = 0x0U, MCU_DRVW_WUPSRC_PTD1 = 0x1U, MCU_DRVW_WUPSRC_PTA4 = 0x2U, MCU_DRVW_WUPSRC_PTC4 = 0x4U, MCU_DRVW_WUPSRC_PTC5 = 0x5U, MCU_DRVW_WUPSRC_PTE0 = 0x6U, MCU_DRVW_WUPSRC_PTE1 = 0x7U, MCU_DRVW_WUPSRC_PTE11 = 0x8U, MCU_DRVW_WUPSRC_PTE13 = 0x9U, MCU_DRVW_WUPSRC_PTE15 = 0xAU, MCU_DRVW_WUPSRC_PTE16 = 0xBU, MCU_DRVW_WUPSRC_PTA8 = 0xCU, MCU_DRVW_WUPSRC_PTA9 = 0xDU, MCU_DRVW_WUPSRC_PTA25 = 0xEU, MCU_DRVW_WUPSRC_PMU = 0xFU, MCU_DRVW_WUPSRC_RTC = 0x10U } Mcu_Drvw_WakeupSourceType; typedef enum { MCU_DRVW_CLOCK_SRC_NO = 0U, MCU_DRVW_CLOCK_SRC_LPO32K = 1U, MCU_DRVW_CLOCK_SRC_SOSC = 2U, MCU_DRVW_CLOCK_SRC_FIRC64M = 3U, MCU_DRVW_CLOCK_SRC_FOSC = 4U, MCU_DRVW_CLOCK_SRC_PLL = 5U } Mcu_Drvw_ClockSrcType; # 271 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" typedef enum { MCU_DRVW_WAKEUP_RESET = 0U, MCU_DRVW_LVD_RESET = 1U, MCU_DRVW_LOC_RESET = 2U, MCU_DRVW_WATCHDOG_RESET = 5U, MCU_DRVW_PIN_RESET = 6U, MCU_DRVW_POWER_ON_RESET = 7U, MCU_DRVW_LOCKUP_RESET = 9U, MCU_DRVW_SW_RESET = 10U, MCU_DRVW_MDM_AP_RESET = 11U, MCU_DRVW_SERU_COLD_RESET = 12U, MCU_DRVW_SERU_SYS_RESET = 13U, MCU_DRVW_SERU_SACKERR = 15U, MCU_DRVW_MULTIPLE_RESET_REASON = 0x55U, MCU_DRVW_RESET_UNDEFINED = 0xFFU } Mcu_Drvw_ResetType; typedef enum { MCU_DRVW_POWERMODE_RUN = 0U, MCU_DRVW_POWERMODE_WAIT, MCU_DRVW_POWERMODE_STOP, MCU_DRVW_POWERMODE_STANDBY } Mcu_Drvw_PowerModeType; typedef struct { const Scc_Drv_ClockConfigType *SccClockConfigPtr; const Scm_Mcu_Drv_ClockConfigType *ScmClockConfigPtr; const Parcc_Drv_SystemParccConfigType *ParccConfigPtr; } Mcu_Drvw_ClockConfigType; # 320 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" typedef struct { const Srmc_Drv_ResetConfigType *SrmcResetConfigPtr; const Srmc_Drv_PowerModeConfigType *SrmcPowerModeConfigPtr; const Scm_Mcu_Drv_ConfigType *ScmConfigPtr; const Pmu_Drv_ConfigType *PmuConfigPtr; } Mcu_Drvw_HwConfigType; # 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h" 2 # 1 "../Generated/inc\\Mcu_Cfg.h" 1 # 30 "../Generated/inc\\Mcu_Cfg.h" # 1 "../Generated/inc/Mcu_PBcfg.h" 1 # 31 "../Generated/inc\\Mcu_Cfg.h" 2 # 32 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h" 2 # 94 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h" typedef enum { MCU_POWER_ON_RESET = 0x00U, MCU_WATCHDOG_RESET, MCU_SW_RESET, MCU_RESET_UNDEFINED, MCU_WAKEUP_RESET, MCU_LVD_RESET, MCU_LOC_RESET, MCU_PIN_RESET, MCU_LOCKUP_RESET, MCU_MDM_AP_RESET, MCU_SERU_COLD_RESET, MCU_SERU_SYS_RESET, MCU_SERU_SACKERR, MCU_HW_TEST_RESET, MCU_MULTIPLE_RESET_REASON } Mcu_ResetType; # 128 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h" typedef enum { MCU_OSC_CLOCK_LOSS_INT = 0U, MCU_OSC_CLOCK_LOSS_RST } Mcu_OscClockLossActType; typedef enum { MCU_FIRC64M_CLOCK_LOSS_INT = 0U, MCU_FIRC64M_CLOCK_LOSS_RST } Mcu_Firc64MClockLossActType; # 157 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h" typedef enum { MCU_WUPSRC_PTD0 = 0x0U, MCU_WUPSRC_PTD1 = 0x1U, MCU_WUPSRC_PTA4 = 0x2U, MCU_WUPSRC_PTC4 = 0x4U, MCU_WUPSRC_PTC5 = 0x5U, MCU_WUPSRC_PTE0 = 0x6U, MCU_WUPSRC_PTE1 = 0x7U, MCU_WUPSRC_PTE11 = 0x8U, MCU_WUPSRC_PTE13 = 0x9U, MCU_WUPSRC_PTE15 = 0xAU, MCU_WUPSRC_PTE16 = 0xBU, MCU_WUPSRC_PTA8 = 0xCU, MCU_WUPSRC_PTA9 = 0xDU, MCU_WUPSRC_PTA25 = 0xEU, MCU_WUPSRC_PMU = 0xFU, MCU_WUPSRC_RTC = 0x10U } Mcu_WakeupSourceType; typedef enum { MCU_PLL_LOCKED = 0U, MCU_PLL_UNLOCKED = 1U, MCU_PLL_STATUS_UNDEFINED = 2U } Mcu_PllStatusType; typedef enum { MCU_POWERMODE_RUN = 0U, MCU_POWERMODE_WAIT, MCU_POWERMODE_STOP, MCU_POWERMODE_STANDBY } Mcu_PowerModeType; typedef uint32 Mcu_RamSectionType; typedef uint32 Mcu_ModeType; typedef uint32 Mcu_ClockType; typedef uint32 Mcu_RawResetType; typedef struct { Mcu_RamSectionType RamSectorId; uint32 RamBaseAddr; uint32 RamSize; uint64 RamDefaultValue; uint32 RamWriteSize; } Mcu_RamConfigType; typedef struct { Mcu_ModeType ModeConfigId; Mcu_PowerModeType PowerMode; } Mcu_ModeConfigType; typedef struct { Mcu_ClockType ClockConfigId; const Mcu_Drvw_ClockConfigType *ClockConfigPtr; } Mcu_ClockConfigType; typedef struct { Mcu_RamSectionType NoOfRamConfigs; Mcu_ModeType NoOfModeConfigs; Mcu_ClockType NoOfClkConfigs; const Mcu_ModeConfigType (*ModeConfigPtr)[((uint32)1U)]; const Mcu_ClockConfigType (*ClockConfigPtr)[((uint32)1U)]; const Mcu_Drvw_HwConfigType *HwConfigPtr; } Mcu_ConfigType; # 31 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2 # 124 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" 1 # 848 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 125 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2 extern const Mcu_ConfigType *const Mcu_PreDefinedConfigPtr; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" 1 # 864 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" #pragma clang section rodata = "" # 128 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2 # 139 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 140 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" #pragma clang section rodata = "" # 143 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" #pragma clang section text = ".mcal_code" # 152 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2 # 161 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" void Mcu_Init(const Mcu_ConfigType *ConfigPtr); # 173 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" Std_ReturnType Mcu_InitRamSection(Mcu_RamSectionType RamSection); # 186 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" Std_ReturnType Mcu_InitClock(Mcu_ClockType ClockSetting); # 200 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" Std_ReturnType Mcu_DistributePllClock(void); # 214 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" Mcu_PllStatusType Mcu_GetPllStatus(void); # 224 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" Mcu_ResetType Mcu_GetResetReason(void); # 234 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" Mcu_RawResetType Mcu_GetResetRawValue(void); # 245 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" void Mcu_PerformReset(void); # 256 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" void Mcu_SetMode(Mcu_ModeType McuMode); # 267 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" void Mcu_GetVersionInfo(Std_VersionInfoType *versioninfo); # 291 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" Mcu_PowerModeType Mcu_GetPowerModeState(void); # 304 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" boolean Mcu_EnableOscClockMonitor(Mcu_OscClockLossActType Act); # 314 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" void Mcu_DisableOscClockMonitor(void); # 326 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" boolean Mcu_EnableFircClockMonitor(Mcu_Firc64MClockLossActType Act); # 336 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" void Mcu_DisableFircClockMonitor(void); # 360 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" void Mcu_SetWakeupSource(Mcu_WakeupSourceType WakeupSource, boolean ActiveHigh, boolean Enable); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" #pragma clang section text = "" # 364 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2 # 8 "../../../Package/Cdd/CddSbc/Cfg\\CddSbc_Cfg.h" 2 # 27 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 # 1 "../../../Package/Cdd/CddTle94x1/Api\\CddTle94x1.h" 1 # 30 "../../../Package/Cdd/CddTle94x1/Api\\CddTle94x1.h" # 1 "../../../Package/Cdd/CddSbc/Cfg\\CddSbc_Router.h" 1 # 28 "../../../Package/Cdd/CddSbc/Cfg\\CddSbc_Router.h" typedef enum { eNoResetMCU = 0, ePowerOnResetMCU, eWatchdogResetMCU, eSoftwareReset, ePLLReset, eECCReset, eMCUSelfTestReset, eUnderVoltage, eOtherReasons }teMCUResetType; typedef enum { eNoResetSBC = 0, ePowerOnResetSBC, eCANWakeUpReset, eWatchdogReset, eInputWakeUpReset }teSBCResetType; void CddSbc_Rou_Init(void); void CddSbc_Rou_DeInit(void); void CddSbc_Rou_SetSleepMode(void); void CddSbc_Rou_SetCanMode(uint8 ucCanChannel, uint8 ucCanMode); uint8 CddSbc_Rou_GetCanMode(uint8 ucCanChannel); uint8 CddSbc_Rou_GetCanUV(void); boolean CddSbc_Rou_GetWakeUpStatus(void); uint8 CddSbc_Rou_GetSBCResetReason(void); void CddSbc_Rou_SetWdgWindowModeAnd10ms(void); void CddSbc_Rou_SetWdgWindowModeAnd200ms(void); void CddSbc_Rou_SetWdgTimeoutModeAnd200ms(void); # 31 "../../../Package/Cdd/CddTle94x1/Api\\CddTle94x1.h" 2 # 48 "../../../Package/Cdd/CddTle94x1/Api\\CddTle94x1.h" # 1 "../../../Package/Cdd/CddTle94x1/Cfg\\../Cfg/CddTle94x1_MemMap.h" 1 # 49 "../../../Package/Cdd/CddTle94x1/Api\\CddTle94x1.h" 2 # 62 "../../../Package/Cdd/CddTle94x1/Api\\CddTle94x1.h" void CddTle94x1_Init(void); void CddTle94x1_DeInit(void); void CddTle94x1_SetSleepMode(void); void CddTle94x1_SetCanMode(uint8 ucCanChannel, uint8 ucCanMode); uint8 CddTle94x1_GetCanMode(uint8 ucCanChannel); uint8 CddTle94x1_GetCanUV(void); boolean CddTle94x1_GetWakeUpStatus(void); void CddSbc_InsertDefaultMessage(void); void CddSbc_ScheduleTableFull(boolean boStatus); uint8 CddTle94x1_GetSBCResetReason(void); void CddTle94x1_SetWdgWindowModeAnd10ms(void); void CddTle94x1_SetWdgTimeoutModeAnd200ms(void); void CddTle94x1_SetWdgWindowModeAnd200ms(void); boolean CddSpi_TransferMsg(uint16 *Data, uint16 *RcData, uint8 len, uint8 Cs); uint8 Spi_Stat_Get(void); # 1 "../../../Package/Cdd/CddTle94x1/Cfg\\../Cfg/CddTle94x1_MemMap.h" 1 # 97 "../../../Package/Cdd/CddTle94x1/Api\\CddTle94x1.h" 2 # 35 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 # 1 "../../../Package/Cdd/CddTle94x1/Cfg\\CddTle94x1_Cfg.h" 1 # 36 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 # 1 "../../../Package/Cdd/CddTle94x1/Gen\\CddTle94x1_Regs.h" 1 # 197 "../../../Package/Cdd/CddTle94x1/Gen\\CddTle94x1_Regs.h" typedef struct { uint8 VCC1_RT : 2; uint8 VCC1_OV_RST : 1; uint8 VCC2_ON : 2; uint8 : 1; uint8 MODE : 2; } tTle94x1_M_S_CTRL_Bit; typedef struct { uint8 Address; union { tTle94x1_M_S_CTRL_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_M_S_CTRL_Register; typedef struct { uint8 CFG1 : 1; uint8 : 1; uint8 CP_EN : 1; uint8 : 2; uint8 FO_ON : 1; uint8 SOFT_RESET_RST: 1; uint8 : 1; } tTle94x1_HW_CTRL_0_Bit; typedef struct { uint8 Address; union { tTle94x1_HW_CTRL_0_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_HW_CTRL_0_Register; typedef struct { uint8 WD_TIMER : 3; uint8 : 1; uint8 WD_EN_WK_BUS : 1; uint8 WD_WIN : 1; uint8 WD_STM_EN_0 : 1; uint8 CHECKSUM : 1; } tTle94x1_WD_CTRL_Bit; typedef struct { uint8 Address; union { tTle94x1_WD_CTRL_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_WD_CTRL_Register; typedef struct { uint8 CAN : 2; uint8 : 6; } tTle94x1_BUS_CTRL_0_Bit; typedef struct { uint8 Address; union { tTle94x1_BUS_CTRL_0_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_BUS_CTRL_0_Register; typedef struct { uint8 : 2; uint8 WD_STM_EN_1 : 1; uint8 : 3; uint8 TIMER_WK_EN : 1; uint8 : 1; } tTle94x1_WK_CTRL_0_Bit; typedef struct { uint8 Address; union { tTle94x1_WK_CTRL_0_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_WK_CTRL_0_Register; typedef struct { uint8 WK_EN : 1; uint8 : 4; uint8 WK_MEAS : 1; uint8 : 1; uint8 INT_GLOBAL : 1; } tTle94x1_WK_CTRL_1_Bit; typedef struct { uint8 Address; union { tTle94x1_WK_CTRL_1_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_WK_CTRL_1_Register; typedef struct { uint8 WK_PUPD : 2; uint8 : 4; uint8 GPIO_WK_PUPD : 2; } tTle94x1_WK_PUPD_CTRL_Bit; typedef struct { uint8 Address; union { tTle94x1_WK_PUPD_CTRL_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_WK_PUPD_CTRL_Register; typedef struct { uint8 : 4; uint8 CAN_FLASH : 1; uint8 : 3; } tTle94x1_BUS_CTRL_3_Bit; typedef struct { uint8 Address; union { tTle94x1_BUS_CTRL_3_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_BUS_CTRL_3_Register; typedef struct { uint8 : 3; uint8 CFG_LOCK_0 : 1; uint8 RSTN_DEL : 1; uint8 TSD2_DEL : 1; uint8 : 1; uint8 RSTN_HYS : 1; } tTle94x1_HW_CTRL_1_Bit; typedef struct { uint8 Address; union { tTle94x1_HW_CTRL_1_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_HW_CTRL_1_Register; typedef struct { uint8 CFG_LOCK_1 : 1; uint8 : 1; uint8 SS_MOD_FR : 2; uint8 I_PEAK_TH : 1; uint8 TwoMHZ_FREQ : 3; } tTle94x1_HW_CTRL_2_Bit; typedef struct { uint8 Address; union { tTle94x1_HW_CTRL_2_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_HW_CTRL_2_Register; typedef struct { uint8 GPIO : 3; uint8 Reserved: 5; } tTle94x1_GPIO_CTRL_Bit; typedef struct { uint8 Address; union { tTle94x1_GPIO_CTRL_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_GPIO_CTRL_Register; typedef struct { uint8 PWM_DC : 8; } tTle94x1_PWM_CTRL_Bit; typedef struct { uint8 Address; union { tTle94x1_PWM_CTRL_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_PWM_CTRL_Register; typedef struct { uint8 ICC1_LIM_ADJ : 2; uint8 TSD_THR : 1; uint8 : 5; } tTle94x1_HW_CTRL_3_Bit; typedef struct { uint8 Address; union { tTle94x1_HW_CTRL_3_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_HW_CTRL_3_Register; typedef struct { uint8 TIMER_PER : 4; uint8 TIMER_ON : 3; uint8 : 1; } tTle94x1_TIMER_CTRL_0_Bit; typedef struct { uint8 Address; union { tTle94x1_TIMER_CTRL_0_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_TIMER_CTRL_0_Register; typedef struct { uint8 SYS_STAT_L : 8; } tTle94x1_SYS_STATUS_CTRL_0_Bit; typedef struct { uint8 Address; union { tTle94x1_SYS_STATUS_CTRL_0_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_SYS_STATUS_CTRL_0_Register; typedef struct { uint8 SYS_STAT_H : 8; } tTle94x1_SYS_STATUS_CTRL_1_Bit; typedef struct { uint8 Address; union { tTle94x1_SYS_STATUS_CTRL_1_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_SYS_STATUS_CTRL_1_Register; typedef struct { uint8 VCC1_WARN : 1; uint8 VCC1_OV : 1; uint8 : 3; uint8 VS_OV : 1; uint8 VS_UV : 1; uint8 : 1; } tTle94x1_SUP_STAT_1_Bit; typedef struct { uint8 Address; union { tTle94x1_SUP_STAT_1_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_SUP_STAT_1_Register; typedef struct { uint8 VCC1_UV : 1; uint8 : 1; uint8 VCC1_SC : 1; uint8 VCC2_UV : 1; uint8 VCC2_OT : 1; uint8 : 2; uint8 POR : 1; } tTle94x1_SUP_STAT_0_Bit; typedef struct { uint8 Address; union { tTle94x1_SUP_STAT_0_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_SUP_STAT_0_Register; typedef struct { uint8 TPW : 1; uint8 TSD1 : 1; uint8 TSD2 : 1; uint8 TSD2_SAFE : 1; uint8 : 4; } tTle94x1_THERM_STAT_Bit; typedef struct { uint8 Address; union { tTle94x1_THERM_STAT_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_THERM_STAT_Register; typedef struct { uint8 VCAN_UV : 1; uint8 CAN_FAIL : 2; uint8 SYSERR : 1; uint8 CANTO : 1; uint8 : 3; } tTle94x1_BUS_STAT_Bit; typedef struct { uint8 Address; union { tTle94x1_BUS_STAT_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_BUS_STAT_Register; typedef struct { uint8 FAILURE : 1; uint8 SPI_FAIL : 1; uint8 WD_FAIL : 2; uint8 : 2; uint8 DEV_STAT :2; } tTle94x1_DEV_STAT_Bit; typedef struct { uint8 Address; union { tTle94x1_DEV_STAT_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_DEV_STAT_Register; typedef struct { uint8 WK_WU : 1; uint8 : 3; uint8 TIMER_WU : 1; uint8 CAN_WU : 1; uint8 : 2; } tTle94x1_WK_STAT_0_Bit; typedef struct { uint8 Address; union { tTle94x1_WK_STAT_0_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_WK_STAT_0_Register; typedef struct { uint8 WK_LVL : 1; uint8 : 3; uint8 GPIO_LVL : 1; uint8 : 1; uint8 CFG0_STATE : 1; uint8 SBC_DEV_LVL : 1; } tTle94x1_WK_LVL_STAT_Bit; typedef struct { uint8 Address; union { tTle94x1_WK_LVL_STAT_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_WK_LVL_STAT_Register; # 687 "../../../Package/Cdd/CddTle94x1/Gen\\CddTle94x1_Regs.h" typedef struct { uint8 PROD : 4; uint8 FAM : 4; } tTle94x1_FAM_PROD_STAT_Bit; typedef struct { uint8 Address; union { tTle94x1_FAM_PROD_STAT_Bit Bit; uint8 Word; } Data; } tTle94x1_Access_FAM_PROD_STAT_Register; typedef struct { tTle94x1_Access_M_S_CTRL_Register M_S_CTRL_Register; tTle94x1_Access_HW_CTRL_0_Register HW_CTRL_0_Register; tTle94x1_Access_HW_CTRL_1_Register HW_CTRL_1_Register; tTle94x1_Access_HW_CTRL_2_Register HW_CTRL_2_Register; tTle94x1_Access_HW_CTRL_3_Register HW_CTRL_3_Register; tTle94x1_Access_BUS_CTRL_0_Register BUS_CTRL_0_Register; tTle94x1_Access_GPIO_CTRL_Register GPIO_CTRL_Register; tTle94x1_Access_WD_CTRL_Register WD_CTRL_Register; tTle94x1_Access_WK_CTRL_0_Register WK_CTRL_0_Register; tTle94x1_Access_WK_CTRL_1_Register WK_CTRL_1_Register; } tCddTle94x1_CtrlReg; typedef struct { tTle94x1_Access_SYS_STATUS_CTRL_0_Register SYS_STATUS_CTRL_0_Register; tTle94x1_Access_WK_STAT_0_Register WK_STAT_0_Register; tTle94x1_Access_SUP_STAT_0_Register SUP_STAT_0_Register; tTle94x1_Access_BUS_STAT_Register BUS_STAT_Register; tTle94x1_Access_DEV_STAT_Register DEV_STAT_Register; tTle94x1_Access_THERM_STAT_Register THERM_STAT_Register; tTle94x1_Access_WK_LVL_STAT_Register WK_LVL_STAT_Register; } tCddTle94x1_StatReg; typedef struct { tCddTle94x1_CtrlReg CtrlTx; tCddTle94x1_CtrlReg CtrlRx; tCddTle94x1_StatReg StatTx; tCddTle94x1_StatReg StatRx; } tCddTle94x1_DataMirror; # 37 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 # 1 "../../../Package/Cdd/CddTle94x1/Gen\\CddTle94x1_Com.h" 1 # 37 "../../../Package/Cdd/CddTle94x1/Gen\\CddTle94x1_Com.h" typedef void(*pfReadClBck) (uint32 ReadVal, uint16 SentVal); typedef struct { boolean CddSbc_boProcessEntry; uint16 CddSbc_unTxData; uint16 CddSbc_unRxData; pfReadClBck CddSbc_ReadClbckFunc; } tCddSbc_SpiScheduleQueue; boolean CddSbc_InsertNewSchedEntry(uint8 ucAddress, uint8 ucData, uint8 ucCommand, pfReadClBck ClbckFunction); # 38 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 # 55 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" # 1 "../../../Package/Cdd/CddTle94x1/Cfg\\../Cfg/CddTle94x1_MemMap.h" 1 # 56 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 static tisSbcErrorState CddTle94x1_ErrorType; static tCddTle94x1_DataMirror CddTle94x1_DataMirror; # 1 "../../../Package/Cdd/CddTle94x1/Cfg\\../Cfg/CddTle94x1_MemMap.h" 1 # 65 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 # 1 "../../../Package/Cdd/CddTle94x1/Cfg\\../Cfg/CddTle94x1_MemMap.h" 1 # 74 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 static teDefaultMsgType CddSbc_eDefaultMsg = eBUS_CTRL_0; # 1 "../../../Package/Cdd/CddTle94x1/Cfg\\../Cfg/CddTle94x1_MemMap.h" 1 # 81 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 # 1 "../../../Package/Cdd/CddTle94x1/Cfg\\../Cfg/CddTle94x1_MemMap.h" 1 # 90 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 static uint16 CddTle94x1_unErrorSequenceCounter; # 1 "../../../Package/Cdd/CddTle94x1/Cfg\\../Cfg/CddTle94x1_MemMap.h" 1 # 98 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 # 1 "../../../Package/Cdd/CddTle94x1/Cfg\\../Cfg/CddTle94x1_MemMap.h" 1 # 107 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 static uint8 CddTle94x1_ucSUP_STAT_0_POR = 0u; static uint8 CddTle94x1_ucWK_STAT_0_CANWU = 0u; static uint8 CddTle94x1_ucDEV_STAT_DEV_STAT = 0u; static uint8 CddTle94x1_ucTHERMO_STAT_TSD2 = 0u; static uint8 CddTle94x1_ucSUP_STAT_0_VCC1_UV = 0u; static uint8 CddTle94x1_ucWK_STAT_0_WK_WU = 0u; static uint8 CddTle94x1_eSBCResetReason = 0u; # 1 "../../../Package/Cdd/CddTle94x1/Cfg\\../Cfg/CddTle94x1_MemMap.h" 1 # 129 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 # 138 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" # 1 "../../../Package/Cdd/CddTle94x1/Cfg\\../Cfg/CddTle94x1_MemMap.h" 1 # 139 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 static boolean CddTle94x1_boIsWdgReset = 0U; # 1 "../../../Package/Cdd/CddTle94x1/Cfg\\../Cfg/CddTle94x1_MemMap.h" 1 # 146 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 # 162 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" # 1 "../../../Package/Cdd/CddTle94x1/Cfg\\../Cfg/CddTle94x1_MemMap.h" 1 # 163 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2 static void CddTle94x1_InitSettings(void); static boolean CddTle94x1_InitStatRead(void); static boolean CddTle94x1_Save_WK_STAT_0(void); static boolean CddTle94x1_Save_SUP_STAT_0(void); static boolean CddTle94x1_WriteClearReg(uint8 ucAddress, uint16 unDataField); static uint16 CddTle94x1_ReadReg(uint8 ucAddress); static void CddTle94x1_CbkGetSupState0(uint32 ulData, uint16 unSentVal); static void CddTle94x1_CbkGetWakeUpStatus(uint32 ulData, uint16 unSentVal); # 188 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static void CddTle94x1_CbkSetCanMode(uint32 ulData, uint16 unSentVal); static void CddTle94x1_CbkGetCanMode(uint32 ulData, uint16 unSentVal); static void CddTle94x1_CbkGetBusState(uint32 ulData, uint16 unSentVal); static boolean CddTle94x1_ValidateCanMode(uint8 ucCanMode); static void CddTle94x1_ErrorSequenceCounterInc(void); static void CddTle94x1_ErrorSequenceCounterClear(void); static void CddTle94x1_StoreSBCResetReason(void); static void CddTle94x1_SetWdgWithSingleOperation(void); static void CddTle94x1_CbkSetWDCtrl(uint32 ulData, uint16 unSentVal); static void CddTle94x1_GetWatchdogFlag(void); # 232 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" void CddTle94x1_Init(void) { if (CddTle94x1_InitStatRead() != 0U) { CddTle94x1_GetWatchdogFlag(); CddTle94x1_InitSettings(); } else { } CddTle94x1_StoreSBCResetReason(); } # 269 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static boolean CddTle94x1_InitStatRead(void) { boolean boReturn = 0U; if ((CddTle94x1_Save_WK_STAT_0() == 1U) && ((CddTle94x1_Save_SUP_STAT_0() == 1U))) { boReturn = 1U; CddTle94x1_ErrorType.boInitStatRead = 0u; } else { CddTle94x1_ErrorType.boInitStatRead = 1u; } return boReturn; } # 302 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static boolean CddTle94x1_Save_WK_STAT_0(void) { boolean boReturn = 0U; uint16 unReadReg = CddTle94x1_ReadReg(0x46U); if (unReadReg != 0xFFFFu) { CddTle94x1_DataMirror.StatRx.WK_STAT_0_Register.Data.Word = (uint8)unReadReg; CddTle94x1_ucWK_STAT_0_CANWU = CddTle94x1_DataMirror.StatRx.WK_STAT_0_Register.Data.Bit.CAN_WU; CddTle94x1_ucWK_STAT_0_WK_WU = CddTle94x1_DataMirror.StatRx.WK_STAT_0_Register.Data.Bit.WK_WU; CddTle94x1_ErrorType.boReadWKStat_Failure = 0u; boReturn = 1U; } else { CddTle94x1_ErrorType.boReadWKStat_Failure = 1u; } return boReturn; } # 339 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static boolean CddTle94x1_Save_SUP_STAT_0(void) { boolean boReturn = 0U; uint16 unReadReg = CddTle94x1_ReadReg(0x41U); if (unReadReg != 0xFFFFu) { CddTle94x1_DataMirror.StatRx.SUP_STAT_0_Register.Data.Word = (uint8)unReadReg; CddTle94x1_ucSUP_STAT_0_POR = CddTle94x1_DataMirror.StatRx.SUP_STAT_0_Register.Data.Bit.POR; CddTle94x1_ucSUP_STAT_0_VCC1_UV = CddTle94x1_DataMirror.StatRx.SUP_STAT_0_Register.Data.Bit.VCC1_UV; CddTle94x1_ErrorType.boReadSUPStat_Failure = 0u; boReturn = 1U; } else { CddTle94x1_ErrorType.boReadSUPStat_Failure = 1u; } return boReturn; } # 376 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static void CddTle94x1_GetWatchdogFlag(void) { uint16 unReadReg_DEV_STAT = CddTle94x1_ReadReg(0x43U); uint16 unReadReg_THERM_STAT = CddTle94x1_ReadReg(0x42U); if ( (unReadReg_DEV_STAT != 0xFFFFu) && (unReadReg_THERM_STAT != 0xFFFFu) ) { CddTle94x1_DataMirror.StatRx.DEV_STAT_Register.Data.Word = (uint8)unReadReg_DEV_STAT; CddTle94x1_ucDEV_STAT_DEV_STAT = CddTle94x1_DataMirror.StatRx.DEV_STAT_Register.Data.Bit.DEV_STAT; CddTle94x1_DataMirror.StatRx.THERM_STAT_Register.Data.Word = (uint8)unReadReg_THERM_STAT; CddTle94x1_ucTHERMO_STAT_TSD2 = (uint8)CddTle94x1_DataMirror.StatRx.THERM_STAT_Register.Data.Bit.TSD2; CddTle94x1_ErrorType.boReadWdgStat_Failure = 0u; } else { CddTle94x1_ErrorType.boReadWdgStat_Failure = 1u; } if ( (CddTle94x1_ucDEV_STAT_DEV_STAT == 1u) && (CddTle94x1_ucTHERMO_STAT_TSD2 == 0u) && (CddTle94x1_ucSUP_STAT_0_VCC1_UV == 0u) ) { CddTle94x1_boIsWdgReset = 1U; } else { CddTle94x1_boIsWdgReset = 0U; } } # 425 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static void CddTle94x1_InitSettings(void) { CddTle94x1_DataMirror.StatTx.SUP_STAT_0_Register.Data.Word = 0x00u; CddTle94x1_DataMirror.StatTx.WK_STAT_0_Register.Data.Word = 0x00u; CddTle94x1_DataMirror.StatTx.DEV_STAT_Register.Data.Word = 0x00u; CddTle94x1_DataMirror.CtrlTx.BUS_CTRL_0_Register.Data.Bit.CAN = 0x03u; CddTle94x1_DataMirror.CtrlTx.HW_CTRL_0_Register.Data.Bit.CP_EN = 1u; CddTle94x1_DataMirror.CtrlTx.HW_CTRL_2_Register.Data.Bit.SS_MOD_FR = 3u; CddTle94x1_DataMirror.CtrlTx.HW_CTRL_3_Register.Data.Bit.TSD_THR = 1u; CddTle94x1_DataMirror.CtrlTx.HW_CTRL_1_Register.Data.Bit.RSTN_DEL = 1u; CddTle94x1_DataMirror.CtrlTx.M_S_CTRL_Register.Data.Bit.VCC1_OV_RST = 1u; CddTle94x1_DataMirror.CtrlTx.M_S_CTRL_Register.Data.Bit.VCC2_ON = 1u; CddTle94x1_DataMirror.CtrlTx.M_S_CTRL_Register.Data.Bit.MODE = 0u; if (CddTle94x1_WriteClearReg(0x41U, CddTle94x1_DataMirror.StatTx.SUP_STAT_0_Register.Data.Word) != 0U) { CddTle94x1_DataMirror.StatRx.SUP_STAT_0_Register.Data.Word = CddTle94x1_DataMirror.StatTx.SUP_STAT_0_Register.Data.Word; } else { CddTle94x1_ErrorType.boInitCtrlWrite = 1u; } if (CddTle94x1_WriteClearReg(0x46U, CddTle94x1_DataMirror.StatTx.WK_STAT_0_Register.Data.Word) != 0U) { CddTle94x1_DataMirror.StatRx.WK_STAT_0_Register.Data.Word = CddTle94x1_DataMirror.StatTx.WK_STAT_0_Register.Data.Word; } else { CddTle94x1_ErrorType.boInitCtrlWrite = 1u; } if (CddTle94x1_WriteClearReg(0x43U, CddTle94x1_DataMirror.StatTx.DEV_STAT_Register.Data.Word) != 0U) { CddTle94x1_DataMirror.StatRx.DEV_STAT_Register.Data.Word = CddTle94x1_DataMirror.StatTx.DEV_STAT_Register.Data.Word; } else { CddTle94x1_ErrorType.boInitCtrlWrite = 1u; } if (CddTle94x1_WriteClearReg(0x04U, CddTle94x1_DataMirror.CtrlTx.BUS_CTRL_0_Register.Data.Word) != 0U) { CddTle94x1_DataMirror.CtrlRx.BUS_CTRL_0_Register.Data.Word = CddTle94x1_DataMirror.CtrlTx.BUS_CTRL_0_Register.Data.Word; } else { CddTle94x1_ErrorType.boInitCtrlWrite = 1u; } if (CddTle94x1_WriteClearReg(0x02U, CddTle94x1_DataMirror.CtrlTx.HW_CTRL_0_Register.Data.Word) != 0U) { CddTle94x1_DataMirror.CtrlRx.HW_CTRL_0_Register.Data.Word = CddTle94x1_DataMirror.CtrlTx.HW_CTRL_0_Register.Data.Word; } else { CddTle94x1_ErrorType.boInitCtrlWrite = 1u; } if (CddTle94x1_WriteClearReg(0x0FU, CddTle94x1_DataMirror.CtrlTx.HW_CTRL_2_Register.Data.Word) != 0U) { CddTle94x1_DataMirror.CtrlRx.HW_CTRL_2_Register.Data.Word = CddTle94x1_DataMirror.CtrlTx.HW_CTRL_2_Register.Data.Word; } else { CddTle94x1_ErrorType.boInitCtrlWrite = 1u; } if (CddTle94x1_WriteClearReg(0x1DU, CddTle94x1_DataMirror.CtrlTx.HW_CTRL_3_Register.Data.Word) != 0U) { CddTle94x1_DataMirror.CtrlRx.HW_CTRL_3_Register.Data.Word = CddTle94x1_DataMirror.CtrlTx.HW_CTRL_3_Register.Data.Word; } else { CddTle94x1_ErrorType.boInitCtrlWrite = 1u; } if (CddTle94x1_WriteClearReg(0x0EU, CddTle94x1_DataMirror.CtrlTx.HW_CTRL_1_Register.Data.Word) != 0U) { CddTle94x1_DataMirror.CtrlRx.HW_CTRL_1_Register.Data.Word = CddTle94x1_DataMirror.CtrlTx.HW_CTRL_1_Register.Data.Word; } else { CddTle94x1_ErrorType.boInitCtrlWrite = 1u; } if (CddTle94x1_WriteClearReg(0x01U, CddTle94x1_DataMirror.CtrlTx.M_S_CTRL_Register.Data.Word) != 0U) { CddTle94x1_DataMirror.CtrlRx.M_S_CTRL_Register.Data.Word = CddTle94x1_DataMirror.CtrlTx.M_S_CTRL_Register.Data.Word; } else { CddTle94x1_ErrorType.boInitCtrlWrite = 1u; } CddSbc_InsertDefaultMessage(); } # 580 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static void CddTle94x1_StoreSBCResetReason(void) { if (CddTle94x1_ucSUP_STAT_0_POR == 1u) { CddTle94x1_eSBCResetReason = (uint8)ePowerOnResetSBC; } else if (CddTle94x1_boIsWdgReset != 0U) { CddTle94x1_eSBCResetReason = (uint8)eWatchdogReset; } else if (CddTle94x1_ucWK_STAT_0_CANWU == 1u) { CddTle94x1_eSBCResetReason = (uint8)eCANWakeUpReset; } else if (CddTle94x1_ucWK_STAT_0_WK_WU == 1u) { CddTle94x1_eSBCResetReason = (uint8)eInputWakeUpReset; } else { CddTle94x1_eSBCResetReason = (uint8)eNoResetSBC; } } # 616 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" uint8 CddTle94x1_GetSBCResetReason(void) { return (uint8)CddTle94x1_eSBCResetReason; } # 644 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" void CddTle94x1_SetSleepMode(void) { volatile uint16 unIndex; CddTle94x1_DataMirror.StatTx.WK_STAT_0_Register.Data.Word = 0x00u; CddTle94x1_DataMirror.StatTx.SUP_STAT_0_Register.Data.Word = 0x00u; CddTle94x1_DataMirror.CtrlTx.HW_CTRL_0_Register.Data.Bit.CP_EN = 0u; CddTle94x1_DataMirror.CtrlTx.BUS_CTRL_0_Register.Data.Bit.CAN = 0x01u; CddTle94x1_DataMirror.CtrlTx.WK_CTRL_1_Register.Data.Bit.WK_EN = 1u; CddTle94x1_DataMirror.CtrlTx.M_S_CTRL_Register.Data.Bit.VCC2_ON = 0u; CddTle94x1_DataMirror.CtrlTx.M_S_CTRL_Register.Data.Bit.MODE = 1u; if (CddTle94x1_WriteClearReg(0x46U, CddTle94x1_DataMirror.StatTx.WK_STAT_0_Register.Data.Word) == 0U) { CddTle94x1_ErrorType.boGotoSleep_SpiFailure = 1u; } if (CddTle94x1_WriteClearReg(0x41U, CddTle94x1_DataMirror.StatTx.SUP_STAT_0_Register.Data.Word) == 0U) { CddTle94x1_ErrorType.boGotoSleep_SpiFailure = 1u; } if (CddTle94x1_WriteClearReg(0x02U, CddTle94x1_DataMirror.CtrlTx.HW_CTRL_0_Register.Data.Word) == 0U) { CddTle94x1_ErrorType.boGotoSleep_SpiFailure = 1u; } if (CddTle94x1_WriteClearReg(0x04U, CddTle94x1_DataMirror.CtrlTx.BUS_CTRL_0_Register.Data.Word) == 0U) { CddTle94x1_ErrorType.boGotoSleep_SpiFailure = 1u; } if (CddTle94x1_WriteClearReg(0x07U, CddTle94x1_DataMirror.CtrlTx.WK_CTRL_1_Register.Data.Word) == 0U) { CddTle94x1_ErrorType.boGotoSleep_SpiFailure = 1u; } if (CddTle94x1_WriteClearReg(0x01U, CddTle94x1_DataMirror.CtrlTx.M_S_CTRL_Register.Data.Word) != 0U) { for (unIndex = 0u; unIndex < 9000u; unIndex++) { } CddTle94x1_ErrorType.boGoToSleep_Failure = 1u; } else { CddTle94x1_ErrorType.boGotoSleep_SpiFailure = 1u; } } # 736 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" void CddTle94x1_SetCanMode(uint8 ucCanChannel, uint8 ucCanMode) { if (ucCanChannel == 0u) { if (CddTle94x1_ValidateCanMode(ucCanMode) == 1U) { CddTle94x1_DataMirror.CtrlTx.BUS_CTRL_0_Register.Data.Bit.CAN = ucCanMode; if (Spi_Stat_Get() == 0x01U) { if (CddTle94x1_WriteClearReg(0x04U, CddTle94x1_DataMirror.CtrlTx.BUS_CTRL_0_Register.Data.Word) != 0U) { CddTle94x1_DataMirror.CtrlRx.BUS_CTRL_0_Register.Data.Word = CddTle94x1_DataMirror.CtrlTx.BUS_CTRL_0_Register.Data.Word; } } else if (Spi_Stat_Get() == 0x02U) { (void)CddSbc_InsertNewSchedEntry(0x04U, CddTle94x1_DataMirror.CtrlTx.BUS_CTRL_0_Register.Data.Word, 0x80u, ((void *)0)); (void)CddSbc_InsertNewSchedEntry(0x04U, 0x00u, 0x00u, CddTle94x1_CbkSetCanMode); } else { } } else { } CddTle94x1_ErrorType.boCanChannelError = 0u; } else { CddTle94x1_ErrorType.boCanChannelError = 1u; } } # 786 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" uint8 CddTle94x1_GetCanMode(uint8 ucCanChannel) { uint8 ucReturn = 0; uint16 unReadReg = 0; if (ucCanChannel == 0u) { if (Spi_Stat_Get() == 0x01U) { unReadReg = CddTle94x1_ReadReg(0x04U); if (unReadReg != 0xFFFFu) { CddTle94x1_DataMirror.CtrlRx.BUS_CTRL_0_Register.Data.Word = (uint8)unReadReg; } } ucReturn = CddTle94x1_DataMirror.CtrlRx.BUS_CTRL_0_Register.Data.Bit.CAN; } else { } return ucReturn; } # 824 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" uint8 CddTle94x1_GetCanUV(void) { uint8 ucReturn = 0; uint16 unReadReg = 0; if (Spi_Stat_Get() == 0x01U) { unReadReg = CddTle94x1_ReadReg(0x44U); if (unReadReg != 0xFFFFu) { CddTle94x1_DataMirror.StatRx.BUS_STAT_Register.Data.Word = (uint8)unReadReg; } } ucReturn = CddTle94x1_DataMirror.StatRx.BUS_STAT_Register.Data.Bit.VCAN_UV; return ucReturn; } # 858 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static void CddTle94x1_CbkGetCanMode(uint32 ulData, uint16 unSentVal) { uint8 ucRxData = (uint8)(ulData >> 8u); uint8 ucAddresse = (uint8)(unSentVal & 0x7Fu); if (ucAddresse == 0x04U) { CddTle94x1_DataMirror.CtrlRx.BUS_CTRL_0_Register.Data.Word = ucRxData; } else { } } # 888 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static void CddTle94x1_CbkGetBusState(uint32 ulData, uint16 unSentVal) { uint8 ucRxData = (uint8)(ulData >> 8u); uint8 ucAddresse = (uint8)(unSentVal & 0x7Fu); if (ucAddresse == 0x44U) { CddTle94x1_DataMirror.StatRx.BUS_STAT_Register.Data.Word = ucRxData; } else { } } # 918 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static void CddTle94x1_CbkSetCanMode(uint32 ulData, uint16 unSentVal) { uint8 ucRxData = (uint8)(ulData >> 8u); (void)unSentVal; if (ucRxData != CddTle94x1_DataMirror.CtrlTx.BUS_CTRL_0_Register.Data.Word) { CddTle94x1_ErrorType.boCyclic_CanMode = 1u; CddTle94x1_ErrorSequenceCounterInc(); } else { CddTle94x1_ErrorSequenceCounterClear(); CddTle94x1_ErrorType.boCyclic_CanMode = 0u; CddTle94x1_DataMirror.CtrlRx.BUS_CTRL_0_Register.Data.Word = ucRxData; } } # 956 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static boolean CddTle94x1_ValidateCanMode(uint8 ucCanMode) { boolean boReturn; switch (ucCanMode) { case 0x00u: case 0x01u: case 0x02u: case 0x03u: { CddTle94x1_ErrorType.boCanModeError = 0u; boReturn = 1U; } break; default: { CddTle94x1_ErrorType.boCanModeError = 1u; boReturn = 0U; } break; } return boReturn; } # 997 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static void CddTle94x1_CbkSetWDCtrl(uint32 ulData, uint16 unSentVal) { uint8 ucRxData = (uint8)(ulData >> 8u); (void)unSentVal; if (ucRxData != CddTle94x1_DataMirror.CtrlTx.WD_CTRL_Register.Data.Word) { CddTle94x1_ErrorType.boSpiWdgFailure = 1u; CddTle94x1_ErrorSequenceCounterInc(); } else { CddTle94x1_ErrorSequenceCounterClear(); CddTle94x1_ErrorType.boSpiWdgFailure = 0u; CddTle94x1_DataMirror.CtrlRx.WD_CTRL_Register.Data.Word = ucRxData; } } # 1031 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" boolean CddTle94x1_GetWakeUpStatus(void) { boolean boReturn = 0U; boReturn = (boolean)CddTle94x1_DataMirror.StatRx.WK_LVL_STAT_Register.Data.Bit.WK_LVL; return boReturn; } # 1051 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static void CddTle94x1_CbkGetWakeUpStatus(uint32 ulData, uint16 unSentVal) { uint8 ucRxData = (uint8)(ulData >> 8u); uint8 ucAddresse = (uint8)(unSentVal & 0x7Fu); if (ucAddresse == 0x48U) { CddTle94x1_DataMirror.StatRx.WK_LVL_STAT_Register.Data.Word = ucRxData; } else { } } # 1083 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static boolean CddTle94x1_WriteClearReg(uint8 ucAddress, uint16 unDataField) { uint8 ucAddressField, ucIterationIndex = 0u; uint16 unTxData, unRxData; boolean boReturn = 0U; ucAddressField = ucAddress | 0x80u; unTxData = unDataField; unTxData = unTxData << 8u; unTxData = unTxData | ucAddressField; while ((CddSpi_TransferMsg(&unTxData, &unRxData, 2u, (uint8)((Spi_SequenceType)1U)) != 1U) && (ucIterationIndex < 10u)) { ucIterationIndex++; } if (ucIterationIndex < 10u) { unRxData = CddTle94x1_ReadReg(ucAddress); if (unRxData == unDataField) { boReturn = 1U; } else { } } else { } return boReturn; } # 1139 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static uint16 CddTle94x1_ReadReg(uint8 ucAddress) { uint8 ucIterationCounter = 0u; uint16 unSpiTxMsg = (uint16)ucAddress; uint16 unReturnValue = (uint16)0xFFFFu; while ((CddSpi_TransferMsg(&unSpiTxMsg, &unSpiTxMsg, 2u, (uint8)((Spi_SequenceType)1U)) != 1U) && (ucIterationCounter < 10u)) { ucIterationCounter++; } if (ucIterationCounter < 10u) { const uint16 unSpiRxMsg = (uint8)(unSpiTxMsg >> 8u); unReturnValue = unSpiRxMsg; } else { } return unReturnValue; } # 1184 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" void CddSbc_InsertDefaultMessage(void) { switch (CddSbc_eDefaultMsg) { case eBUS_CTRL_0: (void)CddSbc_InsertNewSchedEntry(0x04U, 0x00u, 0x00u, ((void *)0)); (void)CddSbc_InsertNewSchedEntry(0x04U, 0x00u, 0x00u, CddTle94x1_CbkGetCanMode); CddSbc_eDefaultMsg = eBUS_STAT; break; case eBUS_STAT: (void)CddSbc_InsertNewSchedEntry(0x44U, 0x00u, 0x00u, ((void *)0)); (void)CddSbc_InsertNewSchedEntry(0x44U, 0x00u, 0x00u, CddTle94x1_CbkGetBusState); CddSbc_eDefaultMsg = eWK_LVL_STAT; break; case eWK_LVL_STAT: (void)CddSbc_InsertNewSchedEntry(0x48U, 0x00u, 0x00u, ((void *)0)); (void)CddSbc_InsertNewSchedEntry(0x48U, 0x00u, 0x00u, CddTle94x1_CbkGetWakeUpStatus); CddSbc_eDefaultMsg = eSUP_STAT_0; break; case eSUP_STAT_0: (void)CddSbc_InsertNewSchedEntry(0x41U, 0x00u, 0x00u, ((void *)0)); (void)CddSbc_InsertNewSchedEntry(0x41U, 0x00u, 0x00u, CddTle94x1_CbkGetSupState0); CddSbc_eDefaultMsg = eBUS_CTRL_0; break; # 1240 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" default: CddSbc_eDefaultMsg = eBUS_STAT; break; } } # 1257 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" void CddSbc_ScheduleTableFull(boolean boStatus) { CddTle94x1_ErrorType.boScheduleTableFull = boStatus; } # 1276 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static void CddTle94x1_CbkGetSupState0(uint32 ulData, uint16 unSentVal) { uint8 ucRxData = (uint8)(ulData >> 8u); uint8 ucAddresse = (uint8)(unSentVal & 0x7Fu); if (ucAddresse == 0x41U) { CddTle94x1_DataMirror.StatRx.SUP_STAT_0_Register.Data.Word = ucRxData; } else { } } # 1337 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static void CddTle94x1_ErrorSequenceCounterInc(void) { if (CddTle94x1_unErrorSequenceCounter < 500u) { CddTle94x1_unErrorSequenceCounter++; } else { CddTle94x1_ErrorType.boCyclic_SPI_Communication = 1u; } } # 1364 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static void CddTle94x1_ErrorSequenceCounterClear(void) { CddTle94x1_unErrorSequenceCounter = 0; CddTle94x1_ErrorType.boCyclic_SPI_Communication = 0u; } # 1384 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" void CddTle94x1_DeInit(void) { (void)CddTle94x1_ucSUP_STAT_0_POR; (void)CddTle94x1_ucWK_STAT_0_CANWU; (void)CddTle94x1_ErrorType; } # 1409 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" static void CddTle94x1_SetWdgWithSingleOperation(void) { if (CddTle94x1_WriteClearReg(0x03U, CddTle94x1_DataMirror.CtrlTx.WD_CTRL_Register.Data.Word) != 0U) { CddTle94x1_DataMirror.CtrlRx.WD_CTRL_Register.Data.Word = CddTle94x1_DataMirror.CtrlTx.WD_CTRL_Register.Data.Word; CddTle94x1_ErrorType.boSpiWdgFailure = 0u; } else { CddTle94x1_ErrorType.boSpiWdgFailure = 1u; } } # 1435 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" void CddTle94x1_SetWdgWindowModeAnd10ms(void) { CddTle94x1_DataMirror.CtrlTx.WD_CTRL_Register.Data.Bit.WD_TIMER = 0u; CddTle94x1_DataMirror.CtrlTx.WD_CTRL_Register.Data.Bit.WD_WIN = 1u; CddTle94x1_DataMirror.CtrlTx.WD_CTRL_Register.Data.Bit.CHECKSUM = 1u; if (Spi_Stat_Get() == 0x01U) { CddTle94x1_SetWdgWithSingleOperation(); } else if (Spi_Stat_Get() == 0x02U) { (void)CddSbc_InsertNewSchedEntry(0x03U, CddTle94x1_DataMirror.CtrlTx.WD_CTRL_Register.Data.Word, 0x80u, ((void *)0)); } else { } } # 1474 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" void CddTle94x1_SetWdgTimeoutModeAnd200ms(void) { CddTle94x1_DataMirror.CtrlTx.WD_CTRL_Register.Data.Bit.WD_TIMER = 4u; CddTle94x1_DataMirror.CtrlTx.WD_CTRL_Register.Data.Bit.WD_WIN = 0u; CddTle94x1_DataMirror.CtrlTx.WD_CTRL_Register.Data.Bit.CHECKSUM = 1u; if (Spi_Stat_Get() == 0x01U) { CddTle94x1_SetWdgWithSingleOperation(); } else if (Spi_Stat_Get() == 0x02U) { (void)CddSbc_InsertNewSchedEntry(0x03U, CddTle94x1_DataMirror.CtrlTx.WD_CTRL_Register.Data.Word, 0x80u, ((void *)0)); } else { } } # 1513 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" void CddTle94x1_SetWdgWindowModeAnd200ms(void) { CddTle94x1_DataMirror.CtrlTx.WD_CTRL_Register.Data.Bit.WD_TIMER = 4u; CddTle94x1_DataMirror.CtrlTx.WD_CTRL_Register.Data.Bit.WD_WIN = 1u; CddTle94x1_DataMirror.CtrlTx.WD_CTRL_Register.Data.Bit.CHECKSUM = 0u; if (Spi_Stat_Get() == 0x01U) { CddTle94x1_DataMirror.CtrlTx.WD_CTRL_Register.Data.Bit.WD_TIMER = 4u; CddTle94x1_DataMirror.CtrlTx.WD_CTRL_Register.Data.Bit.WD_WIN = 0u; CddTle94x1_DataMirror.CtrlTx.WD_CTRL_Register.Data.Bit.CHECKSUM = 1u; CddTle94x1_SetWdgWithSingleOperation(); } else if (Spi_Stat_Get() == 0x02U) { (void)CddSbc_InsertNewSchedEntry(0x03U, CddTle94x1_DataMirror.CtrlTx.WD_CTRL_Register.Data.Word, 0x80u, ((void *)0)); (void)CddSbc_InsertNewSchedEntry(0x03U, 0x00u, 0x00u, CddTle94x1_CbkSetWDCtrl); } else { } } boolean CddSpi_TransferMsg(uint16 *Data, uint16 *RcData, uint8 len, uint8 Cs) { uint8 tepm_data[2]; uint8 tepm_rxdata[2]; uint8 data_0; data_0 = *Data >> 8; tepm_data[0] = data_0<<7 | (data_0<<5 & 0x40) | (data_0<<3 & 0x20) | (data_0<<1 & 0x10) | (data_0>>7 & 0x01) | (data_0>>5 & 0x02) | (data_0>>3 & 0x04) | (data_0 & 0x08); data_0 = *Data; tepm_data[1] = data_0<<7 | (data_0<<5 & 0x40) | (data_0<<3 & 0x20) | (data_0<<1 & 0x10) | (data_0>>7 & 0x01) | (data_0>>5 & 0x02) | (data_0>>3 & 0x04) | (data_0 & 0x08); Spi_SetupEB(Cs, tepm_data, tepm_rxdata, len); Spi_SyncTransmit(Cs); *RcData = tepm_rxdata[0] | (tepm_rxdata[1]<<8); return 1U; } # 1 "../../../Package/Cdd/CddTle94x1/Cfg\\../Cfg/CddTle94x1_MemMap.h" 1 # 1577 "../../../Package/Cdd/CddTle94x1/Gen/CddTle94x1.c" 2