# 1 "../../../Package/Cdd/CddSbc/Gen/CddSbc_Router.c"
# 1 "<built-in>" 1
# 1 "<built-in>" 3
# 387 "<built-in>" 3
# 1 "<command line>" 1
# 1 "<built-in>" 2
# 1 "../../../Package/Cdd/CddSbc/Gen/CddSbc_Router.c" 2
# 21 "../../../Package/Cdd/CddSbc/Gen/CddSbc_Router.c"
# 1 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 1
# 30 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h"
# 1 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h" 1
# 86 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h"
typedef unsigned char boolean;




typedef unsigned char uint8;




typedef unsigned short uint16;




typedef unsigned int uint32;





typedef unsigned long long uint64;




typedef signed char sint8;




typedef signed short sint16;




typedef signed int sint32;





typedef signed long long sint64;




typedef unsigned long uint8_least;




typedef unsigned long uint16_least;





typedef unsigned long uint32_least;




typedef signed long sint8_least;




typedef signed long sint16_least;




typedef signed long sint32_least;




typedef float float32;





typedef double float64;




typedef void *VoidPtr;




typedef const void *ConstVoidPtr;
# 31 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2
# 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 1
# 31 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h"
# 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler_Cfg.h" 1
# 32 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 2
# 32 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2
# 63 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h"
typedef unsigned char StatusType;
# 104 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h"
typedef uint8 Std_ReturnType;




typedef uint8 Std_TransformerClass;




typedef uint8 Std_TransformerForwardCode;





typedef uint8 Std_MessageTypeType;





typedef uint8 Std_MessageResultType;





typedef struct
{
    uint16 vendorID;
    uint16 moduleID;
    uint8 sw_major_version;
    uint8 sw_minor_version;
    uint8 sw_patch_version;
} Std_VersionInfoType;




typedef struct
{
    uint8 errorCode;
    Std_TransformerClass transformerClass;
} Std_TransformerError;





typedef struct
{
    Std_TransformerForwardCode errorCode;
    Std_TransformerClass transformerClass;
} Std_TransformerForward;







typedef Std_ReturnType (*Std_ExtractProtocolHeaderFieldsType)(const uint8 *buffer,
                                                              uint32 bufferLength,
                                                              Std_MessageTypeType *messageType,
                                                              Std_MessageResultType *messageResult);
# 22 "../../../Package/Cdd/CddSbc/Gen/CddSbc_Router.c" 2

# 1 "../../../Package/Cdd/CddSbc/Api\\CddSbc.h" 1
# 22 "../../../Package/Cdd/CddSbc/Api\\CddSbc.h"
# 1 "../../../Package/Cdd/CddSbc/Api\\CddSbc_Type.h" 1
# 293 "../../../Package/Cdd/CddSbc/Api\\CddSbc_Type.h"
typedef unsigned char tieResetReason;

typedef struct
{


tieResetReason eResetReason;


}tisCddSbcStatus;
# 23 "../../../Package/Cdd/CddSbc/Api\\CddSbc.h" 2
# 1 "../../../Package/Cdd/CddSbc/Cfg\\CddSbc_Cfg.h" 1



# 1 "../../../Package/Cdd\\AL_Helper.h" 1
# 20 "../../../Package/Cdd\\AL_Helper.h"
  void AL_Helper_Dummy(const uint32 ulDummyParam);
# 5 "../../../Package/Cdd/CddSbc/Cfg\\CddSbc_Cfg.h" 2
# 1 "../../../Package/Cdd\\CddTle94x1\\Gen\\CddTle94x1_Types.h" 1
# 43 "../../../Package/Cdd\\CddTle94x1\\Gen\\CddTle94x1_Types.h"
typedef struct
{
  boolean boInitStatRead;
  boolean boInitCtrlWrite;
  boolean boGoToStop_Failure;
  boolean boGotoStop_SpiFailure;
  boolean boGoToSleep_Failure;
  boolean boGotoSleep_SpiFailure;
  boolean boCyclic_SPI_Communication;
  boolean boCyclic_CanMode;
  boolean boReadWKStat_Failure;
  boolean boReadSUPStat_Failure;
  boolean boScheduleTableFull;
  boolean boCanModeError;
  boolean boCanChannelError;
  boolean boSpiWdgFailure;
  boolean boReadWdgStat_Failure;
  boolean boErrorReset;
}tisSbcErrorState;





typedef enum teDefaultMsgType
{
  eNoMsg = 0,
  eBUS_CTRL_0,
  eBUS_STAT,
  eWK_LVL_STAT,
  eSUP_STAT_0,
  eTHERM_STAT
}teDefaultMsgType;
# 6 "../../../Package/Cdd/CddSbc/Cfg\\CddSbc_Cfg.h" 2

# 1 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 1
# 30 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
# 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h" 1
# 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h"
# 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 1
# 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h"
# 1 "../Generated/inc\\Mcu_Drvw_Cfg.h" 1
# 30 "../Generated/inc\\Mcu_Drvw_Cfg.h"
# 1 "../Generated/inc/Mcu_Drvw_PBcfg.h" 1
# 31 "../Generated/inc\\Mcu_Drvw_Cfg.h" 2
# 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2
# 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Scc_Drv_Types.h" 1
# 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Scc_Drv_Types.h"
# 1 "../Generated/inc\\Scc_Drv_Cfg.h" 1
# 30 "../Generated/inc\\Scc_Drv_Cfg.h"
# 1 "../Generated/inc/Scc_Drv_PBcfg.h" 1
# 65 "../Generated/inc/Scc_Drv_PBcfg.h"
extern void FOSCClkLossCallbackFunc(void);
# 31 "../Generated/inc\\Scc_Drv_Cfg.h" 2
# 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Scc_Drv_Types.h" 2

# 1 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 1
# 29 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
# 1 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 1
# 30 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h"
# 1 "../Generated/inc\\McalLib_Cfg.h" 1
# 31 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 2
# 273 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h"
static inline uint32 McalLib_ReadControlReg(void)
{
    uint32 res;

    __asm("MRS %0,CONTROL" : "=r" (res));

    return res;
}
# 290 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h"
static inline uint32 McalLib_ReadIpsrReg(void)
{
    uint32 res;
    __asm("MRS %0,IPSR" : "=r" (res));
    return res;
}
# 305 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h"
static inline uint32 McalLib_ReadPriMaskReg(void)
{
    uint32 res;
    __asm("MRS %0,PRIMASK" : "=r" (res));
    return res;
}
# 30 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2
# 184 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
typedef enum
{
    MCALLIB_COUNTER_SOFTWARE,

    MCALLIB_COUNTER_OS,




} McalLib_CounterType;




typedef struct
{
    uint32 CounterId;
    uint32 CounterFreq;
} McalLib_ConfigType;







# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1
# 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h"
#pragma clang section rodata = ".mcal_config_data"
# 211 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2

extern const McalLib_ConfigType *const McalLib_PreDefinedConfigPtr[(1U)];


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1
# 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h"
#pragma clang section rodata = ""
# 216 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2
# 230 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
extern void Sys_SystemReset(void);


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1
# 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h"
#pragma clang section text = ".mcal_code"
# 234 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2







void McalLib_Init(void);
# 254 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
Std_ReturnType McalLib_GetCounterValue(McalLib_CounterType Counter, uint32 *Value);
# 270 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
Std_ReturnType McalLib_GetElapsedValue(McalLib_CounterType Counter, uint32 *const CounterValue,
                                       uint32 *ElapsedValue);
# 282 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
uint32 McalLib_MicroSecToTicks(McalLib_CounterType Counter, uint32 MicroSecond);
# 296 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
void McalLib_SetCounterFreq(McalLib_CounterType Counter, uint32 Freq);
# 309 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
static inline void McalLib_Assert(const uint8 *File, uint32 Line)
{
    (void)File;
    (void)Line;

    for (;;)
    {
    }
}
# 327 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
void McalLib_SuspendAllInterrupts(void);







void McalLib_ResumeAllInterrupts(void);


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1
# 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h"
#pragma clang section text = ""
# 339 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2
# 33 "../../../mcal/Mcu_ZX_K14xM/Inc/Scc_Drv_Types.h" 2
# 90 "../../../mcal/Mcu_ZX_K14xM/Inc/Scc_Drv_Types.h"
typedef enum
{
    SCC_DRV_CLOCK_SRC_NO = 0U,
    SCC_DRV_CLOCK_SRC_LPO32K,
    SCC_DRV_CLOCK_SRC_SOSC,
    SCC_DRV_CLOCK_SRC_FIRC64M,
    SCC_DRV_CLOCK_SRC_FOSC,
    SCC_DRV_CLOCK_SRC_PLL
} Scc_Drv_ClockSrcType;





typedef enum
{
    SCC_DRV_SYS_CLOCK_FIRC64M = 1U,
    SCC_DRV_SYS_CLOCK_FOSC = 2U,
    SCC_DRV_SYS_CLOCK_PLL = 3U
} Scc_Drv_SystemClockType;





typedef enum
{
    SCC_DRV_OSC_XTAL = 0U,
    SCC_DRV_OSC_EXT_SRC
} Scc_Drv_OscModeType;





typedef enum
{
    SCC_DRV_FOSC_FREQ_MODE_LOW = 0U,
    SCC_DRV_FOSC_FREQ_MODE_HIGH
} Scc_Drv_FOscFreqModeType;





typedef enum
{
    SCC_DRV_OSC_CLOCK_LOSS_INT = 0U,
    SCC_DRV_OSC_CLOCK_LOSS_RST
} Scc_Drv_OscClockLossActType;





typedef enum
{
    SCC_DRV_FIRC64M_CLOCK_LOSS_INT = 0U,
    SCC_DRV_FIRC64M_CLOCK_LOSS_RST
} Scc_Drv_Firc64MClockLossActType;
# 167 "../../../mcal/Mcu_ZX_K14xM/Inc/Scc_Drv_Types.h"
typedef enum
{
    SCC_DRV_PLL_REF_FIRC64M = 0U,
    SCC_DRV_PLL_REF_FOSC
} Scc_Drv_PllRefClockType;





typedef enum
{
    SCC_DRV_PLL_PRE_DIV_1 = 0U,
    SCC_DRV_PLL_PRE_DIV_2 = 1U,
    SCC_DRV_PLL_PRE_DIV_4 = 2U
} Scc_Drv_PllPreDivType;





typedef enum
{
    SCC_DRV_PLL_POST_DIV_6 = 3U,
    SCC_DRV_PLL_POST_DIV_8 = 4U,
    SCC_DRV_PLL_POST_DIV_10 = 5U,
    SCC_DRV_PLL_POST_DIV_12 = 6U,
    SCC_DRV_PLL_POST_DIV_14 = 7U
} Scc_Drv_PllPostDivType;





typedef enum
{
    SCC_DRV_PLL_SCALER_1 = 0U,
    SCC_DRV_PLL_SCALER_2 = 1U
} Scc_Drv_PllPreScalerType;





typedef enum
{
    SCC_DRV_SYS_CLOCK_CORE = 0x85U,
    SCC_DRV_SYS_CLOCK_BUS = 0x86U,
    SCC_DRV_SYS_CLOCK_SLOW = 0x87U
} Scc_Drv_SysClockType;





typedef enum
{
    SCC_DRV_SYS_CLOCK_DIV_1 = 0U,
    SCC_DRV_SYS_CLOCK_DIV_2,
    SCC_DRV_SYS_CLOCK_DIV_3,
    SCC_DRV_SYS_CLOCK_DIV_4,
    SCC_DRV_SYS_CLOCK_DIV_5,
    SCC_DRV_SYS_CLOCK_DIV_6,
    SCC_DRV_SYS_CLOCK_DIV_7,
    SCC_DRV_SYS_CLOCK_DIV_8,
    SCC_DRV_SYS_CLOCK_DIV_9,
    SCC_DRV_SYS_CLOCK_DIV_10,
    SCC_DRV_SYS_CLOCK_DIV_11,
    SCC_DRV_SYS_CLOCK_DIV_12,
    SCC_DRV_SYS_CLOCK_DIV_13,
    SCC_DRV_SYS_CLOCK_DIV_14,
    SCC_DRV_SYS_CLOCK_DIV_15,
    SCC_DRV_SYS_CLOCK_DIV_16
} Scc_Drv_SysClockDividerType;





typedef struct
{
    Scc_Drv_PllPreDivType PllPreDivider;
    Scc_Drv_PllPostDivType PllPostDivider;
    uint32 PllMultiplier;
    Scc_Drv_PllRefClockType PllRefClock;
    Scc_Drv_PllPreScalerType PllPreScaler;
    uint32 PllFreq;
} Scc_Drv_PllParamConfigType;





typedef struct
{
    Scc_Drv_PllParamConfigType SccPllClockParamConfig;
    boolean SccPllEnableUnderStop;
    boolean Enable;
} Scc_Drv_PllClockConfigType;





typedef void (*Scc_Drv_LocCallbackFunc)(void);





typedef struct
{

    boolean Firc64MStopEn;

    boolean Enable;

    Scc_Drv_LocCallbackFunc Firc64MLocCallbackFunc;
} Scc_Drv_Firc64MClockConfigType;





typedef struct
{

    Scc_Drv_FOscFreqModeType SccOscHfreq;

    boolean SccOscEnableUnderStop;

    Scc_Drv_OscModeType Mode;

    boolean Enable;

    Scc_Drv_LocCallbackFunc LocCallbackFunc;
} Scc_Drv_FOscClockConfigType;





typedef struct
{
    Scc_Drv_OscModeType Mode;
    boolean Enable;
} Scc_Drv_SOscClockConfigType;




typedef struct
{
    uint32 Enable;
} Scc_Drv_LpoClockConfigType;





typedef struct
{
    Scc_Drv_SystemClockType SccSystemClockSource;
    uint32 SccSystemClockFreq;
    Scc_Drv_SysClockDividerType SccCoreClockDivider;
    Scc_Drv_SysClockDividerType SccBusClockDivider;
    Scc_Drv_SysClockDividerType SccSlowClockDivider;
} Scc_Drv_SystemClockConfigType;





typedef struct
{
    Scc_Drv_SystemClockConfigType SccSystemClockConfig;
    Scc_Drv_Firc64MClockConfigType SccFircClockConfig;
    Scc_Drv_FOscClockConfigType SccFOscClockConfig;
    Scc_Drv_PllClockConfigType SccPllClockConfig;
    Scc_Drv_SOscClockConfigType SccSOscClockConfig;
    Scc_Drv_LpoClockConfigType SccLpoClockConfig;
} Scc_Drv_ClockConfigType;
# 32 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2
# 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Parcc_Drv_Types.h" 1
# 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Parcc_Drv_Types.h"
# 1 "../Generated/inc\\Parcc_Drv_Cfg.h" 1
# 30 "../Generated/inc\\Parcc_Drv_Cfg.h"
# 1 "../Generated/inc/Parcc_Drv_PBcfg.h" 1
# 31 "../Generated/inc\\Parcc_Drv_Cfg.h" 2
# 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Parcc_Drv_Types.h" 2
# 91 "../../../mcal/Mcu_ZX_K14xM/Inc/Parcc_Drv_Types.h"
typedef enum
{
    PARCC_DRV_WDOG = 0x00U,
    PARCC_DRV_EWDT,
    PARCC_DRV_STIM,
    PARCC_DRV_TIM0,
    PARCC_DRV_TIM1,
    PARCC_DRV_TIM2,
    PARCC_DRV_TIM3,
    PARCC_DRV_MCPWM0,
    PARCC_DRV_MCPWM1,
    PARCC_DRV_TDG0,
    PARCC_DRV_TDG1,
    PARCC_DRV_CAN0,
    PARCC_DRV_CAN1,
    PARCC_DRV_CAN2,
    PARCC_DRV_CAN3,
    PARCC_DRV_CAN4,
    PARCC_DRV_CAN5,
    PARCC_DRV_CAN6,
    PARCC_DRV_CAN7,
    PARCC_DRV_UART0,
    PARCC_DRV_UART1,
    PARCC_DRV_UART2,
    PARCC_DRV_UART3,
    PARCC_DRV_UART4,
    PARCC_DRV_UART5,
    PARCC_DRV_SPI0,
    PARCC_DRV_SPI1,
    PARCC_DRV_SPI2,
    PARCC_DRV_SPI3,
    PARCC_DRV_I2C0,
    PARCC_DRV_I2C1,
    PARCC_DRV_I2S0,
    PARCC_DRV_I2S1,
    PARCC_DRV_RESERVED1,
    PARCC_DRV_ADC0,
    PARCC_DRV_ADC1,
    PARCC_DRV_CMP0,
    PARCC_DRV_CRC,
    PARCC_DRV_AES,
    PARCC_DRV_TRNG,
    PARCC_DRV_FLASH,
    PARCC_DRV_RESERVED2,
    PARCC_DRV_DMA,
    PARCC_DRV_DMAMUX,
    PARCC_DRV_PORTA,
    PARCC_DRV_PORTB,
    PARCC_DRV_PORTC,
    PARCC_DRV_PORTD,
    PARCC_DRV_PORTE,
    PARCC_DRV_TMU,
    PARCC_DRV_REGFILE,
    PARCC_DRV_SMPU,
    PARCC_DRV_GPIO
} Parcc_Drv_ModuleType;





typedef enum
{
    PARCC_DRV_CLOCK_SRC_NO = 0U,
    PARCC_DRV_CLOCK_SRC_LPO32K = 1U,
    PARCC_DRV_CLOCK_SRC_SOSC = 2U,
    PARCC_DRV_CLOCK_SRC_FIRC64M = 3U,
    PARCC_DRV_CLOCK_SRC_FOSC = 4U,
    PARCC_DRV_CLOCK_SRC_PLL = 5U,
    PARCC_DRV_CLOCK_SRC_SLOW = 6U,
    PARCC_DRV_CLOCK_SRC_BUS = 7U,
    PARCC_DRV_CLOCK_SRC_CORE = 8U
} Parcc_Drv_ClockSrcType;





typedef enum
{
    PARCC_DRV_CLOCK_DIV_1 = 0U,
    PARCC_DRV_CLOCK_DIV_2,
    PARCC_DRV_CLOCK_DIV_3,
    PARCC_DRV_CLOCK_DIV_4,
    PARCC_DRV_CLOCK_DIV_5,
    PARCC_DRV_CLOCK_DIV_6,
    PARCC_DRV_CLOCK_DIV_7,
    PARCC_DRV_CLOCK_DIV_8,
    PARCC_DRV_CLOCK_DIV_9,
    PARCC_DRV_CLOCK_DIV_10,
    PARCC_DRV_CLOCK_DIV_11,
    PARCC_DRV_CLOCK_DIV_12,
    PARCC_DRV_CLOCK_DIV_13,
    PARCC_DRV_CLOCK_DIV_14,
    PARCC_DRV_CLOCK_DIV_15,
    PARCC_DRV_CLOCK_DIV_16
} Parcc_Drv_ClockDividerType;





typedef enum
{
    PARCC_DRV_STATUS_OK = 0x00U,
    PARCC_DRV_STATUS_NOT_OK = 0x01U,
    PARCC_DRV_STATUS_UNDEFINED = 0x02U
} Parcc_Drv_StatusType;




typedef struct
{
    Parcc_Drv_ModuleType ParccModule;
    Parcc_Drv_ClockSrcType ParccModuleSrc;
    Parcc_Drv_ClockDividerType ParccModuleDivider;
    boolean Enable;
    boolean SupervisorAccessEnable;
    boolean WriteLockEnable;
} Parcc_Drv_ModuleConfigType;





typedef struct
{
    uint32 NumberOfModule;
    const Parcc_Drv_ModuleConfigType *SystemParccConfigPtr;
} Parcc_Drv_SystemParccConfigType;
# 33 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2
# 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Pmu_Drv_Types.h" 1
# 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Pmu_Drv_Types.h"
# 1 "../Generated/inc\\Pmu_Drv_Cfg.h" 1
# 30 "../Generated/inc\\Pmu_Drv_Cfg.h"
# 1 "../Generated/inc/Pmu_Drv_PBcfg.h" 1
# 31 "../Generated/inc\\Pmu_Drv_Cfg.h" 2
# 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Pmu_Drv_Types.h" 2
# 90 "../../../mcal/Mcu_ZX_K14xM/Inc/Pmu_Drv_Types.h"
typedef enum
{
    PMU_DRV_VDD_LVD_LP =
        0U,
    PMU_DRV_VDD_LVD_ACT =
        1U,
    PMU_DRV_VDD_LVD_RE = 3U,
    PMU_DRV_VDD_LVW = 4U,
    PMU_DRV_REF_BUF_1V = 8U
} Pmu_Drv_CtrlType;





typedef enum
{
    PMU_DRV_VDD_LVW_INT = 0U,
    PMU_DRV_VDD_LVD_INT
} Pmu_Drv_IntType;





typedef void (*Pmu_Drv_CallbackFunc)(void);





typedef struct
{
    boolean PmuCtrlLVDLowPowerEnable;
    boolean PmuCtrlLVDActiveEnable;
    boolean PmuCtrlLVDResetEnable;
    boolean PmuCtrlLVWEnable;
    boolean PmuCtrlRef1VEnable;
    boolean PmuLVDInterruptEnable;
    Pmu_Drv_CallbackFunc PmuLVDInterruptCallbackFunc;
    boolean PmuLVWInterruptEnable;
    Pmu_Drv_CallbackFunc PmuLVWInterruptCallbackFunc;
} Pmu_Drv_ConfigType;
# 34 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2
# 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Scm_Mcu_Drv_Types.h" 1
# 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Scm_Mcu_Drv_Types.h"
# 1 "../Generated/inc\\Scm_Mcu_Drv_Cfg.h" 1
# 30 "../Generated/inc\\Scm_Mcu_Drv_Cfg.h"
# 1 "../Generated/inc/Scm_Mcu_Drv_PBcfg.h" 1
# 31 "../Generated/inc\\Scm_Mcu_Drv_Cfg.h" 2
# 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Scm_Mcu_Drv_Types.h" 2
# 93 "../../../mcal/Mcu_ZX_K14xM/Inc/Scm_Mcu_Drv_Types.h"
typedef enum
{
    SCM_MCU_DRV_CLOCK_OUT_DIV_1 = 0U,
    SCM_MCU_DRV_CLOCK_OUT_DIV_2 = 1U,
    SCM_MCU_DRV_CLOCK_OUT_DIV_4 = 2U,
    SCM_MCU_DRV_CLOCK_OUT_DIV_8 = 3U
} Scm_Mcu_Drv_ClockOutDivType;





typedef enum
{
    SCM_MCU_DRV_CLOCK_OUT_DISABLED = 0U,
    SCM_MCU_DRV_CLOCK_OUT_FIRC64M = 1U,
    SCM_MCU_DRV_CLOCK_OUT_FOSC = 2U,
    SCM_MCU_DRV_CLOCK_OUT_PLL = 3U,
    SCM_MCU_DRV_CLOCK_OUT_SLOW = 8U,
    SCM_MCU_DRV_CLOCK_OUT_BUS = 9U,
    SCM_MCU_DRV_CLOCK_OUT_CORE = 10U,
    SCM_MCU_DRV_CLOCK_OUT_SOSC = 11U,
    SCM_MCU_DRV_CLOCK_OUT_LPO32K = 12U
} Scm_Mcu_Drv_ClockOutSrcType;





typedef enum
{
    SCM_MCU_DRV_SRAML = 0U,
    SCM_MCU_DRV_SRAMU = 1U
} Scm_Mcu_Drv_SramType;





typedef enum
{
    SCM_MCU_DRV_TIM0 = 3U,
    SCM_MCU_DRV_TIM1 = 4U,
    SCM_MCU_DRV_TIM2 = 5U,
    SCM_MCU_DRV_TIM3 = 6U,
    SCM_MCU_DRV_MCPWM0 = 7U,
    SCM_MCU_DRV_MCPWM1 = 8U
} Scm_Mcu_Drv_TimerType;





typedef enum
{
    SCM_MCU_DRV_TCLK0 = 0U,
    SCM_MCU_DRV_TCLK1 = 1U,
    SCM_MCU_DRV_TCLK2 = 2U
} Scm_Mcu_Drv_TimerExtClockInputType;





typedef enum
{
    SCM_MCU_DRV_ADC1CH15 = 0U,
    SCM_MCU_DRV_ADC1CH14 = 1U,
    SCM_MCU_DRV_ADC0CH9 = 2U,
    SCM_MCU_DRV_ADC0CH8 = 3U
} Scm_Mcu_Drv_AdcChannelSelectType;





typedef enum
{
    SCM_MCU_DRV_ADCMUX0 = 0U,
    SCM_MCU_DRV_ADCMUX1 = 1U
} Scm_Mcu_Drv_AdcMuxSelectType;





typedef enum
{
    SCM_MCU_DRV_CCACHE_BE_INT = 0U,
    SCM_MCU_DRV_FPU_INEXACT_INT = 1U,
    SCM_MCU_DRV_FPU_OVERFLOW_INT = 2U,
    SCM_MCU_DRV_FPU_UNDERFLOW_INT = 3U,
    SCM_MCU_DRV_FPU_INVALIDOP_INT = 4U,
    SCM_MCU_DRV_FPU_DIVZERO_INT = 5U,
    SCM_MCU_DRV_FPU_DENORMALIN_INT = 6U
} Scm_Mcu_Drv_IntType;





typedef struct
{
    Scm_Mcu_Drv_ClockOutSrcType ScmClockOutputSrc;
    Scm_Mcu_Drv_ClockOutDivType ScmClockOutputDivider;
    boolean Enable;
} Scm_Mcu_Drv_ClockOutputConfigType;





typedef struct
{
    Scm_Mcu_Drv_ClockOutputConfigType ScmClockOutputConfig;
} Scm_Mcu_Drv_ClockConfigType;





typedef struct
{

    boolean CacheBEInterruptEnable;
    boolean FpuInExactInterruptEnable;
    boolean FpuOverflowInterruptEnable;
    boolean FpuUnderflowInterruptEnable;
    boolean FpuInvalidOPInterruptEnable;
    boolean FpuDivzeroInterruptEnable;
    boolean FpuDenormalInterruptEnable;
    boolean SramLReadBufferEnable;
    boolean SramUReadBufferEnable;
    boolean CacheEnable;
    boolean CacheParityFaultEnable;
    boolean CacheParityMissEnable;


    Scm_Mcu_Drv_TimerExtClockInputType Mcpwm0Select;
    Scm_Mcu_Drv_TimerExtClockInputType Mcpwm1Select;
    Scm_Mcu_Drv_TimerExtClockInputType Tim0Select;
    Scm_Mcu_Drv_TimerExtClockInputType Tim1Select;
    Scm_Mcu_Drv_TimerExtClockInputType Tim2Select;
    Scm_Mcu_Drv_TimerExtClockInputType Tim3Select;

    Scm_Mcu_Drv_AdcMuxSelectType Adc0Ch8Select;
    Scm_Mcu_Drv_AdcMuxSelectType Adc0Ch9Select;
    Scm_Mcu_Drv_AdcMuxSelectType Adc1Ch14Select;
    Scm_Mcu_Drv_AdcMuxSelectType Adc1Ch15Select;
} Scm_Mcu_Drv_ConfigType;
# 35 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2
# 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Srmc_Drv_Types.h" 1
# 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Srmc_Drv_Types.h"
# 1 "../Generated/inc\\Srmc_Drv_Cfg.h" 1
# 30 "../Generated/inc\\Srmc_Drv_Cfg.h"
# 1 "../Generated/inc/Srmc_Drv_PBcfg.h" 1
# 31 "../Generated/inc\\Srmc_Drv_Cfg.h" 2
# 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Srmc_Drv_Types.h" 2
# 119 "../../../mcal/Mcu_ZX_K14xM/Inc/Srmc_Drv_Types.h"
typedef enum
{
    SRMC_DRV_RESET_PIN_DISABLE_FILTER = 0U,
    SRMC_DRV_RESET_PIN_BUS_CLOCK_FILTER,
    SRMC_DRV_RESET_PIN_LPO_CLOCK_FILTER
} Srmc_Drv_ResetPinFilterType;





typedef enum
{
    SRMC_DRV_DELAY_8_LPO_CYCLES = 0U,
    SRMC_DRV_DELAY_32_LPO_CYCLES,
    SRMC_DRV_DELAY_128_LPO_CYCLES,
    SRMC_DRV_DELAY_512_LPO_CYCLES
} Srmc_Drv_DelayType;





typedef enum
{
    SRMC_DRV_MODE_RUN = 0U,
    SRMC_DRV_MODE_WAIT,
    SRMC_DRV_MODE_STOP,
    SRMC_DRV_MODE_STANDBY
} Srmc_Drv_PowerModeType;





typedef enum
{
    SRMC_DRV_WUPSRC_PTD0 = 0x0U,
    SRMC_DRV_WUPSRC_PTD1 = 0x1U,
    SRMC_DRV_WUPSRC_PTA4 = 0x2U,
    SRMC_DRV_WUPSRC_PTC4 = 0x4U,
    SRMC_DRV_WUPSRC_PTC5 = 0x5U,
    SRMC_DRV_WUPSRC_PTE0 = 0x6U,
    SRMC_DRV_WUPSRC_PTE1 = 0x7U,
    SRMC_DRV_WUPSRC_PTE11 = 0x8U,
    SRMC_DRV_WUPSRC_PTE13 = 0x9U,
    SRMC_DRV_WUPSRC_PTE15 = 0xAU,
    SRMC_DRV_WUPSRC_PTE16 = 0xBU,
    SRMC_DRV_WUPSRC_PTA8 = 0xCU,
    SRMC_DRV_WUPSRC_PTA9 = 0xDU,
    SRMC_DRV_WUPSRC_PTA25 = 0xEU,
    SRMC_DRV_WUPSRC_PMU = 0xFU,
    SRMC_DRV_WUPSRC_RTC = 0x10U
} Srmc_Drv_WakeupSourceType;





typedef enum
{
    SRMC_DRV_WUPSRC_POLARITY_LOW = 0x0U,
    SRMC_DRV_WUPSRC_POLARITY_HIGH = 0x1U
} Srmc_Drv_WupPolarityType;
# 298 "../../../mcal/Mcu_ZX_K14xM/Inc/Srmc_Drv_Types.h"
typedef struct
{
    Srmc_Drv_ResetPinFilterType ResetPinFilterInNormal;
    Srmc_Drv_ResetPinFilterType ResetPinFilterInStop;
    uint32 ResetPinFilterBusClock;
    boolean CoreLockupResetEnable;
    Srmc_Drv_DelayType ResetDelayTime;
    uint32 ResetInterruptEnable;
} Srmc_Drv_ResetConfigType;




typedef struct
{
    boolean AllowStandbyMode;
    uint32 StopModeAckTimeout;
    uint32 WakeupControl1;
    uint32 WakeupControl2;
} Srmc_Drv_PowerModeConfigType;
# 36 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2
# 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Ram_Drv_Types.h" 1
# 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Ram_Drv_Types.h"
# 1 "../Generated/inc\\Ram_Drv_Cfg.h" 1
# 30 "../Generated/inc\\Ram_Drv_Cfg.h"
# 1 "../Generated/inc/Ram_Drv_PBcfg.h" 1
# 31 "../Generated/inc\\Ram_Drv_Cfg.h" 2
# 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Ram_Drv_Types.h" 2
# 90 "../../../mcal/Mcu_ZX_K14xM/Inc/Ram_Drv_Types.h"
typedef enum
{
    RAM_DRV_STATUS_OK = 0x00U,
    RAM_DRV_STATUS_NOT_OK = 0x01U,
    RAM_DRV_STATUS_UNDEFINED = 0x02U
} Ram_Drv_StatusType;





typedef uint32 Ram_Drv_SectorSizeType;





typedef uint32 Ram_Drv_WriteSizeType;





typedef uint32 Ram_Drv_IndexType;





typedef struct
{
    uint32 RamBaseAddr;
    uint32 RamSize;
    uint64 RamDefaultValue;
    uint32 RamWriteSize;
} Ram_Drv_ConfigType;
# 37 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2
# 202 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h"
typedef enum
{
    MCU_DRVW_OSC_CLOCK_LOSS_INT = 0U,
    MCU_DRVW_OSC_CLOCK_LOSS_RST
} Mcu_Drvw_OscClockLossActType;





typedef enum
{
    MCU_DRVW_FIRC64M_CLOCK_LOSS_INT = 0U,
    MCU_DRVW_FIRC64M_CLOCK_LOSS_RST
} Mcu_Drvw_Firc64MClockLossActType;





typedef enum
{
    MCU_DRVW_WUPSRC_PTD0 = 0x0U,
    MCU_DRVW_WUPSRC_PTD1 = 0x1U,
    MCU_DRVW_WUPSRC_PTA4 = 0x2U,
    MCU_DRVW_WUPSRC_PTC4 = 0x4U,
    MCU_DRVW_WUPSRC_PTC5 = 0x5U,
    MCU_DRVW_WUPSRC_PTE0 = 0x6U,
    MCU_DRVW_WUPSRC_PTE1 = 0x7U,
    MCU_DRVW_WUPSRC_PTE11 = 0x8U,
    MCU_DRVW_WUPSRC_PTE13 = 0x9U,
    MCU_DRVW_WUPSRC_PTE15 = 0xAU,
    MCU_DRVW_WUPSRC_PTE16 = 0xBU,
    MCU_DRVW_WUPSRC_PTA8 = 0xCU,
    MCU_DRVW_WUPSRC_PTA9 = 0xDU,
    MCU_DRVW_WUPSRC_PTA25 = 0xEU,
    MCU_DRVW_WUPSRC_PMU = 0xFU,
    MCU_DRVW_WUPSRC_RTC = 0x10U
} Mcu_Drvw_WakeupSourceType;





typedef enum
{
    MCU_DRVW_CLOCK_SRC_NO = 0U,
    MCU_DRVW_CLOCK_SRC_LPO32K = 1U,
    MCU_DRVW_CLOCK_SRC_SOSC = 2U,
    MCU_DRVW_CLOCK_SRC_FIRC64M = 3U,
    MCU_DRVW_CLOCK_SRC_FOSC = 4U,
    MCU_DRVW_CLOCK_SRC_PLL = 5U
} Mcu_Drvw_ClockSrcType;
# 271 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h"
typedef enum
{
    MCU_DRVW_WAKEUP_RESET = 0U,
    MCU_DRVW_LVD_RESET = 1U,
    MCU_DRVW_LOC_RESET = 2U,
    MCU_DRVW_WATCHDOG_RESET = 5U,
    MCU_DRVW_PIN_RESET = 6U,
    MCU_DRVW_POWER_ON_RESET = 7U,
    MCU_DRVW_LOCKUP_RESET = 9U,
    MCU_DRVW_SW_RESET = 10U,
    MCU_DRVW_MDM_AP_RESET =
        11U,
    MCU_DRVW_SERU_COLD_RESET = 12U,
    MCU_DRVW_SERU_SYS_RESET = 13U,
    MCU_DRVW_SERU_SACKERR = 15U,
    MCU_DRVW_MULTIPLE_RESET_REASON =
        0x55U,
    MCU_DRVW_RESET_UNDEFINED = 0xFFU
} Mcu_Drvw_ResetType;




typedef enum
{
    MCU_DRVW_POWERMODE_RUN = 0U,
    MCU_DRVW_POWERMODE_WAIT,
    MCU_DRVW_POWERMODE_STOP,
    MCU_DRVW_POWERMODE_STANDBY
} Mcu_Drvw_PowerModeType;





typedef struct
{
    const Scc_Drv_ClockConfigType *SccClockConfigPtr;
    const Scm_Mcu_Drv_ClockConfigType *ScmClockConfigPtr;
    const Parcc_Drv_SystemParccConfigType *ParccConfigPtr;
} Mcu_Drvw_ClockConfigType;
# 320 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h"
typedef struct
{

    const Srmc_Drv_ResetConfigType *SrmcResetConfigPtr;

    const Srmc_Drv_PowerModeConfigType *SrmcPowerModeConfigPtr;

    const Scm_Mcu_Drv_ConfigType *ScmConfigPtr;

    const Pmu_Drv_ConfigType *PmuConfigPtr;
} Mcu_Drvw_HwConfigType;
# 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h" 2
# 1 "../Generated/inc\\Mcu_Cfg.h" 1
# 30 "../Generated/inc\\Mcu_Cfg.h"
# 1 "../Generated/inc/Mcu_PBcfg.h" 1
# 31 "../Generated/inc\\Mcu_Cfg.h" 2
# 32 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h" 2
# 94 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h"
typedef enum
{
    MCU_POWER_ON_RESET = 0x00U,
    MCU_WATCHDOG_RESET,
    MCU_SW_RESET,
    MCU_RESET_UNDEFINED,
    MCU_WAKEUP_RESET,
    MCU_LVD_RESET,
    MCU_LOC_RESET,
    MCU_PIN_RESET,
    MCU_LOCKUP_RESET,
    MCU_MDM_AP_RESET,
    MCU_SERU_COLD_RESET,
    MCU_SERU_SYS_RESET,
    MCU_SERU_SACKERR,
    MCU_HW_TEST_RESET,
    MCU_MULTIPLE_RESET_REASON
} Mcu_ResetType;
# 128 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h"
typedef enum
{
    MCU_OSC_CLOCK_LOSS_INT = 0U,
    MCU_OSC_CLOCK_LOSS_RST
} Mcu_OscClockLossActType;




typedef enum
{
    MCU_FIRC64M_CLOCK_LOSS_INT = 0U,
    MCU_FIRC64M_CLOCK_LOSS_RST
} Mcu_Firc64MClockLossActType;
# 157 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h"
typedef enum
{
    MCU_WUPSRC_PTD0 = 0x0U,
    MCU_WUPSRC_PTD1 = 0x1U,
    MCU_WUPSRC_PTA4 = 0x2U,
    MCU_WUPSRC_PTC4 = 0x4U,
    MCU_WUPSRC_PTC5 = 0x5U,
    MCU_WUPSRC_PTE0 = 0x6U,
    MCU_WUPSRC_PTE1 = 0x7U,
    MCU_WUPSRC_PTE11 = 0x8U,
    MCU_WUPSRC_PTE13 = 0x9U,
    MCU_WUPSRC_PTE15 = 0xAU,
    MCU_WUPSRC_PTE16 = 0xBU,
    MCU_WUPSRC_PTA8 = 0xCU,
    MCU_WUPSRC_PTA9 = 0xDU,
    MCU_WUPSRC_PTA25 = 0xEU,
    MCU_WUPSRC_PMU = 0xFU,
    MCU_WUPSRC_RTC = 0x10U
} Mcu_WakeupSourceType;





typedef enum
{
    MCU_PLL_LOCKED = 0U,
    MCU_PLL_UNLOCKED = 1U,
    MCU_PLL_STATUS_UNDEFINED = 2U
} Mcu_PllStatusType;




typedef enum
{
    MCU_POWERMODE_RUN = 0U,
    MCU_POWERMODE_WAIT,
    MCU_POWERMODE_STOP,
    MCU_POWERMODE_STANDBY
} Mcu_PowerModeType;







typedef uint32 Mcu_RamSectionType;







typedef uint32 Mcu_ModeType;







typedef uint32 Mcu_ClockType;







typedef uint32 Mcu_RawResetType;






typedef struct
{
    Mcu_RamSectionType RamSectorId;
    uint32 RamBaseAddr;
    uint32 RamSize;
    uint64 RamDefaultValue;
    uint32 RamWriteSize;
} Mcu_RamConfigType;






typedef struct
{
    Mcu_ModeType ModeConfigId;
    Mcu_PowerModeType PowerMode;
} Mcu_ModeConfigType;






typedef struct
{
    Mcu_ClockType ClockConfigId;
    const Mcu_Drvw_ClockConfigType *ClockConfigPtr;
} Mcu_ClockConfigType;







typedef struct
{

    Mcu_RamSectionType NoOfRamConfigs;


    Mcu_ModeType NoOfModeConfigs;



    Mcu_ClockType NoOfClkConfigs;





    const Mcu_ModeConfigType (*ModeConfigPtr)[((uint32)1U)];



    const Mcu_ClockConfigType (*ClockConfigPtr)[((uint32)1U)];


    const Mcu_Drvw_HwConfigType *HwConfigPtr;
} Mcu_ConfigType;
# 31 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2
# 124 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" 1
# 848 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h"
#pragma clang section rodata = ".mcal_config_data"
# 125 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2
extern const Mcu_ConfigType *const Mcu_PreDefinedConfigPtr;

# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" 1
# 864 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h"
#pragma clang section rodata = ""
# 128 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2
# 139 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" 1
# 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h"
#pragma clang section rodata = ".mcal_config_data"
# 140 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" 1
# 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h"
#pragma clang section rodata = ""
# 143 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2








# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" 1
# 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h"
#pragma clang section text = ".mcal_code"
# 152 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2
# 161 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
void Mcu_Init(const Mcu_ConfigType *ConfigPtr);
# 173 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
Std_ReturnType Mcu_InitRamSection(Mcu_RamSectionType RamSection);
# 186 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
Std_ReturnType Mcu_InitClock(Mcu_ClockType ClockSetting);
# 200 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
Std_ReturnType Mcu_DistributePllClock(void);
# 214 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
Mcu_PllStatusType Mcu_GetPllStatus(void);
# 224 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
Mcu_ResetType Mcu_GetResetReason(void);
# 234 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
Mcu_RawResetType Mcu_GetResetRawValue(void);
# 245 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
void Mcu_PerformReset(void);
# 256 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
void Mcu_SetMode(Mcu_ModeType McuMode);
# 267 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
void Mcu_GetVersionInfo(Std_VersionInfoType *versioninfo);
# 291 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
Mcu_PowerModeType Mcu_GetPowerModeState(void);
# 304 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
boolean Mcu_EnableOscClockMonitor(Mcu_OscClockLossActType Act);
# 314 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
void Mcu_DisableOscClockMonitor(void);
# 326 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
boolean Mcu_EnableFircClockMonitor(Mcu_Firc64MClockLossActType Act);
# 336 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
void Mcu_DisableFircClockMonitor(void);
# 360 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h"
void Mcu_SetWakeupSource(Mcu_WakeupSourceType WakeupSource, boolean ActiveHigh, boolean Enable);


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" 1
# 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h"
#pragma clang section text = ""
# 364 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2
# 8 "../../../Package/Cdd/CddSbc/Cfg\\CddSbc_Cfg.h" 2
# 24 "../../../Package/Cdd/CddSbc/Api\\CddSbc.h" 2
# 1 "../../../Package/Cdd/CddSbc/Cfg\\CddSbc_Router.h" 1
# 28 "../../../Package/Cdd/CddSbc/Cfg\\CddSbc_Router.h"
typedef enum
{
  eNoResetMCU = 0,
  ePowerOnResetMCU,
  eWatchdogResetMCU,
  eSoftwareReset,
  ePLLReset,
  eECCReset,
  eMCUSelfTestReset,
  eUnderVoltage,
  eOtherReasons
}teMCUResetType;

typedef enum
{
  eNoResetSBC = 0,
  ePowerOnResetSBC,
  eCANWakeUpReset,
  eWatchdogReset,
  eInputWakeUpReset
}teSBCResetType;





void CddSbc_Rou_Init(void);
void CddSbc_Rou_DeInit(void);




void CddSbc_Rou_SetSleepMode(void);



void CddSbc_Rou_SetCanMode(uint8 ucCanChannel, uint8 ucCanMode);
uint8 CddSbc_Rou_GetCanMode(uint8 ucCanChannel);
uint8 CddSbc_Rou_GetCanUV(void);



boolean CddSbc_Rou_GetWakeUpStatus(void);



uint8 CddSbc_Rou_GetSBCResetReason(void);




void CddSbc_Rou_SetWdgWindowModeAnd10ms(void);
void CddSbc_Rou_SetWdgWindowModeAnd200ms(void);
void CddSbc_Rou_SetWdgTimeoutModeAnd200ms(void);
# 25 "../../../Package/Cdd/CddSbc/Api\\CddSbc.h" 2
# 41 "../../../Package/Cdd/CddSbc/Api\\CddSbc.h"
# 1 "../../../Package/Cdd/CddSbc/Api\\../Cfg/CddSbc_MemMap.h" 1
# 42 "../../../Package/Cdd/CddSbc/Api\\CddSbc.h" 2





void riCddSbcInit(void);
void CddSbc_Init(void);
void CddSbc_DeInit(void);




void CddSbc_SetSleepMode(void);



void CddSbc_SetCanMode(uint8 ucCanChannel, uint8 ucCanMode);
uint8 CddSbc_GetCanMode(uint8 ucCanChannel);
uint8 CddSbc_GetCanUV(void);





boolean CddSbc_GetWakeUpStatus(void);




void CddSbc_SetWdgWindowModeAnd10ms(void);
void CddSbc_SetWdgWindowModeAnd200ms(void);
void CddSbc_SetWdgTimeoutModeAnd200ms(void);



tieResetReason CddSbc_GetResetReason(void);



# 1 "../../../Package/Cdd/CddSbc/Api\\../Cfg/CddSbc_MemMap.h" 1
# 82 "../../../Package/Cdd/CddSbc/Api\\CddSbc.h" 2
# 24 "../../../Package/Cdd/CddSbc/Gen/CddSbc_Router.c" 2



# 1 "../../../Package/Cdd/CddTle94x1/Api\\CddTle94x1.h" 1
# 48 "../../../Package/Cdd/CddTle94x1/Api\\CddTle94x1.h"
# 1 "../../../Package/Cdd/CddTle94x1/Cfg\\../Cfg/CddTle94x1_MemMap.h" 1
# 49 "../../../Package/Cdd/CddTle94x1/Api\\CddTle94x1.h" 2
# 62 "../../../Package/Cdd/CddTle94x1/Api\\CddTle94x1.h"
void CddTle94x1_Init(void);
void CddTle94x1_DeInit(void);



void CddTle94x1_SetSleepMode(void);



void CddTle94x1_SetCanMode(uint8 ucCanChannel, uint8 ucCanMode);
uint8 CddTle94x1_GetCanMode(uint8 ucCanChannel);
uint8 CddTle94x1_GetCanUV(void);



boolean CddTle94x1_GetWakeUpStatus(void);
void CddSbc_InsertDefaultMessage(void);
void CddSbc_ScheduleTableFull(boolean boStatus);



uint8 CddTle94x1_GetSBCResetReason(void);



void CddTle94x1_SetWdgWindowModeAnd10ms(void);
void CddTle94x1_SetWdgTimeoutModeAnd200ms(void);
void CddTle94x1_SetWdgWindowModeAnd200ms(void);


boolean CddSpi_TransferMsg(uint16 *Data, uint16 *RcData, uint8 len, uint8 Cs);
uint8 Spi_Stat_Get(void);


# 1 "../../../Package/Cdd/CddTle94x1/Cfg\\../Cfg/CddTle94x1_MemMap.h" 1
# 97 "../../../Package/Cdd/CddTle94x1/Api\\CddTle94x1.h" 2
# 28 "../../../Package/Cdd/CddSbc/Gen/CddSbc_Router.c" 2
# 49 "../../../Package/Cdd/CddSbc/Gen/CddSbc_Router.c"
# 1 "../../../Package/Cdd/CddSbc/Api\\../Cfg/CddSbc_MemMap.h" 1
# 50 "../../../Package/Cdd/CddSbc/Gen/CddSbc_Router.c" 2
# 65 "../../../Package/Cdd/CddSbc/Gen/CddSbc_Router.c"
void CddSbc_Rou_Init(void)
{
  CddTle94x1_Init();
}
# 79 "../../../Package/Cdd/CddSbc/Gen/CddSbc_Router.c"
void CddSbc_Rou_DeInit(void)
{
  CddTle94x1_DeInit();
}
# 95 "../../../Package/Cdd/CddSbc/Gen/CddSbc_Router.c"
void CddSbc_Rou_SetSleepMode(void)
{
  CddTle94x1_SetSleepMode();
}
# 112 "../../../Package/Cdd/CddSbc/Gen/CddSbc_Router.c"
void CddSbc_Rou_SetCanMode(uint8 ucCanChannel, uint8 ucCanMode)
{
  CddTle94x1_SetCanMode(ucCanChannel, ucCanMode);
}
# 126 "../../../Package/Cdd/CddSbc/Gen/CddSbc_Router.c"
uint8 CddSbc_Rou_GetCanMode(uint8 ucCanChannel)
{
  return CddTle94x1_GetCanMode(ucCanChannel);
}
# 140 "../../../Package/Cdd/CddSbc/Gen/CddSbc_Router.c"
uint8 CddSbc_Rou_GetCanUV(void)
{
  return CddTle94x1_GetCanUV();
}





boolean CddSbc_Rou_GetWakeUpStatus(void)
{
  return CddTle94x1_GetWakeUpStatus();
}
# 166 "../../../Package/Cdd/CddSbc/Gen/CddSbc_Router.c"
uint8 CddSbc_Rou_GetSBCResetReason(void)
{

  return CddTle94x1_GetSBCResetReason();
}



void CddSbc_Rou_SetWdgWindowModeAnd10ms(void)
{
  CddTle94x1_SetWdgWindowModeAnd10ms();
}

void CddSbc_Rou_SetWdgWindowModeAnd200ms(void)
{
  CddTle94x1_SetWdgWindowModeAnd200ms();
}

void CddSbc_Rou_SetWdgTimeoutModeAnd200ms(void)
{
  CddTle94x1_SetWdgTimeoutModeAnd200ms();
}




# 1 "../../../Package/Cdd/CddSbc/Api\\../Cfg/CddSbc_MemMap.h" 1
# 193 "../../../Package/Cdd/CddSbc/Gen/CddSbc_Router.c" 2