# 1 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
# 1 "<built-in>" 1
# 1 "<built-in>" 3
# 387 "<built-in>" 3
# 1 "<command line>" 1
# 1 "<built-in>" 2
# 1 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c" 2
# 26 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
# 1 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" 1
# 28 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h"
# 1 "../../../mcal/Dma_ZX_K14xM/Inc/CDD_Dma_Types.h" 1
# 27 "../../../mcal/Dma_ZX_K14xM/Inc/CDD_Dma_Types.h"
# 1 "../Generated/inc\\CDD_Dma_Cfg.h" 1
# 30 "../Generated/inc\\CDD_Dma_Cfg.h"
# 1 "../Generated/inc/CDD_Dma_PBcfg.h" 1
# 31 "../Generated/inc\\CDD_Dma_Cfg.h" 2
# 28 "../../../mcal/Dma_ZX_K14xM/Inc/CDD_Dma_Types.h" 2
# 1 "../../../mcal/Dma_ZX_K14xM/Inc/Dma_Drv_Types.h" 1
# 29 "../../../mcal/Dma_ZX_K14xM/Inc/Dma_Drv_Types.h"
# 1 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 1
# 30 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h"
# 1 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h" 1
# 86 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h"
typedef unsigned char boolean;




typedef unsigned char uint8;




typedef unsigned short uint16;




typedef unsigned int uint32;





typedef unsigned long long uint64;




typedef signed char sint8;




typedef signed short sint16;




typedef signed int sint32;





typedef signed long long sint64;




typedef unsigned long uint8_least;




typedef unsigned long uint16_least;





typedef unsigned long uint32_least;




typedef signed long sint8_least;




typedef signed long sint16_least;




typedef signed long sint32_least;




typedef float float32;





typedef double float64;




typedef void *VoidPtr;




typedef const void *ConstVoidPtr;
# 31 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2
# 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 1
# 31 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h"
# 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler_Cfg.h" 1
# 32 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 2
# 32 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2
# 63 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h"
typedef unsigned char StatusType;
# 104 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h"
typedef uint8 Std_ReturnType;




typedef uint8 Std_TransformerClass;




typedef uint8 Std_TransformerForwardCode;





typedef uint8 Std_MessageTypeType;





typedef uint8 Std_MessageResultType;





typedef struct
{
    uint16 vendorID;
    uint16 moduleID;
    uint8 sw_major_version;
    uint8 sw_minor_version;
    uint8 sw_patch_version;
} Std_VersionInfoType;




typedef struct
{
    uint8 errorCode;
    Std_TransformerClass transformerClass;
} Std_TransformerError;





typedef struct
{
    Std_TransformerForwardCode errorCode;
    Std_TransformerClass transformerClass;
} Std_TransformerForward;







typedef Std_ReturnType (*Std_ExtractProtocolHeaderFieldsType)(const uint8 *buffer,
                                                              uint32 bufferLength,
                                                              Std_MessageTypeType *messageType,
                                                              Std_MessageResultType *messageResult);
# 30 "../../../mcal/Dma_ZX_K14xM/Inc/Dma_Drv_Types.h" 2
# 1 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 1
# 29 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
# 1 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 1
# 30 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h"
# 1 "../Generated/inc\\McalLib_Cfg.h" 1
# 31 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 2
# 273 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h"
static inline uint32 McalLib_ReadControlReg(void)
{
    uint32 res;

    __asm("MRS %0,CONTROL" : "=r" (res));

    return res;
}
# 290 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h"
static inline uint32 McalLib_ReadIpsrReg(void)
{
    uint32 res;
    __asm("MRS %0,IPSR" : "=r" (res));
    return res;
}
# 305 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h"
static inline uint32 McalLib_ReadPriMaskReg(void)
{
    uint32 res;
    __asm("MRS %0,PRIMASK" : "=r" (res));
    return res;
}
# 30 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2
# 184 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
typedef enum
{
    MCALLIB_COUNTER_SOFTWARE,

    MCALLIB_COUNTER_OS,




} McalLib_CounterType;




typedef struct
{
    uint32 CounterId;
    uint32 CounterFreq;
} McalLib_ConfigType;







# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1
# 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h"
#pragma clang section rodata = ".mcal_config_data"
# 211 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2

extern const McalLib_ConfigType *const McalLib_PreDefinedConfigPtr[(1U)];


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1
# 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h"
#pragma clang section rodata = ""
# 216 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2
# 230 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
extern void Sys_SystemReset(void);


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1
# 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h"
#pragma clang section text = ".mcal_code"
# 234 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2







void McalLib_Init(void);
# 254 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
Std_ReturnType McalLib_GetCounterValue(McalLib_CounterType Counter, uint32 *Value);
# 270 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
Std_ReturnType McalLib_GetElapsedValue(McalLib_CounterType Counter, uint32 *const CounterValue,
                                       uint32 *ElapsedValue);
# 282 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
uint32 McalLib_MicroSecToTicks(McalLib_CounterType Counter, uint32 MicroSecond);
# 296 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
void McalLib_SetCounterFreq(McalLib_CounterType Counter, uint32 Freq);
# 309 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
static inline void McalLib_Assert(const uint8 *File, uint32 Line)
{
    (void)File;
    (void)Line;

    for (;;)
    {
    }
}
# 327 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
void McalLib_SuspendAllInterrupts(void);







void McalLib_ResumeAllInterrupts(void);


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1
# 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h"
#pragma clang section text = ""
# 339 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2
# 31 "../../../mcal/Dma_ZX_K14xM/Inc/Dma_Drv_Types.h" 2
# 1 "../Generated/inc\\Dma_Drv_Cfg.h" 1
# 30 "../Generated/inc\\Dma_Drv_Cfg.h"
# 1 "../Generated/inc/Dma_Drv_PBcfg.h" 1
# 31 "../Generated/inc\\Dma_Drv_Cfg.h" 2
# 32 "../../../mcal/Dma_ZX_K14xM/Inc/Dma_Drv_Types.h" 2
# 88 "../../../mcal/Dma_ZX_K14xM/Inc/Dma_Drv_Types.h"
typedef enum
{
    DMA_DRV_PHYS_CH_0 = 0U,
    DMA_DRV_PHYS_CH_1,
    DMA_DRV_PHYS_CH_2,
    DMA_DRV_PHYS_CH_3,
    DMA_DRV_PHYS_CH_4,
    DMA_DRV_PHYS_CH_5,
    DMA_DRV_PHYS_CH_6,
    DMA_DRV_PHYS_CH_7,
    DMA_DRV_PHYS_CH_8,
    DMA_DRV_PHYS_CH_9,
    DMA_DRV_PHYS_CH_10,
    DMA_DRV_PHYS_CH_11,
    DMA_DRV_PHYS_CH_12,
    DMA_DRV_PHYS_CH_13,
    DMA_DRV_PHYS_CH_14,
    DMA_DRV_PHYS_CH_15
} Dma_Drv_ChannelType;




typedef void (*Dma_Drv_CallbackType)(const Dma_Drv_ChannelType Channel);




typedef void (*Dma_Drv_ErrIntCallbackType)(const Dma_Drv_ChannelType Channel);




typedef enum
{
    DMA_DRV_PRIORITY_LEVEL_0 = 0U,
    DMA_DRV_PRIORITY_LEVEL_1,
    DMA_DRV_PRIORITY_LEVEL_2,
    DMA_DRV_PRIORITY_LEVEL_3,
    DMA_DRV_PRIORITY_LEVEL_4,
    DMA_DRV_PRIORITY_LEVEL_5,
    DMA_DRV_PRIORITY_LEVEL_6,
    DMA_DRV_PRIORITY_LEVEL_7,
    DMA_DRV_PRIORITY_LEVEL_8,
    DMA_DRV_PRIORITY_LEVEL_9,
    DMA_DRV_PRIORITY_LEVEL_10,
    DMA_DRV_PRIORITY_LEVEL_11,
    DMA_DRV_PRIORITY_LEVEL_12,
    DMA_DRV_PRIORITY_LEVEL_13,
    DMA_DRV_PRIORITY_LEVEL_14,
    DMA_DRV_PRIORITY_LEVEL_15
} Dma_Drv_ChannelPriorityType;





typedef enum
{
    DMA_DRV_TRANSFER_SIZE_1BYTE = 0U,
    DMA_DRV_TRANSFER_SIZE_2BYTE,
    DMA_DRV_TRANSFER_SIZE_4BYTE
} Dma_Drv_TransferSizeType;






typedef enum
{
    DMA_DRV_REQ_I2S0 = 0U,
    DMA_DRV_REQ_I2S1 = 1U,

    DMA_DRV_REQ_UART0_TX = 2U,
    DMA_DRV_REQ_UART0_RX = 3U,
    DMA_DRV_REQ_UART1_TX = 4U,
    DMA_DRV_REQ_UART1_RX = 5U,
    DMA_DRV_REQ_UART2_TX = 6U,
    DMA_DRV_REQ_UART2_RX = 7U,
    DMA_DRV_REQ_UART3_TX = 8U,
    DMA_DRV_REQ_UART3_RX = 9U,
    DMA_DRV_REQ_UART4_TX = 10U,
    DMA_DRV_REQ_UART4_RX = 11U,
    DMA_DRV_REQ_UART5_TX = 12U,
    DMA_DRV_REQ_UART5_RX = 13U,

    DMA_DRV_REQ_SPI0_TX = 14U,
    DMA_DRV_REQ_SPI0_RX = 15U,
    DMA_DRV_REQ_SPI1_TX = 16U,
    DMA_DRV_REQ_SPI1_RX = 17U,
    DMA_DRV_REQ_SPI2_TX = 18U,
    DMA_DRV_REQ_SPI2_RX = 19U,
    DMA_DRV_REQ_SPI3_TX = 20U,
    DMA_DRV_REQ_SPI3_RX = 21U,

    DMA_DRV_REQ_STIM0 = 22U,
    DMA_DRV_REQ_STIM1 = 23U,
    DMA_DRV_REQ_STIM2 = 24U,
    DMA_DRV_REQ_STIM3 = 25U,

    DMA_DRV_REQ_I2C0_TX = 26U,
    DMA_DRV_REQ_I2C0_RX = 27U,
    DMA_DRV_REQ_I2C1_TX = 28U,
    DMA_DRV_REQ_I2C1_RX = 29U,

    DMA_DRV_REQ_CAN0 = 30U,
    DMA_DRV_REQ_CAN1 = 31U,
    DMA_DRV_REQ_CAN2 = 32U,
    DMA_DRV_REQ_CAN3 = 33U,
    DMA_DRV_REQ_CAN4 = 34U,
    DMA_DRV_REQ_CAN5 = 35U,
    DMA_DRV_REQ_CAN6 = 36U,
    DMA_DRV_REQ_CAN7 = 37U,

    DMA_DRV_REQ_TIM0_CHANNEL0 = 38U,
    DMA_DRV_REQ_TIM0_CHANNEL1 = 39U,
    DMA_DRV_REQ_TIM0_CHANNEL2 = 40U,
    DMA_DRV_REQ_TIM0_CHANNEL3 = 41U,
    DMA_DRV_REQ_TIM0_CHANNEL4 = 42U,
    DMA_DRV_REQ_TIM0_CHANNEL5 = 43U,
    DMA_DRV_REQ_TIM0_CHANNEL6 = 44U,
    DMA_DRV_REQ_TIM0_CHANNEL7 = 45U,
    DMA_DRV_REQ_TIM1_CHANNEL0 = 46U,
    DMA_DRV_REQ_TIM1_CHANNEL1 = 47U,
    DMA_DRV_REQ_TIM1_CHANNEL2 = 48U,
    DMA_DRV_REQ_TIM1_CHANNEL3 = 49U,
    DMA_DRV_REQ_TIM1_CHANNEL4 = 50U,
    DMA_DRV_REQ_TIM1_CHANNEL5 = 51U,
    DMA_DRV_REQ_TIM1_CHANNEL6 = 52U,
    DMA_DRV_REQ_TIM1_CHANNEL7 = 53U,
    DMA_DRV_REQ_TIM2_CHANNEL0 = 54U,
    DMA_DRV_REQ_TIM2_CHANNEL1 = 55U,
    DMA_DRV_REQ_TIM2_CHANNEL2 = 56U,
    DMA_DRV_REQ_TIM2_CHANNEL3 = 57U,
    DMA_DRV_REQ_TIM2_CHANNEL4 = 58U,
    DMA_DRV_REQ_TIM2_CHANNEL5 = 59U,
    DMA_DRV_REQ_TIM2_CHANNEL6 = 60U,
    DMA_DRV_REQ_TIM2_CHANNEL7 = 61U,
    DMA_DRV_REQ_TIM3_CHANNEL0 = 62U,
    DMA_DRV_REQ_TIM3_CHANNEL1 = 63U,
    DMA_DRV_REQ_TIM3_CHANNEL2 = 64U,
    DMA_DRV_REQ_TIM3_CHANNEL3 = 65U,
    DMA_DRV_REQ_TIM3_CHANNEL4 = 66U,
    DMA_DRV_REQ_TIM3_CHANNEL5 = 67U,
    DMA_DRV_REQ_TIM3_CHANNEL6 = 68U,
    DMA_DRV_REQ_TIM3_CHANNEL7 = 69U,

    DMA_DRV_REQ_MCPWM0_CHANNEL0 = 70U,
    DMA_DRV_REQ_MCPWM0_CHANNEL1 = 71U,
    DMA_DRV_REQ_MCPWM0_CHANNEL2 = 72U,
    DMA_DRV_REQ_MCPWM0_CHANNEL3 = 73U,
    DMA_DRV_REQ_MCPWM0_CHANNEL4 = 74U,
    DMA_DRV_REQ_MCPWM0_CHANNEL5 = 75U,
    DMA_DRV_REQ_MCPWM0_CHANNEL6 = 76U,
    DMA_DRV_REQ_MCPWM0_CHANNEL7 = 77U,
    DMA_DRV_REQ_MCPWM1_CHANNEL0 = 78U,
    DMA_DRV_REQ_MCPWM1_CHANNEL1 = 79U,
    DMA_DRV_REQ_MCPWM1_CHANNEL2 = 80U,
    DMA_DRV_REQ_MCPWM1_CHANNEL3 = 81U,
    DMA_DRV_REQ_MCPWM1_CHANNEL4 = 82U,
    DMA_DRV_REQ_MCPWM1_CHANNEL5 = 83U,
    DMA_DRV_REQ_MCPWM1_CHANNEL6 = 84U,
    DMA_DRV_REQ_MCPWM1_CHANNEL7 = 85U,

    DMA_DRV_REQ_ADC0 = 88U,
    DMA_DRV_REQ_ADC1 = 89U,

    DMA_DRV_REQ_CMP = 90U,

    DMA_DRV_REQ_PORTA = 91U,
    DMA_DRV_REQ_PORTB = 92U,
    DMA_DRV_REQ_PORTC = 93U,
    DMA_DRV_REQ_PORTD = 94U,
    DMA_DRV_REQ_PORTE = 95U,

    DMA_DRV_REQ_DMAMUX_ALWAYS_ENABLED0 = 96U,
    DMA_DRV_REQ_DMAMUX_ALWAYS_ENABLED1 = 97U,

    DMA_DRV_REQ_SOFTWARE = 128U
} Dma_Drv_RequestSourceType;




typedef struct
{
    Dma_Drv_RequestSourceType MuxReqSrc;
    boolean ReqEn;


} Dma_Drv_RequestConfigType;




typedef struct
{
    uint8 Priority;
    boolean PreemptionDis;


    boolean SuspendEn;


} Dma_Drv_PriorityConfigType;






typedef struct
{
    boolean ErrIntEn;


    boolean MajorIntEn;


    Dma_Drv_RequestConfigType * RequestConfig;
    Dma_Drv_PriorityConfigType * PriorityConfig;
} Dma_Drv_ChannelGlobalConfigType;




typedef struct
{
    uint32 Addr;
    sint16 MinorLoopOffset;
    sint16 MajorLoopOffset;
    Dma_Drv_TransferSizeType TransferSize;
} Dma_Drv_AddrConfigType;

typedef struct
{
    uint32 TransferNum;
    uint16 MinorLoopCnt;
    boolean ReqDis;


} Dma_Drv_TransferControlConfigType;




typedef struct
{
    Dma_Drv_AddrConfigType * SourceConfig;
    Dma_Drv_AddrConfigType * DestinationConfig;
    Dma_Drv_TransferControlConfigType * ControlConfig;
} Dma_Drv_ChannelTransferConfigType;






typedef struct
{
    boolean DebugHalt;



    boolean RoundRobin;


    boolean ErrHalt;



} Dma_Drv_ConfigType;





typedef enum
{
    DMA_DRV_INT_ERROR = 0U,
    DMA_DRV_INT_DONE,
    DMA_DRV_INT_ALL
} Dma_Drv_IntType;




typedef enum
{
    DMA_DRV_HALT_OFF = 0U,
    DMA_DRV_HALT_ON
} Dma_Drv_HaltType;
# 29 "../../../mcal/Dma_ZX_K14xM/Inc/CDD_Dma_Types.h" 2
# 87 "../../../mcal/Dma_ZX_K14xM/Inc/CDD_Dma_Types.h"
typedef void (*Dma_CallbackType)(uint32 LogicChIndex);






typedef enum
{
    DMA_CH_UNINIT_STATE = 0U,
    DMA_CH_READY_STATE = 1U,
    DMA_CH_ERROR_STATE = 2U
} Dma_ChannelStateType;




typedef enum
{
    DMA_TRANSFER_SIZE_1BYTE = 0U,
    DMA_TRANSFER_SIZE_2BYTE,
    DMA_TRANSFER_SIZE_4BYTE
} Dma_TransferSizeType;






typedef enum
{
    DMA_REQ_I2S0 = 0U,
    DMA_REQ_I2S1 = 1U,

    DMA_REQ_UART0_TX = 2U,
    DMA_REQ_UART0_RX = 3U,
    DMA_REQ_UART1_TX = 4U,
    DMA_REQ_UART1_RX = 5U,
    DMA_REQ_UART2_TX = 6U,
    DMA_REQ_UART2_RX = 7U,
    DMA_REQ_UART3_TX = 8U,
    DMA_REQ_UART3_RX = 9U,
    DMA_REQ_UART4_TX = 10U,
    DMA_REQ_UART4_RX = 11U,
    DMA_REQ_UART5_TX = 12U,
    DMA_REQ_UART5_RX = 13U,

    DMA_REQ_SPI0_TX = 14U,
    DMA_REQ_SPI0_RX = 15U,
    DMA_REQ_SPI1_TX = 16U,
    DMA_REQ_SPI1_RX = 17U,
    DMA_REQ_SPI2_TX = 18U,
    DMA_REQ_SPI2_RX = 19U,
    DMA_REQ_SPI3_TX = 20U,
    DMA_REQ_SPI3_RX = 21U,

    DMA_REQ_STIM0 = 22U,
    DMA_REQ_STIM1 = 23U,
    DMA_REQ_STIM2 = 24U,
    DMA_REQ_STIM3 = 25U,

    DMA_REQ_I2C0_TX = 26U,
    DMA_REQ_I2C0_RX = 27U,
    DMA_REQ_I2C1_TX = 28U,
    DMA_REQ_I2C1_RX = 29U,

    DMA_REQ_CAN0 = 30U,
    DMA_REQ_CAN1 = 31U,
    DMA_REQ_CAN2 = 32U,
    DMA_REQ_CAN3 = 33U,
    DMA_REQ_CAN4 = 34U,
    DMA_REQ_CAN5 = 35U,
    DMA_REQ_CAN6 = 36U,
    DMA_REQ_CAN7 = 37U,

    DMA_REQ_TIM0_CHANNEL0 = 38U,
    DMA_REQ_TIM0_CHANNEL1 = 39U,
    DMA_REQ_TIM0_CHANNEL2 = 40U,
    DMA_REQ_TIM0_CHANNEL3 = 41U,
    DMA_REQ_TIM0_CHANNEL4 = 42U,
    DMA_REQ_TIM0_CHANNEL5 = 43U,
    DMA_REQ_TIM0_CHANNEL6 = 44U,
    DMA_REQ_TIM0_CHANNEL7 = 45U,
    DMA_REQ_TIM1_CHANNEL0 = 46U,
    DMA_REQ_TIM1_CHANNEL1 = 47U,
    DMA_REQ_TIM1_CHANNEL2 = 48U,
    DMA_REQ_TIM1_CHANNEL3 = 49U,
    DMA_REQ_TIM1_CHANNEL4 = 50U,
    DMA_REQ_TIM1_CHANNEL5 = 51U,
    DMA_REQ_TIM1_CHANNEL6 = 52U,
    DMA_REQ_TIM1_CHANNEL7 = 53U,
    DMA_REQ_TIM2_CHANNEL0 = 54U,
    DMA_REQ_TIM2_CHANNEL1 = 55U,
    DMA_REQ_TIM2_CHANNEL2 = 56U,
    DMA_REQ_TIM2_CHANNEL3 = 57U,
    DMA_REQ_TIM2_CHANNEL4 = 58U,
    DMA_REQ_TIM2_CHANNEL5 = 59U,
    DMA_REQ_TIM2_CHANNEL6 = 60U,
    DMA_REQ_TIM2_CHANNEL7 = 61U,
    DMA_REQ_TIM3_CHANNEL0 = 62U,
    DMA_REQ_TIM3_CHANNEL1 = 63U,
    DMA_REQ_TIM3_CHANNEL2 = 64U,
    DMA_REQ_TIM3_CHANNEL3 = 65U,
    DMA_REQ_TIM3_CHANNEL4 = 66U,
    DMA_REQ_TIM3_CHANNEL5 = 67U,
    DMA_REQ_TIM3_CHANNEL6 = 68U,
    DMA_REQ_TIM3_CHANNEL7 = 69U,

    DMA_REQ_MCPWM0_CHANNEL0 = 70U,
    DMA_REQ_MCPWM0_CHANNEL1 = 71U,
    DMA_REQ_MCPWM0_CHANNEL2 = 72U,
    DMA_REQ_MCPWM0_CHANNEL3 = 73U,
    DMA_REQ_MCPWM0_CHANNEL4 = 74U,
    DMA_REQ_MCPWM0_CHANNEL5 = 75U,
    DMA_REQ_MCPWM0_CHANNEL6 = 76U,
    DMA_REQ_MCPWM0_CHANNEL7 = 77U,
    DMA_REQ_MCPWM1_CHANNEL0 = 78U,
    DMA_REQ_MCPWM1_CHANNEL1 = 79U,
    DMA_REQ_MCPWM1_CHANNEL2 = 80U,
    DMA_REQ_MCPWM1_CHANNEL3 = 81U,
    DMA_REQ_MCPWM1_CHANNEL4 = 82U,
    DMA_REQ_MCPWM1_CHANNEL5 = 83U,
    DMA_REQ_MCPWM1_CHANNEL6 = 84U,
    DMA_REQ_MCPWM1_CHANNEL7 = 85U,

    DMA_REQ_ADC0 = 88U,
    DMA_REQ_ADC1 = 89U,

    DMA_REQ_CMP = 90U,

    DMA_REQ_PORTA = 91U,
    DMA_REQ_PORTB = 92U,
    DMA_REQ_PORTC = 93U,
    DMA_REQ_PORTD = 94U,
    DMA_REQ_PORTE = 95U,

    DMA_REQ_DMAMUX_ALWAYS_ENABLED0 = 96U,
    DMA_REQ_DMAMUX_ALWAYS_ENABLED1 = 97U,

    DMA_REQ_SOFTWARE = 128U
} Dma_RequestSourceType;




typedef struct
{
    uint32 Addr;
    sint16 MinorLoopOffset;
    sint16 MajorLoopOffset;
    Dma_TransferSizeType TransferSize;
} Dma_AddrConfigType;

typedef Dma_Drv_TransferControlConfigType Dma_TransferControlConfigType;




typedef struct
{
    Dma_AddrConfigType * SourceConfig;
    Dma_AddrConfigType * DestinationConfig;
    Dma_TransferControlConfigType * ControlConfig;
} Dma_ChannelTransferConfigType;




typedef struct
{
    Dma_RequestSourceType MuxReqSrc;
    boolean ReqEn;


} Dma_RequestConfigType;




typedef Dma_Drv_PriorityConfigType Dma_PriorityConfigType;





typedef struct
{
    boolean ErrIntEn;


    boolean MajorIntEn;


    Dma_RequestConfigType * RequestConfig;
    Dma_PriorityConfigType * PriorityConfig;
} Dma_ChannelGlobalConfigType;





typedef struct
{
    uint32 ChErrState;
    Dma_ChannelStateType ChState;
} Dma_ChannelOptStateType;



typedef struct
{
    Dma_Drv_ChannelType PhyChId;
    Dma_CallbackType ErrIntCallback;

    Dma_CallbackType MajorIntCallback;

    const Dma_Drv_ChannelGlobalConfigType * ChGlobalCfgPtr;

    const Dma_Drv_ChannelTransferConfigType * ChTransferCfgPtr;


} Dma_ChannelConfigType;



typedef struct
{
    const Dma_ChannelConfigType * const * ChCfgArrayPtr;

    const Dma_Drv_ConfigType * const * ModuleCfgArrayPtr;

} Dma_ConfigType;






typedef struct
{
    Dma_ChannelStateType State;
    uint32 Error;
# 342 "../../../mcal/Dma_ZX_K14xM/Inc/CDD_Dma_Types.h"
    boolean Busy;


    boolean Done;


} Dma_ChannelStatusType;





typedef struct
{
    uint16 LastErrChStatus;
    uint16 ChannelsErrStatus;
    boolean Busy;


    boolean Halt;


} Dma_ModuleStatusType;




typedef enum
{
    DMA_INT_ERROR = 0U,
    DMA_INT_DONE,
    DMA_INT_ALL
} Dma_IntType;




typedef enum
{
    DMA_HALT_OFF = 0U,
    DMA_HALT_ON
} Dma_HaltType;
# 29 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" 2
# 99 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h"
# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 848 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section rodata = ".mcal_config_data"
# 100 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" 2

extern const Dma_ConfigType *const Dma_PreDefinedConfigPtr;


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 864 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section rodata = ""
# 105 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" 2
# 123 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h"
# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section text = ".mcal_code"
# 124 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" 2
# 134 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h"
void Dma_Init(const Dma_ConfigType * const CfgPtr);
# 146 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h"
void Dma_GetChannelStatus(const uint32 LogicChIndex, Dma_ChannelStatusType * const StatusPtr);
# 159 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h"
void Dma_Halt(Dma_HaltType Cmd);
# 173 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h"
Std_ReturnType Dma_ConfigChannelTransfer(const uint32 LogicChIndex,
                               const Dma_ChannelTransferConfigType *ChConfigPtr);
# 188 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h"
Std_ReturnType Dma_ConfigChannelGlobalParam(const uint32 LogicChIndex,
                                  const Dma_ChannelGlobalConfigType *ChConfigPtr);
# 201 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h"
void Dma_EnableChannelHwRequest(const uint32 LogicChIndex, boolean Enable);
# 212 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h"
void Dma_TriggerChannelStartBySw(const uint32 LogicChIndex);
# 227 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h"
void Dma_ClearIntStatus(const uint32 LogicChIndex, Dma_IntType Int);
# 238 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h"
void Dma_GetHwModuleStatus(Dma_ModuleStatusType * const StatusPtr);
# 250 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h"
void Dma_SetSourceAddr(const uint32 LogicChIndex, uint32 Address);
# 262 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h"
void Dma_SetDestAddr(const uint32 LogicChIndex, uint32 Address);
# 274 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h"
void Dma_GetVersionInfo(Std_VersionInfoType * const VersionInfo);
# 289 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h"
Std_ReturnType Dma_GetChannelTransferConfig(const uint32 LogicChIndex,
                                            const Dma_ChannelTransferConfigType * ChConfigPtr);
# 304 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h"
Std_ReturnType Dma_GetChannelGlobalParam(const uint32 LogicChIndex,
                                        Dma_ChannelGlobalConfigType * ChConfigPtr);


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section text = ""
# 309 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" 2
# 27 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c" 2
# 1 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h" 1
# 67 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section rodata = ".mcal_config_data"
# 68 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h" 2



extern const Dma_Drv_ConfigType * const Dma_Drv_ModuleCfgArrayPtr[((uint32)1U)]; extern const Dma_Drv_ChannelGlobalConfigType Dma_Drv_ChGlobalCfg0; extern const Dma_Drv_ChannelGlobalConfigType Dma_Drv_ChGlobalCfg1; extern const Dma_Drv_ChannelGlobalConfigType Dma_Drv_ChGlobalCfg2; extern const Dma_Drv_ChannelGlobalConfigType Dma_Drv_ChGlobalCfg3; extern const Dma_Drv_ChannelGlobalConfigType Dma_Drv_ChGlobalCfg4; extern const Dma_Drv_ChannelTransferConfigType Dma_Drv_ChTransferCfg0; extern const Dma_Drv_ChannelTransferConfigType Dma_Drv_ChTransferCfg1; extern const Dma_Drv_ChannelTransferConfigType Dma_Drv_ChTransferCfg2;


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section rodata = ""
# 75 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h" 2







# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section text = ".mcal_code"
# 83 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h" 2
# 97 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
Dma_Drv_ChannelType Dma_Drv_GetLastErrorChannel(uint16 ErrStateRegVal);
# 108 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_InitDoneIrqHandle(const Dma_Drv_ChannelType Channel, Dma_Drv_CallbackType MajorIntCallback);
# 120 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_HaltControl(Dma_Drv_HaltType Cmd);
# 130 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_EnableChannelRequest(Dma_Drv_ChannelType Channel);
# 140 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_DisableChannelRequest(Dma_Drv_ChannelType Channel);
# 154 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_ClearIntStatus(Dma_Drv_ChannelType Channel, Dma_Drv_IntType IntType);
# 165 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
boolean Dma_Drv_GetBusyStatus(void);
# 177 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
boolean Dma_Drv_GetHaltStatus(void);
# 189 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
boolean Dma_Drv_GetChannelErrorStatus(Dma_Drv_ChannelType Channel);
# 199 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
uint16 Dma_Drv_GetAllChannelsErrorStatus(void);
# 210 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetSourceAddr(Dma_Drv_ChannelType Channel, uint32 Address);
# 221 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetSourceTransferSize(Dma_Drv_ChannelType Channel,
                                                 Dma_Drv_TransferSizeType Size);
# 233 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetDestAddr(Dma_Drv_ChannelType Channel, uint32 Address);
# 244 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetMinorLoopSrcOffset(Dma_Drv_ChannelType Channel, sint16 Offset);
# 255 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetMinorLoopDestOffset(Dma_Drv_ChannelType Channel, sint16 Offset);
# 266 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetMajorLoopSrcOffset(Dma_Drv_ChannelType Channel, sint16 Offset);
# 277 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetMajorLoopDestOffset(Dma_Drv_ChannelType Channel, sint16 Offset);
# 288 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetMinorLoopNum(Dma_Drv_ChannelType Channel, uint16 Num);
# 298 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
uint16 Dma_Drv_GetRestMinorLoopNum(Dma_Drv_ChannelType Channel);
# 309 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetDestTransferSize(Dma_Drv_ChannelType Channel,
                                             Dma_Drv_TransferSizeType Size);
# 321 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetTransferByteNum(Dma_Drv_ChannelType Channel, uint32 Num);
# 334 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetDisableRequestAfterDone(Dma_Drv_ChannelType Channel, boolean Cmd);
# 344 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_TriggerChannelStart(Dma_Drv_ChannelType Channel);
# 356 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
boolean Dma_Drv_GetChannelBusyStatus(Dma_Drv_ChannelType Channel);
# 368 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
boolean Dma_Drv_GetDoneStatus(Dma_Drv_ChannelType Channel);
# 378 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_Init(const Dma_Drv_ConfigType * ModuleCfgPtr);
# 388 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_ClearDoneStatus(Dma_Drv_ChannelType Channel);
# 399 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetChannelTransferConfig(const Dma_Drv_ChannelType Channel,
                                     const Dma_Drv_ChannelTransferConfigType * ChTransCfgPtr);
# 411 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetChannelGlobalConfig(const Dma_Drv_ChannelType Channel,
                                     const Dma_Drv_ChannelGlobalConfigType * ChGlobalCfgPtr);
# 422 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
uint16 Dma_Drv_GetLastErrorStatus(void);
# 439 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_ControlInt(Dma_Drv_ChannelType Channel, Dma_Drv_IntType IntType,
                                    boolean Control);
# 450 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_ErrorIntHandler(void);
# 460 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_DoneIntHandler(Dma_Drv_ChannelType Channel);
# 470 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_InstallErrIntCallbackFunc(Dma_Drv_ErrIntCallbackType CbFunPtr);
# 481 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_GetChannelTransferConfig(Dma_Drv_ChannelType Channel,
                                    const Dma_Drv_ChannelTransferConfigType * ChTransCfgPtr);
# 493 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_GetChannelGlobalConfig(Dma_Drv_ChannelType Channel,
                                    Dma_Drv_ChannelGlobalConfigType * ChGlobalCfgPtr);


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section text = ""
# 498 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h" 2
# 28 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c" 2



# 1 "../../../mcal/Det_ZX_K14xM/Inc\\Det.h" 1
# 61 "../../../mcal/Det_ZX_K14xM/Inc\\Det.h"
void Det_Init(void);

Std_ReturnType Det_ReportError(uint16 ModuleId, uint8 InstanceId, uint8 ApiId, uint8 ErrorId);

Std_ReturnType Det_ReportRuntimeError(uint16 ModuleId, uint8 InstanceId, uint8 ApiId,
                                      uint8 ErrorId);

Std_ReturnType Det_ReportTransientFault(uint16 ModuleId, uint8 InstanceId, uint8 ApiId,
                                        uint8 FaultId);

void Det_Start(void);
# 32 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c" 2
# 99 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 1436 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section bss = ".mcal_bss"
# 100 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c" 2

static Dma_ChannelOptStateType Dma_ChannelStateArray[(((uint32)5U))];


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 1452 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section bss = ""
# 105 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c" 2


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 1408 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section bss = ".mcal_bss"
# 108 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c" 2





static const Dma_ConfigType *Dma_CfgPtr;


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 1424 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section bss = ""
# 117 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c" 2
# 141 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section text = ".mcal_code"
# 142 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c" 2


static inline Std_ReturnType Dma_CheckInit(const Dma_ConfigType * const CfgPtr);

static uint8 Dma_GetLogicChIndexOfPhyCh(const Dma_Drv_ChannelType PhysChId);
static void Dma_HandlePhysChannelErrInt(const Dma_Drv_ChannelType PhysChId);
static void Dma_HandlePhysChannelDoneInt(const Dma_Drv_ChannelType PhysChId);
static void Dma_UpdateErrorState(const uint32 LogicChIndex);


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section text = ""
# 153 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c" 2







# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section text = ".mcal_code"
# 161 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c" 2
# 172 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
static inline Std_ReturnType Dma_CheckInit(const Dma_ConfigType * const CfgPtr)
{
    Std_ReturnType Ret = (Std_ReturnType)0x00U;
    if (((void *)0) == Dma_CfgPtr)
    {
# 187 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
            if (((void *)0) != CfgPtr)
            {
                (void)Det_ReportError(2049U, 0,
                    ((uint8)0x00U), ((uint8)0x07U));
                Ret = 0x01U;
            }
            else
            {

            }

        }



    else
    {
        (void)Det_ReportError(2049U, 0,
            ((uint8)0x00U), ((uint8)0x07U));
        Ret = 0x01U;
    }

    return Ret;
}
# 223 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
static uint8 Dma_GetLogicChIndexOfPhyCh(const Dma_Drv_ChannelType PhysChId)
{
    uint8 LogicChIndex = 0xFF;
    uint8 Cnt = 0U;

    for(Cnt = 0U; Cnt < (((uint32)5U)); Cnt++)
    {
        if (Dma_CfgPtr->ChCfgArrayPtr[Cnt]->PhyChId == PhysChId)
        {
            LogicChIndex = Cnt;
            break;
        }
    }

    return LogicChIndex;
}
# 248 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
static void Dma_HandlePhysChannelErrInt(const Dma_Drv_ChannelType PhysChId)
{
    uint8 LogicChIndex;
    uint16 LastErrStatus;
    Dma_CallbackType ErrIntCallback;

    LogicChIndex = Dma_GetLogicChIndexOfPhyCh(PhysChId);
    if ((uint8)0xFF != LogicChIndex)
    {

        Dma_ChannelStateArray[LogicChIndex].ChState = DMA_CH_ERROR_STATE;
        LastErrStatus = Dma_Drv_GetLastErrorStatus();
        if (Dma_Drv_GetLastErrorChannel(LastErrStatus) == PhysChId)
        {

            Dma_ChannelStateArray[LogicChIndex].ChErrState = LastErrStatus;
        }

        ErrIntCallback = Dma_CfgPtr->ChCfgArrayPtr[LogicChIndex]->ErrIntCallback;

        if (ErrIntCallback != ((void *)0))
        {
            ErrIntCallback(LogicChIndex);
        }
    }
}
# 283 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
static void Dma_HandlePhysChannelDoneInt(const Dma_Drv_ChannelType PhysChId)
{
    uint8 LogicChIndex;
    Dma_CallbackType MajorIntCallback;

    LogicChIndex = Dma_GetLogicChIndexOfPhyCh(PhysChId);
    if ((uint8)0xFF != LogicChIndex)
    {
        MajorIntCallback = Dma_CfgPtr->ChCfgArrayPtr[LogicChIndex]->MajorIntCallback;

        if (MajorIntCallback != ((void *)0))
        {
            MajorIntCallback(LogicChIndex);
        }
    }
}
# 309 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
static void Dma_UpdateErrorState(const uint32 LogicChIndex)
{
    Dma_Drv_ChannelType PhysChId;
    uint16 LastErrStatus;


    if (1U != Dma_CfgPtr->ChCfgArrayPtr[LogicChIndex]->ChGlobalCfgPtr->ErrIntEn)
    {

        PhysChId = Dma_CfgPtr->ChCfgArrayPtr[LogicChIndex]->PhyChId;

        if (1U == Dma_Drv_GetChannelErrorStatus(PhysChId))
        {

            Dma_ChannelStateArray[LogicChIndex].ChState = DMA_CH_ERROR_STATE;
            LastErrStatus = Dma_Drv_GetLastErrorStatus();
            if (Dma_Drv_GetLastErrorChannel(LastErrStatus) == PhysChId)
            {
                Dma_ChannelStateArray[LogicChIndex].ChErrState = LastErrStatus;
            }
            else
            {
                Dma_ChannelStateArray[LogicChIndex].ChErrState = (0xFFFFU);
            }
        }
    }
}


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section text = ""
# 339 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c" 2







# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section text = ".mcal_code"
# 347 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c" 2
# 357 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
void Dma_Init(const Dma_ConfigType * const CfgPtr)
{
    uint8 LogicChIndex;
    Dma_Drv_ChannelType PhysChId;
    Dma_ChannelOptStateType * ChOptSta;
    const Dma_Drv_ChannelGlobalConfigType * ChGlobalCfg;
    const Dma_Drv_ChannelTransferConfigType * ChTransCfg;


    if (0x00U == Dma_CheckInit(CfgPtr))
    {



        Dma_CfgPtr = Dma_PreDefinedConfigPtr;
        (void)CfgPtr;




        Dma_Drv_Init(Dma_CfgPtr->ModuleCfgArrayPtr[0]);

        Dma_Drv_InstallErrIntCallbackFunc(Dma_HandlePhysChannelErrInt);


        for (LogicChIndex = 0U; LogicChIndex < (((uint32)5U)); LogicChIndex++)
        {
            ChOptSta = &Dma_ChannelStateArray[LogicChIndex];
            PhysChId = Dma_CfgPtr->ChCfgArrayPtr[LogicChIndex]->PhyChId;


            Dma_Drv_ClearIntStatus(PhysChId, DMA_DRV_INT_ALL);


            ChGlobalCfg = Dma_CfgPtr->ChCfgArrayPtr[LogicChIndex]->ChGlobalCfgPtr;
            Dma_Drv_SetChannelGlobalConfig(PhysChId, ChGlobalCfg);

            Dma_Drv_InitDoneIrqHandle(PhysChId, Dma_HandlePhysChannelDoneInt);

            ChTransCfg = Dma_CfgPtr->ChCfgArrayPtr[LogicChIndex]->ChTransferCfgPtr;
            if (((void *)0) != ChTransCfg)
            {
                Dma_Drv_SetChannelTransferConfig(PhysChId, ChTransCfg);
            }

            ChOptSta->ChErrState = 0U;
            ChOptSta->ChState = DMA_CH_READY_STATE;
        }

    }

}
# 433 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
void Dma_GetChannelStatus(const uint32 LogicChIndex,
                        Dma_ChannelStatusType * const StatusPtr)
{
    Dma_Drv_ChannelType PhysChId;

    boolean DetErrFlag = 0U;
    if ((((uint32)5U)) <= LogicChIndex)
    {
        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x01U), ((uint8)0x03U));
        DetErrFlag = 1U;
    }
    else
    {
        if (DMA_CH_UNINIT_STATE == Dma_ChannelStateArray[LogicChIndex].ChState)
        {
            (void)Det_ReportError(2049U, (uint8)0,
                ((uint8)0x01U), ((uint8)0x01U));
            DetErrFlag = 1U;
        }
        else
        {
            if (((void *)0) == StatusPtr)
            {
                (void)Det_ReportError(2049U, (uint8)0,
                    ((uint8)0x01U), ((uint8)0x02U));
                DetErrFlag = 1U;
            }
        }
    }
    if (0U == DetErrFlag)
    {

        PhysChId = Dma_CfgPtr->ChCfgArrayPtr[LogicChIndex]->PhyChId;

        Dma_UpdateErrorState(LogicChIndex);

        StatusPtr->Error = Dma_ChannelStateArray[LogicChIndex].ChErrState;
        StatusPtr->State = Dma_ChannelStateArray[LogicChIndex].ChState;
        StatusPtr->Busy = Dma_Drv_GetChannelBusyStatus(PhysChId);
        StatusPtr->Done = Dma_Drv_GetDoneStatus(PhysChId);

    }

}
# 490 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
void Dma_Halt(Dma_HaltType Cmd)
{
    if (Cmd > DMA_HALT_ON)
    {

        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x02U), ((uint8)0x04U));

    }
    else
    {
        Dma_Drv_HaltControl((Dma_Drv_HaltType)Cmd);
    }
}
# 517 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
Std_ReturnType Dma_ConfigChannelTransfer(const uint32 LogicChIndex,
                                         const Dma_ChannelTransferConfigType *ChConfigPtr)
{
    Std_ReturnType RetVal = (Std_ReturnType)0x00U;
    Dma_Drv_ChannelType PhysChId;


    if ((((uint32)5U)) <= LogicChIndex)
    {
        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x03U), ((uint8)0x03U));
        RetVal = (Std_ReturnType)0x01U;
    }
    else if (((void *)0) == ChConfigPtr)
    {
        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x03U), ((uint8)0x02U));
        RetVal = (Std_ReturnType)0x01U;
    }
    else if (DMA_CH_UNINIT_STATE == Dma_ChannelStateArray[LogicChIndex].ChState)
    {
        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x03U), ((uint8)0x01U));
        RetVal = (Std_ReturnType)0x01U;
    }
    else
    {

    }

    if ((Std_ReturnType)0x00U == RetVal)
    {
        Dma_UpdateErrorState(LogicChIndex);

        if (DMA_CH_READY_STATE == Dma_ChannelStateArray[LogicChIndex].ChState)
        {

            PhysChId = Dma_CfgPtr->ChCfgArrayPtr[LogicChIndex]->PhyChId;
            Dma_Drv_ClearIntStatus(PhysChId, DMA_DRV_INT_DONE);



            Dma_Drv_SetChannelTransferConfig(PhysChId,
                                            (const Dma_Drv_ChannelTransferConfigType *)ChConfigPtr);
        }
        else
        {
            RetVal = (Std_ReturnType)0x01U;

            (void)Det_ReportError(2049U, (uint8)0,
                ((uint8)0x03U), ((uint8)0x06U));

        }
    }

    return RetVal;
}
# 587 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
Std_ReturnType Dma_ConfigChannelGlobalParam(const uint32 LogicChIndex,
                                    const Dma_ChannelGlobalConfigType *ChConfigPtr)
{
    Std_ReturnType RetVal = (Std_ReturnType)0x00U;
    Dma_Drv_ChannelType PhysChId;

    if ((((uint32)5U)) <= LogicChIndex)
    {
        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x04U), ((uint8)0x03U));
        RetVal = (Std_ReturnType)0x01U;
    }
    else if (((void *)0) == ChConfigPtr)
    {
        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x04U), ((uint8)0x02U));
        RetVal = (Std_ReturnType)0x01U;
    }
    else if (DMA_CH_UNINIT_STATE == Dma_ChannelStateArray[LogicChIndex].ChState)
    {
        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x04U), ((uint8)0x01U));
        RetVal = (Std_ReturnType)0x01U;
    }
    else if (((void *)0) != ChConfigPtr->RequestConfig)
    {
        if (((boolean)1U == ChConfigPtr->RequestConfig->ReqEn)
            && (DMA_REQ_SOFTWARE == ChConfigPtr->RequestConfig->MuxReqSrc))
        {
            (void)Det_ReportError(2049U, (uint8)0,
                ((uint8)0x04U), ((uint8)0x05U));
            RetVal = (Std_ReturnType)0x01U;
        }
    }
    else
    {

    }

    if ((Std_ReturnType)0x00U == RetVal)
    {
        Dma_UpdateErrorState(LogicChIndex);

        if (DMA_CH_READY_STATE == Dma_ChannelStateArray[LogicChIndex].ChState)
        {

            PhysChId = Dma_CfgPtr->ChCfgArrayPtr[LogicChIndex]->PhyChId;



            Dma_Drv_SetChannelGlobalConfig(PhysChId,
                                        (const Dma_Drv_ChannelGlobalConfigType *)ChConfigPtr);
        }
        else
        {
            RetVal = (Std_ReturnType)0x01U;

            (void)Det_ReportError(2049U, (uint8)0,
                ((uint8)0x04U), ((uint8)0x06U));

        }
    }

    return RetVal;
}
# 663 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
void Dma_EnableChannelHwRequest(const uint32 LogicChIndex, boolean Enable)
{
    Dma_Drv_ChannelType PhysChId;

    boolean DetErrFlag = 0U;
    if ((((uint32)5U)) <= LogicChIndex)
    {
        (void)Det_ReportError(2049U, (uint8)0,
                        ((uint8)0x05U), ((uint8)0x03U));
        DetErrFlag = 1U;
    }
    else
    {
        if (DMA_CH_READY_STATE != Dma_ChannelStateArray[LogicChIndex].ChState)
        {
            (void)Det_ReportError(2049U, (uint8)0,
                ((uint8)0x05U), ((uint8)0x06U));
            DetErrFlag = 1U;
        }
        else
        {
            if (1U < Enable)
            {
                (void)Det_ReportError(2049U, (uint8)0,
                            ((uint8)0x05U), ((uint8)0x05U));
                DetErrFlag = 1U;
            }
        }
    }
    if (0U == DetErrFlag)
    {

        PhysChId = Dma_CfgPtr->ChCfgArrayPtr[LogicChIndex]->PhyChId;
        if (1U == Enable)
        {
            Dma_Drv_EnableChannelRequest(PhysChId);
        }
        else
        {
            Dma_Drv_DisableChannelRequest(PhysChId);
        }


    }

}
# 719 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
void Dma_TriggerChannelStartBySw(const uint32 LogicChIndex)
{

    boolean DetErrFlag = 0U;
    if ((((uint32)5U)) <= LogicChIndex)
    {
        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x06U), ((uint8)0x03U));
        DetErrFlag = 1U;
    }
    else
    {
        if (DMA_CH_READY_STATE != Dma_ChannelStateArray[LogicChIndex].ChState)
        {
            (void)Det_ReportError(2049U, (uint8)0,
                ((uint8)0x06U), ((uint8)0x06U));
            DetErrFlag = 1U;
        }
        else
        {

        }
    }
    if (0U == DetErrFlag)
    {

        Dma_Drv_ChannelType PhysChId = Dma_CfgPtr->ChCfgArrayPtr[LogicChIndex]->PhyChId;

        Dma_Drv_TriggerChannelStart(PhysChId);

    }

}
# 766 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
void Dma_ClearIntStatus(const uint32 LogicChIndex, Dma_IntType Int)
{
    Dma_Drv_ChannelType PhysChId;

    boolean DetErrFlag = 0U;
    if ((((uint32)5U)) <= LogicChIndex)
    {
        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x07U), ((uint8)0x03U));
        DetErrFlag = 1U;
    }
    else
    {
        if (DMA_CH_UNINIT_STATE == Dma_ChannelStateArray[LogicChIndex].ChState)
        {
            (void)Det_ReportError(2049U, (uint8)0,
                ((uint8)0x07U), ((uint8)0x01U));
            DetErrFlag = 1U;
        }
        else
        {
            if (DMA_INT_ALL < Int)
            {
                (void)Det_ReportError(2049U, (uint8)0,
                    ((uint8)0x07U), ((uint8)0x05U));
                DetErrFlag = 1U;
            }
        }
    }

    if (0U == DetErrFlag)
    {

        PhysChId = Dma_CfgPtr->ChCfgArrayPtr[LogicChIndex]->PhyChId;

        Dma_Drv_ClearIntStatus(PhysChId, (Dma_Drv_IntType)Int);
        if ((DMA_INT_ERROR == Int) && (DMA_CH_ERROR_STATE ==
            Dma_ChannelStateArray[LogicChIndex].ChState))
        {
            Dma_ChannelStateArray[LogicChIndex].ChState = DMA_CH_READY_STATE;
        }

    }

}
# 821 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
void Dma_GetHwModuleStatus(Dma_ModuleStatusType * const StatusPtr)
{

    boolean DetErrFlag = 0U;

    if (((void *)0) == StatusPtr)
    {
        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x08U), ((uint8)0x02U));
        DetErrFlag = 1U;
    }
    else
    {

    }

    if (0U == DetErrFlag)
    {

        StatusPtr->Busy = Dma_Drv_GetBusyStatus();
        StatusPtr->Halt = Dma_Drv_GetHaltStatus();
        StatusPtr->ChannelsErrStatus = Dma_Drv_GetAllChannelsErrorStatus();
        StatusPtr->LastErrChStatus = Dma_Drv_GetLastErrorStatus();


    }

}
# 860 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
void Dma_SetSourceAddr(const uint32 LogicChIndex, uint32 Address)
{
    Dma_Drv_ChannelType PhysChId;

    boolean DetErrFlag = 0U;
    if ((((uint32)5U)) <= LogicChIndex)
    {
        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x09U), ((uint8)0x03U));
        DetErrFlag = 1U;
    }
    else if (DMA_CH_UNINIT_STATE == Dma_ChannelStateArray[LogicChIndex].ChState)
    {
        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x09U), ((uint8)0x01U));
        DetErrFlag = 1U;
    }
    else
    {

    }
    if (0U == DetErrFlag)
    {


        PhysChId = Dma_CfgPtr->ChCfgArrayPtr[LogicChIndex]->PhyChId;

        Dma_Drv_SetSourceAddr(PhysChId, Address);

    }

}
# 903 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
void Dma_SetDestAddr(const uint32 LogicChIndex, uint32 Address)
{
    Dma_Drv_ChannelType PhysChId;

    boolean DetErrFlag = 0U;
    if ((((uint32)5U)) <= LogicChIndex)
    {
        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x0AU), ((uint8)0x03U));
        DetErrFlag = 1U;
    }
    else if (DMA_CH_UNINIT_STATE == Dma_ChannelStateArray[LogicChIndex].ChState)
    {
        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x0AU), ((uint8)0x01U));
        DetErrFlag = 1U;
    }
    else
    {

    }
    if (0U == DetErrFlag)
    {


        PhysChId = Dma_CfgPtr->ChCfgArrayPtr[LogicChIndex]->PhyChId;

        Dma_Drv_SetDestAddr(PhysChId, Address);

    }

}
# 946 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
void Dma_GetVersionInfo(Std_VersionInfoType * const VersionInfo)
{

    if (((void *)0) == VersionInfo)
    {
        (void)Det_ReportError((uint16)2049U, (uint8)0,
            ((uint8)0x0BU), ((uint8)0x02U));
    }
    else
    {

    VersionInfo->vendorID = (uint16)0x00B3U;
    VersionInfo->moduleID = (uint16)2049U;
    VersionInfo->sw_major_version = (uint8)1U;
    VersionInfo->sw_minor_version = (uint8)2U;
    VersionInfo->sw_patch_version = (uint8)0U;

    }

}
# 980 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
Std_ReturnType Dma_GetChannelTransferConfig(const uint32 LogicChIndex,
                                            const Dma_ChannelTransferConfigType * ChConfigPtr)
{
    Std_ReturnType RetVal = (Std_ReturnType)0x00U;
    Dma_Drv_ChannelType PhysChId;


    if ((((uint32)5U)) <= LogicChIndex)
    {
        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x0CU), ((uint8)0x03U));
        RetVal = (Std_ReturnType)0x01U;
    }
    else if (((void *)0) == ChConfigPtr)
    {
        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x0CU), ((uint8)0x02U));
        RetVal = (Std_ReturnType)0x01U;
    }
    else
    {

    }

    if ((Std_ReturnType)0x00U == RetVal)
    {

        PhysChId = Dma_CfgPtr->ChCfgArrayPtr[LogicChIndex]->PhyChId;



        Dma_Drv_GetChannelTransferConfig(PhysChId,
                                        (const Dma_Drv_ChannelTransferConfigType *)ChConfigPtr);
    }
    return RetVal;
}
# 1029 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c"
Std_ReturnType Dma_GetChannelGlobalParam(const uint32 LogicChIndex,
                                        Dma_ChannelGlobalConfigType * ChConfigPtr)
{
    Std_ReturnType RetVal = (Std_ReturnType)0x00U;
    Dma_Drv_ChannelType PhysChId;

    if ((((uint32)5U)) <= LogicChIndex)
    {
        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x0DU), ((uint8)0x03U));
        RetVal = (Std_ReturnType)0x01U;
    }
    else if (((void *)0) == ChConfigPtr)
    {
        (void)Det_ReportError(2049U, (uint8)0,
            ((uint8)0x0DU), ((uint8)0x02U));
        RetVal = (Std_ReturnType)0x01U;
    }
    else
    {

    }

    if ((Std_ReturnType)0x00U == RetVal)
    {

        PhysChId = Dma_CfgPtr->ChCfgArrayPtr[LogicChIndex]->PhyChId;



        Dma_Drv_GetChannelGlobalConfig(PhysChId,
                                    (Dma_Drv_ChannelGlobalConfigType *)ChConfigPtr);
    }

    return RetVal;
}


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section text = ""
# 1068 "../../../mcal/Dma_ZX_K14xM/Src/CDD_Dma.c" 2