# 1 "../Src/can_func.c" # 1 "" 1 # 1 "" 3 # 387 "" 3 # 1 "" 1 # 1 "" 2 # 1 "../Src/can_func.c" 2 # 1 "../Src/main.h" 1 # 1 "../Src/def.h" 1 # 7 "../Src/main.h" 2 # 1 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 1 # 30 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" # 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h" 1 # 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h" # 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 1 # 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" # 1 "../Generated/inc\\Mcu_Drvw_Cfg.h" 1 # 30 "../Generated/inc\\Mcu_Drvw_Cfg.h" # 1 "../Generated/inc/Mcu_Drvw_PBcfg.h" 1 # 31 "../Generated/inc\\Mcu_Drvw_Cfg.h" 2 # 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2 # 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Scc_Drv_Types.h" 1 # 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Scc_Drv_Types.h" # 1 "../Generated/inc\\Scc_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Scc_Drv_Cfg.h" # 1 "../Generated/inc/Scc_Drv_PBcfg.h" 1 # 65 "../Generated/inc/Scc_Drv_PBcfg.h" extern void FOSCClkLossCallbackFunc(void); # 31 "../Generated/inc\\Scc_Drv_Cfg.h" 2 # 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Scc_Drv_Types.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 1 # 30 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h" 1 # 86 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h" typedef unsigned char boolean; typedef unsigned char uint8; typedef unsigned short uint16; typedef unsigned int uint32; typedef unsigned long long uint64; typedef signed char sint8; typedef signed short sint16; typedef signed int sint32; typedef signed long long sint64; typedef unsigned long uint8_least; typedef unsigned long uint16_least; typedef unsigned long uint32_least; typedef signed long sint8_least; typedef signed long sint16_least; typedef signed long sint32_least; typedef float float32; typedef double float64; typedef void *VoidPtr; typedef const void *ConstVoidPtr; # 31 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 1 # 31 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler_Cfg.h" 1 # 32 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 2 # 32 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2 # 63 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" typedef unsigned char StatusType; # 104 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" typedef uint8 Std_ReturnType; typedef uint8 Std_TransformerClass; typedef uint8 Std_TransformerForwardCode; typedef uint8 Std_MessageTypeType; typedef uint8 Std_MessageResultType; typedef struct { uint16 vendorID; uint16 moduleID; uint8 sw_major_version; uint8 sw_minor_version; uint8 sw_patch_version; } Std_VersionInfoType; typedef struct { uint8 errorCode; Std_TransformerClass transformerClass; } Std_TransformerError; typedef struct { Std_TransformerForwardCode errorCode; Std_TransformerClass transformerClass; } Std_TransformerForward; typedef Std_ReturnType (*Std_ExtractProtocolHeaderFieldsType)(const uint8 *buffer, uint32 bufferLength, Std_MessageTypeType *messageType, Std_MessageResultType *messageResult); # 32 "../../../mcal/Mcu_ZX_K14xM/Inc/Scc_Drv_Types.h" 2 # 1 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 1 # 29 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" # 1 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 1 # 30 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" # 1 "../Generated/inc\\McalLib_Cfg.h" 1 # 31 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 2 # 273 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" static inline uint32 McalLib_ReadControlReg(void) { uint32 res; __asm("MRS %0,CONTROL" : "=r" (res)); return res; } # 290 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" static inline uint32 McalLib_ReadIpsrReg(void) { uint32 res; __asm("MRS %0,IPSR" : "=r" (res)); return res; } # 305 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" static inline uint32 McalLib_ReadPriMaskReg(void) { uint32 res; __asm("MRS %0,PRIMASK" : "=r" (res)); return res; } # 30 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 # 184 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" typedef enum { MCALLIB_COUNTER_SOFTWARE, MCALLIB_COUNTER_OS, } McalLib_CounterType; typedef struct { uint32 CounterId; uint32 CounterFreq; } McalLib_ConfigType; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 211 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 extern const McalLib_ConfigType *const McalLib_PreDefinedConfigPtr[(1U)]; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section rodata = "" # 216 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 # 230 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" extern void Sys_SystemReset(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section text = ".mcal_code" # 234 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 void McalLib_Init(void); # 254 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" Std_ReturnType McalLib_GetCounterValue(McalLib_CounterType Counter, uint32 *Value); # 270 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" Std_ReturnType McalLib_GetElapsedValue(McalLib_CounterType Counter, uint32 *const CounterValue, uint32 *ElapsedValue); # 282 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" uint32 McalLib_MicroSecToTicks(McalLib_CounterType Counter, uint32 MicroSecond); # 296 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" void McalLib_SetCounterFreq(McalLib_CounterType Counter, uint32 Freq); # 309 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" static inline void McalLib_Assert(const uint8 *File, uint32 Line) { (void)File; (void)Line; for (;;) { } } # 327 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" void McalLib_SuspendAllInterrupts(void); void McalLib_ResumeAllInterrupts(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" #pragma clang section text = "" # 339 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2 # 33 "../../../mcal/Mcu_ZX_K14xM/Inc/Scc_Drv_Types.h" 2 # 90 "../../../mcal/Mcu_ZX_K14xM/Inc/Scc_Drv_Types.h" typedef enum { SCC_DRV_CLOCK_SRC_NO = 0U, SCC_DRV_CLOCK_SRC_LPO32K, SCC_DRV_CLOCK_SRC_SOSC, SCC_DRV_CLOCK_SRC_FIRC64M, SCC_DRV_CLOCK_SRC_FOSC, SCC_DRV_CLOCK_SRC_PLL } Scc_Drv_ClockSrcType; typedef enum { SCC_DRV_SYS_CLOCK_FIRC64M = 1U, SCC_DRV_SYS_CLOCK_FOSC = 2U, SCC_DRV_SYS_CLOCK_PLL = 3U } Scc_Drv_SystemClockType; typedef enum { SCC_DRV_OSC_XTAL = 0U, SCC_DRV_OSC_EXT_SRC } Scc_Drv_OscModeType; typedef enum { SCC_DRV_FOSC_FREQ_MODE_LOW = 0U, SCC_DRV_FOSC_FREQ_MODE_HIGH } Scc_Drv_FOscFreqModeType; typedef enum { SCC_DRV_OSC_CLOCK_LOSS_INT = 0U, SCC_DRV_OSC_CLOCK_LOSS_RST } Scc_Drv_OscClockLossActType; typedef enum { SCC_DRV_FIRC64M_CLOCK_LOSS_INT = 0U, SCC_DRV_FIRC64M_CLOCK_LOSS_RST } Scc_Drv_Firc64MClockLossActType; # 167 "../../../mcal/Mcu_ZX_K14xM/Inc/Scc_Drv_Types.h" typedef enum { SCC_DRV_PLL_REF_FIRC64M = 0U, SCC_DRV_PLL_REF_FOSC } Scc_Drv_PllRefClockType; typedef enum { SCC_DRV_PLL_PRE_DIV_1 = 0U, SCC_DRV_PLL_PRE_DIV_2 = 1U, SCC_DRV_PLL_PRE_DIV_4 = 2U } Scc_Drv_PllPreDivType; typedef enum { SCC_DRV_PLL_POST_DIV_6 = 3U, SCC_DRV_PLL_POST_DIV_8 = 4U, SCC_DRV_PLL_POST_DIV_10 = 5U, SCC_DRV_PLL_POST_DIV_12 = 6U, SCC_DRV_PLL_POST_DIV_14 = 7U } Scc_Drv_PllPostDivType; typedef enum { SCC_DRV_PLL_SCALER_1 = 0U, SCC_DRV_PLL_SCALER_2 = 1U } Scc_Drv_PllPreScalerType; typedef enum { SCC_DRV_SYS_CLOCK_CORE = 0x85U, SCC_DRV_SYS_CLOCK_BUS = 0x86U, SCC_DRV_SYS_CLOCK_SLOW = 0x87U } Scc_Drv_SysClockType; typedef enum { SCC_DRV_SYS_CLOCK_DIV_1 = 0U, SCC_DRV_SYS_CLOCK_DIV_2, SCC_DRV_SYS_CLOCK_DIV_3, SCC_DRV_SYS_CLOCK_DIV_4, SCC_DRV_SYS_CLOCK_DIV_5, SCC_DRV_SYS_CLOCK_DIV_6, SCC_DRV_SYS_CLOCK_DIV_7, SCC_DRV_SYS_CLOCK_DIV_8, SCC_DRV_SYS_CLOCK_DIV_9, SCC_DRV_SYS_CLOCK_DIV_10, SCC_DRV_SYS_CLOCK_DIV_11, SCC_DRV_SYS_CLOCK_DIV_12, SCC_DRV_SYS_CLOCK_DIV_13, SCC_DRV_SYS_CLOCK_DIV_14, SCC_DRV_SYS_CLOCK_DIV_15, SCC_DRV_SYS_CLOCK_DIV_16 } Scc_Drv_SysClockDividerType; typedef struct { Scc_Drv_PllPreDivType PllPreDivider; Scc_Drv_PllPostDivType PllPostDivider; uint32 PllMultiplier; Scc_Drv_PllRefClockType PllRefClock; Scc_Drv_PllPreScalerType PllPreScaler; uint32 PllFreq; } Scc_Drv_PllParamConfigType; typedef struct { Scc_Drv_PllParamConfigType SccPllClockParamConfig; boolean SccPllEnableUnderStop; boolean Enable; } Scc_Drv_PllClockConfigType; typedef void (*Scc_Drv_LocCallbackFunc)(void); typedef struct { boolean Firc64MStopEn; boolean Enable; Scc_Drv_LocCallbackFunc Firc64MLocCallbackFunc; } Scc_Drv_Firc64MClockConfigType; typedef struct { Scc_Drv_FOscFreqModeType SccOscHfreq; boolean SccOscEnableUnderStop; Scc_Drv_OscModeType Mode; boolean Enable; Scc_Drv_LocCallbackFunc LocCallbackFunc; } Scc_Drv_FOscClockConfigType; typedef struct { Scc_Drv_OscModeType Mode; boolean Enable; } Scc_Drv_SOscClockConfigType; typedef struct { uint32 Enable; } Scc_Drv_LpoClockConfigType; typedef struct { Scc_Drv_SystemClockType SccSystemClockSource; uint32 SccSystemClockFreq; Scc_Drv_SysClockDividerType SccCoreClockDivider; Scc_Drv_SysClockDividerType SccBusClockDivider; Scc_Drv_SysClockDividerType SccSlowClockDivider; } Scc_Drv_SystemClockConfigType; typedef struct { Scc_Drv_SystemClockConfigType SccSystemClockConfig; Scc_Drv_Firc64MClockConfigType SccFircClockConfig; Scc_Drv_FOscClockConfigType SccFOscClockConfig; Scc_Drv_PllClockConfigType SccPllClockConfig; Scc_Drv_SOscClockConfigType SccSOscClockConfig; Scc_Drv_LpoClockConfigType SccLpoClockConfig; } Scc_Drv_ClockConfigType; # 32 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2 # 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Parcc_Drv_Types.h" 1 # 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Parcc_Drv_Types.h" # 1 "../Generated/inc\\Parcc_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Parcc_Drv_Cfg.h" # 1 "../Generated/inc/Parcc_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Parcc_Drv_Cfg.h" 2 # 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Parcc_Drv_Types.h" 2 # 91 "../../../mcal/Mcu_ZX_K14xM/Inc/Parcc_Drv_Types.h" typedef enum { PARCC_DRV_WDOG = 0x00U, PARCC_DRV_EWDT, PARCC_DRV_STIM, PARCC_DRV_TIM0, PARCC_DRV_TIM1, PARCC_DRV_TIM2, PARCC_DRV_TIM3, PARCC_DRV_MCPWM0, PARCC_DRV_MCPWM1, PARCC_DRV_TDG0, PARCC_DRV_TDG1, PARCC_DRV_CAN0, PARCC_DRV_CAN1, PARCC_DRV_CAN2, PARCC_DRV_CAN3, PARCC_DRV_CAN4, PARCC_DRV_CAN5, PARCC_DRV_CAN6, PARCC_DRV_CAN7, PARCC_DRV_UART0, PARCC_DRV_UART1, PARCC_DRV_UART2, PARCC_DRV_UART3, PARCC_DRV_UART4, PARCC_DRV_UART5, PARCC_DRV_SPI0, PARCC_DRV_SPI1, PARCC_DRV_SPI2, PARCC_DRV_SPI3, PARCC_DRV_I2C0, PARCC_DRV_I2C1, PARCC_DRV_I2S0, PARCC_DRV_I2S1, PARCC_DRV_RESERVED1, PARCC_DRV_ADC0, PARCC_DRV_ADC1, PARCC_DRV_CMP0, PARCC_DRV_CRC, PARCC_DRV_AES, PARCC_DRV_TRNG, PARCC_DRV_FLASH, PARCC_DRV_RESERVED2, PARCC_DRV_DMA, PARCC_DRV_DMAMUX, PARCC_DRV_PORTA, PARCC_DRV_PORTB, PARCC_DRV_PORTC, PARCC_DRV_PORTD, PARCC_DRV_PORTE, PARCC_DRV_TMU, PARCC_DRV_REGFILE, PARCC_DRV_SMPU, PARCC_DRV_GPIO } Parcc_Drv_ModuleType; typedef enum { PARCC_DRV_CLOCK_SRC_NO = 0U, PARCC_DRV_CLOCK_SRC_LPO32K = 1U, PARCC_DRV_CLOCK_SRC_SOSC = 2U, PARCC_DRV_CLOCK_SRC_FIRC64M = 3U, PARCC_DRV_CLOCK_SRC_FOSC = 4U, PARCC_DRV_CLOCK_SRC_PLL = 5U, PARCC_DRV_CLOCK_SRC_SLOW = 6U, PARCC_DRV_CLOCK_SRC_BUS = 7U, PARCC_DRV_CLOCK_SRC_CORE = 8U } Parcc_Drv_ClockSrcType; typedef enum { PARCC_DRV_CLOCK_DIV_1 = 0U, PARCC_DRV_CLOCK_DIV_2, PARCC_DRV_CLOCK_DIV_3, PARCC_DRV_CLOCK_DIV_4, PARCC_DRV_CLOCK_DIV_5, PARCC_DRV_CLOCK_DIV_6, PARCC_DRV_CLOCK_DIV_7, PARCC_DRV_CLOCK_DIV_8, PARCC_DRV_CLOCK_DIV_9, PARCC_DRV_CLOCK_DIV_10, PARCC_DRV_CLOCK_DIV_11, PARCC_DRV_CLOCK_DIV_12, PARCC_DRV_CLOCK_DIV_13, PARCC_DRV_CLOCK_DIV_14, PARCC_DRV_CLOCK_DIV_15, PARCC_DRV_CLOCK_DIV_16 } Parcc_Drv_ClockDividerType; typedef enum { PARCC_DRV_STATUS_OK = 0x00U, PARCC_DRV_STATUS_NOT_OK = 0x01U, PARCC_DRV_STATUS_UNDEFINED = 0x02U } Parcc_Drv_StatusType; typedef struct { Parcc_Drv_ModuleType ParccModule; Parcc_Drv_ClockSrcType ParccModuleSrc; Parcc_Drv_ClockDividerType ParccModuleDivider; boolean Enable; boolean SupervisorAccessEnable; boolean WriteLockEnable; } Parcc_Drv_ModuleConfigType; typedef struct { uint32 NumberOfModule; const Parcc_Drv_ModuleConfigType *SystemParccConfigPtr; } Parcc_Drv_SystemParccConfigType; # 33 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2 # 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Pmu_Drv_Types.h" 1 # 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Pmu_Drv_Types.h" # 1 "../Generated/inc\\Pmu_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Pmu_Drv_Cfg.h" # 1 "../Generated/inc/Pmu_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Pmu_Drv_Cfg.h" 2 # 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Pmu_Drv_Types.h" 2 # 90 "../../../mcal/Mcu_ZX_K14xM/Inc/Pmu_Drv_Types.h" typedef enum { PMU_DRV_VDD_LVD_LP = 0U, PMU_DRV_VDD_LVD_ACT = 1U, PMU_DRV_VDD_LVD_RE = 3U, PMU_DRV_VDD_LVW = 4U, PMU_DRV_REF_BUF_1V = 8U } Pmu_Drv_CtrlType; typedef enum { PMU_DRV_VDD_LVW_INT = 0U, PMU_DRV_VDD_LVD_INT } Pmu_Drv_IntType; typedef void (*Pmu_Drv_CallbackFunc)(void); typedef struct { boolean PmuCtrlLVDLowPowerEnable; boolean PmuCtrlLVDActiveEnable; boolean PmuCtrlLVDResetEnable; boolean PmuCtrlLVWEnable; boolean PmuCtrlRef1VEnable; boolean PmuLVDInterruptEnable; Pmu_Drv_CallbackFunc PmuLVDInterruptCallbackFunc; boolean PmuLVWInterruptEnable; Pmu_Drv_CallbackFunc PmuLVWInterruptCallbackFunc; } Pmu_Drv_ConfigType; # 34 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2 # 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Scm_Mcu_Drv_Types.h" 1 # 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Scm_Mcu_Drv_Types.h" # 1 "../Generated/inc\\Scm_Mcu_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Scm_Mcu_Drv_Cfg.h" # 1 "../Generated/inc/Scm_Mcu_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Scm_Mcu_Drv_Cfg.h" 2 # 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Scm_Mcu_Drv_Types.h" 2 # 93 "../../../mcal/Mcu_ZX_K14xM/Inc/Scm_Mcu_Drv_Types.h" typedef enum { SCM_MCU_DRV_CLOCK_OUT_DIV_1 = 0U, SCM_MCU_DRV_CLOCK_OUT_DIV_2 = 1U, SCM_MCU_DRV_CLOCK_OUT_DIV_4 = 2U, SCM_MCU_DRV_CLOCK_OUT_DIV_8 = 3U } Scm_Mcu_Drv_ClockOutDivType; typedef enum { SCM_MCU_DRV_CLOCK_OUT_DISABLED = 0U, SCM_MCU_DRV_CLOCK_OUT_FIRC64M = 1U, SCM_MCU_DRV_CLOCK_OUT_FOSC = 2U, SCM_MCU_DRV_CLOCK_OUT_PLL = 3U, SCM_MCU_DRV_CLOCK_OUT_SLOW = 8U, SCM_MCU_DRV_CLOCK_OUT_BUS = 9U, SCM_MCU_DRV_CLOCK_OUT_CORE = 10U, SCM_MCU_DRV_CLOCK_OUT_SOSC = 11U, SCM_MCU_DRV_CLOCK_OUT_LPO32K = 12U } Scm_Mcu_Drv_ClockOutSrcType; typedef enum { SCM_MCU_DRV_SRAML = 0U, SCM_MCU_DRV_SRAMU = 1U } Scm_Mcu_Drv_SramType; typedef enum { SCM_MCU_DRV_TIM0 = 3U, SCM_MCU_DRV_TIM1 = 4U, SCM_MCU_DRV_TIM2 = 5U, SCM_MCU_DRV_TIM3 = 6U, SCM_MCU_DRV_MCPWM0 = 7U, SCM_MCU_DRV_MCPWM1 = 8U } Scm_Mcu_Drv_TimerType; typedef enum { SCM_MCU_DRV_TCLK0 = 0U, SCM_MCU_DRV_TCLK1 = 1U, SCM_MCU_DRV_TCLK2 = 2U } Scm_Mcu_Drv_TimerExtClockInputType; typedef enum { SCM_MCU_DRV_ADC1CH15 = 0U, SCM_MCU_DRV_ADC1CH14 = 1U, SCM_MCU_DRV_ADC0CH9 = 2U, SCM_MCU_DRV_ADC0CH8 = 3U } Scm_Mcu_Drv_AdcChannelSelectType; typedef enum { SCM_MCU_DRV_ADCMUX0 = 0U, SCM_MCU_DRV_ADCMUX1 = 1U } Scm_Mcu_Drv_AdcMuxSelectType; typedef enum { SCM_MCU_DRV_CCACHE_BE_INT = 0U, SCM_MCU_DRV_FPU_INEXACT_INT = 1U, SCM_MCU_DRV_FPU_OVERFLOW_INT = 2U, SCM_MCU_DRV_FPU_UNDERFLOW_INT = 3U, SCM_MCU_DRV_FPU_INVALIDOP_INT = 4U, SCM_MCU_DRV_FPU_DIVZERO_INT = 5U, SCM_MCU_DRV_FPU_DENORMALIN_INT = 6U } Scm_Mcu_Drv_IntType; typedef struct { Scm_Mcu_Drv_ClockOutSrcType ScmClockOutputSrc; Scm_Mcu_Drv_ClockOutDivType ScmClockOutputDivider; boolean Enable; } Scm_Mcu_Drv_ClockOutputConfigType; typedef struct { Scm_Mcu_Drv_ClockOutputConfigType ScmClockOutputConfig; } Scm_Mcu_Drv_ClockConfigType; typedef struct { boolean CacheBEInterruptEnable; boolean FpuInExactInterruptEnable; boolean FpuOverflowInterruptEnable; boolean FpuUnderflowInterruptEnable; boolean FpuInvalidOPInterruptEnable; boolean FpuDivzeroInterruptEnable; boolean FpuDenormalInterruptEnable; boolean SramLReadBufferEnable; boolean SramUReadBufferEnable; boolean CacheEnable; boolean CacheParityFaultEnable; boolean CacheParityMissEnable; Scm_Mcu_Drv_TimerExtClockInputType Mcpwm0Select; Scm_Mcu_Drv_TimerExtClockInputType Mcpwm1Select; Scm_Mcu_Drv_TimerExtClockInputType Tim0Select; Scm_Mcu_Drv_TimerExtClockInputType Tim1Select; Scm_Mcu_Drv_TimerExtClockInputType Tim2Select; Scm_Mcu_Drv_TimerExtClockInputType Tim3Select; Scm_Mcu_Drv_AdcMuxSelectType Adc0Ch8Select; Scm_Mcu_Drv_AdcMuxSelectType Adc0Ch9Select; Scm_Mcu_Drv_AdcMuxSelectType Adc1Ch14Select; Scm_Mcu_Drv_AdcMuxSelectType Adc1Ch15Select; } Scm_Mcu_Drv_ConfigType; # 35 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2 # 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Srmc_Drv_Types.h" 1 # 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Srmc_Drv_Types.h" # 1 "../Generated/inc\\Srmc_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Srmc_Drv_Cfg.h" # 1 "../Generated/inc/Srmc_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Srmc_Drv_Cfg.h" 2 # 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Srmc_Drv_Types.h" 2 # 119 "../../../mcal/Mcu_ZX_K14xM/Inc/Srmc_Drv_Types.h" typedef enum { SRMC_DRV_RESET_PIN_DISABLE_FILTER = 0U, SRMC_DRV_RESET_PIN_BUS_CLOCK_FILTER, SRMC_DRV_RESET_PIN_LPO_CLOCK_FILTER } Srmc_Drv_ResetPinFilterType; typedef enum { SRMC_DRV_DELAY_8_LPO_CYCLES = 0U, SRMC_DRV_DELAY_32_LPO_CYCLES, SRMC_DRV_DELAY_128_LPO_CYCLES, SRMC_DRV_DELAY_512_LPO_CYCLES } Srmc_Drv_DelayType; typedef enum { SRMC_DRV_MODE_RUN = 0U, SRMC_DRV_MODE_WAIT, SRMC_DRV_MODE_STOP, SRMC_DRV_MODE_STANDBY } Srmc_Drv_PowerModeType; typedef enum { SRMC_DRV_WUPSRC_PTD0 = 0x0U, SRMC_DRV_WUPSRC_PTD1 = 0x1U, SRMC_DRV_WUPSRC_PTA4 = 0x2U, SRMC_DRV_WUPSRC_PTC4 = 0x4U, SRMC_DRV_WUPSRC_PTC5 = 0x5U, SRMC_DRV_WUPSRC_PTE0 = 0x6U, SRMC_DRV_WUPSRC_PTE1 = 0x7U, SRMC_DRV_WUPSRC_PTE11 = 0x8U, SRMC_DRV_WUPSRC_PTE13 = 0x9U, SRMC_DRV_WUPSRC_PTE15 = 0xAU, SRMC_DRV_WUPSRC_PTE16 = 0xBU, SRMC_DRV_WUPSRC_PTA8 = 0xCU, SRMC_DRV_WUPSRC_PTA9 = 0xDU, SRMC_DRV_WUPSRC_PTA25 = 0xEU, SRMC_DRV_WUPSRC_PMU = 0xFU, SRMC_DRV_WUPSRC_RTC = 0x10U } Srmc_Drv_WakeupSourceType; typedef enum { SRMC_DRV_WUPSRC_POLARITY_LOW = 0x0U, SRMC_DRV_WUPSRC_POLARITY_HIGH = 0x1U } Srmc_Drv_WupPolarityType; # 298 "../../../mcal/Mcu_ZX_K14xM/Inc/Srmc_Drv_Types.h" typedef struct { Srmc_Drv_ResetPinFilterType ResetPinFilterInNormal; Srmc_Drv_ResetPinFilterType ResetPinFilterInStop; uint32 ResetPinFilterBusClock; boolean CoreLockupResetEnable; Srmc_Drv_DelayType ResetDelayTime; uint32 ResetInterruptEnable; } Srmc_Drv_ResetConfigType; typedef struct { boolean AllowStandbyMode; uint32 StopModeAckTimeout; uint32 WakeupControl1; uint32 WakeupControl2; } Srmc_Drv_PowerModeConfigType; # 36 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2 # 1 "../../../mcal/Mcu_ZX_K14xM/Inc/Ram_Drv_Types.h" 1 # 30 "../../../mcal/Mcu_ZX_K14xM/Inc/Ram_Drv_Types.h" # 1 "../Generated/inc\\Ram_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Ram_Drv_Cfg.h" # 1 "../Generated/inc/Ram_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Ram_Drv_Cfg.h" 2 # 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Ram_Drv_Types.h" 2 # 90 "../../../mcal/Mcu_ZX_K14xM/Inc/Ram_Drv_Types.h" typedef enum { RAM_DRV_STATUS_OK = 0x00U, RAM_DRV_STATUS_NOT_OK = 0x01U, RAM_DRV_STATUS_UNDEFINED = 0x02U } Ram_Drv_StatusType; typedef uint32 Ram_Drv_SectorSizeType; typedef uint32 Ram_Drv_WriteSizeType; typedef uint32 Ram_Drv_IndexType; typedef struct { uint32 RamBaseAddr; uint32 RamSize; uint64 RamDefaultValue; uint32 RamWriteSize; } Ram_Drv_ConfigType; # 37 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" 2 # 202 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" typedef enum { MCU_DRVW_OSC_CLOCK_LOSS_INT = 0U, MCU_DRVW_OSC_CLOCK_LOSS_RST } Mcu_Drvw_OscClockLossActType; typedef enum { MCU_DRVW_FIRC64M_CLOCK_LOSS_INT = 0U, MCU_DRVW_FIRC64M_CLOCK_LOSS_RST } Mcu_Drvw_Firc64MClockLossActType; typedef enum { MCU_DRVW_WUPSRC_PTD0 = 0x0U, MCU_DRVW_WUPSRC_PTD1 = 0x1U, MCU_DRVW_WUPSRC_PTA4 = 0x2U, MCU_DRVW_WUPSRC_PTC4 = 0x4U, MCU_DRVW_WUPSRC_PTC5 = 0x5U, MCU_DRVW_WUPSRC_PTE0 = 0x6U, MCU_DRVW_WUPSRC_PTE1 = 0x7U, MCU_DRVW_WUPSRC_PTE11 = 0x8U, MCU_DRVW_WUPSRC_PTE13 = 0x9U, MCU_DRVW_WUPSRC_PTE15 = 0xAU, MCU_DRVW_WUPSRC_PTE16 = 0xBU, MCU_DRVW_WUPSRC_PTA8 = 0xCU, MCU_DRVW_WUPSRC_PTA9 = 0xDU, MCU_DRVW_WUPSRC_PTA25 = 0xEU, MCU_DRVW_WUPSRC_PMU = 0xFU, MCU_DRVW_WUPSRC_RTC = 0x10U } Mcu_Drvw_WakeupSourceType; typedef enum { MCU_DRVW_CLOCK_SRC_NO = 0U, MCU_DRVW_CLOCK_SRC_LPO32K = 1U, MCU_DRVW_CLOCK_SRC_SOSC = 2U, MCU_DRVW_CLOCK_SRC_FIRC64M = 3U, MCU_DRVW_CLOCK_SRC_FOSC = 4U, MCU_DRVW_CLOCK_SRC_PLL = 5U } Mcu_Drvw_ClockSrcType; # 271 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" typedef enum { MCU_DRVW_WAKEUP_RESET = 0U, MCU_DRVW_LVD_RESET = 1U, MCU_DRVW_LOC_RESET = 2U, MCU_DRVW_WATCHDOG_RESET = 5U, MCU_DRVW_PIN_RESET = 6U, MCU_DRVW_POWER_ON_RESET = 7U, MCU_DRVW_LOCKUP_RESET = 9U, MCU_DRVW_SW_RESET = 10U, MCU_DRVW_MDM_AP_RESET = 11U, MCU_DRVW_SERU_COLD_RESET = 12U, MCU_DRVW_SERU_SYS_RESET = 13U, MCU_DRVW_SERU_SACKERR = 15U, MCU_DRVW_MULTIPLE_RESET_REASON = 0x55U, MCU_DRVW_RESET_UNDEFINED = 0xFFU } Mcu_Drvw_ResetType; typedef enum { MCU_DRVW_POWERMODE_RUN = 0U, MCU_DRVW_POWERMODE_WAIT, MCU_DRVW_POWERMODE_STOP, MCU_DRVW_POWERMODE_STANDBY } Mcu_Drvw_PowerModeType; typedef struct { const Scc_Drv_ClockConfigType *SccClockConfigPtr; const Scm_Mcu_Drv_ClockConfigType *ScmClockConfigPtr; const Parcc_Drv_SystemParccConfigType *ParccConfigPtr; } Mcu_Drvw_ClockConfigType; # 320 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Drvw_Types.h" typedef struct { const Srmc_Drv_ResetConfigType *SrmcResetConfigPtr; const Srmc_Drv_PowerModeConfigType *SrmcPowerModeConfigPtr; const Scm_Mcu_Drv_ConfigType *ScmConfigPtr; const Pmu_Drv_ConfigType *PmuConfigPtr; } Mcu_Drvw_HwConfigType; # 31 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h" 2 # 1 "../Generated/inc\\Mcu_Cfg.h" 1 # 30 "../Generated/inc\\Mcu_Cfg.h" # 1 "../Generated/inc/Mcu_PBcfg.h" 1 # 31 "../Generated/inc\\Mcu_Cfg.h" 2 # 32 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h" 2 # 94 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h" typedef enum { MCU_POWER_ON_RESET = 0x00U, MCU_WATCHDOG_RESET, MCU_SW_RESET, MCU_RESET_UNDEFINED, MCU_WAKEUP_RESET, MCU_LVD_RESET, MCU_LOC_RESET, MCU_PIN_RESET, MCU_LOCKUP_RESET, MCU_MDM_AP_RESET, MCU_SERU_COLD_RESET, MCU_SERU_SYS_RESET, MCU_SERU_SACKERR, MCU_HW_TEST_RESET, MCU_MULTIPLE_RESET_REASON } Mcu_ResetType; # 128 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h" typedef enum { MCU_OSC_CLOCK_LOSS_INT = 0U, MCU_OSC_CLOCK_LOSS_RST } Mcu_OscClockLossActType; typedef enum { MCU_FIRC64M_CLOCK_LOSS_INT = 0U, MCU_FIRC64M_CLOCK_LOSS_RST } Mcu_Firc64MClockLossActType; # 157 "../../../mcal/Mcu_ZX_K14xM/Inc/Mcu_Types.h" typedef enum { MCU_WUPSRC_PTD0 = 0x0U, MCU_WUPSRC_PTD1 = 0x1U, MCU_WUPSRC_PTA4 = 0x2U, MCU_WUPSRC_PTC4 = 0x4U, MCU_WUPSRC_PTC5 = 0x5U, MCU_WUPSRC_PTE0 = 0x6U, MCU_WUPSRC_PTE1 = 0x7U, MCU_WUPSRC_PTE11 = 0x8U, MCU_WUPSRC_PTE13 = 0x9U, MCU_WUPSRC_PTE15 = 0xAU, MCU_WUPSRC_PTE16 = 0xBU, MCU_WUPSRC_PTA8 = 0xCU, MCU_WUPSRC_PTA9 = 0xDU, MCU_WUPSRC_PTA25 = 0xEU, MCU_WUPSRC_PMU = 0xFU, MCU_WUPSRC_RTC = 0x10U } Mcu_WakeupSourceType; typedef enum { MCU_PLL_LOCKED = 0U, MCU_PLL_UNLOCKED = 1U, MCU_PLL_STATUS_UNDEFINED = 2U } Mcu_PllStatusType; typedef enum { MCU_POWERMODE_RUN = 0U, MCU_POWERMODE_WAIT, MCU_POWERMODE_STOP, MCU_POWERMODE_STANDBY } Mcu_PowerModeType; typedef uint32 Mcu_RamSectionType; typedef uint32 Mcu_ModeType; typedef uint32 Mcu_ClockType; typedef uint32 Mcu_RawResetType; typedef struct { Mcu_RamSectionType RamSectorId; uint32 RamBaseAddr; uint32 RamSize; uint64 RamDefaultValue; uint32 RamWriteSize; } Mcu_RamConfigType; typedef struct { Mcu_ModeType ModeConfigId; Mcu_PowerModeType PowerMode; } Mcu_ModeConfigType; typedef struct { Mcu_ClockType ClockConfigId; const Mcu_Drvw_ClockConfigType *ClockConfigPtr; } Mcu_ClockConfigType; typedef struct { Mcu_RamSectionType NoOfRamConfigs; Mcu_ModeType NoOfModeConfigs; Mcu_ClockType NoOfClkConfigs; const Mcu_ModeConfigType (*ModeConfigPtr)[((uint32)1U)]; const Mcu_ClockConfigType (*ClockConfigPtr)[((uint32)1U)]; const Mcu_Drvw_HwConfigType *HwConfigPtr; } Mcu_ConfigType; # 31 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2 # 124 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" 1 # 848 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 125 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2 extern const Mcu_ConfigType *const Mcu_PreDefinedConfigPtr; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" 1 # 864 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" #pragma clang section rodata = "" # 128 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2 # 139 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 140 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" #pragma clang section rodata = "" # 143 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" #pragma clang section text = ".mcal_code" # 152 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2 # 161 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" void Mcu_Init(const Mcu_ConfigType *ConfigPtr); # 173 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" Std_ReturnType Mcu_InitRamSection(Mcu_RamSectionType RamSection); # 186 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" Std_ReturnType Mcu_InitClock(Mcu_ClockType ClockSetting); # 200 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" Std_ReturnType Mcu_DistributePllClock(void); # 214 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" Mcu_PllStatusType Mcu_GetPllStatus(void); # 224 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" Mcu_ResetType Mcu_GetResetReason(void); # 234 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" Mcu_RawResetType Mcu_GetResetRawValue(void); # 245 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" void Mcu_PerformReset(void); # 256 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" void Mcu_SetMode(Mcu_ModeType McuMode); # 267 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" void Mcu_GetVersionInfo(Std_VersionInfoType *versioninfo); # 291 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" Mcu_PowerModeType Mcu_GetPowerModeState(void); # 304 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" boolean Mcu_EnableOscClockMonitor(Mcu_OscClockLossActType Act); # 314 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" void Mcu_DisableOscClockMonitor(void); # 326 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" boolean Mcu_EnableFircClockMonitor(Mcu_Firc64MClockLossActType Act); # 336 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" void Mcu_DisableFircClockMonitor(void); # 360 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" void Mcu_SetWakeupSource(Mcu_WakeupSourceType WakeupSource, boolean ActiveHigh, boolean Enable); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Mcu_MemMap.h" #pragma clang section text = "" # 364 "../../../mcal/Mcu_ZX_K14xM/Inc\\Mcu.h" 2 # 10 "../Src/main.h" 2 # 1 "../../../mcal/Port_ZX_K14xM/Inc\\Port.h" 1 # 29 "../../../mcal/Port_ZX_K14xM/Inc\\Port.h" # 1 "../../../mcal/Port_ZX_K14xM/Inc/Port_Types.h" 1 # 29 "../../../mcal/Port_ZX_K14xM/Inc/Port_Types.h" # 1 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drvw_Types.h" 1 # 30 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drvw_Types.h" # 1 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drv_Types.h" 1 # 31 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drv_Types.h" # 1 "../Generated/inc\\Port_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Port_Drv_Cfg.h" # 1 "../Generated/inc/Port_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Port_Drv_Cfg.h" 2 # 68 "../Generated/inc\\Port_Drv_Cfg.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 69 "../Generated/inc\\Port_Drv_Cfg.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section rodata = "" # 78 "../Generated/inc\\Port_Drv_Cfg.h" 2 # 32 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drv_Types.h" 2 # 77 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drv_Types.h" typedef enum { PORT_DRV_PULL_DISABLED = 0U, PORT_DRV_PULL_DOWN = 2U, PORT_DRV_PULL_UP = 3U, } Port_Drv_PullConfigType; typedef enum { PORT_DRV_PIN_MODE_ALT0 = 0U, PORT_DRV_PIN_MODE_GPIO = 1U, PORT_DRV_PIN_MODE_ALT2 = 2U, PORT_DRV_PIN_MODE_ALT3 = 3U, PORT_DRV_PIN_MODE_ALT4 = 4U, PORT_DRV_PIN_MODE_ALT5 = 5U, PORT_DRV_PIN_MODE_ALT6 = 6U, PORT_DRV_PIN_MODE_ALT7 = 7U } Port_Drv_PortMuxType; typedef enum { PORT_DRV_PIN_IN = 0U, PORT_DRV_PIN_OUT = 1U, } Port_Drv_DirectionType; typedef enum { PORT_DRV_PORT_A = 0U, PORT_DRV_PORT_B, PORT_DRV_PORT_C, PORT_DRV_PORT_D, PORT_DRV_PORT_E } Port_Drv_PortIdType; typedef enum { PORT_DRV_FAST_RATE = 0U, PORT_DRV_SLOW_RATE } Port_Drv_SlewRateType; typedef enum { PORT_DRV_LEVEL_LOW = 0U, PORT_DRV_LEVEL_HIGH } Port_Drv_GpioLvlType; typedef enum { PORT_DRV_GPIO_0 = 0U, PORT_DRV_GPIO_1, PORT_DRV_GPIO_2, PORT_DRV_GPIO_3, PORT_DRV_GPIO_4, PORT_DRV_GPIO_5, PORT_DRV_GPIO_6, PORT_DRV_GPIO_7, PORT_DRV_GPIO_8, PORT_DRV_GPIO_9, PORT_DRV_GPIO_10, PORT_DRV_GPIO_11, PORT_DRV_GPIO_12, PORT_DRV_GPIO_13, PORT_DRV_GPIO_14, PORT_DRV_GPIO_15, PORT_DRV_GPIO_16, PORT_DRV_GPIO_17, PORT_DRV_GPIO_18, PORT_DRV_GPIO_19, PORT_DRV_GPIO_20, PORT_DRV_GPIO_21, PORT_DRV_GPIO_22, PORT_DRV_GPIO_23, PORT_DRV_GPIO_24, PORT_DRV_GPIO_25, PORT_DRV_GPIO_26, PORT_DRV_GPIO_27, PORT_DRV_GPIO_28, PORT_DRV_GPIO_29, PORT_DRV_GPIO_30, PORT_DRV_GPIO_31 } Port_Drv_GpioNoType; typedef struct { Port_Drv_PortIdType PortId; Port_Drv_GpioNoType GpioNo; Port_Drv_PullConfigType PullConfig; Port_Drv_PortMuxType PinMode; Port_Drv_DirectionType Direction; Port_Drv_SlewRateType SlewRate; boolean PassiveFilter; boolean FilterEnable; uint8 FilterConfig; boolean OpenDrainConfig; Port_Drv_GpioLvlType InitValue; } Port_Drv_ConfigType; # 31 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drvw_Types.h" 2 # 1 "../Generated/inc\\Port_Drvw_Cfg.h" 1 # 31 "../Generated/inc\\Port_Drvw_Cfg.h" # 1 "../Generated/inc/Port_Drvw_PBcfg.h" 1 # 32 "../Generated/inc\\Port_Drvw_Cfg.h" 2 # 82 "../Generated/inc\\Port_Drvw_Cfg.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 83 "../Generated/inc\\Port_Drvw_Cfg.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section rodata = "" # 89 "../Generated/inc\\Port_Drvw_Cfg.h" 2 # 32 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drvw_Types.h" 2 # 77 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drvw_Types.h" typedef uint32 Port_Drvw_PinType; typedef uint8 Port_Drvw_PinModeType; # 97 "../../../mcal/Port_ZX_K14xM/Inc/Port_Drvw_Types.h" typedef enum { PORT_DRVW_PORT_A = 0U, PORT_DRVW_PORT_B, PORT_DRVW_PORT_C, PORT_DRVW_PORT_D, PORT_DRVW_PORT_E } Port_Drvw_PortIdType; typedef enum { PORT_DRVW_GPIO_0 = 0U, PORT_DRVW_GPIO_1, PORT_DRVW_GPIO_2, PORT_DRVW_GPIO_3, PORT_DRVW_GPIO_4, PORT_DRVW_GPIO_5, PORT_DRVW_GPIO_6, PORT_DRVW_GPIO_7, PORT_DRVW_GPIO_8, PORT_DRVW_GPIO_9, PORT_DRVW_GPIO_10, PORT_DRVW_GPIO_11, PORT_DRVW_GPIO_12, PORT_DRVW_GPIO_13, PORT_DRVW_GPIO_14, PORT_DRVW_GPIO_15, PORT_DRVW_GPIO_16, PORT_DRVW_GPIO_17, PORT_DRVW_GPIO_18, PORT_DRVW_GPIO_19, PORT_DRVW_GPIO_20, PORT_DRVW_GPIO_21, PORT_DRVW_GPIO_22, PORT_DRVW_GPIO_23, PORT_DRVW_GPIO_24, PORT_DRVW_GPIO_25, PORT_DRVW_GPIO_26, PORT_DRVW_GPIO_27, PORT_DRVW_GPIO_28, PORT_DRVW_GPIO_29, PORT_DRVW_GPIO_30, PORT_DRVW_GPIO_31 } Port_Drvw_GpioNoType; typedef enum { PORT_DRVW_PIN_IN = 0U, PORT_DRVW_PIN_OUT, } Port_Drvw_DirectionType; typedef enum { PORT_DRVW_LEVEL_LOW = 0U, PORT_DRVW_LEVEL_HIGH } Port_Drvw_GpioLvlType; typedef enum { PORT_DRVW_FAST_RATE = 0U, PORT_DRVW_SLOW_RATE } Port_Drvw_SlewRateType; typedef enum { PORT_DRVW_PULL_DISABLED = 0U, PORT_DRVW_PULL_DOWN = 2U, PORT_DRVW_PULL_UP = 3U, } Port_Drvw_PullConfigType; typedef struct { Port_Drvw_DirectionType PinDirection; uint8 PinOutputLevel; Port_Drvw_SlewRateType PinSlewRate; Port_Drvw_PullConfigType PinPullConfig; } Port_Drvw_UnconfigPinAttrType; typedef struct { uint16 Pin; uint8 PinOutputLevel; Port_Drvw_DirectionType PinDirection; boolean GPIO; boolean DirectionChangebility; boolean ModeChangebility; } Port_Drvw_ConfigPinAttrType; typedef struct { uint16 NumConfigPins; uint16 NumUnconfigPins; const uint16 *UnconfigPinList; const Port_Drvw_UnconfigPinAttrType *UnconfigPinConfigAttr; const Port_Drvw_ConfigPinAttrType *ConfigPinAttr; const Port_Drv_ConfigType *DrvConfigPtr; } Port_Drvw_ConfigType; # 30 "../../../mcal/Port_ZX_K14xM/Inc/Port_Types.h" 2 # 1 "../Generated/inc\\Port_Cfg.h" 1 # 29 "../Generated/inc\\Port_Cfg.h" # 1 "../Generated/inc/Port_PBcfg.h" 1 # 30 "../Generated/inc\\Port_Cfg.h" 2 # 31 "../../../mcal/Port_ZX_K14xM/Inc/Port_Types.h" 2 # 77 "../../../mcal/Port_ZX_K14xM/Inc/Port_Types.h" typedef uint32 Port_PinType; typedef uint8 Port_PinModeType; # 103 "../../../mcal/Port_ZX_K14xM/Inc/Port_Types.h" typedef enum { PORT_PIN_IN = 0U, PORT_PIN_OUT, } Port_PinDirectionType; typedef struct { uint16 Pin; uint8 PinOutputLevel; Port_PinDirectionType PinDirection; boolean GPIO; boolean DirectionChangebility; boolean ModeChangebility; } Port_PinConfigType; typedef struct { uint16 NumConfigPins; const uint32 *Port_PinsPartitionTable; const uint8 *Port_PartitionTable; const Port_Drvw_ConfigType *DrvwConfigPtr; } Port_ConfigType; # 30 "../../../mcal/Port_ZX_K14xM/Inc\\Port.h" 2 # 101 "../../../mcal/Port_ZX_K14xM/Inc\\Port.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 848 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 102 "../../../mcal/Port_ZX_K14xM/Inc\\Port.h" 2 extern const Port_ConfigType *const Port_PreDefinedConfigPtr[1]; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 864 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section rodata = "" # 105 "../../../mcal/Port_ZX_K14xM/Inc\\Port.h" 2 # 122 "../../../mcal/Port_ZX_K14xM/Inc\\Port.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section text = ".mcal_code" # 123 "../../../mcal/Port_ZX_K14xM/Inc\\Port.h" 2 # 132 "../../../mcal/Port_ZX_K14xM/Inc\\Port.h" void Port_Init(const Port_ConfigType *ConfigPtr); # 143 "../../../mcal/Port_ZX_K14xM/Inc\\Port.h" void Port_SetPinDirection(Port_PinType Pin, Port_PinDirectionType Direction); # 155 "../../../mcal/Port_ZX_K14xM/Inc\\Port.h" void Port_SetPinMode(Port_PinType Pin, Port_PinModeType Mode); # 166 "../../../mcal/Port_ZX_K14xM/Inc\\Port.h" void Port_GetVersionInfo(Std_VersionInfoType *versioninfo); # 176 "../../../mcal/Port_ZX_K14xM/Inc\\Port.h" void Port_RefreshPortDirection(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Port_MemMap.h" #pragma clang section text = "" # 180 "../../../mcal/Port_ZX_K14xM/Inc\\Port.h" 2 # 11 "../Src/main.h" 2 # 1 "../../../mcal/Dio_ZX_K14xM/Inc\\Dio.h" 1 # 28 "../../../mcal/Dio_ZX_K14xM/Inc\\Dio.h" # 1 "../../../mcal/Dio_ZX_K14xM/Inc/Dio_Types.h" 1 # 28 "../../../mcal/Dio_ZX_K14xM/Inc/Dio_Types.h" # 1 "../../../mcal/Dio_ZX_K14xM/Inc/Dio_Drvw_Types.h" 1 # 28 "../../../mcal/Dio_ZX_K14xM/Inc/Dio_Drvw_Types.h" # 1 "../../../mcal/Dio_ZX_K14xM/Inc/Gpio_Drv_Types.h" 1 # 69 "../../../mcal/Dio_ZX_K14xM/Inc/Gpio_Drv_Types.h" typedef uint32 Gpio_Drv_PinsChannelType; typedef uint8 Gpio_Drv_PinsLevelType; # 29 "../../../mcal/Dio_ZX_K14xM/Inc/Dio_Drvw_Types.h" 2 # 1 "../Generated/inc\\Dio_Drvw_Cfg.h" 1 # 30 "../../../mcal/Dio_ZX_K14xM/Inc/Dio_Drvw_Types.h" 2 # 88 "../../../mcal/Dio_ZX_K14xM/Inc/Dio_Drvw_Types.h" typedef uint8 Dio_Drvw_PortType; typedef uint16 Dio_Drvw_ChannelType; typedef uint32 Dio_Drvw_PortLevelType; typedef uint8 Dio_Drvw_LevelType; typedef struct { Dio_Drvw_PortType PortId; uint8 BitOffset; Dio_Drvw_PortLevelType GroupMask; } Dio_Drvw_ChannelGroupType; typedef struct { uint8 ChannelGroupNum; const Dio_Drvw_ChannelGroupType *ChannelGroupListPtr; const uint32 *ChannelPartitionMapPtr; const uint32 *PortPartitionMapPtr; } Dio_Drvw_ConfigType; # 29 "../../../mcal/Dio_ZX_K14xM/Inc/Dio_Types.h" 2 # 1 "../Generated/inc\\Dio_Cfg.h" 1 # 30 "../../../mcal/Dio_ZX_K14xM/Inc/Dio_Types.h" 2 # 86 "../../../mcal/Dio_ZX_K14xM/Inc/Dio_Types.h" typedef Dio_Drvw_PortType Dio_PortType; typedef Dio_Drvw_ChannelType Dio_ChannelType; typedef Dio_Drvw_PortLevelType Dio_PortLevelType; typedef Dio_Drvw_LevelType Dio_LevelType; typedef Dio_Drvw_ChannelGroupType Dio_ChannelGroupType; typedef Dio_Drvw_ConfigType Dio_ConfigType; # 127 "../../../mcal/Dio_ZX_K14xM/Inc/Dio_Types.h" typedef uint32 Dio_PointerSizeType; # 29 "../../../mcal/Dio_ZX_K14xM/Inc\\Dio.h" 2 # 96 "../../../mcal/Dio_ZX_K14xM/Inc\\Dio.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dio_MemMap.h" 1 # 848 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dio_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 97 "../../../mcal/Dio_ZX_K14xM/Inc\\Dio.h" 2 extern const Dio_ConfigType *const Dio_PreDefinedConfigPtr; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dio_MemMap.h" 1 # 864 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dio_MemMap.h" #pragma clang section rodata = "" # 100 "../../../mcal/Dio_ZX_K14xM/Inc\\Dio.h" 2 extern const Dio_PortLevelType Dio_AvailablePinsForWrite[((uint16)0x5U)];extern const Dio_PortLevelType Dio_AvailablePinsForRead[((uint16)0x5U)]; # 112 "../../../mcal/Dio_ZX_K14xM/Inc\\Dio.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dio_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dio_MemMap.h" #pragma clang section text = ".mcal_code" # 113 "../../../mcal/Dio_ZX_K14xM/Inc\\Dio.h" 2 # 122 "../../../mcal/Dio_ZX_K14xM/Inc\\Dio.h" void Dio_GetVersionInfo(Std_VersionInfoType *VersionInfo); # 141 "../../../mcal/Dio_ZX_K14xM/Inc\\Dio.h" Dio_LevelType Dio_FlipChannel(Dio_ChannelType ChannelId); # 156 "../../../mcal/Dio_ZX_K14xM/Inc\\Dio.h" void Dio_MaskedWritePort(Dio_PortType PortId, Dio_PortLevelType Level, Dio_PortLevelType Mask); # 170 "../../../mcal/Dio_ZX_K14xM/Inc\\Dio.h" Dio_LevelType Dio_ReadChannel(Dio_ChannelType ChannelId); # 182 "../../../mcal/Dio_ZX_K14xM/Inc\\Dio.h" Dio_PortLevelType Dio_ReadPort(Dio_PortType PortId); # 193 "../../../mcal/Dio_ZX_K14xM/Inc\\Dio.h" Dio_PortLevelType Dio_ReadChannelGroup(const Dio_ChannelGroupType *ChannelGroupIdPtr); # 203 "../../../mcal/Dio_ZX_K14xM/Inc\\Dio.h" void Dio_WriteChannel(Dio_ChannelType ChannelId, Dio_LevelType Level); # 215 "../../../mcal/Dio_ZX_K14xM/Inc\\Dio.h" void Dio_WritePort(Dio_PortType PortId, Dio_PortLevelType Level); # 228 "../../../mcal/Dio_ZX_K14xM/Inc\\Dio.h" void Dio_WriteChannelGroup(const Dio_ChannelGroupType *ChannelGroupIdPtr, Dio_PortLevelType Level); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dio_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dio_MemMap.h" #pragma clang section text = "" # 235 "../../../mcal/Dio_ZX_K14xM/Inc\\Dio.h" 2 # 12 "../Src/main.h" 2 # 1 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" 1 # 29 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" # 1 "../../../mcal/Can_ZX_K14xM/Inc/Can_Types.h" 1 # 29 "../../../mcal/Can_ZX_K14xM/Inc/Can_Types.h" # 1 "../../../mcal/Can_ZX_K14xM/Inc/Can_Drv_Types.h" 1 # 30 "../../../mcal/Can_ZX_K14xM/Inc/Can_Drv_Types.h" # 1 "../Generated/inc\\Can_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Can_Drv_Cfg.h" # 1 "../Generated/inc/Can_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Can_Drv_Cfg.h" 2 # 31 "../../../mcal/Can_ZX_K14xM/Inc/Can_Drv_Types.h" 2 # 165 "../../../mcal/Can_ZX_K14xM/Inc/Can_Drv_Types.h" typedef enum { CAN_DRV_SUCCESS = 0U, CAN_DRV_ERROR, CAN_DRV_ENTER_BUSY, CAN_DRV_NO_TRANSMIT } Can_Drv_ControllerStatus; typedef enum { CAN_DRV_ID_0 = 0U, CAN_DRV_ID_1 = 1U, CAN_DRV_ID_2 = 2U, CAN_DRV_ID_3 = 3U, CAN_DRV_ID_4 = 4U, CAN_DRV_ID_5 = 5U, CAN_DRV_ID_6 = 6U, CAN_DRV_ID_7 = 7U } Can_Drv_IdType; typedef enum { CAN_DRV_CAN_FD_MB_REGION_0 = 0U, CAN_DRV_CAN_FD_MB_REGION_1, CAN_DRV_CAN_FD_MB_REGION_2, CAN_DRV_CAN_FD_MB_REGION_3 } Can_Drv_FdMbRegionType; typedef enum { CAN_DRV_RX_FIFO_ACCEPTANCE_FORMAT_A = 0U, CAN_DRV_RX_FIFO_ACCEPTANCE_FORMAT_B, CAN_DRV_RX_FIFO_ACCEPTANCE_FORMAT_C, CAN_DRV_RX_FIFO_ACCEPTANCE_FORMAT_D } Can_Drv_RxAcceptanceType; typedef enum { CAN_DRV_RX_FIFO_FILTERS_8 = 0x0U, CAN_DRV_RX_FIFO_FILTERS_16 = 0x1U, CAN_DRV_RX_FIFO_FILTERS_24 = 0x2U, CAN_DRV_RX_FIFO_FILTERS_32 = 0x3U, CAN_DRV_RX_FIFO_FILTERS_40 = 0x4U, CAN_DRV_RX_FIFO_FILTERS_48 = 0x5U, CAN_DRV_RX_FIFO_FILTERS_56 = 0x6U, CAN_DRV_RX_FIFO_FILTERS_64 = 0x7U, CAN_DRV_RX_FIFO_FILTERS_72 = 0x8U, CAN_DRV_RX_FIFO_FILTERS_80 = 0x9U, CAN_DRV_RX_FIFO_FILTERS_88 = 0xAU, CAN_DRV_RX_FIFO_FILTERS_96 = 0xBU, CAN_DRV_RX_FIFO_FILTERS_104 = 0xCU, CAN_DRV_RX_FIFO_FILTERS_112 = 0xDU, CAN_DRV_RX_FIFO_FILTERS_120 = 0xEU, CAN_DRV_RX_FIFO_FILTERS_128 = 0xFU } Can_Drv_RxFifoFilterNumType; typedef enum { CAN_DRV_RXFIFO_INTERRUPTS = 0U, CAN_DRV_RXFIFO_DMA, CAN_DRV_RXFIFO_POLLING } Can_Drv_RxFifoTransferType; typedef enum { CAN_DRV_OBJECT_PL_8 = 0U, CAN_DRV_OBJECT_PL_16, CAN_DRV_OBJECT_PL_32, CAN_DRV_OBJECT_PL_64 } Can_Drv_FdPayloadLengthType; typedef struct { Can_Drv_FdPayloadLengthType Block0; Can_Drv_FdPayloadLengthType Block1; Can_Drv_FdPayloadLengthType Block2; Can_Drv_FdPayloadLengthType Block3; } Can_Drv_FdPayloadBlockType; typedef enum { CAN_DRV_MODE_NORMAL = 0U, CAN_DRV_MODE_LISTEN_ONLY, CAN_DRV_MODE_LOOPBACK, CAN_DRV_MODE_FREEZE, CAN_DRV_MODE_DISABLE } Can_Drv_ModeType; typedef enum { CAN_DRV_MSG_ID_STD = 0U, CAN_DRV_MSG_ID_EXT } Can_Drv_MsgIdType; typedef enum { CAN_DRV_RX_MASK_GLOBAL = 0U, CAN_DRV_RX_MASK_INDIVIDUAL } Can_Drv_RxMaskType; typedef enum { CAN_DRV_MB_RX_INACTIVE = 0x0, CAN_DRV_MB_RX_FULL = 0x2, CAN_DRV_MB_RX_EMPTY = 0x4, CAN_DRV_MB_RX_OVERRUN = 0x6, CAN_DRV_MB_RX_RANSWER = 0xA, CAN_DRV_MB_TX_INACTIVE = 0x08, CAN_DRV_MB_TX_ABORT = 0x09, CAN_DRV_MB_TX_DATA_REMOTE = 0x0C, CAN_DRV_MB_TX_TANSWER = 0x0E, CAN_DRV_NOT_USED = 0x0F } Can_Drv_MbCodeType; typedef enum { CAN_DRV_INT_BUS_OFF = 0U, CAN_DRV_INT_ERR = 1U, CAN_DRV_INT_TXW = 2U, CAN_DRV_INT_RXW = 3U, CAN_DRV_INT_BUS_OFF_DONE = 4U, CAN_DRV_INT_ERR_FAST = 5U, CAN_DRV_INT_SELF_WAKEUP = 6U, CAN_DRV_INT_RXFIFO_FRAME = 7U, CAN_DRV_INT_RXFIFO_WARNING = 8U, CAN_DRV_INT_RXFIFO_OVERFLOW = 9U, CAN_DRV_INT_HOST_MEM_ERR = 10U, CAN_DRV_INT_MEM_ERR = 11U, CAN_DRV_INT_COR_MEM_ERR = 12U, CAN_DRV_INT_PN_WAKEUP_MATCH = 13U, CAN_DRV_INT_PN_WAKEUP_TIMEOUT = 14U, CAN_DRV_INT_MB_RECEIVE = 15U, CAN_DRV_MB_TRANSMIT = 16U, CAN_DRV_DMA_COMPLETE = 17U, CAN_DRV_DMA_ERROR = 18U, CAN_DRV_INT_ALL = 19U } Can_Drv_IntType; typedef enum { CAN_DRV_STATE_NOT_SYNC = 0U, CAN_DRV_STATE_IDLE = 1U, CAN_DRV_STATE_TX = 2U, CAN_DRV_STATE_RX = 3U, CAN_DRV_STATE_DMA_ERROR = 4U, CAN_DRV_STATE_INVALID = 5U } Can_Drv_ControllerStateType; typedef struct { uint32 PropSeg; uint32 PhaseSeg1; uint32 PhaseSeg2; uint32 PreDivider; uint32 RJumpWidth; } Can_Drv_BitTimingType; typedef struct { boolean IsRemoteFrame; boolean IsExtendedFrame; uint32 Id; } Can_Drv_IdFilterType; typedef struct { Can_Drv_MsgIdType IdType; uint8 DataLen; boolean RemoteFlag; boolean FdEn; uint8 FdPadding; boolean BrsEn; } Can_Drv_MessageInfoType; typedef struct { uint32 Cs; uint32 MsgId; uint8 Data[64]; uint8 DataLen; uint32 TimeStamp; } Can_Drv_MsgBufType; typedef struct { Can_Drv_MsgBufType *MbMessagePtr; boolean IsPolling; boolean RemoteFlag; uint32 TimeStamp; Can_Drv_ControllerStateType State; volatile boolean IsDmaBusy; } Can_Drv_MbHandleType; typedef struct Can_Drv_State { Can_Drv_MbHandleType Mb[(64)]; Can_Drv_RxFifoTransferType TransferType; boolean RxFifoEn; boolean InterEn; uint32 MaxMbNumber; void (*IrqCallback)(uint8 Id, Can_Drv_IntType InterType, uint32 MbIdx, const struct Can_Drv_State *State); void (*ErrCallback)(uint8 Id, Can_Drv_IntType InterType, uint32 Data); uint8 RxFifoDMAChannel; } Can_Drv_StateType; typedef struct { uint32 MbMaxNum; boolean RxFifoEn; Can_Drv_RxFifoFilterNumType RxFifoIdFilterNum; Can_Drv_RxFifoTransferType TransferType; Can_Drv_ModeType Mode; boolean BitRateSwitch; Can_Drv_BitTimingType BitTiming; boolean FdEn; Can_Drv_FdPayloadBlockType Payload; Can_Drv_BitTimingType BitTimingFdData; uint32 CtrlConfig; uint8 RxFifoDMAChannel; void (*IrqCallback)(uint8 Id, Can_Drv_IntType InterType, uint32 MbIdx, const struct Can_Drv_State *State); void (*ErrCallback)(uint8 Id, Can_Drv_IntType InterType, uint32 Data); } Can_Drv_ConfigType; # 30 "../../../mcal/Can_ZX_K14xM/Inc/Can_Types.h" 2 # 1 "../Generated/inc\\Can_Cfg.h" 1 # 29 "../Generated/inc\\Can_Cfg.h" # 1 "../Generated/inc/Can_PBcfg.h" 1 # 30 "../Generated/inc\\Can_Cfg.h" 2 # 306 "../Generated/inc\\Can_Cfg.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" #pragma clang section text = ".mcal_code" # 307 "../Generated/inc\\Can_Cfg.h" 2 extern void Can1_MemNotify(void); extern void Can1_CorrMemNotify(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" #pragma clang section text = "" # 316 "../Generated/inc\\Can_Cfg.h" 2 # 31 "../../../mcal/Can_ZX_K14xM/Inc/Can_Types.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc\\Can_GeneralTypes.h" 1 # 28 "../../../mcal/Base_ZX_K14xM/Inc\\Can_GeneralTypes.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/ComStack_Types.h" 1 # 53 "../../../mcal/Base_ZX_K14xM/Inc/ComStack_Types.h" typedef uint32 PduLengthType; typedef uint16 PduIdType; typedef struct { uint8 *SduDataPtr; uint8 *MetaDataPtr; PduLengthType SduLength; } PduInfoType; typedef uint8 IcomConfigIdType; typedef enum { ICOM_SWITCH_E_OK = 0U, ICOM_SWITCH_E_FAILED, } IcomSwitch_ErrorType; # 29 "../../../mcal/Base_ZX_K14xM/Inc\\Can_GeneralTypes.h" 2 # 61 "../../../mcal/Base_ZX_K14xM/Inc\\Can_GeneralTypes.h" typedef uint32 Can_IdType; # 75 "../../../mcal/Base_ZX_K14xM/Inc\\Can_GeneralTypes.h" typedef uint8 Can_HwHandleType; typedef enum { CAN_ERRORSTATE_ACTIVE = 0U, CAN_ERRORSTATE_PASSIVE, CAN_ERRORSTATE_BUSOFF } Can_ErrorStateType; typedef enum { CAN_CS_UNINIT = 0x00U, CAN_CS_STARTED = 0x01U, CAN_CS_STOPPED = 0x02U, CAN_CS_SLEEP = 0x03U } Can_ControllerStateType; typedef enum { CAN_ERROR_BIT_MONITORING1 = 0x01U, CAN_ERROR_BIT_MONITORING0 = 0x02U, CAN_ERROR_BIT = 0x03U, CAN_ERROR_CHECK_ACK_FAILED = 0x04U, CAN_ERROR_ACK_DELIMITER = 0x05U, CAN_ERROR_ARBITRATION_LOST = 0x06U, CAN_ERROR_OVERLOAD = 0x07U, CAN_ERROR_CHECK_FORM_FAILED = 0x08U, CAN_ERROR_CHECK_STUFFING_FAILED = 0x09U, CAN_ERROR_CHECK_CRC_FAILED = 0x0AU, CAN_ERROR_BUS_LOCK = 0x0BU, } Can_ErrorType; typedef struct { PduIdType swPduHandle; uint8 length; Can_IdType id; uint8 *sdu; } Can_PduType; typedef struct { Can_IdType CanId; Can_HwHandleType Hoh; uint8 ControllerId; } Can_HwType; # 32 "../../../mcal/Can_ZX_K14xM/Inc/Can_Types.h" 2 # 152 "../../../mcal/Can_ZX_K14xM/Inc/Can_Types.h" typedef enum { CAN_UNINIT = 0U, CAN_READY } Can_DriverStateType; typedef enum { CAN_BASIC = 0U, CAN_FULL } Can_HandleType; typedef enum { CAN_MSG_ID_STANDARD = 0U, CAN_MSG_ID_EXTENDED, CAN_MSG_ID_MIXED } Can_MessageIdType; typedef enum { CAN_OBJ_RECEIVE = 0U, CAN_OBJ_TRANSMIT, CAN_OBJ_FIFO } Can_HwObjectType; typedef enum { CAN_RX_FIFO_FORMAT_A = 0U, CAN_RX_FIFO_FORMAT_B, CAN_RX_FIFO_FORMAT_C, } Can_RxAcceptanceType; typedef struct { uint32 CanHwFilterCode; uint32 CanHwFilterMask; } Can_HardwareFilterType; typedef struct { const uint8 CanFdPaddingValue; const Can_HandleType CanHandleType; const Can_MessageIdType CanIdMessageType; const Can_HwHandleType CanHwObjectId; const boolean CanHwUsesPolling; const boolean CanTriggerTransmitStatus; const uint8 CanMainFunctionRwPeriodIndex; const uint8 CanHwObjectCount; const uint8 CanPayloadLength; const uint8 CanHwFilterCount; const Can_HardwareFilterType *CanHwFilterPtr; const Can_HwObjectType CanObjectType; const uint8 CanHwBufferIndex; } Can_HwObjConfigType; typedef void (*Can_NotifyFuncType)(void); typedef struct { const Can_RxAcceptanceType CanRxFifoType; const uint32 CanRxFifoGlobalFilterMask; const Can_NotifyFuncType CanOverFlowNotify; const Can_NotifyFuncType CanWarnNotify; const Can_NotifyFuncType CanAvailNotify; } Can_RxFifoConfigType; typedef struct { const uint8 CanPropSeg; const uint8 CanPhaseSeg1; const uint8 CanPhaseSeg2; const uint16 CanPreDivider; const uint8 CanRJumpWidth; } Can_BitTimingType; typedef struct { const uint8 CanControlTxArbitrationStartDelay; const Can_BitTimingType CanBitRate; const boolean CanFdEnable; const Can_BitTimingType CanFdDataBitRate; const boolean CanBitRateSwitch; const boolean CanTransmitCompEnable; const uint8 CanControllerSspOffset; } Can_ControllerBaudrateConfigType; typedef struct { const Can_Drv_ConfigType *CanHwConfigPtr; } Can_HwChannelConfigType; typedef struct { const uint8 CanControllerId; const uint8 CanInterfaceId; const uint8 CanControllerOffset; const boolean CanActiveStatus; const Can_RxFifoConfigType *CanRxFifoConfigPtr; const uint32 CanProcessConfig; const boolean CanErrEnable; const Can_NotifyFuncType CanErrNotify; const Can_NotifyFuncType CanFdErrNotify; const uint16 CanDefaultBaudrateIndex; const uint16 CanBaudrateCount; const Can_ControllerBaudrateConfigType *CanBaudratePtr; const uint8 CanHwObjectRefCount; const Can_HwObjConfigType *const *CanHwObjectPPtr; const Can_HwChannelConfigType *CanHwChannelConfigPtr; const Can_NotifyFuncType CanDmaErrorNotify; Can_Drv_MsgBufType *DmaDstAddr; const uint32 CanEccEnable; const Can_NotifyFuncType CanHostAccessNotify; const Can_NotifyFuncType CanAccessMemoryNotify; const Can_NotifyFuncType CanCorrectableMemoryNotify; const boolean CanErrInjectEnable; } Can_ControllerConfigType; typedef struct { const uint32 CanCoreId; const Can_HwHandleType CanFirstHTHIndex; const uint32 CanControllerCounter; const uint8 *CanControllerIndexPtr; const uint32 CanHardwareCounter; const uint8 *CanHwObjIndexPtr; const Can_HwObjConfigType *CanHwObjConfigPtr; const Can_ControllerConfigType *const *CanControllerConfigPtr; } Can_ConfigType; # 30 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" 2 # 74 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1 # 848 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 75 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" 2 extern const Can_ConfigType *const Can_PreDefinedConfigPtr[1U]; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1 # 864 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" #pragma clang section rodata = "" # 78 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" 2 # 98 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" #pragma clang section text = ".mcal_code" # 99 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" 2 extern void Can1_ErrNotifyFunc(void); extern void Can1_HostMemNotify(void); # 110 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" void Can_Init(const Can_ConfigType *Config); # 120 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" void Can_DeInit(void); # 147 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" void Can_GetVersionInfo(Std_VersionInfoType *versioninfo); # 162 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" Std_ReturnType Can_SetControllerMode(uint8 Controller, Can_ControllerStateType Transition); # 172 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" void Can_DisableControllerInterrupts(uint8 Controller); # 182 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" void Can_EnableControllerInterrupts(uint8 Controller); # 210 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" Std_ReturnType Can_GetControllerErrorState(uint8 Controller, Can_ErrorStateType *ErrorStatePtr); # 224 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" Std_ReturnType Can_GetControllerRxErrorCounter(uint8 Controller, uint8 *RxErrorCounterPtr); # 238 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" Std_ReturnType Can_GetControllerTxErrorCounter(uint8 Controller, uint8 *TxErrorCounterPtr); # 252 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" Std_ReturnType Can_GetControllerMode(uint8 Controller, Can_ControllerStateType *ControllerModePtr); # 267 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" Std_ReturnType Can_Write(Can_HwHandleType Hth, const Can_PduType *PduInfo); # 278 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" void Can_AbortHwObjectSend(Can_HwHandleType Hth); # 292 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" void Can_ProcessMbCommonInterrupt(uint8 Id, uint8 MbIdx, Can_HwObjectType Type); # 305 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" void Can_ProcessRxFiFoDmaInterrupt(uint8 Id, Can_Drv_IntType IntType); # 328 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" void Can_ProcessBusOffInterrupt(uint8 Id); # 341 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" void Can_ProcessErrorInterrupt(uint8 CtrlOffset, boolean IsErrFast, uint32 Data); # 355 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" void Can_ProcessEccInterrupt(uint8 CtrlOffset, uint32 IntType, uint32 Data); # 368 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" Std_ReturnType Can_InjectError(uint8 ControllerId); # 380 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" Std_ReturnType Can_ClearInjectError(uint8 ControllerId); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" #pragma clang section text = "" # 388 "../../../mcal/Can_ZX_K14xM/Inc\\Can.h" 2 # 13 "../Src/main.h" 2 # 1 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" 1 # 30 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" # 1 "../../../mcal/Gpt_ZX_K14xM/Inc/Gpt_Types.h" 1 # 29 "../../../mcal/Gpt_ZX_K14xM/Inc/Gpt_Types.h" # 1 "../../../mcal/Gpt_ZX_K14xM/Inc/Gpt_Drvw_Types.h" 1 # 29 "../../../mcal/Gpt_ZX_K14xM/Inc/Gpt_Drvw_Types.h" # 1 "../Generated/inc\\Gpt_Drvw_Cfg.h" 1 # 29 "../Generated/inc\\Gpt_Drvw_Cfg.h" # 1 "../Generated/inc/Gpt_Drvw_PBcfg.h" 1 # 30 "../Generated/inc\\Gpt_Drvw_Cfg.h" 2 # 30 "../../../mcal/Gpt_ZX_K14xM/Inc/Gpt_Drvw_Types.h" 2 # 1 "../../../mcal/Gpt_ZX_K14xM/Inc/Rtc_Drv_Types.h" 1 # 31 "../../../mcal/Gpt_ZX_K14xM/Inc/Rtc_Drv_Types.h" # 1 "../Generated/inc\\Rtc_Drv_Cfg.h" 1 # 28 "../Generated/inc\\Rtc_Drv_Cfg.h" # 1 "../Generated/inc/Rtc_Drv_PBcfg.h" 1 # 29 "../Generated/inc\\Rtc_Drv_Cfg.h" 2 # 32 "../../../mcal/Gpt_ZX_K14xM/Inc/Rtc_Drv_Types.h" 2 # 104 "../../../mcal/Gpt_ZX_K14xM/Inc/Rtc_Drv_Types.h" typedef void (*Rtc_Drv_CallbackType)(uint8 CallbackParam); typedef enum { RTC_DRV_SECONDS = 0U, RTC_DRV_32K_CLK } Rtc_Drv_ClockOutType; typedef enum { RTC_DRV_CLK_OSC32K_INT = 0U, RTC_DRV_CLK_OSC32K_EXT, RTC_DRV_CLK_LPO32K } Rtc_Drv_ClockSourceType; typedef enum { RTC_DRV_INT_OVERFLOW = 0U, RTC_DRV_INT_ALARM, RTC_DRV_INT_SECOND, RTC_DRV_INT_PERIODIC, RTC_DRV_INT_ALL } Rtc_Drv_InterruptType; typedef enum { RTC_DRV_SUCCESS = 0x00U, RTC_DRV_ERROR = 0x01U } Rtc_Drv_StatusType; typedef enum { RTC_DRV_SECOND_1 = 0U, RTC_DRV_SECOND_64, RTC_DRV_SECOND_32, RTC_DRV_SECOND_16, RTC_DRV_SECOND_8, RTC_DRV_SECOND_4, RTC_DRV_SECOND_2, RTC_DRV_SECOND_128 } Rtc_Drv_SecondIntMuxSelType; # 175 "../../../mcal/Gpt_ZX_K14xM/Inc/Rtc_Drv_Types.h" typedef struct { Rtc_Drv_ClockSourceType ClockSource; Rtc_Drv_ClockOutType ClockOutSelect; Rtc_Drv_InterruptType ModeSelect; Rtc_Drv_CallbackType Callback; uint8 CallbackParam; } Rtc_Drv_ConfigType; typedef struct { uint16 Year; uint16 Month; uint16 Day; uint16 Hour; uint16 Minutes; uint8 Seconds; } Rtc_Drv_TimedateType; typedef struct { Rtc_Drv_TimedateType AlarmTime; uint32 AlarmRepetitionInterval; uint32 AlarmRepeatsNumber; boolean RepeatForever; boolean AlarmIntEnable; Rtc_Drv_CallbackType AlarmCallback; uint8 AlarmCallbackParams; } Rtc_Drv_AlarmConfigType; typedef struct { Rtc_Drv_InterruptType ModeSelect; boolean AlarmInit; uint32 AlarmRepetitionInterval; volatile uint32 AlarmRepeatsNumber; boolean RepeatForever; boolean AlarmIntEnable; Rtc_Drv_CallbackType AlarmCallback; uint8 AlarmCallbackParams; volatile boolean IsAlarmMatchTimeNew; boolean ChannelInit; Rtc_Drv_CallbackType Callback; uint8 CallbackParam; } Rtc_Drv_StateType; # 31 "../../../mcal/Gpt_ZX_K14xM/Inc/Gpt_Drvw_Types.h" 2 # 1 "../../../mcal/Gpt_ZX_K14xM/Inc/Stim_Drv_Types.h" 1 # 32 "../../../mcal/Gpt_ZX_K14xM/Inc/Stim_Drv_Types.h" # 1 "../Generated/inc\\Stim_Drv_Cfg.h" 1 # 28 "../Generated/inc\\Stim_Drv_Cfg.h" # 1 "../Generated/inc/Stim_Drv_PBcfg.h" 1 # 29 "../Generated/inc\\Stim_Drv_Cfg.h" 2 # 33 "../../../mcal/Gpt_ZX_K14xM/Inc/Stim_Drv_Types.h" 2 # 104 "../../../mcal/Gpt_ZX_K14xM/Inc/Stim_Drv_Types.h" typedef enum { STIM_DRV_FUNCTION_CLOCK = 0U, STIM_DRV_BUS_CLOCK, STIM_DRV_OSC40M, STIM_DRV_LPO32K } Stim_Drv_ClockSourceType; typedef enum { STIM_DRV_SUCCESS = 0x00U, STIM_DRV_ERROR = 0x01U, STIM_DRV_TIMEOUT = 0x03 } Stim_Drv_StatusType; typedef enum { STIM_DRV_DIV_2 = 0U, STIM_DRV_DIV_4, STIM_DRV_DIV_8, STIM_DRV_DIV_16, STIM_DRV_DIV_32, STIM_DRV_DIV_64, STIM_DRV_DIV_128, STIM_DRV_DIV_256, STIM_DRV_DIV_512, STIM_DRV_DIV_1024, STIM_DRV_DIV_2048, STIM_DRV_DIV_4096, STIM_DRV_DIV_8192, STIM_DRV_DIV_16384, STIM_DRV_DIV_32768, STIM_DRV_DIV_65536 } Stim_Drv_PrescalerType; # 159 "../../../mcal/Gpt_ZX_K14xM/Inc/Stim_Drv_Types.h" typedef void (*Stim_Drv_CallbackType)(uint8 CallbackParam); typedef struct { uint8 HwChannel; boolean PrescalerEnable; Stim_Drv_PrescalerType ClockPrescaler; Stim_Drv_ClockSourceType ClockSource; Stim_Drv_CallbackType Callback; uint8 CallbackParam; } Stim_Drv_ChannelConfigType; typedef struct { boolean ChannelInit; Stim_Drv_CallbackType Callback; uint8 CallbackParam; } Stim_Drv_StateType; typedef struct { Stim_Drv_PrescalerType ClockPrescaler; Stim_Drv_PrescalerType ClockAlternatePrescaler; } Stim_Drv_ClockStateType; # 32 "../../../mcal/Gpt_ZX_K14xM/Inc/Gpt_Drvw_Types.h" 2 # 1 "../../../mcal/Gpt_ZX_K14xM/Inc/Tim_Drv_Types.h" 1 # 32 "../../../mcal/Gpt_ZX_K14xM/Inc/Tim_Drv_Types.h" # 1 "../Generated/inc\\Tim_Drv_Cfg.h" 1 # 28 "../Generated/inc\\Tim_Drv_Cfg.h" # 1 "../Generated/inc/Tim_Drv_PBcfg.h" 1 # 29 "../Generated/inc\\Tim_Drv_Cfg.h" 2 # 33 "../../../mcal/Gpt_ZX_K14xM/Inc/Tim_Drv_Types.h" 2 # 100 "../../../mcal/Gpt_ZX_K14xM/Inc/Tim_Drv_Types.h" typedef enum { TIM_DRV_CLK_SOURCE_DISABLED = 0U, TIM_DRV_CLK_SOURCE_SYSTEM, TIM_DRV_CLK_SOURCE_FUNCTION, TIM_DRV_CLK_SOURCE_EXTERNAL } Tim_Drv_ClockSourceType; typedef enum { TIM_DRV_CLK_DIV_1 = 0U, TIM_DRV_CLK_DIV_2, TIM_DRV_CLK_DIV_4, TIM_DRV_CLK_DIV_8, TIM_DRV_CLK_DIV_16, TIM_DRV_CLK_DIV_32, TIM_DRV_CLK_DIV_64, TIM_DRV_CLK_DIV_128 } Tim_Drv_PrescalerType; typedef enum { TIM_DRV_COUNTING_UP = 0U, TIM_DRV_COUNTING_UP_DOWN } Tim_Drv_CountingModeType; # 146 "../../../mcal/Gpt_ZX_K14xM/Inc/Tim_Drv_Types.h" typedef enum { TIM_DRV_IDLE = 0U, TIM_DRV_BUSY } Tim_Drv_StatusType; typedef void (*Tim_Drv_CallbackType)(uint8 CallbackParam); typedef struct { boolean FreezeBit; Tim_Drv_ClockSourceType ClockSource; Tim_Drv_PrescalerType ClockPrescaler; Tim_Drv_CountingModeType Mode; } Tim_Drv_InstanceConfigType; typedef struct { uint8 HwChannel; Tim_Drv_ClockSourceType ClockSource; Tim_Drv_CallbackType Callback; uint8 CallbackParam; } Tim_Drv_ChannelConfigType; typedef struct { Tim_Drv_StatusType ChannelStatus; Tim_Drv_CallbackType Callback; uint8 CallbackParam; } Tim_Drv_ChannelStateType; typedef struct { Tim_Drv_PrescalerType ClockPrescaler; Tim_Drv_PrescalerType ClockAlternatePrescaler; } Tim_Drv_InstanceStateType; # 33 "../../../mcal/Gpt_ZX_K14xM/Inc/Gpt_Drvw_Types.h" 2 # 126 "../../../mcal/Gpt_ZX_K14xM/Inc/Gpt_Drvw_Types.h" typedef uint8 Gpt_Drvw_PrescalerType; typedef uint8 Gpt_Drvw_ClockSourceType; typedef enum { GPT_DRVW_TIM_MODULE= 0, GPT_DRVW_RTC_MODULE, GPT_DRVW_STIM_MODULE, } Gpt_Drvw_ModuleType; typedef struct { const Tim_Drv_InstanceConfigType * Tim_Drv_InstanceConfig; } Gpt_Drvw_InstanceConfigType; typedef struct { const Tim_Drv_ChannelConfigType *TimChannelConfig; const Rtc_Drv_ConfigType *RtcChannelConfig; const Stim_Drv_ChannelConfigType *StimChannelConfig; } Gpt_Drvw_ChannelConfigType; typedef struct { Gpt_Drvw_ModuleType InstanceType; uint8 Instance; const Gpt_Drvw_InstanceConfigType InstanceConfig; } Gpt_Drvw_HwInstanceConfigType; typedef struct { Gpt_Drvw_ModuleType InstanceType; uint8 Instance; uint8 Channel; const Gpt_Drvw_ChannelConfigType ChannelConfig; } Gpt_Drvw_HwChannelConfigType; # 198 "../../../mcal/Gpt_ZX_K14xM/Inc/Gpt_Drvw_Types.h" typedef struct { Gpt_Drvw_ModuleType InstanceType; uint8 Instance; uint8 Channel; Gpt_Drvw_PrescalerType Prescaler; Gpt_Drvw_ClockSourceType ClockSource; } Gpt_Drvw_HwPredefChannelConfigType; typedef struct { boolean ChannelRollover; uint32 TargetTime; } Gpt_Drvw_HwChannelInfoType; typedef enum { GPT_DRVW_PREDEF_TIMER_1US_16BIT = 0U, GPT_DRVW_PREDEF_TIMER_1US_24BIT, GPT_DRVW_PREDEF_TIMER_1US_32BIT, GPT_DRVW_PREDEF_TIMER_100US_32BIT } Gpt_Drvw_PredefTimerType; # 30 "../../../mcal/Gpt_ZX_K14xM/Inc/Gpt_Types.h" 2 # 1 "../Generated/inc\\Gpt_Cfg.h" 1 # 30 "../Generated/inc\\Gpt_Cfg.h" # 1 "../Generated/inc/Gpt_PBcfg.h" 1 # 31 "../Generated/inc\\Gpt_Cfg.h" 2 # 31 "../../../mcal/Gpt_ZX_K14xM/Inc/Gpt_Types.h" 2 # 1 "../../../mcal/EcuM_ZX_K14xM/Inc\\EcuM.h" 1 # 55 "../../../mcal/EcuM_ZX_K14xM/Inc\\EcuM.h" typedef uint32 EcuM_WakeupSourceType; # 66 "../../../mcal/EcuM_ZX_K14xM/Inc\\EcuM.h" extern EcuM_WakeupSourceType EcuMLastWakeupEvent; # 80 "../../../mcal/EcuM_ZX_K14xM/Inc\\EcuM.h" void EcuM_SetWakeupEvent(EcuM_WakeupSourceType sources); void EcuM_ValidateWakeupEvent(EcuM_WakeupSourceType sources); # 96 "../../../mcal/EcuM_ZX_K14xM/Inc\\EcuM.h" void EcuM_CheckWakeup(EcuM_WakeupSourceType WakeupSource); # 34 "../../../mcal/Gpt_ZX_K14xM/Inc/Gpt_Types.h" 2 # 97 "../../../mcal/Gpt_ZX_K14xM/Inc/Gpt_Types.h" typedef enum { GPT_STATUS_UNINITIALIZED = 0, GPT_STATUS_INITIALIZED, GPT_STATUS_STOPPED, GPT_STATUS_EXPIRED, GPT_STATUS_RUNNING } Gpt_ChannelStatusType; typedef struct { Gpt_ChannelStatusType ChannelStatus; boolean NotificationEnabled; boolean WakeupEnabled; boolean WakeupGenerated; } Gpt_ChannelInfoType; # 132 "../../../mcal/Gpt_ZX_K14xM/Inc/Gpt_Types.h" typedef uint32 Gpt_ChannelType; typedef uint32 Gpt_ValueType; typedef void (*Gpt_NotificationType)(void); typedef enum { GPT_MODE_NORMAL = 0U, GPT_MODE_SLEEP } Gpt_ModeType; typedef enum { GPT_CH_MODE_CONTINUOUS = 0U, GPT_CH_MODE_ONESHOT } Gpt_ChannelModeType; # 186 "../../../mcal/Gpt_ZX_K14xM/Inc/Gpt_Types.h" typedef enum { GPT_PREDEF_TIMER_1US_16BIT = 0U, GPT_PREDEF_TIMER_1US_24BIT, GPT_PREDEF_TIMER_1US_32BIT, GPT_PREDEF_TIMER_100US_32BIT } Gpt_PredefTimerType; typedef struct { boolean GptEnableWakeup; Gpt_NotificationType GptNotification; EcuM_WakeupSourceType GptWakeupSource; float64 GptChannelTickFrequency; Gpt_ValueType GptChannelTickValueMax; Gpt_ChannelModeType GptChannelMode; const Gpt_Drvw_HwChannelConfigType *GptDrvwHwChannelConfigPtr; } Gpt_ChannelConfigType; typedef struct { Gpt_ChannelType ChannelCount; const Gpt_ChannelConfigType (*GptChannelConfig)[]; uint8 InstanceCount; const Gpt_Drvw_HwInstanceConfigType (*GptInstanceConfig)[]; const Gpt_Drvw_HwPredefChannelConfigType *const(*GptChannelPredefConfigType); const uint8 (*GptChannelIdToIndexMap)[]; } Gpt_ConfigType; # 31 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" 2 # 300 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Gpt_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Gpt_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 301 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" 2 extern const Gpt_ConfigType *const Gpt_PreDefinedConfigPtr[(1U)]; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Gpt_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Gpt_MemMap.h" #pragma clang section rodata = "" # 308 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Gpt_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Gpt_MemMap.h" #pragma clang section text = ".mcal_code" # 317 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" 2 # 330 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" void Gpt_GetVersionInfo(Std_VersionInfoType *VersionInfoPtr); # 344 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" void Gpt_Init(const Gpt_ConfigType *ConfigPtr); # 356 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" void Gpt_DeInit(void); # 372 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" Gpt_ValueType Gpt_GetTimeElapsed(Gpt_ChannelType Channel); # 388 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" Gpt_ValueType Gpt_GetTimeRemaining(Gpt_ChannelType Channel); # 403 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" void Gpt_StartTimer(Gpt_ChannelType Channel, Gpt_ValueType Value); # 416 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" void Gpt_StopTimer(Gpt_ChannelType Channel); # 431 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" void Gpt_EnableNotification(Gpt_ChannelType Channel); # 445 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" void Gpt_DisableNotification(Gpt_ChannelType Channel); # 462 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" void Gpt_SetMode(Gpt_ModeType Mode); # 476 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" void Gpt_DisableWakeup(Gpt_ChannelType Channel); # 490 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" void Gpt_EnableWakeup(Gpt_ChannelType Channel); # 505 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" void Gpt_CheckWakeup(EcuM_WakeupSourceType WakeupSource); # 523 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" Std_ReturnType Gpt_GetPredefTimerValue(Gpt_PredefTimerType PredefTimer, uint32 *TimeValuePtr); # 544 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Gpt_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Gpt_MemMap.h" #pragma clang section text = "" # 545 "../../../mcal/Gpt_ZX_K14xM/Inc\\Gpt.h" 2 # 14 "../Src/main.h" 2 # 1 "../../../mcal/Platform_ZX_K14xM/Inc\\Platform.h" 1 # 29 "../../../mcal/Platform_ZX_K14xM/Inc\\Platform.h" # 1 "../../../mcal/Platform_ZX_K14xM/Inc/Platform_TypesDef.h" 1 # 29 "../../../mcal/Platform_ZX_K14xM/Inc/Platform_TypesDef.h" # 1 "../Generated/inc\\Platform_Cfg.h" 1 # 74 "../Generated/inc\\Platform_Cfg.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 75 "../Generated/inc\\Platform_Cfg.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" #pragma clang section rodata = "" # 82 "../Generated/inc\\Platform_Cfg.h" 2 # 30 "../../../mcal/Platform_ZX_K14xM/Inc/Platform_TypesDef.h" 2 # 1 "../../../mcal/Platform_ZX_K14xM/Inc/Interrupt_Drv_Types.h" 1 # 28 "../../../mcal/Platform_ZX_K14xM/Inc/Interrupt_Drv_Types.h" # 1 "../Generated/inc\\Interrupt_Drv_Cfg.h" 1 # 98 "../Generated/inc\\Interrupt_Drv_Cfg.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" #pragma clang section text = ".mcal_code" # 99 "../Generated/inc\\Interrupt_Drv_Cfg.h" 2 extern void undefined_handler(void); extern void Dma_Drv_Ch0IrqHandler(void); extern void Dma_Drv_Ch1IrqHandler(void); extern void Dma_Drv_Ch2IrqHandler(void); extern void Dma_Drv_Ch3IrqHandler(void); extern void Dma_Drv_Ch4IrqHandler(void); extern void Spi_Drv_1_TxeIrqHandler(void); extern void Spi_Drv_1_TxoIrqHandler(void); extern void Spi_Drv_1_RxfIrqHandler(void); extern void Spi_Drv_1_RxoIrqHandler(void); extern void Spi_Drv_1_RxuIrqHandler(void); extern void Can_Drv_1_BusOffIrqHandler(void); extern void Can_Drv_1_TxWarnIrqHandler(void); extern void Can_Drv_1_RxWarnIrqHandler(void); extern void Can_Drv_1_ErrIrqHandler(void); extern void Can_Drv_1_SelfWakeupIrqHandler(void); extern void Can_Drv_1_EccIrqHandler(void); extern void Can_Drv_1_Mb0To15IrqHandler(void); extern void Can_Drv_1_Mb16To31IrqHandler(void); extern void Can_Drv_1_Mb32To47IrqHandler(void); extern void Can_Drv_1_Mb48To63IrqHandler(void); extern void Stim_Drv_IrqHandler(void); extern void Adc_Drv_0_IrqHandler(void); extern void Adc_Drv_1_IrqHandler(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" #pragma clang section text = "" # 129 "../Generated/inc\\Interrupt_Drv_Cfg.h" 2 # 29 "../../../mcal/Platform_ZX_K14xM/Inc/Interrupt_Drv_Types.h" 2 # 1 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices\\Device_Regs.h" 1 # 17 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices\\Device_Regs.h" # 1 "../Generated/inc\\Device_Cfg.h" 1 # 18 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices\\Device_Regs.h" 2 # 1 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices/Z20K148M.h" 1 # 43 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices/Z20K148M.h" typedef enum IRQn { NMI_IRQn = -14, HardFalut_IRQn = -13, MemManageFault_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, DMA_Ch0_IRQn = 0, DMA_Ch1_IRQn = 1, DMA_Ch2_IRQn = 2, DMA_Ch3_IRQn = 3, DMA_Ch4_IRQn = 4, DMA_Ch5_IRQn = 5, DMA_Ch6_IRQn = 6, DMA_Ch7_IRQn = 7, DMA_Ch8_IRQn = 8, DMA_Ch9_IRQn = 9, DMA_Ch10_IRQn = 10, DMA_Ch11_IRQn = 11, DMA_Ch12_IRQn = 12, DMA_Ch13_IRQn = 13, DMA_Ch14_IRQn = 14, DMA_Ch15_IRQn = 15, DMA_Err_IRQn = 16, FLASH_CmdComplete_IRQn = 17, FLASH_Ecc_IRQn = 18, PMU_IRQn = 19, WDOG_IRQn = 20, EWDT_IRQn = 21, SRMC_IRQn = 22, I2C0_IRQn = 23, I2C1_IRQn = 24, SPI0_Txe_IRQn = 25, SPI0_Txo_IRQn = 26, SPI0_Rxf_IRQn = 27, SPI0_Rxo_IRQn = 28, SPI0_Rxu_IRQn = 29, Reserved30_IRQn = 30, SPI1_Txe_IRQn = 31, SPI1_Txo_IRQn = 32, SPI1_Rxf_IRQn = 33, SPI1_Rxo_IRQn = 34, SPI1_Rxu_IRQn = 35, Reserved36_IRQn = 36, SPI2_Txe_IRQn = 37, SPI2_Txo_IRQn = 38, SPI2_Rxf_IRQn = 39, SPI2_Rxo_IRQn = 40, SPI2_Rxu_IRQn = 41, Reserved42_IRQn = 42, SPI3_Txe_IRQn = 43, SPI3_Txo_IRQn = 44, SPI3_Rxf_IRQn = 45, SPI3_Rxo_IRQn = 46, SPI3_Rxu_IRQn = 47, Reserved48_IRQn = 48, UART0_IRQn = 49, UART1_IRQn = 50, UART2_IRQn = 51, UART3_IRQn = 52, UART4_IRQn = 53, UART5_IRQn = 54, CAN0_BusOff_IRQn = 55, CAN0_TxWarn_IRQn = 56, CAN0_RxWarn_IRQn = 57, CAN0_Err_IRQn = 58, CAN0_ErrFd_IRQn = 59, CAN0_PnWake_IRQn = 60, CAN0_SelfWakeup_IRQn = 61, CAN0_Ecc_IRQn = 62, CAN0_Mb0To15_IRQn = 63, CAN0_Mb16To31_IRQn = 64, CAN0_Mb32To47_IRQn = 65, CAN0_Mb48To63_IRQn = 66, CAN1_BusOff_IRQn = 67, CAN1_TxWarn_IRQn = 68, CAN1_RxWarn_IRQn = 69, CAN1_Err_IRQn = 70, CAN1_ErrFd_IRQn = 71, CAN1_PnWake_IRQn = 72, CAN1_SelfWakeup_IRQn = 73, CAN1_Ecc_IRQn = 74, CAN1_Mb0To15_IRQn = 75, CAN1_Mb16To31_IRQn = 76, CAN1_Mb32To47_IRQn = 77, CAN1_Mb48To63_IRQn = 78, CAN2_BusOff_IRQn = 79, CAN2_TxWarn_IRQn = 80, CAN2_RxWarn_IRQn = 81, CAN2_Err_IRQn = 82, CAN2_ErrFd_IRQn = 83, CAN2_PnWake_IRQn = 84, CAN2_SelfWakeup_IRQn = 85, CAN2_Ecc_IRQn = 86, CAN2_Mb0To15_IRQn = 87, CAN2_Mb16To31_IRQn = 88, CAN2_Mb32To47_IRQn = 89, CAN2_Mb48To63_IRQn = 90, CAN3_BusOff_IRQn = 91, CAN3_TxWarn_IRQn = 92, CAN3_RxWarn_IRQn = 93, CAN3_Err_IRQn = 94, CAN3_ErrFd_IRQn = 95, CAN3_PnWake_IRQn = 96, CAN3_SelfWakeup_IRQn = 97, CAN3_Ecc_IRQn = 98, CAN3_Mb0To15_IRQn = 99, CAN3_Mb16To31_IRQn = 100, CAN3_Mb32To47_IRQn = 101, CAN3_Mb48To63_IRQn = 102, CAN4_BusOff_IRQn = 103, CAN4_TxWarn_IRQn = 104, CAN4_RxWarn_IRQn = 105, CAN4_Err_IRQn = 106, CAN4_ErrFd_IRQn = 107, CAN4_PnWake_IRQn = 108, CAN4_SelfWakeup_IRQn = 109, CAN4_Ecc_IRQn = 110, CAN4_Mb0To15_IRQn = 111, CAN4_Mb16To31_IRQn = 112, CAN4_Mb32To47_IRQn = 113, CAN4_Mb48To63_IRQn = 114, CAN5_BusOff_IRQn = 115, CAN5_TxWarn_IRQn = 116, CAN5_RxWarn_IRQn = 117, CAN5_Err_IRQn = 118, CAN5_ErrFd_IRQn = 119, CAN5_PnWake_IRQn = 120, CAN5_SelfWakeup_IRQn = 121, CAN5_Ecc_IRQn = 122, CAN5_Mb0To15_IRQn = 123, CAN5_Mb16To31_IRQn = 124, CAN5_Mb32To47_IRQn = 125, CAN5_Mb48To63_IRQn = 126, CAN6_BusOff_IRQn = 127, CAN6_TxWarn_IRQn = 128, CAN6_RxWarn_IRQn = 129, CAN6_Err_IRQn = 130, CAN6_ErrFd_IRQn = 131, CAN6_PnWake_IRQn = 132, CAN6_SelfWakeup_IRQn = 133, CAN6_Ecc_IRQn = 134, CAN6_Mb0To31_IRQn = 135, CAN6_Mb32To63_IRQn = 136, CAN6_Mb64To95_IRQn = 137, CAN6_Mb96To127_IRQn = 138, CAN7_BusOff_IRQn = 139, CAN7_TxWarn_IRQn = 140, CAN7_RxWarn_IRQn = 141, CAN7_Err_IRQn = 142, CAN7_ErrFd_IRQn = 143, CAN7_PnWake_IRQn = 144, CAN7_SelfWakeup_IRQn = 145, CAN7_Ecc_IRQn = 146, CAN7_Mb0To31_IRQn = 147, CAN7_Mb32To63_IRQn = 148, CAN7_Mb64To95_IRQn = 149, CAN7_Mb96To127_IRQn = 150, Reserved151_IRQn = 151, Reserved152_IRQn = 152, Reserved153_IRQn = 153, TIM0_Ch_IRQn = 154, TIM0_Fault_IRQn = 155, TIM0_Overflow_IRQn = 156, TIM0_Rlfl_IRQn = 157, TIM1_Ch_IRQn = 158, TIM1_Fault_IRQn = 159, TIM1_Overflow_IRQn = 160, TIM1_Rlfl_IRQn = 161, TIM2_Ch_IRQn = 162, TIM2_Fault_IRQn = 163, TIM2_Overflow_IRQn = 164, TIM2_Rlfl_IRQn = 165, TIM3_Ch_IRQn = 166, TIM3_Fault_IRQn = 167, TIM3_Overflow_IRQn = 168, TIM3_Rlfl_IRQn = 169, TDG0_Tco_IRQn = 170, TDG0_Err_IRQn = 171, TDG1_Tco_IRQn = 172, TDG1_Err_IRQn = 173, I2S0_IRQn = 174, I2S1_IRQn = 175, PORTA_IRQn = 176, PORTB_IRQn = 177, PORTC_IRQn = 178, PORTD_IRQn = 179, PORTE_IRQn = 180, STIM_IRQn = 181, RTC_Alarm_IRQn = 182, RTC_Second_IRQn = 183, AES_IRQn = 184, TRNG_IRQn = 185, CMU0_IRQn = 186, CMU1_IRQn = 187, CMU2_IRQn = 188, SERU_ParityErr_IRQn = 189, SERU_ChErr_IRQn = 190, SCC_IRQn = 191, MCPWM0_Ch_IRQn = 192, MCPWM0_Fault_IRQn = 193, MCPWM0_Overflow_IRQn = 194, MCPWM0_Rlfl_IRQn = 195, MCPWM1_Ch_IRQn = 196, MCPWM1_Fault_IRQn = 197, MCPWM1_Overflow_IRQn = 198, MCPWM1_Rlfl_IRQn = 199, ADC0_IRQn = 200, ADC1_IRQn = 201, CMP_IRQn = 202, FPU_Err_IRQn = 203, CACHE_Err_IRQn = 204, } IRQn_Type; # 352 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices/Z20K148M.h" typedef struct { uint32 RESERVED0[1U]; volatile const uint32 ICTR; volatile uint32 ACTLR; } Z20_SCnSCBType; typedef struct { volatile const uint32 CPUID; volatile uint32 ICSR; volatile uint32 VTOR; volatile uint32 AIRCR; volatile uint32 SCR; volatile uint32 CCR; volatile uint8 SHP[12U]; volatile uint32 SHCSR; volatile uint32 CFSR; volatile uint32 HFSR; volatile uint32 DFSR; volatile uint32 MMFAR; volatile uint32 BFAR; volatile uint32 AFSR; volatile const uint32 PFR[2U]; volatile const uint32 DFR; volatile const uint32 ADR; volatile const uint32 MMFR[4U]; volatile const uint32 ISAR[5U]; uint32 RESERVED0[5U]; volatile uint32 CPACR; } Z20_SCBType; typedef struct { volatile uint32 CTRL; volatile uint32 LOAD; volatile uint32 VAL; volatile const uint32 CALIB; } Z20_SysTickType; typedef struct { volatile uint32 ISER[8U]; uint32 RESERVED0[24U]; volatile uint32 ICER[8U]; uint32 RSERVED1[24U]; volatile uint32 ISPR[8U]; uint32 RESERVED2[24U]; volatile uint32 ICPR[8U]; uint32 RESERVED3[24U]; volatile uint32 IABR[8U]; uint32 RESERVED4[56U]; volatile uint8 IP[240U]; uint32 RESERVED5[644U]; volatile uint32 STIR; } Z20_NVICType; typedef struct { volatile uint32 CTRL; volatile uint32 CYCCNT; volatile uint32 CPICNT; volatile uint32 EXCCNT; volatile uint32 SLEEPCNT; volatile uint32 LSUCNT; volatile uint32 FOLDCNT; volatile const uint32 PCSR; volatile uint32 COMP0; volatile uint32 MASK0; volatile uint32 FUNCTION0; uint32 RESERVED0[1U]; volatile uint32 COMP1; volatile uint32 MASK1; volatile uint32 FUNCTION1; uint32 RESERVED1[1U]; volatile uint32 COMP2; volatile uint32 MASK2; volatile uint32 FUNCTION2; uint32 RESERVED2[1U]; volatile uint32 COMP3; volatile uint32 MASK3; volatile uint32 FUNCTION3; } Z20_DWTType; typedef struct { volatile uint32 DHCSR; volatile uint32 DCRSR; volatile uint32 DCRDR; volatile uint32 DEMCR; } Z20_CoreDebugType; typedef struct { uint32 RESERVED0[1U]; volatile uint32 FPCCR; volatile uint32 FPCAR; volatile uint32 FPDSCR; volatile const uint32 MVFR0; volatile const uint32 MVFR1; } Z20_FPUType; # 496 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices/Z20K148M.h" struct Reg_Adc_Bf { uint32 zResverd0x000; struct { uint32 RSVD_7_0 : 8; uint32 FIFO_SIZE : 8; uint32 RSVD_31_16 : 16; } ADC_PARAM; struct { uint32 ADC_EN : 1; uint32 CAL_REQ : 1; uint32 RST : 1; uint32 DOZEN : 1; uint32 TRIG_MODE_ENABLE : 1; uint32 TRIG_MODE : 1; uint32 MODE1_RST : 1; uint32 LMD : 3; uint32 IREF_SEL : 1; uint32 STABLE_T : 11; uint32 RSVD_31_22 : 10; } ADC_CTRL; struct { uint32 FWM_INT : 1; uint32 FOF : 1; uint32 TCOMP_INT : 1; uint32 CMP_INT : 1; uint32 DMA_REQ : 1; uint32 RDY : 1; uint32 CAL_RDY : 1; uint32 ADC_ACTIVE : 1; uint32 LSI : 1; uint32 TC_ERR : 1; uint32 RSVD_31_10 : 22; } ADC_STAT; struct { uint32 FWM_IE : 1; uint32 FOF_IE : 1; uint32 TCOM_IE : 1; uint32 CMP_IE : 1; uint32 FWMDE : 1; uint32 ERR_INT_IE : 1; uint32 RSVD_31_6 : 26; } ADC_IE; struct { uint32 DIFF_MODE : 1; uint32 CHSELP : 5; uint32 CHSELN : 2; uint32 RSVD_10_8 : 3; uint32 CTYPE : 1; uint32 CMPS : 3; uint32 HWT_EN : 1; uint32 REF_SEL : 1; uint32 RES : 2; uint32 AVGS : 3; uint32 STS : 10; } ADC_CFG; struct { uint32 CVL : 12; uint32 RSVD_15_12 : 4; uint32 CVH : 12; uint32 RSVD_31_28 : 4; } ADC_CV; uint8 zResverd0x01C[4]; struct { uint32 ADC_DATA_RD : 17; uint32 RSVD_31_17 : 15; } ADC_DATA_RD; struct { uint32 FCOUNT : 5; uint32 RSVD_15_5 : 11; uint32 FWMARK : 4; uint32 FDRD : 5; uint32 RSVD_31_25 : 7; } ADC_FCTRL; struct { uint32 ADC_SWTRIG : 1; uint32 RSVD_31_1 : 31; } ADC_SWTRIG; struct { uint32 ADC_CAL_VAL : 13; uint32 RSVD_31_13 : 19; } ADC_CAL_VAL; struct { uint32 CMD0 : 5; uint32 CMD0_INT_EN : 1; uint32 RSVD_7_6 : 2; uint32 CMD1 : 5; uint32 CMD1_INT_EN : 1; uint32 RSVD_15_14 : 2; uint32 CMD2 : 5; uint32 CMD2_INT_EN : 1; uint32 RSVD_23_22 : 2; uint32 CMD3 : 5; uint32 CMD3_INT_EN : 1; uint32 RSVD_31_30 : 2; } ADC_CMD_BUFF0; struct { uint32 CMD4 : 5; uint32 CMD4_INT_EN : 1; uint32 RSVD_7_6 : 2; uint32 CMD5 : 5; uint32 CMD5_INT_EN : 1; uint32 RSVD_31_14 : 18; } ADC_CMD_BUFF1; }; struct Reg_Adc_W { uint32 zResverd0x000; uint32 ADC_PARAM; uint32 ADC_CTRL; uint32 ADC_STAT; uint32 ADC_IE; uint32 ADC_CFG; uint32 ADC_CV; uint8 zResverd0x01C[4]; uint32 ADC_DATA_RD; uint32 ADC_FCTRL; uint32 ADC_SWTRIG; uint32 ADC_CAL_VAL; uint32 ADC_CMD_BUFF0; uint32 ADC_CMD_BUFF1; }; typedef volatile struct Reg_Adc_Bf Reg_Adc_BfType; typedef volatile struct Reg_Adc_W Reg_Adc_WType; struct Reg_Aes_Bf { uint32 zResverd0x0000; struct { uint32 R : 1; uint32 ERR : 8; uint32 RSVD_31_9 : 23; } AES_STATUS; struct { uint32 S : 1; uint32 RND : 4; uint32 RSVD_31_5 : 27; } AES_CONTROL; struct { uint32 CD : 1; uint32 KSS : 2; uint32 RSVD_3 : 1; uint32 RSVD_7_4 : 4; uint32 MODE : 8; uint32 BS : 8; uint32 ALGO : 8; } AES_CONFIG; uint8 zResverd0x010[12]; struct { uint32 DATA_I : 32; } AES_DATA_I0; struct { uint32 DATA_I : 32; } AES_DATA_I1; struct { uint32 DATA_I : 32; } AES_DATA_I2; struct { uint32 DATA_I : 32; } AES_DATA_I3; struct { uint32 DATA_O : 32; } AES_DATA_O0; struct { uint32 DATA_O : 32; } AES_DATA_O1; struct { uint32 DATA_O : 32; } AES_DATA_O2; struct { uint32 DATA_O : 32; } AES_DATA_O3; struct { uint32 KEY0 : 32; } AES_KEY0; struct { uint32 KEY1 : 32; } AES_KEY1; struct { uint32 KEY2 : 32; } AES_KEY2; struct { uint32 KEY3 : 32; } AES_KEY3; uint8 zResverd0x04C[16]; struct { uint32 IV0 : 32; } AES_IV0; struct { uint32 IV1 : 32; } AES_IV1; struct { uint32 IV2 : 32; } AES_IV2; struct { uint32 IV3 : 32; } AES_IV3; }; struct Reg_Aes_W { uint32 zResverd0x0000; uint32 AES_STATUS; uint32 AES_CONTROL; uint32 AES_CONFIG; uint8 zResverd0x010[12]; uint32 AES_DATA_I0; uint32 AES_DATA_I1; uint32 AES_DATA_I2; uint32 AES_DATA_I3; uint32 AES_DATA_O0; uint32 AES_DATA_O1; uint32 AES_DATA_O2; uint32 AES_DATA_O3; uint32 AES_KEY0; uint32 AES_KEY1; uint32 AES_KEY2; uint32 AES_KEY3; uint8 zResverd0x04C[16]; uint32 AES_IV0; uint32 AES_IV1; uint32 AES_IV2; uint32 AES_IV3; }; typedef volatile struct Reg_Aes_Bf Reg_Aes_BfType; typedef volatile struct Reg_Aes_W Reg_Aes_WType; struct Reg_Can_Bf { struct { uint32 MAXMB : 7; uint32 RSVD_7 : 1; uint32 IDAM : 2; uint32 RSVD_10 : 1; uint32 FDEN : 1; uint32 AEN : 1; uint32 LPRIOEN : 1; uint32 PNET_EN : 1; uint32 DMAE : 1; uint32 IRMQ : 1; uint32 SRXDIS : 1; uint32 DOZE : 1; uint32 WAKSRC : 1; uint32 LPMACK : 1; uint32 WRNEN : 1; uint32 SLFWAK : 1; uint32 SUPV : 1; uint32 FRZACK : 1; uint32 SOFTRST : 1; uint32 WAKMSK : 1; uint32 NOTRDY : 1; uint32 HALT : 1; uint32 RFEN : 1; uint32 FRZ : 1; uint32 MDIS : 1; } CAN_MCR; struct { uint32 PROPSEG : 3; uint32 LOM : 1; uint32 LBUF : 1; uint32 TSYC : 1; uint32 BOFFREC : 1; uint32 SMP : 1; uint32 RSVD_9_8 : 2; uint32 RWRNMSK : 1; uint32 TWRNMSK : 1; uint32 LPB : 1; uint32 RSVD_13 : 1; uint32 ERRMSK : 1; uint32 BOFFMSK : 1; uint32 PSEG2 : 3; uint32 PSEG1 : 3; uint32 RJW : 2; uint32 PRESDIV : 8; } CAN_CTRL1; struct { uint32 TIMER : 16; uint32 RSVD_31_16 : 16; } CAN_TIMER; uint8 zResverd0x0C[4]; struct { uint32 MG : 32; } CAN_RXMGMSK; struct { uint32 RX14M : 32; } CAN_RX14MASK; struct { uint32 RX15M : 32; } CAN_RX15MASK; struct { uint32 TXERRCNT : 8; uint32 RXERRCNT : 8; uint32 TX_ERRCNT_FAST : 8; uint32 RX_ERRCNT_FAST : 8; } CAN_ECR; struct { uint32 WAKINT : 1; uint32 ERRINT : 1; uint32 BOFFINT : 1; uint32 RX : 1; uint32 FLTCONF : 2; uint32 TX : 1; uint32 IDLE : 1; uint32 RXWRN : 1; uint32 TXWRN : 1; uint32 STFERR : 1; uint32 FRAMERR : 1; uint32 CRCERR : 1; uint32 ACKERR : 1; uint32 BIT0ERR : 1; uint32 BIT1ERR : 1; uint32 RWRNINT : 1; uint32 TWRNINT : 1; uint32 SYNCH : 1; uint32 BUSOFFDONEINT : 1; uint32 ERRINT_FAST : 1; uint32 ERROVR : 1; uint32 RSVD_25_22 : 4; uint32 STFERR_FAST : 1; uint32 FRAMERR_FAST : 1; uint32 CRCERR_FAST : 1; uint32 RSVD_29 : 1; uint32 BIT0ERR_FAST : 1; uint32 BIT1ERR_FAST : 1; } CAN_ESR1; struct { uint32 BUF63TO32M : 32; } CAN_IMASK2; struct { uint32 BUF31TO0M : 32; } CAN_IMASK1; struct { uint32 BUF63TO32I : 32; } CAN_IFLAG2; struct { uint32 BUF0I : 1; uint32 BUF4TO1I : 4; uint32 BUF5I : 1; uint32 BUF6I : 1; uint32 BUF7I : 1; uint32 BUF31TO8I : 24; } CAN_IFLAG1; struct { uint32 RSVD_10_0 : 11; uint32 EDFLTDIS : 1; uint32 ISOCANFDEN : 1; uint32 RSVD_13 : 1; uint32 PREXCEN : 1; uint32 TIMER_SRC : 1; uint32 EACEN : 1; uint32 RRS : 1; uint32 MRP : 1; uint32 TASD : 5; uint32 RFFN : 4; uint32 WRMFRZ : 1; uint32 ECRWRE : 1; uint32 BOFFDONEMSK : 1; uint32 ERRMASK_FAST : 1; } CAN_CTRL2; struct { uint32 RSVD_12_0 : 13; uint32 IMB : 1; uint32 VPS : 1; uint32 RSVD_15 : 1; uint32 LPTM : 7; uint32 RSVD_31_23 : 9; } CAN_ESR2; uint8 zResverd0x03C[8]; struct { uint32 TXCRC : 15; uint32 RSVD_15 : 1; uint32 MBCRC : 7; uint32 RSVD_31_23 : 9; } CAN_CRCR; struct { uint32 FGM : 32; } CAN_RXFGMASK; struct { uint32 IDHIT : 9; uint32 RSVD_31_9 : 23; } CAN_RXFIR; struct { uint32 EPSEG2 : 5; uint32 EPSEG1 : 5; uint32 EPROPSEG : 6; uint32 ERJW : 5; uint32 EPRESDIV : 10; uint32 BTF : 1; } CAN_CBT; uint8 zResverd0x054[20]; struct { uint32 BUF127TO96M : 32; } CAN_IMASK4; struct { uint32 BUF95TO64M : 32; } CAN_IMASK3; struct { uint32 BUF127TO96I : 32; } CAN_IFLAG4; struct { uint32 BUF95TO64I : 32; } CAN_IFLAG3; uint8 zResverd0x078[8]; struct { struct { uint32 TIME_STAMP : 16; uint32 DLC : 4; uint32 RTR : 1; uint32 IDE : 1; uint32 SRR : 1; uint32 RSVD_23 : 1; uint32 CODE : 4; uint32 RSVD_28 : 1; uint32 ESI : 1; uint32 BRS : 1; uint32 EDL : 1; } CAN_MB_CS; struct { uint32 ID_EXTEND : 18; uint32 ID_STD_EXD : 11; uint32 PRIO : 3; } CAN_MB_ID; struct { uint32 DATA_BYTE03 : 32; } CAN_MB_DATA03; struct { uint32 DATA_BYTE47 : 32; } CAN_MB_DATA47; } CAN_MB[128]; struct { uint32 MI : 32; } CAN_RXIMRn[128]; uint8 zResverd0x0A80[96]; struct { uint32 RSVD_6_0 : 7; uint32 NCEFAFRZ : 1; uint32 ECCDIS : 1; uint32 RERRDIS : 1; uint32 RSVD_12_10 : 3; uint32 EXTERRIE : 1; uint32 FAERRIE : 1; uint32 HAERRI : 1; uint32 CEI_MSK : 1; uint32 RSVD_17 : 1; uint32 FANCEI_MSK : 1; uint32 HANCEI_MSK : 1; uint32 RSVD_30_20 : 11; uint32 ECRWRDIS : 1; } CAN_MECR; struct { uint32 INJADDR_L : 2; uint32 INJADDR_H : 12; uint32 RSVD_31_14 : 18; } CAN_ERRIAR; struct { uint32 DFLIP : 32; } CAN_ERRIDPR; struct { uint32 PFLIP0 : 5; uint32 RSVD_7_5 : 3; uint32 PFLIP1 : 5; uint32 RSVD_15_13 : 3; uint32 PFLIP2 : 5; uint32 RSVD_23_21 : 3; uint32 PFLIP3 : 5; uint32 RSVD_31_29 : 3; } CAN_ERRIPPR; struct { uint32 ERRADDR : 14; uint32 RSVD_15_14 : 2; uint32 SAID : 3; uint32 RSVD_23_19 : 5; uint32 NCE : 1; uint32 RSVD_31_25 : 7; } CAN_RERRAR; struct { uint32 RDATA : 32; } CAN_RERRDR; struct { uint32 SYND0 : 5; uint32 RSVD_6_5 : 2; uint32 BE0 : 1; uint32 SYND1 : 5; uint32 RSVD_14_13 : 2; uint32 BE1 : 1; uint32 SYND2 : 5; uint32 RSVD_22_21 : 2; uint32 BE2 : 1; uint32 SYND3 : 5; uint32 RSVD_30_29 : 2; uint32 BE3 : 1; } CAN_RERRSYNR; struct { uint32 CEIOF : 1; uint32 RSVD_1 : 1; uint32 FANCEIOF : 1; uint32 HANCEIOF : 1; uint32 RSVD_15_4 : 12; uint32 CEIF : 1; uint32 RSVD_17 : 1; uint32 FANCEIF : 1; uint32 HANCEIF : 1; uint32 RSVD_31_20 : 12; } CAN_ERRSR; struct { uint32 FCS : 2; uint32 IDFS : 2; uint32 PLFS : 2; uint32 RSVD_7_6 : 2; uint32 NMATCH : 8; uint32 WUMF_MSK : 1; uint32 WTOF_MSK : 1; uint32 RSVD_31_18 : 14; } CAN_CTRL1_PN; struct { uint32 MATCHTO : 16; uint32 RSVD_31_16 : 16; } CAN_CTRL2_PN; struct { uint32 RSVD_7_0 : 8; uint32 MCOUNTER : 8; uint32 WUMF : 1; uint32 WTOF : 1; uint32 RSVD_31_18 : 14; } CAN_WU_MTC; struct { uint32 FLT_ID1 : 29; uint32 FLT_RTR : 1; uint32 FLT_IDE : 1; uint32 RSVD_31 : 1; } CAN_FLT_ID1; struct { uint32 FLT_DLC_HI : 4; uint32 RSVD_15_4 : 12; uint32 FLT_DLC_LO : 4; uint32 RSVD_31_20 : 12; } CAN_FLT_DLC; struct { uint32 DATA_BYTE_3 : 8; uint32 DATA_BYTE_2 : 8; uint32 DATA_BYTE_1 : 8; uint32 DATA_BYTE_0 : 8; } CAN_PL1_LO; struct { uint32 DATA_BYTE_7 : 8; uint32 DATA_BYTE_6 : 8; uint32 DATA_BYTE_5 : 8; uint32 DATA_BYTE_4 : 8; } CAN_PL1_HI; struct { uint32 FLT_ID2_IDMASK : 29; uint32 RTR_MSK : 1; uint32 IDE_MSK : 1; uint32 RSVD_31 : 1; } CAN_FLT_ID2_IDMASK; struct { uint32 DATA_BYTE_3 : 8; uint32 DATA_BYTE_2 : 8; uint32 DATA_BYTE_1 : 8; uint32 DATA_BYTE_0 : 8; } CAN_PL2_PLMASK_LO; struct { uint32 DATA_BYTE_7 : 8; uint32 DATA_BYTE_6 : 8; uint32 DATA_BYTE_5 : 8; uint32 DATA_BYTE_4 : 8; } CAN_PL2_PLMASK_HI; uint8 zResverd0x0B28[24]; struct { struct { uint32 RSVD_15_0 : 16; uint32 DLC : 4; uint32 RTR : 1; uint32 IDE : 1; uint32 SRR : 1; uint32 RSVD_31_23 : 9; } CAN_WMB_CS; struct { uint32 ID : 29; uint32 RSVD_31_29 : 3; } CAN_WMB_ID; struct { uint32 DATA_BYTE_3 : 8; uint32 DATA_BYTE_2 : 8; uint32 DATA_BYTE_1 : 8; uint32 DATA_BYTE_0 : 8; } CAN_WMB_D03; struct { uint32 DATA_BYTE_7 : 8; uint32 DATA_BYTE_6 : 8; uint32 DATA_BYTE_5 : 8; uint32 DATA_BYTE_4 : 8; } CAN_WMB_D47; } CAN_WMB[4]; uint8 zResverd0x0B80[128]; struct { uint32 TDCVAL : 6; uint32 RSVD_7_6 : 2; uint32 TDCOFF : 5; uint32 RSVD_13 : 1; uint32 TDCFAIL : 1; uint32 TDCEN : 1; uint32 MBDSR0 : 2; uint32 RSVD_18 : 1; uint32 MBDSR1 : 2; uint32 RSVD_21 : 1; uint32 MBDSR2 : 2; uint32 RSVD_24 : 1; uint32 MBDSR3 : 2; uint32 RSVD_30_27 : 4; uint32 FD_RATE : 1; } CAN_FDCTRL; struct { uint32 FPSEG2 : 3; uint32 RSVD_4_3 : 2; uint32 FPSEG1 : 3; uint32 RSVD_9_8 : 2; uint32 FPROPSEG : 5; uint32 RSVD_15 : 1; uint32 FRJW : 3; uint32 RSVD_19 : 1; uint32 FPRESDIV : 10; uint32 RSVD_31_30 : 2; } CAN_FDCBT; struct { uint32 FD_TXCRC : 21; uint32 RSVD_23_21 : 3; uint32 FD_MBCRC : 7; uint32 RSVD_31 : 1; } CAN_FDCRC; }; struct Reg_Can_W { uint32 CAN_MCR; uint32 CAN_CTRL1; uint32 CAN_TIMER; uint8 zResverd0x0C[4]; uint32 CAN_RXMGMSK; uint32 CAN_RX14MASK; uint32 CAN_RX15MASK; uint32 CAN_ECR; uint32 CAN_ESR1; uint32 CAN_IMASK2; uint32 CAN_IMASK1; uint32 CAN_IFLAG2; uint32 CAN_IFLAG1; uint32 CAN_CTRL2; uint32 CAN_ESR2; uint8 zResverd0x03C[8]; uint32 CAN_CRCR; uint32 CAN_RXFGMASK; uint32 CAN_RXFIR; uint32 CAN_CBT; uint8 zResverd0x054[20]; uint32 CAN_IMASK4; uint32 CAN_IMASK3; uint32 CAN_IFLAG4; uint32 CAN_IFLAG3; uint8 zResverd0x078[8]; struct { uint32 MB0; uint32 MB1; uint32 MB2; uint32 MB3; } CAN_MB[128]; uint32 CAN_RXIMR[128]; uint8 zResverd0x0A80[96]; uint32 CAN_MECR; uint32 CAN_ERRIAR; uint32 CAN_ERRIDPR; uint32 CAN_ERRIPPR; uint32 CAN_RERRAR; uint32 CAN_RERRDR; uint32 CAN_RERRSYNR; uint32 CAN_ERRSR; uint32 CAN_CTRL1_PN; uint32 CAN_CTRL2_PN; uint32 CAN_WU_MTC; uint32 CAN_FLT_ID1; uint32 CAN_FLT_DLC; uint32 CAN_PL1_LO; uint32 CAN_PL1_HI; uint32 CAN_FLT_ID2_IDMASK; uint32 CAN_PL2_PLMASK_LO; uint32 CAN_PL2_PLMASK_HI; uint8 zResverd0x0B28[24]; struct { uint32 CAN_WMB_CS; uint32 CAN_WMB_ID; uint32 CAN_WMB_D03; uint32 CAN_WMB_D47; } CAN_WMB[4]; uint8 zResverd0x0B80[128]; uint32 CAN_FDCTRL; uint32 CAN_FDCBT; uint32 CAN_FDCRC; }; typedef volatile struct Reg_Can_Bf Reg_Can_BfType; typedef volatile struct Reg_Can_W Reg_Can_WType; struct Reg_Cmp_Bf { uint32 zResverd0x0; struct { uint32 DAC_RES : 4; uint32 RSVD_31_4 : 28; } CMP_PARAM; struct { uint32 CMP_SEL : 1; uint32 CMP_EN : 1; uint32 SOC_TRG_EN : 1; uint32 STOP_EN : 1; uint32 RSVD_31_4 : 28; } CMP_CCR0; struct { uint32 WINDOW_EN : 1; uint32 SAMPLE_EN : 1; uint32 DMA_EN : 1; uint32 COUT_INV : 1; uint32 COUT_SEL : 1; uint32 COUT_PEN : 1; uint32 COUT_OWE : 1; uint32 COUT_OW : 1; uint32 RSVD_15_8 : 8; uint32 FILT_CNT : 3; uint32 RSVD_23_19 : 5; uint32 FILT_PER : 8; } CMP_CCR1; struct { uint32 HS_HSTCTR : 2; uint32 RSVD_3_2 : 2; uint32 LS_HSTCTR : 2; uint32 RSVD_15_6 : 10; uint32 HS_PSEL : 4; uint32 HS_MSEL : 4; uint32 LS_PSEL : 4; uint32 LS_MSEL : 4; } CMP_CCR2; struct { uint32 DAC_EN : 1; uint32 DAC_BUFF_EN : 1; uint32 RSVD_7_2 : 6; uint32 VREF_SEL : 1; uint32 RSVD_15_9 : 7; uint32 DAC_SEL : 8; uint32 RSVD_31_24 : 8; } CMP_DCR; struct { uint32 CFR_IE : 1; uint32 CFF_IE : 1; uint32 RSVD_31_2 : 30; } CMP_IER; struct { uint32 CFR : 1; uint32 CFF : 1; uint32 RSVD_7_2 : 6; uint32 COUT : 1; uint32 RSVD_31_9 : 23; } CMP_CSR; }; struct Reg_Cmp_W { uint32 zResverd0x0; uint32 CMP_PARAM; uint32 CMP_CCR0; uint32 CMP_CCR1; uint32 CMP_CCR2; uint32 CMP_DCR; uint32 CMP_IER; uint32 CMP_CSR; }; typedef volatile struct Reg_Cmp_Bf Reg_Cmp_BfType; typedef volatile struct Reg_Cmp_W Reg_Cmp_WType; struct Reg_Cmu_Bf { uint32 zResverd0x0; struct { uint32 RST_IMP : 1; uint32 RSVD_31_1 : 31; } CMU_PARAM; struct { uint32 CME : 1; uint32 RSVD_3_1 : 3; uint32 CMMD : 1; uint32 RSVD_7_5 : 3; uint32 FAHTRSTE : 1; uint32 FBLTRSTE : 1; uint32 RSVD_15_10 : 6; uint32 FAHTIE : 1; uint32 FBLTIE : 1; uint32 RSVD_30_18 : 13; uint32 LOCK : 1; } CMU_CTRL; struct { uint32 MONST : 2; uint32 RSVD_3_2 : 2; uint32 STARTMEA : 1; uint32 RSVD_15_5 : 11; uint32 FAHTIF : 1; uint32 FBLTIF : 1; uint32 RSVD_31_18 : 14; } CMU_STAT; struct { uint32 MONWIN : 32; } CMU_MONWIN; struct { uint32 HCT4INT : 32; } CMU_CUMHCT4INT; struct { uint32 LCT4INT : 32; } CMU_CUMLCT4INT; struct { uint32 HCT4RST : 32; } CMU_CUMHCT4RST; struct { uint32 LCT4RST : 32; } CMU_CUMLCT4RST; struct { uint32 MEARSLT : 32; } CMU_CUMMEARSLT; }; struct Reg_Cmu_W { uint32 zResverd0x0; uint32 CMU_PARAM; uint32 CMU_CTRL; uint32 CMU_STAT; uint32 CMU_MONWIN; uint32 CMU_CUMHCT4INT; uint32 CMU_CUMLCT4INT; uint32 CMU_CUMHCT4RST; uint32 CMU_CUMLCT4RST; uint32 CMU_CUMMEARSLT; }; typedef volatile struct Reg_Cmu_Bf Reg_Cmu_BfType; typedef volatile struct Reg_Cmu_W Reg_Cmu_WType; struct Reg_Crc_Bf { uint32 zResverd0x0; struct { uint32 RSVD_31_0 : 32; } CRC_PARAM; struct { uint32 BYTE0 : 8; uint32 BYTE1 : 8; uint32 BYTE2 : 8; uint32 BYTE3 : 8; } CRC_DATA; struct { uint32 LPHW : 16; uint32 HPHW : 16; } CRC_POLY; struct { uint32 MODE : 1; uint32 WS : 1; uint32 CR : 1; uint32 RSVD_3 : 1; uint32 RT : 2; uint32 WT : 2; uint32 RSVD_31_8 : 24; } CRC_CTRL; }; struct Reg_Crc_W { uint32 zResverd0x0; uint32 CRC_PARAM; uint32 CRC_DATA; uint32 CRC_POLY; uint32 CRC_CTRL; }; typedef volatile struct Reg_Crc_Bf Reg_Crc_BfType; typedef volatile struct Reg_Crc_W Reg_Crc_WType; struct Reg_Dmamux_Bf { struct { uint32 ENABLE : 1; uint32 SRC_MUX : 7; uint32 RSVD_31_8 : 24; } DMA_MUX_CH_CFG[16]; }; struct Reg_Dmamux_W { uint32 DMA_MUX_CH_CFG[16]; }; struct Reg_Dma_Bf { struct { uint32 HALT : 1; uint32 HOEE : 1; uint32 RRCAE : 1; uint32 DBGE : 1; uint32 RSVD_5_4 : 2; uint32 BUSY : 1; uint32 RSVD_31_7 : 25; } DMA_CONF; struct { uint32 DMAE0 : 1; uint32 DMAE1 : 1; uint32 DMAE2 : 1; uint32 DMAE3 : 1; uint32 DMAE4 : 1; uint32 DMAE5 : 1; uint32 DMAE6 : 1; uint32 DMAE7 : 1; uint32 DMAE8 : 1; uint32 DMAE9 : 1; uint32 DMAE10 : 1; uint32 DMAE11 : 1; uint32 DMAE12 : 1; uint32 DMAE13 : 1; uint32 DMAE14 : 1; uint32 DMAE15 : 1; uint32 RSVD_31_16 : 16; } DMA_DMAE; uint8 zResverd0x08[4]; struct { uint32 EIE0 : 1; uint32 EIE1 : 1; uint32 EIE2 : 1; uint32 EIE3 : 1; uint32 EIE4 : 1; uint32 EIE5 : 1; uint32 EIE6 : 1; uint32 EIE7 : 1; uint32 EIE8 : 1; uint32 EIE9 : 1; uint32 EIE10 : 1; uint32 EIE11 : 1; uint32 EIE12 : 1; uint32 EIE13 : 1; uint32 EIE14 : 1; uint32 EIE15 : 1; uint32 RSVD_31_16 : 16; } DMA_EIE; uint8 zResverd0x010[4]; struct { uint32 CCDONE : 4; uint32 RSVD_5_4 : 2; uint32 CACDONE : 1; uint32 WPEN0 : 1; uint32 SCSTART : 4; uint32 RSVD_13_12 : 2; uint32 SACSTART : 1; uint32 WPEN1 : 1; uint32 CCES : 4; uint32 RSVD_21_20 : 2; uint32 CACES : 1; uint32 WPEN2 : 1; uint32 CCIS : 4; uint32 RSVD_29_28 : 2; uint32 CACIS : 1; uint32 WPEN3 : 1; } DMA_GCC; struct { uint32 DBEF : 1; uint32 SBEF : 1; uint32 RSVD_2 : 1; uint32 NUMEF : 1; uint32 DOEF : 1; uint32 DAEF : 1; uint32 SOEF : 1; uint32 SAEF : 1; uint32 CHEF : 4; uint32 RSVD_12 : 1; uint32 PRIEF : 1; uint32 RSVD_14 : 1; uint32 ERRF : 1; uint32 RSVD_31_16 : 16; } DMA_ES; struct { uint32 ERR0 : 1; uint32 ERR1 : 1; uint32 ERR2 : 1; uint32 ERR3 : 1; uint32 ERR4 : 1; uint32 ERR5 : 1; uint32 ERR6 : 1; uint32 ERR7 : 1; uint32 ERR8 : 1; uint32 ERR9 : 1; uint32 ERR10 : 1; uint32 ERR11 : 1; uint32 ERR12 : 1; uint32 ERR13 : 1; uint32 ERR14 : 1; uint32 ERR15 : 1; uint32 RSVD_31_16 : 16; } DMA_CES; struct { uint32 INT0 : 1; uint32 INT1 : 1; uint32 INT2 : 1; uint32 INT3 : 1; uint32 INT4 : 1; uint32 INT5 : 1; uint32 INT6 : 1; uint32 INT7 : 1; uint32 INT8 : 1; uint32 INT9 : 1; uint32 INT10 : 1; uint32 INT11 : 1; uint32 INT12 : 1; uint32 INT13 : 1; uint32 INT14 : 1; uint32 INT15 : 1; uint32 RSVD_31_16 : 16; } DMA_CIS; struct { uint32 HRS0 : 1; uint32 HRS1 : 1; uint32 HRS2 : 1; uint32 HRS3 : 1; uint32 HRS4 : 1; uint32 HRS5 : 1; uint32 HRS6 : 1; uint32 HRS7 : 1; uint32 HRS8 : 1; uint32 HRS9 : 1; uint32 HRS10 : 1; uint32 HRS11 : 1; uint32 HRS12 : 1; uint32 HRS13 : 1; uint32 HRS14 : 1; uint32 HRS15 : 1; uint32 RSVD_31_16 : 16; } DMA_CHRS; struct { uint32 CPRI3 : 4; uint32 RSVD_5_4 : 2; uint32 CPDIS3 : 1; uint32 CSE3 : 1; uint32 CPRI2 : 4; uint32 RSVD_13_12 : 2; uint32 CPDIS2 : 1; uint32 CSE2 : 1; uint32 CPRI1 : 4; uint32 RSVD_21_20 : 2; uint32 CPDIS1 : 1; uint32 CSE1 : 1; uint32 CPRI0 : 4; uint32 RSVD_29_28 : 2; uint32 CPDIS0 : 1; uint32 CSE0 : 1; } DMA_CPRI0; struct { uint32 CPRI7 : 4; uint32 RSVD_5_4 : 2; uint32 CPDIS7 : 1; uint32 CSE7 : 1; uint32 CPRI6 : 4; uint32 RSVD_13_12 : 2; uint32 CPDIS6 : 1; uint32 CSE6 : 1; uint32 CPRI5 : 4; uint32 RSVD_21_20 : 2; uint32 CPDIS5 : 1; uint32 CSE5 : 1; uint32 CPRI4 : 4; uint32 RSVD_29_28 : 2; uint32 CPDIS4 : 1; uint32 CSE4 : 1; } DMA_CPRI1; struct { uint32 CPRI11 : 4; uint32 RSVD_5_4 : 2; uint32 CPDIS11 : 1; uint32 CSE11 : 1; uint32 CPRI10 : 4; uint32 RSVD_13_12 : 2; uint32 CPDIS10 : 1; uint32 CSE10 : 1; uint32 CPRI9 : 4; uint32 RSVD_21_20 : 2; uint32 CPDIS9 : 1; uint32 CSE9 : 1; uint32 CPRI8 : 4; uint32 RSVD_29_28 : 2; uint32 CPDIS8 : 1; uint32 CSE8 : 1; } DMA_CPRI2; struct { uint32 CPRI15 : 4; uint32 RSVD_5_4 : 2; uint32 CPDIS15 : 1; uint32 CSE15 : 1; uint32 CPRI14 : 4; uint32 RSVD_13_12 : 2; uint32 CPDIS14 : 1; uint32 CSE14 : 1; uint32 CPRI13 : 4; uint32 RSVD_21_20 : 2; uint32 CPDIS13 : 1; uint32 CSE13 : 1; uint32 CPRI12 : 4; uint32 RSVD_29_28 : 2; uint32 CPDIS12 : 1; uint32 CSE12 : 1; } DMA_CPRI3; uint8 zResverd0x038[456]; struct { struct { uint32 SADDR : 32; } DMA_SADDR; struct { uint32 DADDR : 32; } DMA_DADDR; struct { sint32 SAOFF : 16; sint32 DAOFF : 16; } DMA_AOFF; struct { sint32 MLSAOFF : 16; sint32 MLDAOFF : 16; } DMA_MLAOFF; struct { uint32 NUM : 32; } DMA_NUM; struct { uint32 MLITER : 16; uint32 MLSTA : 16; } DMA_ITER; struct { uint32 START : 1; uint32 INTE : 1; uint32 RSVD_2 : 1; uint32 REQDIS : 1; uint32 RSVD_5_4 : 2; uint32 BUSY : 1; uint32 DONE : 1; uint32 RSVD_15_8 : 8; uint32 DSIZE : 2; uint32 RSVD_23_18 : 6; uint32 SSIZE : 2; uint32 RSVD_31_26 : 6; } DMA_CS; uint8 zResverd[4]; } DMA_CH_CONFIG[16]; }; struct Reg_Dma_W { uint32 DMA_CONF; uint32 DMA_DMAE; uint8 zResverd0x08[4]; uint32 DMA_EIE; uint8 zResverd0x010[4]; uint32 DMA_GCC; uint32 DMA_ES; uint32 DMA_CES; uint32 DMA_CIS; uint32 DMA_CHRS; uint32 DMA_CPRI0; uint32 DMA_CPRI1; uint32 DMA_CPRI2; uint32 DMA_CPRI3; uint8 zResverd0x038[456]; struct { uint32 DMA_SADDR; uint32 DMA_DADDR; uint32 DMA_AOFF; uint32 DMA_MLAOFF; uint32 DMA_NUM; uint32 DMA_ITER; uint32 DMA_CS; uint8 zResverd[4]; } DMA_CH_CONFIG[16]; }; typedef volatile struct Reg_Dmamux_Bf Reg_Dmamux_BfType; typedef volatile struct Reg_Dmamux_W Reg_Dmamux_WType; typedef volatile struct Reg_Dma_Bf Reg_Dma_BfType; typedef volatile struct Reg_Dma_W Reg_Dma_WType; struct Reg_Eiru_Bf { struct { uint32 SRAM0_ER_DIS : 1; uint32 SRAM0_EW_DIS : 1; uint32 SRAM0_ESB_DIS : 1; uint32 SRAM0_EMB_DIS : 1; uint32 SRAM0_EEI_EN : 1; uint32 RSVD_7_5 : 3; uint32 SRAM1_ER_DIS : 1; uint32 SRAM1_EW_DIS : 1; uint32 SRAM1_ESB_DIS : 1; uint32 SRAM1_EMB_DIS : 1; uint32 SRAM1_EEI_EN : 1; uint32 RSVD_30_13 : 18; uint32 LOCK : 1; } EIRU_CR; struct { uint32 RSVD_1_0 : 2; uint32 EEIADDR : 30; } EIRU_EEIADDR; uint8 zResverd0x08[8]; struct { struct { uint32 EFPROT : 4; uint32 EFSIZE : 3; uint32 RSVD_7 : 1; uint32 EFMST : 8; uint32 RSVD_28_16 : 13; uint32 SBERR : 1; uint32 MBERR : 1; uint32 OVERRUN : 1; } EIRU_SRAMn_EESR; struct { uint32 EFADDR : 32; } EIRU_SRAMn_FADDR; struct { uint32 EFDATA : 32; } EIRU_SRAMn_FDATA; struct { uint32 ECCMASK : 7; uint32 RSVD_31_7 : 25; } EIRU_SRAMn_ECCMASK; struct { uint32 DATAMASK : 32; } EIRU_SRAMn_DATAMASK; uint8 zResverd0x024[12]; } EIRU_SRAMn_SC[2]; }; struct Reg_Eiru_W { uint32 EIRU_CR; uint32 EIRU_EEIADDR; uint8 zResverd0x08[8]; struct { uint32 EIRU_SRAMn_EESR; uint32 EIRU_SRAMn_FADDR; uint32 EIRU_SRAMn_FDATA; uint32 EIRU_SRAMn_ECCMASK; uint32 EIRU_SRAMn_DATAMASK; uint8 zResverd0x024[12]; } EIRU_SRAMn_SC[2]; }; typedef volatile struct Reg_Eiru_Bf Reg_Eiru_BfType; typedef volatile struct Reg_Eiru_W Reg_Eiru_WType; struct Reg_Ewdt_Bf { uint32 zResverd0x0; struct { uint32 RSVD_31_0 : 32; } EWDT_PARAM; struct { uint32 EWDTE : 1; uint32 DEBUGE : 1; uint32 WAITE : 1; uint32 RSVD_3 : 1; uint32 INTE : 1; uint32 INPE : 1; uint32 INPP : 1; uint32 RSVD_23_7 : 17; uint32 INTF : 1; uint32 RSVD_31_25 : 7; } EWDT_CS; struct { uint32 COMPH : 32; } EWDT_COMPH; struct { uint32 COMPL : 32; } EWDT_COMPL; struct { uint32 CNT : 32; } EWDT_CNT; }; struct Reg_Ewdt_W { uint32 zResverd0x0; uint32 EWDT_PARAM; uint32 EWDT_CS; uint32 EWDT_COMPH; uint32 EWDT_COMPL; uint32 EWDT_CNT; }; typedef volatile struct Reg_Ewdt_Bf Reg_Ewdt_BfType; typedef volatile struct Reg_Ewdt_W Reg_Ewdt_WType; struct Reg_Flash_Bf { struct { uint32 FAIL : 1; uint32 RSVD_1 : 1; uint32 CMDABT : 1; uint32 RSVD_4_3 : 2; uint32 ACCERR : 1; uint32 PREABT : 1; uint32 CCIF : 1; uint32 RSVD_10_8 : 3; uint32 CMDWRF : 1; uint32 RSVD_15_12 : 4; uint32 DFDIF : 1; uint32 SFDIF : 1; uint32 RSVD_29_18 : 12; uint32 DBG_ERSALL_DIS : 1; uint32 FSEC : 1; } FLASH_FSTAT; struct { uint32 BK_QUERY : 1; uint32 RSVD_6_1 : 6; uint32 CCIE : 1; uint32 DBG_ERS_FLG : 1; uint32 RSVD_15_9 : 7; uint32 DFDIE : 1; uint32 SFDIE : 1; uint32 RSVD_31_18 : 14; } FLASH_FCNFG; struct { uint32 RWSC : 4; uint32 RSVD_7_4 : 4; uint32 LSMODE : 1; uint32 RSVD_15_9 : 7; uint32 FECCF : 1; uint32 RSVD_23_17 : 7; uint32 ABTREQ : 1; uint32 RSVD_31_25 : 7; } FLASH_FCTRL; uint8 zResverd0x0C[4]; struct { uint32 CMDCODE : 8; uint32 RSVD_31_8 : 24; } FLASH_FCMD; uint8 zResverd0x14[4]; struct { uint32 CMDADDR : 32; } FLASH_FADDR; struct { uint32 CMDADDRE : 32; } FLASH_FADDR_END; struct { uint32 CMDDATA0 : 32; } FLASH_FDATA0; struct { uint32 CMDDATA1 : 32; } FLASH_FDATA1; struct { uint32 CMDDATA2 : 32; } FLASH_FDATA2; struct { uint32 CMDDATA3 : 32; } FLASH_FDATA3; struct { uint32 RSVD_3_0 : 4; uint32 BED_ADDR_STRT : 28; } FLASH_BED_ADDR_STRT; struct { uint32 RSVD_3_0 : 4; uint32 BED_ADDR_END : 28; } FLASH_BED_ADDR_END; struct { uint32 RSVD_3_0 : 4; uint32 ECC_IN_ADDR : 28; } FLASH_ECC_IN_ADDR; struct { uint32 ECC_9BIT : 9; uint32 ECC_IN_EN : 1; uint32 RSVD_30_10 : 21; uint32 LOCK : 1; } FLASH_ECC_IN_CTRL; struct { uint32 MBE_FLAG : 1; uint32 MBE_OVERRUN : 1; uint32 RSVD_3_2 : 2; uint32 MBE_ADDR : 28; } FLASH_MBE_STATE; struct { uint32 SBE_FLAG : 1; uint32 SBE_OVERRUN : 1; uint32 RSVD_3_2 : 2; uint32 SBE_ADDR : 28; } FLASH_SBE_STATE; }; struct Reg_Flash_W { uint32 FLASH_FSTAT; uint32 FLASH_FCNFG; uint32 FLASH_FCTRL; uint8 zResverd0x0C[4]; uint32 FLASH_FCMD; uint8 zResverd0x14[4]; uint32 FLASH_FADDR; uint32 FLASH_FADDR_END; uint32 FLASH_FDATA0; uint32 FLASH_FDATA1; uint32 FLASH_FDATA2; uint32 FLASH_FDATA3; uint32 FLASH_BED_ADDR_STRT; uint32 FLASH_BED_ADDR_END; uint32 FLASH_ECC_IN_ADDR; uint32 FLASH_ECC_IN_CTRL; uint32 FLASH_MBE_STATE; uint32 FLASH_SBE_STATE; }; typedef volatile struct Reg_Flash_Bf Reg_Flash_BfType; typedef volatile struct Reg_Flash_W Reg_Flash_WType; struct Reg_Gpio_Bf { struct { uint32 PDO : 32; } GPIOx_PDOR; struct { uint32 PSO : 32; } GPIOx_PSOR; struct { uint32 PCO : 32; } GPIOx_PCOR; struct { uint32 PTO : 32; } GPIOx_PTOR; struct { uint32 PDI : 32; } GPIOx_PDIR; struct { uint32 PDD : 32; } GPIOx_PDDR; }; struct Reg_Gpio_W { uint32 GPIOx_PDOR; uint32 GPIOx_PSOR; uint32 GPIOx_PCOR; uint32 GPIOx_PTOR; uint32 GPIOx_PDIR; uint32 GPIOx_PDDR; }; typedef volatile struct Reg_Gpio_Bf Reg_Gpio_BfType; typedef volatile struct Reg_Gpio_W Reg_Gpio_WType; struct Reg_I2c_Bf { uint32 zResverd0x00; struct { uint32 I2C_SUPPORT_SPEED : 2; uint32 DMA_SUPPORT : 1; uint32 TXFIFO_DEPTH : 4; uint32 RXFIFO_DEPTH : 4; uint32 RSVD_31_11 : 21; } I2C_PARAMETER; struct { uint32 MODULE_EN : 1; uint32 SLAVE_ACK_GENCALL : 1; uint32 SLAVE_NACK : 1; uint32 SDA_RECOVER_EN : 1; uint32 MASTER_ABORT : 1; uint32 MASTER_BUS_RECOVER_EN : 1; uint32 MASTER_BLK_TXFIFO : 1; uint32 H_MCODE : 3; uint32 RSVD_31_10 : 22; } I2C_CONFIG0; struct { uint32 SLAVE_MODE_DIS : 1; uint32 MASTER_MODE_EN : 1; uint32 MASTER_RESTART_EN : 1; uint32 SLAVE_STOP_DET_EN : 1; uint32 MASTER_STOP_DET_EN : 1; uint32 TXFIFO_EMPTY_EN : 1; uint32 SPEED_SEL : 2; uint32 HOLD_EN_RXFIFO_FULL : 1; uint32 SLAVE_10BIT_ADDR_SEL : 1; uint32 MASTER_10BIT_ADDR_SEL : 1; uint32 RSVD_31_11 : 21; } I2C_CONFIG1; struct { uint32 SDA_SETUP_TIMING : 8; uint32 RSVD_31_8 : 24; } I2C_SDA_SETUP_TIMING; struct { uint32 SDA_TX_HOLD_TIMING : 16; uint32 SDA_RX_HOLD_TIMING : 8; uint32 RSVD_31_24 : 8; } I2C_SDA_HOLD_TIMING; struct { uint32 RXFIFO_DMA_EN : 1; uint32 TXFIFO_DMA_EN : 1; uint32 DMA_TXFIFO_WATERMARK : 2; uint32 DMA_RXFIFO_WATERMARK : 2; uint32 RSVD_31_6 : 26; } I2C_DMA_CTRL; struct { uint32 I2C_CALL_IE : 1; uint32 I2C_TX_OVF_IE : 1; uint32 I2C_ERROR_ABORT_IE : 1; uint32 I2C_ACTIVITY_DET_IE : 1; uint32 I2C_STOP_DET_IE : 1; uint32 I2C_START_DET_IE : 1; uint32 RSVD_21_6 : 16; uint32 SLAVE_RD_REQ_IE : 1; uint32 RX_DONE_IE : 1; uint32 RX_UNDER_IE : 1; uint32 RX_OVF_IE : 1; uint32 RESTART_DET_IE : 1; uint32 SCL_STUCK_AT_LOW_IE : 1; uint32 RSVD_29_28 : 2; uint32 RX_FULL_IE : 1; uint32 TX_EMPTY_IE : 1; } I2C_INT_ENABLE; struct { uint32 DATA : 8; uint32 CMD_MASTER_DIRECTION : 1; uint32 CMD_STOP : 1; uint32 CMD_RESTART : 1; uint32 RSVD_31_11 : 21; } I2C_COMMAND_DATA; struct { uint32 DEST_ADDR : 10; uint32 MASTER_CMD_SEL : 2; uint32 RSVD_31_12 : 20; } I2C_DEST_ADDR; struct { uint32 SLV_ADDR : 10; uint32 RSVD_31_10 : 22; } I2C_SLAVE_ADDR; struct { uint32 STD_SCL_HCNT : 16; uint32 RSVD_31_16 : 16; } I2C_STD_SCL_HCNT; struct { uint32 STD_SCL_LCNT : 16; uint32 RSVD_31_16 : 16; } I2C_STD_SCL_LCNT; struct { uint32 FST_SCL_HCNT : 16; uint32 RSVD_31_16 : 16; } I2C_FST_SCL_HCNT; struct { uint32 FST_SCL_LCNT : 16; uint32 RSVD_31_16 : 16; } I2C_FST_SCL_LCNT; struct { uint32 HS_SCL_HCNT : 16; uint32 RSVD_31_16 : 16; } I2C_HS_SCL_HCNT; struct { uint32 HS_SCL_LCNT : 16; uint32 RSVD_31_16 : 16; } I2C_HS_SCL_LCNT; struct { uint32 RXFIFO_WATER_MARK : 2; uint32 RSVD_31_2 : 30; } I2C_RXFIFO_WATER_MARK; struct { uint32 TXFIFO_WATER_MARK : 2; uint32 RSVD_31_2 : 30; } I2C_TXFIFO_WATER_MARK; struct { uint32 TX_FIFO_CNT : 3; uint32 RSVD_31_3 : 29; } I2C_TX_FIFO_CNT; struct { uint32 RX_FIFO_CNT : 3; uint32 RSVD_31_3 : 29; } I2C_RX_FIFO_CNT; struct { uint32 FSTD_SPKLEN : 8; uint32 RSVD_31_8 : 24; } I2C_FSTD_SPKCNT; struct { uint32 HS_SPKLEN : 8; uint32 RSVD_31_8 : 24; } I2C_HS_SPKCNT; struct { uint32 GENERAL_CALL : 1; uint32 TXFIFO_OVERUN : 1; uint32 ERROR_ABORT : 1; uint32 ACTIVITY : 1; uint32 STOP_DETECT : 1; uint32 START_DETECT : 1; uint32 RSVD_21_6 : 16; uint32 SLAVE_READ_REQ : 1; uint32 RXFIFO_DONE : 1; uint32 RXFIFO_UNDERUN : 1; uint32 RXFIFO_OVERUN : 1; uint32 RESTART_DET : 1; uint32 SCL_STUCK_AT_LOW : 1; uint32 RSVD_29_28 : 2; uint32 RXFIFO_FULL : 1; uint32 TXFIFO_EMPTY : 1; } I2C_STATUS0; struct { uint32 MASTER_IS_ACTIVE : 1; uint32 SLAVE_IS_ACTIVE : 1; uint32 TXFIFO_EMPTY_MASTER_HOLD : 1; uint32 TXFIFO_EMPTY_SLAVE_HOLD : 1; uint32 RXFIFO_FULL_MASTER_HOLD : 1; uint32 RXFIFO_FULL_SLAVE_HOLD : 1; uint32 TXFIO_IS_NOT_FULL : 1; uint32 TXFIFO_IS_EMPTY : 1; uint32 RXFIFO_IS_NOT_EMPTY : 1; uint32 RXFIO_IS_FULL : 1; uint32 SDA_ERR_RECOVER_STUCK_LOW : 1; uint32 SLAVE_IS_DISABLED_UNDER_ACT : 1; uint32 SLAVE_RX_DATA_DISCARD : 1; uint32 I2C_IS_ENABLE : 1; uint32 RSVD_31_14 : 18; } I2C_STATUS1; struct { uint32 ERR_GEN_CALL_NO_ACK : 1; uint32 ERR_GEN_CALL_READ : 1; uint32 ERR_START_BYTE_ACK_DET : 1; uint32 ERR_SBYTE_NORSTRT : 1; uint32 ERR_H_NO_RSTRT : 1; uint32 ERR_H_MCODE_ACK_DET : 1; uint32 ERR_7BIT_ADDR_NO_ACK : 1; uint32 ERR_10BIT_ADDR1_NO_ACK : 1; uint32 ERR_10BIT_ADDR2_NO_ACK : 1; uint32 ERR_10BIT_READ_NO_RSTRT : 1; uint32 ERR_DATA_NO_ACK : 1; uint32 ERR_MASTER_ABRT : 1; uint32 ERR_MASTER_DIS : 1; uint32 ERR_SLAVE_ARBLOST : 1; uint32 ERR_MASTER_LOST : 1; uint32 ERR_SLAVE_READ_REQ : 1; uint32 ERR_SLAVE_FLUSH_TXFIFO : 1; uint32 ERR_SDA_LOW_TIMEOUT : 1; uint32 ERR_TXFIFO_FLUSH_CNT : 3; uint32 RSVD_31_21 : 11; } I2C_ERROR_STATUS; struct { uint32 SCL_LOW_TIMEOUT : 32; } I2C_SCL_LOW_TIMEOUT; struct { uint32 SDA_LOW_TIMEOUT : 32; } I2C_SDA_LOW_TIMEOUT; struct { uint32 CLR_ERR : 1; uint32 RSVD_31_1 : 31; } I2C_RD_CLR_ERR_STATUS; }; struct Reg_I2c_W { uint32 zResverd0x00; uint32 I2C_PARAMETER; uint32 I2C_CONFIG0; uint32 I2C_CONFIG1; uint32 I2C_SDA_SETUP_TIMING; uint32 I2C_SDA_HOLD_TIMING; uint32 I2C_DMA_CTRL; uint32 I2C_INT_ENABLE; uint32 I2C_COMMAND_DATA; uint32 I2C_DEST_ADDR; uint32 I2C_SLAVE_ADDR; uint32 I2C_STD_SCL_HCNT; uint32 I2C_STD_SCL_LCNT; uint32 I2C_FST_SCL_HCNT; uint32 I2C_FST_SCL_LCNT; uint32 I2C_HS_SCL_HCNT; uint32 I2C_HS_SCL_LCNT; uint32 I2C_RXFIFO_WATER_MARK; uint32 I2C_TXFIFO_WATER_MARK; uint32 I2C_TX_FIFO_CNT; uint32 I2C_RX_FIFO_CNT; uint32 I2C_FSTD_SPKCNT; uint32 I2C_HS_SPKCNT; uint32 I2C_STATUS0; uint32 I2C_STATUS1; uint32 I2C_ERROR_STATUS; uint32 I2C_SCL_LOW_TIMEOUT; uint32 I2C_SDA_LOW_TIMEOUT; uint32 I2C_RD_CLR_ERR_STATUS; }; typedef volatile struct Reg_I2c_Bf Reg_I2c_BfType; typedef volatile struct Reg_I2c_W Reg_I2c_WType; struct Reg_I2s_Bf { struct { uint32 I2S_MODULE_EN : 1; uint32 I2S_TE : 1; uint32 I2S_RE : 1; uint32 I2S_TXFIFO_RESET : 1; uint32 I2S_RXFIFO_RESET : 1; uint32 RSVD_31_5 : 27; } I2S_CONTROL; struct { uint32 I2S_MASTER_EN : 1; uint32 I2S_NUM_BCLK : 2; uint32 RSVD_4_3 : 2; uint32 I2S_NUM_BCLK_GATE : 3; uint32 MCK_DIV : 8; uint32 RSVD_31_16 : 16; } I2S_MASTER_CONFIG; struct { struct { uint32 LEFT_DATA : 32; } I2S_CHn_LEFT_DATA; struct { uint32 RIGHT_DATA : 32; } I2S_CHn_RIGHT_DATA; struct { uint32 TX_EN : 1; uint32 RX_EN : 1; uint32 TX_AUDIO_RESOLUTION : 3; uint32 RX_AUDIO_RESOLUTION : 3; uint32 RSVD_31_8 : 24; } I2S_CHn_CFG; struct { uint32 RXFIFO_AVAILABLE_IE : 1; uint32 RXFIFO_OVERUN_IE : 1; uint32 TXFIFO_EMPTY_IE : 1; uint32 TXFIFO_OVERUN_IE : 1; uint32 RXFIFO_DAF : 1; uint32 RXFIFO_ORF : 1; uint32 TXFIFO_EMPTYF : 1; uint32 TXFIFO_ORF : 1; uint32 RSVD_31_8 : 24; } I2S_CHn_INT_CFG; struct { uint32 RXFIFO_FULL_TRIG_LEV : 4; uint32 TXFIFO_EMPTY_TRIG_LEV : 4; uint32 CH_TXFIFO_RESET : 1; uint32 CH_RXFIFO_RESET : 1; uint32 RSVD_31_10 : 22; } I2S_CHn_TRIGGER_LEVEL_CFG; } I2S_CHANNEL_REG[4]; struct { uint32 CYCLE_TX_DATA : 32; } I2S_CYCLE_TX_DATA; struct { uint32 CYCLE_TX_RESET : 1; uint32 RSVD_31_1 : 31; } I2S_CYCLE_TX_RESET; struct { uint32 CYCLE_RX_DATA : 32; } I2S_CYCLE_RX_DATA; struct { uint32 CYCLE_RX_RESET : 1; uint32 RSVD_31_1 : 31; } I2S_CYCLE_RX_RESET; }; struct Reg_I2s_W { uint32 I2S_CONTROL; uint32 I2S_MASTER_CONFIG; struct { uint32 I2S_CHn_LEFT_DATA; uint32 I2S_CHn_RIGHT_DATA; uint32 I2S_CHn_CFG; uint32 I2S_CHn_INT_CFG; uint32 I2S_CHn_TRIGGER_LEVEL_CFG; } I2S_CHANNEL_REG[4]; uint32 I2S_CYCLE_TX_DATA; uint32 I2S_CYCLE_TX_RESET; uint32 I2S_CYCLE_RX_DATA; uint32 I2S_CYCLE_RX_RESET; }; typedef volatile struct Reg_I2s_Bf Reg_I2s_BfType; typedef volatile struct Reg_I2s_W Reg_I2s_WType; struct Reg_Mcpwm_Bf { struct { uint32 CKSRC : 2; uint32 PSDIV : 3; uint32 DBGM : 2; uint32 RSVD_31_7 : 25; } MCPWM_TIMEBASE; struct { uint32 CNT : 16; uint32 RSVD_31_16 : 16; } MCPWM_CNTn[4]; struct { uint32 MOD : 16; uint32 RSVD_31_16 : 16; } MCPWM_MODn[4]; struct { uint32 DTVAL : 12; uint32 RSVD_31_12 : 20; } MCPWM_DTVALn[4]; struct { uint32 CHOE0 : 1; uint32 CHOE1 : 1; uint32 CHOE2 : 1; uint32 CHOE3 : 1; uint32 CHOE4 : 1; uint32 CHOE5 : 1; uint32 CHOE6 : 1; uint32 CHOE7 : 1; uint32 CNTM0 : 1; uint32 CNTM1 : 1; uint32 CNTM2 : 1; uint32 CNTM3 : 1; uint32 CNTEN0 : 1; uint32 CNTEN1 : 1; uint32 CNTEN2 : 1; uint32 CNTEN3 : 1; uint32 RLDIE0 : 1; uint32 RLDIE1 : 1; uint32 RLDIE2 : 1; uint32 RLDIE3 : 1; uint32 TOIE0 : 1; uint32 TOIE1 : 1; uint32 TOIE2 : 1; uint32 TOIE3 : 1; uint32 RSVD_29_24 : 6; uint32 WPEN : 1; uint32 GLBCNTEN : 1; } MCPWM_GLBCR; struct { uint32 CH0F : 1; uint32 CH1F : 1; uint32 CH2F : 1; uint32 CH3F : 1; uint32 CH4F : 1; uint32 CH5F : 1; uint32 CH6F : 1; uint32 CH7F : 1; uint32 RLDF0 : 1; uint32 RLDF1 : 1; uint32 RLDF2 : 1; uint32 RLDF3 : 1; uint32 TOF0 : 1; uint32 TOF1 : 1; uint32 TOF2 : 1; uint32 TOF3 : 1; uint32 WPDIS : 1; uint32 RSVD_31_17 : 15; } MCPWM_GLBSR; struct { uint32 CPP : 1; uint32 RSVD_3_1 : 3; uint32 CHIE : 1; uint32 CHF : 1; uint32 DMA : 1; uint32 RSVD_31_7 : 25; } MCPWM_CFGn[8]; struct { uint32 CV : 16; uint32 RSVD_31_16 : 16; } MCPWM_CVn[8]; struct { uint32 POL0 : 1; uint32 POL1 : 1; uint32 POL2 : 1; uint32 POL3 : 1; uint32 POL4 : 1; uint32 POL5 : 1; uint32 POL6 : 1; uint32 POL7 : 1; uint32 OFFVAL0 : 1; uint32 OFFVAL1 : 1; uint32 OFFVAL2 : 1; uint32 OFFVAL3 : 1; uint32 OFFVAL4 : 1; uint32 OFFVAL5 : 1; uint32 OFFVAL6 : 1; uint32 OFFVAL7 : 1; uint32 RSVD_31_16 : 16; } MCPWM_OUTCR; struct { uint32 TRIGE0 : 1; uint32 TRIGE1 : 1; uint32 TRIGE2 : 1; uint32 TRIGE3 : 1; uint32 TRIGE4 : 1; uint32 TRIGE5 : 1; uint32 TRIGE6 : 1; uint32 TRIGE7 : 1; uint32 INITRIGE : 1; uint32 TRIGF : 1; uint32 RSVD_31_10 : 22; } MCPWM_OUTTRIG; struct { uint32 CH0OC : 1; uint32 CH1OC : 1; uint32 CH2OC : 1; uint32 CH3OC : 1; uint32 CH4OC : 1; uint32 CH5OC : 1; uint32 CH6OC : 1; uint32 CH7OC : 1; uint32 CH0OCV : 1; uint32 CH1OCV : 1; uint32 CH2OCV : 1; uint32 CH3OCV : 1; uint32 CH4OCV : 1; uint32 CH5OCV : 1; uint32 CH6OCV : 1; uint32 CH7OCV : 1; uint32 RSVD_31_16 : 16; } MCPWM_OUTSWCR; struct { uint32 FCTLEN0 : 1; uint32 DTEN0 : 1; uint32 SYNCEN0 : 1; uint32 ASYMEN0 : 1; uint32 CVSEL0 : 1; uint32 PEC0 : 1; uint32 COMB0 : 1; uint32 RSVD_7 : 1; uint32 FCTLEN1 : 1; uint32 DTEN1 : 1; uint32 SYNCEN1 : 1; uint32 ASYMEN1 : 1; uint32 CVSEL1 : 1; uint32 PEC1 : 1; uint32 COMB1 : 1; uint32 RSVD_15 : 1; uint32 FCTLEN2 : 1; uint32 DTEN2 : 1; uint32 SYNCEN2 : 1; uint32 ASYMEN2 : 1; uint32 CVSEL2 : 1; uint32 PEC2 : 1; uint32 COMB2 : 1; uint32 RSVD_23 : 1; uint32 FCTLEN3 : 1; uint32 DTEN3 : 1; uint32 SYNCEN3 : 1; uint32 ASYMEN3 : 1; uint32 CVSEL3 : 1; uint32 PEC3 : 1; uint32 COMB3 : 1; uint32 RSVD_31 : 1; } MCPWM_PCR; struct { uint32 FIFEN0 : 1; uint32 FIFEN1 : 1; uint32 FIFEN2 : 1; uint32 FIFEN3 : 1; uint32 FLTEN0 : 1; uint32 FLTEN1 : 1; uint32 FLTEN2 : 1; uint32 FLTEN3 : 1; uint32 FLTPOL0 : 1; uint32 FLTPOL1 : 1; uint32 FLTPOL2 : 1; uint32 FLTPOL3 : 1; uint32 FLTIE : 1; uint32 FLTCM : 1; uint32 RSVD_15_14 : 2; uint32 FIFVAL : 4; uint32 FSTATE : 1; uint32 RSVD_31_21 : 11; } MCPWM_FLTCR; struct { uint32 FAULTF0 : 1; uint32 FAULTF1 : 1; uint32 FAULTF2 : 1; uint32 FAULTF3 : 1; uint32 FAULTFA : 1; uint32 FAULTFB : 1; uint32 FAULTINA : 1; uint32 FAULTINB : 1; uint32 RSVD_31_8 : 24; } MCPWM_FLTSR; struct { uint32 FLTASS0 : 1; uint32 FLTASS1 : 1; uint32 FLTASS2 : 1; uint32 FLTASS3 : 1; uint32 FLTASS4 : 1; uint32 FLTASS5 : 1; uint32 FLTASS6 : 1; uint32 FLTASS7 : 1; uint32 RSVD_31_8 : 24; } MCPWM_FLTASS; struct { uint32 FLTBSS0 : 1; uint32 FLTBSS1 : 1; uint32 FLTBSS2 : 1; uint32 FLTBSS3 : 1; uint32 FLTBSS4 : 1; uint32 FLTBSS5 : 1; uint32 FLTBSS6 : 1; uint32 FLTBSS7 : 1; uint32 RSVD_31_8 : 24; } MCPWM_FLTBSS; struct { uint32 SWTRIG : 1; uint32 SYNCOSWC : 1; uint32 SWWRBUF : 1; uint32 SWRSTCNT : 1; uint32 RSVD_31_4 : 28; } MCPWM_SYNC; struct { uint32 CPWMFCR0 : 1; uint32 CPWMFCR1 : 1; uint32 CPWMFCR2 : 1; uint32 CPWMFCR3 : 1; uint32 CPWMHCR0 : 1; uint32 CPWMHCR1 : 1; uint32 CPWMHCR2 : 1; uint32 CPWMHCR3 : 1; uint32 LOADEN0 : 1; uint32 LOADEN1 : 1; uint32 LOADEN2 : 1; uint32 LOADEN3 : 1; uint32 RSVD_31_12 : 20; } MCPWM_RELOAD; struct { uint32 LDFREQ0 : 5; uint32 RSVD_7_5 : 3; uint32 LDFREQ1 : 5; uint32 RSVD_15_13 : 3; uint32 LDFREQ2 : 5; uint32 RSVD_23_21 : 3; uint32 LDFREQ3 : 5; uint32 RSVD_31_29 : 3; } MCPWM_LDFREQ; uint8 zResverd0x0A8[88]; struct { uint32 MOD_DITHER : 5; uint32 RSVD_31_5 : 27; } MCPWM_MODn_DITHER[4]; struct { uint32 CV_DITHER : 5; uint32 RSVD_31_5 : 27; } MCPWM_CVn_DITHER[8]; }; struct Reg_Mcpwm_W { uint32 MCPWM_TIMEBASE; uint32 MCPWM_CNTn[4]; uint32 MCPWM_MODn[4]; uint32 MCPWM_DTVALn[4]; uint32 MCPWM_GLBCR; uint32 MCPWM_GLBSR; uint32 MCPWM_CFGn[8]; uint32 MCPWM_CVn[8]; uint32 MCPWM_OUTCR; uint32 MCPWM_OUTTRIG; uint32 MCPWM_OUTSWCR; uint32 MCPWM_PCR; uint32 MCPWM_FLTCR; uint32 MCPWM_FLTSR; uint32 MCPWM_FLTASS; uint32 MCPWM_FLTBSS; uint32 MCPWM_SYNC; uint32 MCPWM_RELOAD; uint32 MCPWM_LDFREQ; uint8 zResverd0x0A8[88]; uint32 MCPWM_MODn_DITHER[4]; uint32 MCPWM_CVn_DITHER[8]; }; typedef volatile struct Reg_Mcpwm_Bf Reg_Mcpwm_BfType; typedef volatile struct Reg_Mcpwm_W Reg_Mcpwm_WType; struct Reg_Parcc_Bf { struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_WDOG; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_EWDT; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_STIM; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_TIM0; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_TIM1; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_TIM2; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_TIM3; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_MCPWM0; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_MCPWM1; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_TDG0; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_TDG1; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CAN0; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CAN1; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CAN2; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CAN3; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CAN4; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CAN5; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CAN6; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CAN7; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_UART0; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_UART1; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_UART2; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_UART3; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_UART4; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_UART5; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_SPI0; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_SPI1; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_SPI2; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_SPI3; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_I2C0; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_I2C1; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_I2S0; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_I2S1; uint32 zResverd0x84; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_ADC0; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_ADC1; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CMP0; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_CRC; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_AES; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_TRNG; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 RSVD_16 : 1; uint32 RSVD_19_17 : 3; uint32 RSVD_20 : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_FLASH; uint32 zResverd0xA4; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_DMA; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_DMAMUX; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_PORTA; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_PORTB; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_PORTC; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_PORTD; struct { uint32 PCKMD : 2; uint32 RSVD_3_2 : 2; uint32 CLKMUX : 3; uint32 RSVD_7 : 1; uint32 CLKDIV : 4; uint32 RSVD_15_12 : 4; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_PORTE; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_TMU; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_REGFILE; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_SMPU; struct { uint32 PCKMD : 2; uint32 RSVD_15_2 : 14; uint32 PWLK : 1; uint32 RSVD_19_17 : 3; uint32 PSUPVACEN : 1; uint32 PRSTB : 1; uint32 RSVD_23_22 : 2; uint32 PPR : 1; uint32 PCLKMUXPR : 1; uint32 PCLKDIVPR : 1; uint32 PSUPVACPR : 1; uint32 RSVD_30_28 : 3; uint32 LOCK : 1; } PARCC_GPIO; }; struct Reg_Parcc_W { uint32 PARCC_WDOG; uint32 PARCC_EWDT; uint32 PARCC_STIM; uint32 PARCC_TIM0; uint32 PARCC_TIM1; uint32 PARCC_TIM2; uint32 PARCC_TIM3; uint32 PARCC_MCPWM0; uint32 PARCC_MCPWM1; uint32 PARCC_TDG0; uint32 PARCC_TDG1; uint32 PARCC_CAN0; uint32 PARCC_CAN1; uint32 PARCC_CAN2; uint32 PARCC_CAN3; uint32 PARCC_CAN4; uint32 PARCC_CAN5; uint32 PARCC_CAN6; uint32 PARCC_CAN7; uint32 PARCC_UART0; uint32 PARCC_UART1; uint32 PARCC_UART2; uint32 PARCC_UART3; uint32 PARCC_UART4; uint32 PARCC_UART5; uint32 PARCC_SPI0; uint32 PARCC_SPI1; uint32 PARCC_SPI2; uint32 PARCC_SPI3; uint32 PARCC_I2C0; uint32 PARCC_I2C1; uint32 PARCC_I2S0; uint32 PARCC_I2S1; uint32 zResverd0x84; uint32 PARCC_ADC0; uint32 PARCC_ADC1; uint32 PARCC_CMP0; uint32 PARCC_CRC; uint32 PARCC_AES; uint32 PARCC_TRNG; uint32 PARCC_FLASH; uint32 zResverd0xA4; uint32 PARCC_DMA; uint32 PARCC_DMAMUX; uint32 PARCC_PORTA; uint32 PARCC_PORTB; uint32 PARCC_PORTC; uint32 PARCC_PORTD; uint32 PARCC_PORTE; uint32 PARCC_TMU; uint32 PARCC_REGFILE; uint32 PARCC_SMPU; uint32 PARCC_GPIO; }; typedef volatile struct Reg_Parcc_Bf Reg_Parcc_BfType; typedef volatile struct Reg_Parcc_W Reg_Parcc_WType; struct Reg_Pmu_Bf { struct { uint32 RSVD_30_0 : 31; uint32 LOCK : 1; } PMU_LOCK; struct { uint32 LPO_CLK_DIS : 1; uint32 RSVD_1 : 1; uint32 LPO_CLK_READY : 1; uint32 RSVD_31_3 : 29; } PMU_LPO_32K_CFG; uint8 zResverd0x08[4]; struct { uint32 ISO_CLR : 1; uint32 RSVD_31_1 : 31; } PMU_ISO_CLR; struct { uint32 VDD_LVD_LP_EN : 1; uint32 VDD_LVD_ACT_EN : 1; uint32 VDD_LVD_IE : 1; uint32 VDD_LVD_RE : 1; uint32 VDD_LVW_EN : 1; uint32 VDD_LVW_IE : 1; uint32 LVWF_VDD : 1; uint32 LVDF_VDD : 1; uint32 REF_BUF_1V_EN : 1; uint32 RSVD_31_9 : 23; } PMU_CSR; struct { uint32 LDO_CORE_EN : 1; uint32 LDO_CLOCK_EN : 1; uint32 LDO_FLASH_EN : 1; uint32 RSVD_3 : 1; uint32 LDO_CORE_LPEN : 1; uint32 LDO_CLOCK_LPEN : 1; uint32 LDO_FLASH_LPEN : 1; uint32 RSVD_31_7 : 25; } PMU_LDO_EN_CFG; struct { uint32 LVD_CORE_FLAG : 1; uint32 LVD_CLOCK_FLAG : 1; uint32 LVD_FLASH_FLAG : 1; uint32 RSVD_3 : 1; uint32 LVD_AOA_FLAG : 1; uint32 RSVD_31_5 : 27; } PMU_LDO_LVD_STATUS; struct { uint32 LVD_CORE_RE : 1; uint32 LVD_CLOCK_RE : 1; uint32 LVD_FLASH_RE : 1; uint32 RSVD_3 : 1; uint32 LVD_AOA_RE : 1; uint32 ACT_CORE_LVDE : 1; uint32 ACT_CLOCK_LVDE : 1; uint32 RSVD_8_7 : 2; uint32 ACT_AOA_LVDE : 1; uint32 LP_CORE_LVDE : 1; uint32 LP_CLOCK_LVDE : 1; uint32 RSVD_13_12 : 2; uint32 LP_AOA_LVDE : 1; uint32 RSVD_31_15 : 17; } PMU_LDO_LVD_CFG; }; struct Reg_Pmu_W { uint32 PMU_LOCK; uint32 PMU_LPO_32K_CFG; uint8 zResverd0x08[4]; uint32 PMU_ISO_CLR; uint32 PMU_CSR; uint32 PMU_LDO_EN_CFG; uint32 PMU_LDO_LVD_STATUS; uint32 PMU_LDO_LVD_CFG; }; typedef volatile struct Reg_Pmu_Bf Reg_Pmu_BfType; typedef volatile struct Reg_Pmu_W Reg_Pmu_WType; struct Reg_Port_Bf { uint8 zResverd0x0[8]; struct { uint32 GPWD : 32; } PORTx_GLBDAT; struct { uint32 GPWE : 32; } PORTx_GLBCTL; struct { uint32 PS : 1; uint32 PE : 1; uint32 RSVD_2 : 1; uint32 SRE : 1; uint32 PFE : 1; uint32 ODE : 1; uint32 RSVD_7_6 : 2; uint32 MUX : 3; uint32 RSVD_14_11 : 4; uint32 LK : 1; uint32 IRQC : 4; uint32 RSVD_22_20 : 3; uint32 ISF : 1; uint32 FLT : 5; uint32 RSVD_30_29 : 2; uint32 FLTEN : 1; } PORTx_PCRn[32]; struct { uint32 ISF : 32; } PORTx_IRQFLG; }; struct Reg_Port_W { uint8 zResverd0x0[8]; uint32 PORTx_GLBDAT; uint32 PORTx_GLBCTL; uint32 PORTx_PCRn[32]; uint32 PORTx_IRQFLG; }; typedef volatile struct Reg_Port_Bf Reg_Port_BfType; typedef volatile struct Reg_Port_W Reg_Port_WType; struct Reg_Regfile_Bf { struct { uint32 DATA : 32; } REGFILE_REGn[32]; }; struct Reg_Regfile_W { uint32 REGFILE_REGn[32]; }; typedef volatile struct Reg_Regfile_Bf Reg_Regfile_BfType; typedef volatile struct Reg_Regfile_W Reg_Regfile_WType; struct Reg_Rtc_Bf { struct { uint32 CRYSTAL_EN : 1; uint32 CNT_CLK_SEL : 1; uint32 CLKOUT_SEL : 1; uint32 CLKOUT_PIN_EN : 1; uint32 SUP_EN : 1; uint32 SW_RST : 1; uint32 COUNT_EN : 1; uint32 OVF : 1; uint32 ALARM_MATCHF : 1; uint32 OSC_RDY : 1; uint32 EXTAL_32K_EN : 1; uint32 SECONDS_INT_FLAG : 1; uint32 PERIODIC_CNT_EN : 1; uint32 PERIODIC_MATCH_FLG : 1; uint32 RSVD_31_14 : 18; } RTC_CSR; struct { uint32 SECOND_INT_MUX_SEL : 3; uint32 OVFLOW_IE : 1; uint32 ALARM_IE : 1; uint32 SECONDS_IE : 1; uint32 PERIODIC_IE : 1; uint32 RSVD_31_7 : 25; } RTC_IER; struct { uint32 ALARM_CNT : 32; } RTC_ALARM_CNTR; struct { uint32 ONE_SECOND_CNT : 16; uint32 RSVD_31_16 : 16; } RTC_ONE_SECOND_CNTR; struct { uint32 MATCH_CNT : 32; } RTC_MATCH_CNTR; struct { uint32 COMP_CNT : 7; uint32 COMP_DIRECTION : 1; uint32 DLY : 8; uint32 CCOMP_CNT : 8; uint32 CDLY : 8; } RTC_COMPENSATIONR; struct { uint32 RSVD_30_0 : 31; uint32 LOCK : 1; } RTC_LOCKR; uint8 zResverd0x01C[4]; struct { uint32 PERIODIC_TMR_CNT : 32; } RTC_PERIODIC_TMR_CNT; struct { uint32 PERIODIC_MATCH_CNT : 32; } RTC_PERIODIC_TMR_MATCH_CNT; }; struct Reg_Rtc_W { uint32 RTC_CSR; uint32 RTC_IER; uint32 RTC_ALARM_CNTR; uint32 RTC_ONE_SECOND_CNTR; uint32 RTC_MATCH_CNTR; uint32 RTC_COMPENSATIONR; uint32 RTC_LOCKR; uint8 zResverd0x01C[4]; uint32 RTC_PERIODIC_TMR_CNT; uint32 RTC_PERIODIC_TMR_MATCH_CNT; }; typedef volatile struct Reg_Rtc_Bf Reg_Rtc_BfType; typedef volatile struct Reg_Rtc_W Reg_Rtc_WType; struct Reg_Scc_Bf { uint32 zResverd0x0; struct { uint32 CLKSPRES : 5; uint32 RSVD_27_5 : 23; uint32 DIVPRES : 3; uint32 RSVD_31 : 1; } SCC_PARAM; struct { uint32 DIVSLOW : 4; uint32 DIVBUS : 4; uint32 DIVCORE : 4; uint32 RSVD_15_12 : 4; uint32 SCS : 3; uint32 RSVD_31_19 : 13; } SCC_CST; struct { uint32 DIVSLOW : 4; uint32 DIVBUS : 4; uint32 DIVCORE : 4; uint32 RSVD_15_12 : 4; uint32 SCS : 3; uint32 RSVD_30_19 : 12; uint32 LOCK : 1; } SCC_CFG; struct { uint32 RSVD_15_0 : 16; uint32 CLKOUTSEL : 4; uint32 RSVD_31_20 : 12; } SCC_CLKOUTCFG; struct { uint32 OSCEN : 1; uint32 OSCSTOPEN : 1; uint32 RSVD_3_2 : 2; uint32 OSCLOCINTEN : 1; uint32 RSVD_8_5 : 4; uint32 OSCCME : 1; uint32 OSCCMRE : 1; uint32 RSVD_15_11 : 5; uint32 OSCRDY : 1; uint32 OSCSELD : 1; uint32 OSCLOC : 1; uint32 RSVD_30_19 : 12; uint32 LOCK : 1; } SCC_OSCCS; struct { uint32 EXCLKS : 1; uint32 OLMEN : 1; uint32 HFREQ : 1; uint32 RSVD_7_3 : 5; uint32 ITRIM : 2; uint32 RSVD_30_10 : 21; uint32 LOCK : 1; } SCC_OSCCFG; struct { uint32 FIRCEN : 1; uint32 FIRCSTOPEN : 1; uint32 RSVD_3_2 : 2; uint32 FIRCLOCINTEN : 1; uint32 RSVD_8_5 : 4; uint32 FIRCCME : 1; uint32 FIRCCMRE : 1; uint32 RSVD_11 : 1; uint32 RSVD_12 : 1; uint32 RSVD_15_13 : 3; uint32 FIRCRDY : 1; uint32 FIRCSELD : 1; uint32 FIRCLOC : 1; uint32 RSVD_30_19 : 12; uint32 LOCK : 1; } SCC_FIRCCS; uint8 zResverd0x020[8]; struct { uint32 SPLLEN : 1; uint32 SPLLSTOPEN : 1; uint32 RSVD_3_2 : 2; uint32 RSVD_4 : 1; uint32 RSVD_8_5 : 4; uint32 RDYEN : 1; uint32 RSVD_10 : 1; uint32 RSVD_11 : 1; uint32 LOCKWIN : 2; uint32 RSVD_15_14 : 2; uint32 SPLLRDY : 1; uint32 SPLLSELD : 1; uint32 RSVD_18 : 1; uint32 RSVD_24_19 : 6; uint32 OUTEN : 1; uint32 RSVD_30_26 : 5; uint32 LOCK : 1; } SCC_SPLLCS; struct { uint32 PREDIV : 2; uint32 RSVD_3_2 : 2; uint32 FBPRESEN : 1; uint32 REFCKS : 1; uint32 RSVD_7_6 : 2; uint32 MULT : 8; uint32 POSTDIV : 3; uint32 RSVD_30_19 : 12; uint32 LOCK : 1; } SCC_SPLLCFG1; struct { uint32 CPIR : 2; uint32 CPIC : 2; uint32 CS : 2; uint32 CAP : 2; uint32 RES : 3; uint32 KVCO : 1; uint32 VCODIV : 1; uint32 PFDDIEN : 1; uint32 CPISEL : 1; uint32 RSVD_15 : 1; uint32 RSVD_23_16 : 8; uint32 LDOODEN : 1; uint32 RSVD_30_25 : 6; uint32 LOCK : 1; } SCC_SPLLCFG2; }; struct Reg_Scc_W { uint32 zResverd0x0; uint32 SCC_PARAM; uint32 SCC_CST; uint32 SCC_CFG; uint32 SCC_CLKOUTCFG; uint32 SCC_OSCCS; uint32 SCC_OSCCFG; uint32 SCC_FIRCCS; uint8 zResverd0x020[8]; uint32 SCC_SPLLCS; uint32 SCC_SPLLCFG1; uint32 SCC_SPLLCFG2; }; typedef volatile struct Reg_Scc_Bf Reg_Scc_BfType; typedef volatile struct Reg_Scc_W Reg_Scc_WType; struct Reg_Scm_Bf { struct { uint32 RSVD_3_0 : 4; uint32 CLKOUTSEL : 2; uint32 RSVD_7_6 : 2; uint32 CLKOUTDIV : 3; uint32 CLKOUTEN : 1; uint32 RSVD_31_12 : 20; } SCM_CHIPCTL; struct { uint32 SWTRIG0 : 1; uint32 SWTRIG1 : 1; uint32 SWTRIG2 : 1; uint32 SWTRIG3 : 1; uint32 SRAML_READ_BUFF_EN : 1; uint32 SRAMU_READ_BUFF_EN : 1; uint32 XBAR_ROUND_ROBIN : 1; uint32 RSVD_7 : 1; uint32 RSVD_8 : 1; uint32 RSVD_9 : 1; uint32 RSVD_10 : 1; uint32 CCACHE_CLR : 1; uint32 CCACHE_PARITY_MISS_EN : 1; uint32 CCACHE_PARITY_FAULT_EN : 1; uint32 CACHE_DIS : 1; uint32 RSVD_15 : 1; uint32 CCACHE_BE_INT_EN : 1; uint32 RSVD_23_17 : 7; uint32 FPU_INEXACT_INT_EN : 1; uint32 FPU_OVERFLOW_INT_EN : 1; uint32 FPU_UNDERFLOW_INT_EN : 1; uint32 FPU_INVALIDOP_INT_EN : 1; uint32 FPU_DIVZERO_INT_EN : 1; uint32 FPU_DENORMALIN_INT_EN : 1; uint32 RSVD_31_30 : 2; } SCM_MISCCTL1; uint8 zResverd0x08[32]; struct { uint32 RSVD_7_0 : 8; uint32 MCPWM0_TCLK_SEL : 2; uint32 MCPWM1_TCLK_SEL : 2; uint32 TIM0_TCLK_SEL : 2; uint32 TIM1_TCLK_SEL : 2; uint32 TIM2_TCLK_SEL : 2; uint32 TIM3_TCLK_SEL : 2; uint32 RSVD_23_20 : 4; uint32 ADC0_CH8_SEL : 1; uint32 ADC0_CH9_SEL : 1; uint32 ADC1_CH14_SEL : 1; uint32 ADC1_CH15_SEL : 1; uint32 RSVD_31_28 : 4; } SCM_MISCCTL2; uint8 zResverd0x02C[20]; struct { uint32 RSVD_14_0 : 15; uint32 RSVD_15 : 1; uint32 CCACHE_BE_FLAG : 8; uint32 FPU_INEXACT_FLAG : 1; uint32 FPU_OVERFLOW_FLAG : 1; uint32 FPU_UNDERFLOW_FLAG : 1; uint32 FPU_INVALIDOP_FLAG : 1; uint32 FPU_DIVZERO_FLAG : 1; uint32 FPU_DENORMALIN_FLAG : 1; uint32 RSVD_31_30 : 2; } SCM_MISCSTAT1; struct { uint32 CACHE_BE_ADDR : 32; } SCM_MISCDATA1; struct { uint32 CACHE_BE_DATA : 32; } SCM_MISCDATA2; uint8 zResverd0x04C[180]; struct { uint32 CCACHE_DIS_IFR : 1; uint32 FPU_DIS : 1; uint32 RSVD_31_2 : 30; } SCM_CHIPOPT; struct { uint32 RSVD_23_0 : 24; uint32 PFSIZE : 4; uint32 DFSIZE : 4; } SCM_FLSCFG; struct { uint32 CACHESIZE : 4; uint32 RSVD_27_4 : 24; uint32 RAMSIZE : 4; } SCM_RAMCFG; uint8 zResverd0x010C[16]; struct { uint32 MEMSIZE_ID : 4; uint32 SERIES_ID : 3; uint32 SUBFAMILY_ID : 5; uint32 FAMILY_ID : 4; uint32 REV_ID : 4; uint32 FEATURE_ID : 7; uint32 PACKAGE_ID : 5; } SCM_DEVID; struct { uint32 UID_31_0 : 32; } SCM_UNIQUE0; struct { uint32 UID_63_32 : 32; } SCM_UNIQUE1; struct { uint32 UID_95_64 : 32; } SCM_UNIQUE2; struct { uint32 UID_127_96 : 32; } SCM_UNIQUE3; }; struct Reg_Scm_W { uint32 SCM_CHIPCTL; uint32 SCM_MISCCTL1; uint8 zResverd0x08[32]; uint32 SCM_MISCCTL2; uint8 zResverd0x02C[20]; uint32 SCM_MISCSTAT1; uint32 SCM_MISCDATA1; uint32 SCM_MISCDATA2; uint8 zResverd0x04C[180]; uint32 SCM_CHIPOPT; uint32 SCM_FLSCFG; uint32 SCM_RAMCFG; uint8 zResverd0x010C[16]; uint32 SCM_DEVID; uint32 SCM_UNIQUE0; uint32 SCM_UNIQUE1; uint32 SCM_UNIQUE2; uint32 SCM_UNIQUE3; }; typedef volatile struct Reg_Scm_Bf Reg_Scm_BfType; typedef volatile struct Reg_Scm_W Reg_Scm_WType; struct Reg_Seru_Bf { uint32 zResverd0x0; struct { uint32 PARAM : 32; } SERU_PARAM; struct { uint32 CRPAR_INT_EN : 1; uint32 RSVD_3_1 : 3; uint32 EOUT_PS : 1; uint32 EOUT0_IO_EN : 1; uint32 EOUT1_IO_EN : 1; uint32 FFI_EN : 1; uint32 CFG_MODE : 1; uint32 RSVD_31_9 : 23; } SERU_CSR; struct { uint32 S_CRPAR_ERR : 1; uint32 RSVD_31_1 : 31; } SERU_INTF; struct { uint32 KEY : 32; } SERU_CFG_KEY; struct { uint32 CH_FFI_6_0 : 7; uint32 RSVD_7 : 1; uint32 CH_FFI_14_8 : 7; uint32 RSVD_15 : 1; uint32 CH_FFI_16 : 1; uint32 RSVD_31_17 : 15; } SERU_CH_FFI; struct { uint32 SWERR_CH0 : 1; uint32 SWERR_CH1 : 1; uint32 SWERR_CH2 : 1; uint32 RSVD_31_3 : 29; } SERU_SWERR_GNT; struct { uint32 CH_FLAG_6_0 : 7; uint32 RSVD_7 : 1; uint32 CH_FLAG_14_8 : 7; uint32 RSVD_15 : 1; uint32 CH_FLAG_16 : 1; uint32 RSVD_31_17 : 15; } SERU_CH_FLAG; struct { uint32 CH_EN : 1; uint32 CH_INT_CFG : 1; uint32 CH_INT_TYP : 1; uint32 CH_EOUT_CFG : 1; uint32 CH_RESET_CFG : 1; uint32 CH_RESET_TYP : 1; uint32 CH_RESET_DLY : 2; uint32 CH_FLAG : 1; uint32 RSVD_31_9 : 23; } SERU_CFG_CHn[17]; }; struct Reg_Seru_W { uint32 zResverd0x0; uint32 SERU_PARAM; uint32 SERU_CSR; uint32 SERU_INTF; uint32 SERU_CFG_KEY; uint32 SERU_CH_FFI; uint32 SERU_SWERR_GNT; uint32 SERU_CH_FLAG; uint32 SERU_CFG_CHn[17]; }; typedef volatile struct Reg_Seru_Bf Reg_Seru_BfType; typedef volatile struct Reg_Seru_W Reg_Seru_WType; struct Reg_Smpu_Bf { uint32 zResverd0x00; struct { uint32 S0ERR : 1; uint32 S1ERR : 1; uint32 S2ERR : 1; uint32 RSVD_3 : 1; uint32 RSVD_7_4 : 4; uint32 GLBEN : 1; uint32 RSVD_31_9 : 23; } SMPU_CS; uint8 zResverd0x08[8]; struct { uint32 EADDR : 32; } SMPU_Sn_EA[3]; uint8 zResverd0x01C[20]; struct { uint32 EMRC : 16; uint32 RSVD_23_16 : 8; uint32 EMN : 4; uint32 EATTR : 1; uint32 EUS : 1; uint32 RSVD_30 : 1; uint32 ERW : 1; } SMPU_Sn_ES[3]; uint8 zResverd0x03C[196]; struct { struct { uint32 RSVD_4_0 : 5; uint32 SADDR : 27; } SMPU_MRCn_W0; struct { uint32 RSVD_4_0 : 5; uint32 EADDR : 27; } SMPU_MRCn_W1; struct { uint32 M0UX : 1; uint32 M0UW : 1; uint32 M0UR : 1; uint32 M0SM : 2; uint32 RSVD_5 : 1; uint32 M1UX : 1; uint32 M1UW : 1; uint32 M1UR : 1; uint32 M1SM : 2; uint32 RSVD_11 : 1; uint32 M2UX : 1; uint32 M2UW : 1; uint32 M2UR : 1; uint32 M2SM : 2; uint32 RSVD_31_17 : 15; } SMPU_MRCn_W2; struct { uint32 RSVD_15_0 : 16; uint32 EN : 1; uint32 RSVD_31_17 : 15; } SMPU_MRCn_W3; } SMPU_MRCn_W[16]; }; struct Reg_Smpu_W { uint32 zResverd0x00; uint32 SMPU_CS; uint8 zResverd0x08[8]; uint32 SMPU_Sn_EA[3]; uint8 zResverd0x01C[20]; uint32 SMPU_Sn_ES[3]; uint8 zResverd0x03C[196]; struct { uint32 SMPU_MRCn_W0; uint32 SMPU_MRCn_W1; uint32 SMPU_MRCn_W2; uint32 SMPU_MRCn_W3; } SMPU_MRCn_W[16]; }; typedef volatile struct Reg_Smpu_Bf Reg_Smpu_BfType; typedef volatile struct Reg_Smpu_W Reg_Smpu_WType; struct Reg_Spi_Bf { struct { uint32 RSVD_5_0 : 6; uint32 SCPH : 1; uint32 SCPOL : 1; uint32 TMOD : 2; uint32 RSVD_10 : 1; uint32 RSVD_11 : 1; uint32 RSVD_15_12 : 4; uint32 DFS_32 : 5; uint32 MST_MODE : 1; uint32 RSVD_22 : 1; uint32 RSVD_23 : 1; uint32 RSVD_24 : 1; uint32 RSVD_31_25 : 7; } SPI_CTRLR0; struct { uint32 NDF : 16; uint32 RSVD_31_16 : 16; } SPI_CTRLR1; struct { uint32 SPI_EN : 1; uint32 RSVD_15_1 : 15; uint32 SER : 2; uint32 RSVD_31_18 : 14; } SPI_SSENR; struct { uint32 SCKDV : 16; uint32 RSVD_31_16 : 16; } SPI_BAUDR; struct { uint32 TFT : 2; uint32 RSVD_15_2 : 14; uint32 RFT : 2; uint32 RSVD_31_18 : 14; } SPI_FTLR; struct { uint32 TXTFL : 3; uint32 RSVD_15_3 : 13; uint32 RXTFL : 3; uint32 RSVD_31_19 : 13; } SPI_FLR; struct { uint32 BUSY : 1; uint32 TFNF : 1; uint32 TFE : 1; uint32 RFNE : 1; uint32 RFF : 1; uint32 TXE : 1; uint32 RSVD_31_6 : 26; } SPI_SR; struct { uint32 TXEIE : 1; uint32 TXOIE : 1; uint32 RXUIE : 1; uint32 RXOIE : 1; uint32 RXFIE : 1; uint32 RSVD_31_5 : 27; } SPI_IER; struct { uint32 TXEIS : 1; uint32 TXOIS : 1; uint32 RXUIS : 1; uint32 RXOIS : 1; uint32 RXFIS : 1; uint32 RSVD_15_5 : 11; uint32 TXEIR : 1; uint32 TXOIR : 1; uint32 RXUIR : 1; uint32 RXOIR : 1; uint32 RXFIR : 1; uint32 RSVD_31_21 : 11; } SPI_ISR; struct { uint32 TXOICR : 1; uint32 RSVD_31_1 : 31; } SPI_TXOICR; struct { uint32 RXOICR : 1; uint32 RSVD_31_1 : 31; } SPI_RXOICR; struct { uint32 RXUICR : 1; uint32 RSVD_31_1 : 31; } SPI_RXUICR; uint8 zResverd0x030[4]; struct { uint32 ICR : 1; uint32 RSVD_31_1 : 31; } SPI_ICR; struct { uint32 RDMAE : 1; uint32 TDMAE : 1; uint32 RSVD_31_2 : 30; } SPI_DMACR; struct { uint32 DMATDL : 2; uint32 RSVD_31_2 : 30; } SPI_DMATDLR; struct { uint32 DMARDL : 2; uint32 RSVD_31_2 : 30; } SPI_DMARDLR; uint8 zResverd0x044[28]; struct { uint32 DR : 32; } SPI_DR_LOW; uint8 zResverd0x064[136]; struct { uint32 DR : 32; } SPI_DR_HIGH; }; struct Reg_Spi_W { uint32 SPI_CTRLR0; uint32 SPI_CTRLR1; uint32 SPI_SSENR; uint32 SPI_BAUDR; uint32 SPI_FTLR; uint32 SPI_FLR; uint32 SPI_SR; uint32 SPI_IER; uint32 SPI_ISR; uint32 SPI_TXOICR; uint32 SPI_RXOICR; uint32 SPI_RXUICR; uint8 zResverd0x030[4]; uint32 SPI_ICR; uint32 SPI_DMACR; uint32 SPI_DMATDLR; uint32 SPI_DMARDLR; uint8 zResverd0x044[28]; uint32 SPI_DR_LOW; uint8 zResverd0x064[136]; uint32 SPI_DR_HIGH; }; typedef volatile struct Reg_Spi_Bf Reg_Spi_BfType; typedef volatile struct Reg_Spi_W Reg_Spi_WType; struct Reg_Srmc_Bf { uint32 zResverd0x00; struct { uint32 EWAKEUP : 1; uint32 ELVD : 1; uint32 ELOC : 1; uint32 RSVD_3 : 1; uint32 RSVD_4 : 1; uint32 EWDOG : 1; uint32 EPIN : 1; uint32 EPOR : 1; uint32 RSVD_8 : 1; uint32 ELOCKUP : 1; uint32 ESW : 1; uint32 EADM_AP : 1; uint32 RSVD_12 : 1; uint32 ESACKERR : 1; uint32 RSVD_15_14 : 2; uint32 ESTB : 1; uint32 RSVD_31_17 : 15; } SRMC_PARAM; struct { uint32 WAKEUP : 1; uint32 LVD : 1; uint32 LOC : 1; uint32 RSVD_4_3 : 2; uint32 WDOG : 1; uint32 PIN : 1; uint32 POR : 1; uint32 RSVD_8 : 1; uint32 LOCKUP : 1; uint32 SW : 1; uint32 ADM_AP : 1; uint32 SERU_COLD : 1; uint32 SERU_SYS : 1; uint32 RSVD_14 : 1; uint32 SACKERR : 1; uint32 RSVD_31_16 : 16; } SRMC_SRS; struct { uint32 RSTFLTSRW : 2; uint32 RSTFLTSS : 1; uint32 RSVD_7_3 : 5; uint32 RSTFLTSEL : 5; uint32 RSVD_30_13 : 18; uint32 LOCKUP_RST_EN : 1; } SRMC_CTRL; uint8 zResverd0x010[8]; struct { uint32 SWAKEUP : 1; uint32 SLVD : 1; uint32 SLOC : 1; uint32 RSVD_4_3 : 2; uint32 SWDOG : 1; uint32 SPIN : 1; uint32 SPOR : 1; uint32 RSVD_8 : 1; uint32 SLOCKUP : 1; uint32 SSW : 1; uint32 SADM_AP : 1; uint32 SSERU_COLD : 1; uint32 SSERU_SYS : 1; uint32 RSVD_14 : 1; uint32 SSACKERR : 1; uint32 RSVD_31_16 : 16; } SRMC_SSRS; struct { uint32 DELAY : 2; uint32 LOC : 1; uint32 RSVD_4_3 : 2; uint32 WDOG : 1; uint32 PIN : 1; uint32 GIE : 1; uint32 RSVD_8 : 1; uint32 LOCKUP : 1; uint32 SW : 1; uint32 RSVD_11 : 1; uint32 SERU_COLD : 1; uint32 SERU_SYS : 1; uint32 RSVD_14 : 1; uint32 SACKERR : 1; uint32 RSVD_31_16 : 16; } SRMC_SRIE; struct { uint32 APD : 1; uint32 RSVD_31_1 : 31; } SRMC_PMPORT; struct { uint32 DSMC : 2; uint32 RSVD_7_2 : 6; uint32 DSMACKTMO : 8; uint32 RSVD_31_16 : 16; } SRMC_PMCTRL; struct { uint32 PMSTAT : 4; uint32 RSVD_7_4 : 4; uint32 DSMABORT : 1; uint32 RSVD_31_9 : 23; } SRMC_PMSTAT; struct { uint32 WUPSRC_EN2_0 : 3; uint32 RSVD_3 : 1; uint32 WUPSRC_EN15_4 : 12; uint32 WUPSRC_PL2_0 : 3; uint32 RSVD_19 : 1; uint32 WUPSRC_PL14_4 : 11; uint32 RSVD_31 : 1; } SRMC_DSMWUPC1; struct { uint32 WUPSRC_EN16 : 1; uint32 RSVD_31_1 : 31; } SRMC_DSMWUPC2; struct { uint32 WUPS_2_0 : 3; uint32 RSVD_3 : 1; uint32 WUPS_16_4 : 13; uint32 RSVD_31_17 : 15; } SRMC_DSMWUPS; }; struct Reg_Srmc_W { uint32 zResverd0x00; uint32 SRMC_PARAM; uint32 SRMC_SRS; uint32 SRMC_CTRL; uint8 zResverd0x010[8]; uint32 SRMC_SSRS; uint32 SRMC_SRIE; uint32 SRMC_PMPORT; uint32 SRMC_PMCTRL; uint32 SRMC_PMSTAT; uint32 SRMC_DSMWUPC1; uint32 SRMC_DSMWUPC2; uint32 SRMC_DSMWUPS; }; typedef volatile struct Reg_Srmc_Bf Reg_Srmc_BfType; typedef volatile struct Reg_Srmc_W Reg_Srmc_WType; struct Reg_Stim_Bf { uint32 zResverd0x00; struct { uint32 CNT : 32; } STIM_CNTn[4]; struct { uint32 CV : 32; } STIM_CVn[4]; struct { uint32 CLKS : 2; uint32 PSDIV : 4; uint32 PSEN : 1; uint32 POL : 1; uint32 PSRC : 2; uint32 MODE : 1; uint32 RSTDIS : 1; uint32 DMAE : 1; uint32 IE : 1; uint32 EN : 1; uint32 FLAG : 1; uint32 RSVD_31_16 : 16; } STIM_SCn[4]; }; struct Reg_Stim_W { uint32 zResverd0x00; uint32 STIM_CNTn[4]; uint32 STIM_CVn[4]; uint32 STIM_SCn[4]; }; typedef volatile struct Reg_Stim_Bf Reg_Stim_BfType; typedef volatile struct Reg_Stim_W Reg_Stim_WType; struct Reg_Tdg_Bf { uint32 zResverd0x0; struct { uint32 DOPNUM : 4; uint32 CHNUM : 4; uint32 RSVD_31_8 : 24; } TDG_PARAM; struct { uint32 TDGEN : 1; uint32 RSVD_3_1 : 3; uint32 TRIGS : 1; uint32 CNTMD : 1; uint32 CLRMD : 1; uint32 RSVD_7 : 1; uint32 PRES : 3; uint32 RSVD_15_11 : 5; uint32 CFGUP : 1; uint32 SWTRG : 1; uint32 RSVD_19_18 : 2; uint32 UPMD : 2; uint32 RSVD_31_22 : 10; } TDG_CTRL1; struct { uint32 CDO0IE : 1; uint32 CDO1IE : 1; uint32 CDO2IE : 1; uint32 CDO3IE : 1; uint32 CDO4IE : 1; uint32 CDO5IE : 1; uint32 RSVD_7_6 : 2; uint32 ERRIE : 1; uint32 RSVD_15_9 : 7; uint32 CH0E : 1; uint32 CH1E : 1; uint32 CH2E : 1; uint32 CH3E : 1; uint32 CH4E : 1; uint32 CH5E : 1; uint32 RSVD_31_22 : 10; } TDG_CTRL2; struct { uint32 CDO0IF : 1; uint32 CDO1IF : 1; uint32 CDO2IF : 1; uint32 CDO3IF : 1; uint32 CDO4IF : 1; uint32 CDO5IF : 1; uint32 RSVD_7_6 : 2; uint32 ERRIF : 1; uint32 RSVD_31_9 : 23; } TDG_STAT; struct { uint32 MOD : 16; uint32 RSVD_31_16 : 16; } TDG_MOD; struct { uint32 CNT : 16; uint32 RSVD_31_16 : 16; } TDG_CNT; struct { struct { uint32 RSVD_7_0 : 8; uint32 DO0E : 1; uint32 DO1E : 1; uint32 DO2E : 1; uint32 DO3E : 1; uint32 DO4E : 1; uint32 DO5E : 1; uint32 DO6E : 1; uint32 DO7E : 1; uint32 RSVD_31_16 : 16; } TDG_CHCTRL; struct { uint32 DO0OFS : 16; uint32 RSVD_31_16 : 16; } TDG_CHDOOFS[8]; struct { uint32 CDOINTDLY : 10; uint32 RSVD_15_10 : 6; uint32 LDCO : 1; uint32 RSVD_31_17 : 15; } TDG_CHCDOINTDLY; } TDG_CHCFG[6]; }; struct Reg_Tdg_W { uint32 zResverd0x0; uint32 TDG_PARAM; uint32 TDG_CTRL1; uint32 TDG_CTRL2; uint32 TDG_STAT; uint32 TDG_MOD; uint32 TDG_CNT; struct { uint32 TDG_CHCTRL; uint32 TDG_CHDOOFS[8]; uint32 TDG_CHCDOINTDLY; } TDG_CHCFG[6]; }; typedef volatile struct Reg_Tdg_Bf Reg_Tdg_BfType; typedef volatile struct Reg_Tdg_W Reg_Tdg_WType; struct Reg_Tim_Bf { struct { uint32 CKSRC : 2; uint32 PSDIV : 3; uint32 DBGM : 2; uint32 RSVD_31_7 : 25; } TIM_TIMEBASE; struct { uint32 CNT : 16; uint32 RSVD_31_16 : 16; } TIM_CNT; struct { uint32 CNTINIT : 16; uint32 RSVD_31_16 : 16; } TIM_CNTINIT; struct { uint32 MOD : 16; uint32 RSVD_31_16 : 16; } TIM_MOD; struct { uint32 CHOE0 : 1; uint32 CHOE1 : 1; uint32 CHOE2 : 1; uint32 CHOE3 : 1; uint32 CHOE4 : 1; uint32 CHOE5 : 1; uint32 CHOE6 : 1; uint32 CHOE7 : 1; uint32 RLDIE : 1; uint32 TOIE : 1; uint32 CNTMODE : 1; uint32 INIT : 1; uint32 RSVD_31_12 : 20; } TIM_GLBCR; struct { uint32 CH0F : 1; uint32 CH1F : 1; uint32 CH2F : 1; uint32 CH3F : 1; uint32 CH4F : 1; uint32 CH5F : 1; uint32 CH6F : 1; uint32 CH7F : 1; uint32 RLDF : 1; uint32 TOF : 1; uint32 WPDIS : 1; uint32 RSVD_31_11 : 21; } TIM_GLBSR; struct { uint32 ELS : 2; uint32 CMS : 2; uint32 CHIE : 1; uint32 CHF : 1; uint32 DMAEN : 1; uint32 ICRST : 1; uint32 RSVD_31_8 : 24; } TIM_CMCn[8]; struct { uint32 CCV : 16; uint32 RSVD_31_16 : 16; } TIM_CCVn[8]; struct { uint32 INIT0 : 1; uint32 INIT1 : 1; uint32 INIT2 : 1; uint32 INIT3 : 1; uint32 INIT4 : 1; uint32 INIT5 : 1; uint32 INIT6 : 1; uint32 INIT7 : 1; uint32 POL0 : 1; uint32 POL1 : 1; uint32 POL2 : 1; uint32 POL3 : 1; uint32 POL4 : 1; uint32 POL5 : 1; uint32 POL6 : 1; uint32 POL7 : 1; uint32 TRIGE0 : 1; uint32 TRIGE1 : 1; uint32 TRIGE2 : 1; uint32 TRIGE3 : 1; uint32 TRIGE4 : 1; uint32 TRIGE5 : 1; uint32 TRIGE6 : 1; uint32 TRIGE7 : 1; uint32 INITRIGE : 1; uint32 TRIGF : 1; uint32 RSVD_31_26 : 6; } TIM_OUTCR; struct { uint32 CH0OC : 1; uint32 CH1OC : 1; uint32 CH2OC : 1; uint32 CH3OC : 1; uint32 CH4OC : 1; uint32 CH5OC : 1; uint32 CH6OC : 1; uint32 CH7OC : 1; uint32 CH0OCV : 1; uint32 CH1OCV : 1; uint32 CH2OCV : 1; uint32 CH3OCV : 1; uint32 CH4OCV : 1; uint32 CH5OCV : 1; uint32 CH6OCV : 1; uint32 CH7OCV : 1; uint32 RSVD_31_16 : 16; } TIM_OUTSWCR; struct { uint32 FCTLEN0 : 1; uint32 DTEN0 : 1; uint32 COMB0 : 1; uint32 SYNCEN0 : 1; uint32 DECAPEN0 : 1; uint32 DECAP0 : 1; uint32 RSVD_7_6 : 2; uint32 FCTLEN1 : 1; uint32 DTEN1 : 1; uint32 COMB1 : 1; uint32 SYNCEN1 : 1; uint32 DECAPEN1 : 1; uint32 DECAP1 : 1; uint32 RSVD_15_14 : 2; uint32 FCTLEN2 : 1; uint32 DTEN2 : 1; uint32 COMB2 : 1; uint32 SYNCEN2 : 1; uint32 DECAPEN2 : 1; uint32 DECAP2 : 1; uint32 RSVD_23_22 : 2; uint32 FCTLEN3 : 1; uint32 DTEN3 : 1; uint32 COMB3 : 1; uint32 SYNCEN3 : 1; uint32 DECAPEN3 : 1; uint32 DECAP3 : 1; uint32 RSVD_31_30 : 2; } TIM_PCR; struct { uint32 FILVAL0 : 4; uint32 FILVAL1 : 4; uint32 FILVAL2 : 4; uint32 FILVAL3 : 4; uint32 DTPS : 2; uint32 DTVAL : 6; uint32 RSVD_31_24 : 8; } TIM_FILTER; struct { uint32 FAULTEN0 : 1; uint32 FIFEN0 : 1; uint32 FLTPOL0 : 1; uint32 FAULTEN1 : 1; uint32 FIFEN1 : 1; uint32 FLTPOL1 : 1; uint32 FLTIE : 1; uint32 FLTCEN : 1; uint32 FLTCM : 1; uint32 RSVD_10_9 : 2; uint32 FIFVAL : 4; uint32 FSTATE : 1; uint32 RSVD_31_16 : 16; } TIM_FLTCR; struct { uint32 FAULTF0 : 1; uint32 FAULTF1 : 1; uint32 RSVD_3_2 : 2; uint32 FAULTF : 1; uint32 FAULTIN : 1; uint32 WPEN : 1; uint32 RSVD_31_7 : 25; } TIM_FLTSR; struct { uint32 SWTRIG : 1; uint32 RSVD_7_1 : 7; uint32 SYNCINIT : 1; uint32 SYNCOSWC : 1; uint32 RSVD_17_10 : 8; uint32 SWWRBUF : 1; uint32 SWRSTCNT : 1; uint32 RSVD_31_20 : 12; } TIM_SYNC; struct { uint32 CH0SEL : 1; uint32 CH1SEL : 1; uint32 CH2SEL : 1; uint32 CH3SEL : 1; uint32 CH4SEL : 1; uint32 CH5SEL : 1; uint32 CH6SEL : 1; uint32 CH7SEL : 1; uint32 LOADEN : 1; uint32 RSVD_10_9 : 2; uint32 HCSEL : 1; uint32 RSVD_15_12 : 4; uint32 LDFREQ : 5; uint32 RSVD_31_21 : 11; } TIM_RELOAD; struct { uint32 HCV : 16; uint32 RSVD_31_16 : 16; } TIM_HCV; }; struct Reg_Tim_W { uint32 TIM_TIMEBASE; uint32 TIM_CNT; uint32 TIM_CNTINIT; uint32 TIM_MOD; uint32 TIM_GLBCR; uint32 TIM_GLBSR; uint32 TIM_CMCn[8]; uint32 TIM_CCVn[8]; uint32 TIM_OUTCR; uint32 TIM_OUTSWCR; uint32 TIM_PCR; uint32 TIM_FILTER; uint32 TIM_FLTCR; uint32 TIM_FLTSR; uint32 TIM_SYNC; uint32 TIM_RELOAD; uint32 TIM_HCV; }; typedef volatile struct Reg_Tim_Bf Reg_Tim_BfType; typedef volatile struct Reg_Tim_W Reg_Tim_WType; struct Reg_Tmu_Bf { struct { uint32 SEL : 16; uint32 EN : 1; uint32 RSVD_30_17 : 14; uint32 LOCK : 1; } TMU_CFGn[40]; }; struct Reg_Tmu_W { uint32 TMU_CFGn[40]; }; typedef volatile struct Reg_Tmu_Bf Reg_Tmu_BfType; typedef volatile struct Reg_Tmu_W Reg_Tmu_WType; struct Reg_Trng_Bf { uint32 zResverd0x0000; uint32 zResverd0x0004; struct { uint32 RD : 1; uint32 IN : 1; uint32 TA : 1; uint32 CA : 1; uint32 RSVD_31_4 : 28; } TRNG_STATUS; struct { uint32 EN : 1; uint32 SM : 1; uint32 RSVD_3_2 : 2; uint32 DEC : 10; uint32 LP : 5; uint32 RSVD_31_19 : 13; } TRNG_CONFIG; struct { uint32 GE : 1; uint32 IN : 1; uint32 HT : 1; uint32 UN : 1; uint32 RS : 1; uint32 AK : 1; uint32 RSVD_31_6 : 26; } CTR_DRBG_CONTROL; struct { uint32 RS : 12; uint32 RP : 20; } CTR_DRBG_REQUEST_SIZE; struct { uint32 RP : 32; } CTR_DRBG_CONFIG_1; struct { uint32 HTP : 32; } CTR_DRBG_CONFIG_2; struct { uint32 AL0 : 1; uint32 AL1 : 1; uint32 AL2 : 1; uint32 AL3 : 1; uint32 VA : 1; uint32 RSVD_31_5 : 27; } TRNG_ALARM; struct { uint32 AL0 : 1; uint32 AL1 : 1; uint32 AL2 : 1; uint32 VA : 1; uint32 RSVD_31_4 : 28; } CTR_DRBG_ALARM; struct { uint32 FL : 1; uint32 RSVD_31_1 : 31; } TRNG_RAW_RANDOM_CONTROL; struct { uint32 DATA : 16; uint32 VA : 1; uint32 RSVD_31_17 : 15; } TRNG_RAW_RANDOM_DATA; struct { uint32 DATA : 16; uint32 VA : 1; uint32 RSVD_31_17 : 15; } CTR_DRBG_RANDOM_DATA; struct { uint32 I0 : 1; uint32 I1 : 1; uint32 I2 : 1; uint32 I3 : 1; uint32 MC : 1; uint32 RE : 1; uint32 E0 : 1; uint32 E1 : 1; uint32 E2 : 1; uint32 E3 : 1; uint32 SE : 1; uint32 RSVD_31_11 : 21; } ADDITIONAL_CONFIG_0; struct { uint32 AC1 : 11; uint32 RSVD_31_11 : 21; } ADDITIONAL_CONFIG_1; struct { uint32 AC2 : 32; } ADDITIONAL_CONFIG_2; struct { uint32 NS : 1; uint32 RSVD_31_1 : 31; } ADDITIONAL_MEAS_CONTROL; struct { uint32 TIME : 30; uint32 SEL : 2; } ADDITIONAL_MEAS_CONFIG; struct { uint32 RD : 1; uint32 OV : 1; uint32 RSVD_31_2 : 30; } ADDITIONAL_MEAS_STATUS; struct { uint32 D0 : 32; } ADDITIONAL_MEAS_DATA_0; struct { uint32 D1 : 32; } ADDITIONAL_MEAS_DATA_1; struct { uint32 IS0 : 1; uint32 IS1 : 1; uint32 IS2 : 1; uint32 IS3 : 1; uint32 RSVD_31_4 : 28; } IRQ_STATUS; struct { uint32 CL0 : 1; uint32 CL1 : 1; uint32 CL2 : 1; uint32 CL3 : 1; uint32 RSVD_31_4 : 28; } IRQ_CLEAR; struct { uint32 E0 : 1; uint32 E1 : 1; uint32 E2 : 1; uint32 E3 : 1; uint32 RSVD_31_4 : 28; } IRQ_CONFIG; struct { uint32 TIMEOUT : 32; } ERROR_CONFIG; struct { uint32 ST : 1; uint32 RSVD_31_1 : 31; } ERROR_CONTROL; struct { uint32 RD : 1; uint32 OV : 1; uint32 TR : 1; uint32 RSVD_31_3 : 29; } ERROR_STATUS; struct { uint32 MO : 1; uint32 RSVD_31_1 : 31; } STATS_CONFIG; struct { uint32 CL : 1; uint32 RSVD_31_1 : 31; } STATS_CONTROL; struct { uint32 EV : 16; uint32 PA : 16; } STATS_DATA; }; struct Reg_Trng_W { uint32 zResverd0x0000; uint32 zResverd0x0004; uint32 TRNG_STATUS; uint32 TRNG_CONFIG; uint32 CTR_DRBG_CONTROL; uint32 CTR_DRBG_REQUEST_SIZE; uint32 CTR_DRBG_CONFIG_1; uint32 CTR_DRBG_CONFIG_2; uint32 TRNG_ALARM; uint32 CTR_DRBG_ALARM; uint32 TRNG_RAW_RANDOM_CONTROL; uint32 TRNG_RAW_RANDOM_DATA; uint32 CTR_DRBG_RANDOM_DATA; uint32 ADDITIONAL_CONFIG_0; uint32 ADDITIONAL_CONFIG_1; uint32 ADDITIONAL_CONFIG_2; uint32 ADDITIONAL_MEAS_CONTROL; uint32 ADDITIONAL_MEAS_CONFIG; uint32 ADDITIONAL_MEAS_STATUS; uint32 ADDITIONAL_MEAS_DATA_0; uint32 ADDITIONAL_MEAS_DATA_1; uint32 IRQ_STATUS; uint32 IRQ_CLEAR; uint32 IRQ_CONFIG; uint32 ERROR_CONFIG; uint32 ERROR_CONTROL; uint32 ERROR_STATUS; uint32 STATS_CONFIG; uint32 STATS_CONTROL; uint32 STATS_DATA; }; typedef volatile struct Reg_Trng_Bf Reg_Trng_BfType; typedef volatile struct Reg_Trng_W Reg_Trng_WType; struct Reg_Uart_Bf { union { struct { uint32 RBR_LSB : 8; uint32 RBR_MSB : 1; uint32 RSVD_31_9 : 23; } UART_RBR; struct { uint32 THR_LSB : 8; uint32 THR_MSB : 1; uint32 RSVD_31_9 : 23; } UART_THR; struct { uint32 DL_L : 8; uint32 RSVD_31_8 : 24; } UART_DLL; } UART_RBR_THR_DLL; union { struct { uint32 DL_H : 8; uint32 RSVD_31_8 : 24; } UART_DLH; struct { uint32 ERBFI : 1; uint32 ETBEI : 1; uint32 ELSI : 1; uint32 EDSSI : 1; uint32 RSVD_6_4 : 3; uint32 PTIME : 1; uint32 HEADER_DONE_INT_EN : 1; uint32 RSP_DONE_INT_EN : 1; uint32 ASYNC_INT_EN : 1; uint32 RSVD_31_11 : 21; } UART_IER; } UART_DLH_IER; union { struct { uint32 IID : 4; uint32 RSVD_5_4 : 2; uint32 FIFOSE : 2; uint32 RSVD_31_8 : 24; } UART_IIR; struct { uint32 FIFOE : 1; uint32 RFIFOR : 1; uint32 XFIFOR : 1; uint32 RSVD_3 : 1; uint32 TET : 2; uint32 RCVR : 2; uint32 RSVD_31_8 : 24; } UART_FCR; } UART_IIR_FCR; struct { uint32 DLS : 2; uint32 STOP : 1; uint32 PEN : 1; uint32 EPS : 1; uint32 RSVD_5 : 1; uint32 BC : 1; uint32 DLAB : 1; uint32 LBKEN : 1; uint32 LBKM : 5; uint32 IDLE_DET_LENGTH : 3; uint32 IDLE_DET_EN : 1; uint32 AUTO_SYNC_EN : 1; uint32 DEBUG_EN : 1; uint32 RSVD_31_20 : 12; } UART_LCR; struct { uint32 RSVD_0 : 1; uint32 RTS : 1; uint32 RSVD_2 : 1; uint32 RSVD_3 : 1; uint32 LB : 1; uint32 AFCE : 1; uint32 RSVD_6 : 1; uint32 RSVD_31_7 : 25; } UART_AFCR; struct { uint32 DR : 1; uint32 OE : 1; uint32 PE : 1; uint32 FE : 1; uint32 BI : 1; uint32 THRE : 1; uint32 TEMT : 1; uint32 RFE : 1; uint32 ADDR_RCVD : 1; uint32 ASYNC_INT : 1; uint32 SYNC_FIELD_ERROR : 1; uint32 PID_ERR : 1; uint32 CHECKSUM_ERROR : 1; uint32 TO_ERROR : 1; uint32 HEADER_OP_DONE : 1; uint32 RSP_OP_DONE : 1; uint32 RSVD_31_16 : 16; } UART_LSR; struct { uint32 RSVD_3_0 : 4; uint32 CTS : 1; uint32 RSVD_31_5 : 27; } UART_MSR; uint8 zResverd0x01C[96]; struct { uint32 BUSY : 1; uint32 RSVD_31_1 : 31; } UART_USR; uint8 zResverd0x080[40]; struct { uint32 RSVD_0 : 1; uint32 RSVD_31_1 : 31; } UART_DMA_SA; uint8 zResverd0x0AC[20]; struct { uint32 FD : 4; uint32 RSVD_31_4 : 28; } UART_FD; struct { uint32 RAR : 8; uint32 RSVD_31_8 : 24; } UART_RAR; struct { uint32 TAR : 8; uint32 RSVD_31_8 : 24; } UART_TAR; struct { uint32 DLS_E : 1; uint32 ADDR_MATCH : 1; uint32 SEND_ADDR : 1; uint32 TRANSMIST_MODE : 1; uint32 RSVD_31_4 : 28; } UART_LCR_EXT; uint8 zResverd0x0D0[48]; struct { uint32 LIN_MODE : 1; uint32 MASTER_MODE : 1; uint32 HEADER_OP_START : 1; uint32 RSP_OP_START : 1; uint32 RSP_DIR : 1; uint32 RSVD_31_5 : 27; } UART_LIN_CTL; struct { uint32 RSP_LENGTH : 4; uint32 RSVD_31_4 : 28; } UART_LIN_RSP_LENGTH; struct { uint32 PID : 8; uint32 RSVD_31_8 : 24; } UART_LIN_PID_VALUE; struct { uint32 CHECKSUM_TYPE : 1; uint32 RSVD_7_1 : 7; uint32 RSVD_31_8 : 24; } UART_LIN_CHECKSUM; struct { uint32 LIN_DEL_LENGTH : 3; uint32 RSVD_31_3 : 29; } UART_LIN_DEL_LENGTH; struct { uint32 FID0 : 6; uint32 RSVD_7_6 : 2; uint32 FID1 : 6; uint32 RSVD_15_14 : 2; uint32 FID2 : 6; uint32 RSVD_23_22 : 2; uint32 FID3 : 6; uint32 RSVD_31_30 : 2; } UART_LIN_PID_FILTER_0; struct { uint32 FID4 : 6; uint32 RSVD_7_6 : 2; uint32 FID5 : 6; uint32 RSVD_15_14 : 2; uint32 FID6 : 6; uint32 RSVD_23_22 : 2; uint32 FID7 : 6; uint32 RSVD_31_30 : 2; } UART_LIN_PID_FILTER_1; struct { uint32 FID8 : 6; uint32 RSVD_7_6 : 2; uint32 FID9 : 6; uint32 RSVD_15_14 : 2; uint32 FID10 : 6; uint32 RSVD_23_22 : 2; uint32 FID11 : 6; uint32 RSVD_31_30 : 2; } UART_LIN_PID_FILTER_2; struct { uint32 FID12 : 6; uint32 RSVD_7_6 : 2; uint32 FID13 : 6; uint32 RSVD_15_14 : 2; uint32 FID14 : 6; uint32 RSVD_23_22 : 2; uint32 FID15 : 6; uint32 RSVD_31_30 : 2; } UART_LIN_PID_FILTER_3; struct { uint32 FID_VAGUE : 6; uint32 RSVD_31_6 : 26; } UART_LIN_PID_FILTER_VAGUE; struct { uint32 FID_MASK : 17; uint32 FID_VAGUE_MASK : 6; uint32 LIN_FILTER_EN : 1; uint32 RSVD_31_24 : 8; } UART_LIN_PID_FILTER_CTRL; }; struct Reg_Uart_W { union { uint32 UART_RBR; uint32 UART_THR; uint32 UART_DLL; } UART_RBR_THR_DLL; union { uint32 UART_DLH; uint32 UART_IER; } UART_DLH_IER; union { uint32 UART_IIR; uint32 UART_FCR; } UART_IIR_FCR; uint32 UART_LCR; uint32 UART_AFCR; uint32 UART_LSR; uint32 UART_MSR; uint8 zResverd0x01C[96]; uint32 UART_USR; uint8 zResverd0x080[40]; uint32 UART_DMA_SA; uint8 zResverd0x0AC[20]; uint32 UART_FD; uint32 UART_RAR; uint32 UART_TAR; uint32 UART_LCR_EXT; uint8 zResverd0x0D0[48]; uint32 UART_LIN_CTL; uint32 UART_LIN_RSP_LENGTH; uint32 UART_LIN_PID_VALUE; uint32 UART_LIN_CHECKSUM; uint32 UART_LIN_DEL_LENGTH; uint32 UART_LIN_PID_FILTER_0; uint32 UART_LIN_PID_FILTER_1; uint32 UART_LIN_PID_FILTER_2; uint32 UART_LIN_PID_FILTER_3; uint32 UART_LIN_PID_FILTER_VAGUE; uint32 UART_LIN_PID_FILTER_CTRL; }; typedef volatile struct Reg_Uart_Bf Reg_Uart_BfType; typedef volatile struct Reg_Uart_W Reg_Uart_WType; struct Reg_Wdog_Bf { uint32 zResverd0x0; struct { uint32 INT_PRESENT : 1; uint32 RSVD_31_1 : 31; } WDOG_PARAM; struct { uint32 WDOGE : 1; uint32 DEBUGE : 1; uint32 WAITE : 1; uint32 STOPE : 1; uint32 INTE : 1; uint32 WINE : 1; uint32 CFGUA : 1; uint32 RSVD_7 : 1; uint32 CLKS : 2; uint32 RSVD_15_10 : 6; uint32 TSTM : 3; uint32 RSVD_23_19 : 5; uint32 CFGUF : 1; uint32 UNLKF : 1; uint32 INTF : 1; uint32 RSVD_31_27 : 5; } WDOG_CS; struct { uint32 TMO : 32; } WDOG_TMO; struct { uint32 WIN : 32; } WDOG_WIN; struct { uint32 CNT : 32; } WDOG_CNT; }; struct Reg_Wdog_W { uint32 zResverd0x0; uint32 WDOG_PARAM; uint32 WDOG_CS; uint32 WDOG_TMO; uint32 WDOG_WIN; uint32 WDOG_CNT; }; typedef volatile struct Reg_Wdog_Bf Reg_Wdog_BfType; typedef volatile struct Reg_Wdog_W Reg_Wdog_WType; # 20 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices\\Device_Regs.h" 2 # 32 "../../../mcal/Platform_ZX_K14xM/Inc/Interrupt_Drv_Types.h" 2 # 96 "../../../mcal/Platform_ZX_K14xM/Inc/Interrupt_Drv_Types.h" typedef void (*Interrupt_Drv_IrqHandlerType)(void); typedef struct { IRQn_Type IrqNumber; boolean IrqEnabled; uint8 IrqPriority; Interrupt_Drv_IrqHandlerType IrqHandler; } Interrupt_Drv_IrqConfigType; typedef struct { uint32 ConfigIrqCount; const Interrupt_Drv_IrqConfigType *IrqConfigList; } Interrupt_Drv_ConfigType; # 31 "../../../mcal/Platform_ZX_K14xM/Inc/Platform_TypesDef.h" 2 # 156 "../../../mcal/Platform_ZX_K14xM/Inc/Platform_TypesDef.h" typedef struct { const Interrupt_Drv_ConfigType *InterruptConfigPtr; } Platform_ConfigType; typedef Interrupt_Drv_IrqHandlerType Platform_IrqHandlerType; # 30 "../../../mcal/Platform_ZX_K14xM/Inc\\Platform.h" 2 # 81 "../../../mcal/Platform_ZX_K14xM/Inc\\Platform.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 82 "../../../mcal/Platform_ZX_K14xM/Inc\\Platform.h" 2 extern const Platform_ConfigType Platform_Configuration; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" #pragma clang section rodata = "" # 87 "../../../mcal/Platform_ZX_K14xM/Inc\\Platform.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" #pragma clang section text = ".mcal_code" # 95 "../../../mcal/Platform_ZX_K14xM/Inc\\Platform.h" 2 # 104 "../../../mcal/Platform_ZX_K14xM/Inc\\Platform.h" void Platform_Init(const Platform_ConfigType *ConfigPtr); # 116 "../../../mcal/Platform_ZX_K14xM/Inc\\Platform.h" Std_ReturnType Platform_SetIrq(IRQn_Type IrqNumber, boolean Enable); # 128 "../../../mcal/Platform_ZX_K14xM/Inc\\Platform.h" Std_ReturnType Platform_SetIrqPriority(IRQn_Type IrqNumber, uint32 Priority); # 140 "../../../mcal/Platform_ZX_K14xM/Inc\\Platform.h" Std_ReturnType Platform_GetIrqPriority(IRQn_Type IrqNumber, uint32 *PriorityPtr); # 153 "../../../mcal/Platform_ZX_K14xM/Inc\\Platform.h" Std_ReturnType Platform_InstallIrqHandler(IRQn_Type IrqNumber, const Platform_IrqHandlerType NewHandler, Platform_IrqHandlerType *const OldHandlerPtr); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Platform_MemMap.h" #pragma clang section text = "" # 159 "../../../mcal/Platform_ZX_K14xM/Inc\\Platform.h" 2 # 15 "../Src/main.h" 2 # 1 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Can.h" 1 # 59 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Can.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Rte_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Rte_MemMap.h" #pragma clang section text = ".mcal_code" # 60 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Can.h" 2 extern void SchM_Enter_Can_DisableIntGlobal(void); extern void SchM_Exit_Can_DisableIntGlobal(void); extern void SchM_Enter_Can_DisableModule(void); extern void SchM_Exit_Can_DisableModule(void); extern void SchM_Enter_Can_DisableClock(void); extern void SchM_Exit_Can_DisableClock(void); extern void SchM_Enter_Can_SetStandardBitTiming(void); extern void SchM_Exit_Can_SetStandardBitTiming(void); extern void SchM_Enter_Can_ConfigFdDataBitTiming(void); extern void SchM_Exit_Can_ConfigFdDataBitTiming(void); extern void SchM_Enter_Can_ConfigFdCompensation(void); extern void SchM_Exit_Can_ConfigFdCompensation(void); extern void SchM_Enter_Can_SetTxArbitrationDelay(void); extern void SchM_Exit_Can_SetTxArbitrationDelay(void); extern void SchM_Enter_Can_InterMaskBuff(void); extern void SchM_Exit_Can_InterMaskBuff(void); extern void SchM_Enter_Can_ConfigTimeStamp(void); extern void SchM_Exit_Can_ConfigTimeStamp(void); extern void SchM_Enter_Can_RecoveryBusOff(void); extern void SchM_Exit_Can_RecoveryBusOff(void); extern void SchM_Enter_Can_CanCtl1Reg(void); extern void SchM_Exit_Can_CanCtl1Reg(void); extern void SchM_Enter_Can_CanCtl2Reg(void); extern void SchM_Exit_Can_CanCtl2Reg(void); extern void SchM_Enter_Can_CanMcrReg(void); extern void SchM_Exit_Can_CanMcrReg(void); extern void SchM_Enter_Can_CanMecrReg(void); extern void SchM_Exit_Can_CanMecrReg(void); extern void SchM_Enter_Can_CanRxmgMskReg(void); extern void SchM_Exit_Can_CanRxmgMskReg(void); extern void SchM_Enter_Can_SetFdArbitrationBitTiming(void); extern void SchM_Exit_Can_SetFdArbitrationBitTiming(void); extern void SchM_Enter_Can_SetSelfWakeup(void); extern void SchM_Exit_Can_SetSelfWakeup(void); # 211 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Can.h" extern void Can_MainFunction_BusOff(void); extern void Can_MainFunction_Write(void); extern void Can_MainFunction_Read(void); # 231 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Can.h" extern void Can_MainFunction_Mode(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Rte_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Rte_MemMap.h" #pragma clang section text = "" # 235 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Can.h" 2 # 16 "../Src/main.h" 2 # 1 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" 1 # 28 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" # 1 "../../../mcal/Dma_ZX_K14xM/Inc/CDD_Dma_Types.h" 1 # 27 "../../../mcal/Dma_ZX_K14xM/Inc/CDD_Dma_Types.h" # 1 "../Generated/inc\\CDD_Dma_Cfg.h" 1 # 30 "../Generated/inc\\CDD_Dma_Cfg.h" # 1 "../Generated/inc/CDD_Dma_PBcfg.h" 1 # 31 "../Generated/inc\\CDD_Dma_Cfg.h" 2 # 28 "../../../mcal/Dma_ZX_K14xM/Inc/CDD_Dma_Types.h" 2 # 1 "../../../mcal/Dma_ZX_K14xM/Inc/Dma_Drv_Types.h" 1 # 31 "../../../mcal/Dma_ZX_K14xM/Inc/Dma_Drv_Types.h" # 1 "../Generated/inc\\Dma_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Dma_Drv_Cfg.h" # 1 "../Generated/inc/Dma_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Dma_Drv_Cfg.h" 2 # 32 "../../../mcal/Dma_ZX_K14xM/Inc/Dma_Drv_Types.h" 2 # 88 "../../../mcal/Dma_ZX_K14xM/Inc/Dma_Drv_Types.h" typedef enum { DMA_DRV_PHYS_CH_0 = 0U, DMA_DRV_PHYS_CH_1, DMA_DRV_PHYS_CH_2, DMA_DRV_PHYS_CH_3, DMA_DRV_PHYS_CH_4, DMA_DRV_PHYS_CH_5, DMA_DRV_PHYS_CH_6, DMA_DRV_PHYS_CH_7, DMA_DRV_PHYS_CH_8, DMA_DRV_PHYS_CH_9, DMA_DRV_PHYS_CH_10, DMA_DRV_PHYS_CH_11, DMA_DRV_PHYS_CH_12, DMA_DRV_PHYS_CH_13, DMA_DRV_PHYS_CH_14, DMA_DRV_PHYS_CH_15 } Dma_Drv_ChannelType; typedef void (*Dma_Drv_CallbackType)(const Dma_Drv_ChannelType Channel); typedef void (*Dma_Drv_ErrIntCallbackType)(const Dma_Drv_ChannelType Channel); typedef enum { DMA_DRV_PRIORITY_LEVEL_0 = 0U, DMA_DRV_PRIORITY_LEVEL_1, DMA_DRV_PRIORITY_LEVEL_2, DMA_DRV_PRIORITY_LEVEL_3, DMA_DRV_PRIORITY_LEVEL_4, DMA_DRV_PRIORITY_LEVEL_5, DMA_DRV_PRIORITY_LEVEL_6, DMA_DRV_PRIORITY_LEVEL_7, DMA_DRV_PRIORITY_LEVEL_8, DMA_DRV_PRIORITY_LEVEL_9, DMA_DRV_PRIORITY_LEVEL_10, DMA_DRV_PRIORITY_LEVEL_11, DMA_DRV_PRIORITY_LEVEL_12, DMA_DRV_PRIORITY_LEVEL_13, DMA_DRV_PRIORITY_LEVEL_14, DMA_DRV_PRIORITY_LEVEL_15 } Dma_Drv_ChannelPriorityType; typedef enum { DMA_DRV_TRANSFER_SIZE_1BYTE = 0U, DMA_DRV_TRANSFER_SIZE_2BYTE, DMA_DRV_TRANSFER_SIZE_4BYTE } Dma_Drv_TransferSizeType; typedef enum { DMA_DRV_REQ_I2S0 = 0U, DMA_DRV_REQ_I2S1 = 1U, DMA_DRV_REQ_UART0_TX = 2U, DMA_DRV_REQ_UART0_RX = 3U, DMA_DRV_REQ_UART1_TX = 4U, DMA_DRV_REQ_UART1_RX = 5U, DMA_DRV_REQ_UART2_TX = 6U, DMA_DRV_REQ_UART2_RX = 7U, DMA_DRV_REQ_UART3_TX = 8U, DMA_DRV_REQ_UART3_RX = 9U, DMA_DRV_REQ_UART4_TX = 10U, DMA_DRV_REQ_UART4_RX = 11U, DMA_DRV_REQ_UART5_TX = 12U, DMA_DRV_REQ_UART5_RX = 13U, DMA_DRV_REQ_SPI0_TX = 14U, DMA_DRV_REQ_SPI0_RX = 15U, DMA_DRV_REQ_SPI1_TX = 16U, DMA_DRV_REQ_SPI1_RX = 17U, DMA_DRV_REQ_SPI2_TX = 18U, DMA_DRV_REQ_SPI2_RX = 19U, DMA_DRV_REQ_SPI3_TX = 20U, DMA_DRV_REQ_SPI3_RX = 21U, DMA_DRV_REQ_STIM0 = 22U, DMA_DRV_REQ_STIM1 = 23U, DMA_DRV_REQ_STIM2 = 24U, DMA_DRV_REQ_STIM3 = 25U, DMA_DRV_REQ_I2C0_TX = 26U, DMA_DRV_REQ_I2C0_RX = 27U, DMA_DRV_REQ_I2C1_TX = 28U, DMA_DRV_REQ_I2C1_RX = 29U, DMA_DRV_REQ_CAN0 = 30U, DMA_DRV_REQ_CAN1 = 31U, DMA_DRV_REQ_CAN2 = 32U, DMA_DRV_REQ_CAN3 = 33U, DMA_DRV_REQ_CAN4 = 34U, DMA_DRV_REQ_CAN5 = 35U, DMA_DRV_REQ_CAN6 = 36U, DMA_DRV_REQ_CAN7 = 37U, DMA_DRV_REQ_TIM0_CHANNEL0 = 38U, DMA_DRV_REQ_TIM0_CHANNEL1 = 39U, DMA_DRV_REQ_TIM0_CHANNEL2 = 40U, DMA_DRV_REQ_TIM0_CHANNEL3 = 41U, DMA_DRV_REQ_TIM0_CHANNEL4 = 42U, DMA_DRV_REQ_TIM0_CHANNEL5 = 43U, DMA_DRV_REQ_TIM0_CHANNEL6 = 44U, DMA_DRV_REQ_TIM0_CHANNEL7 = 45U, DMA_DRV_REQ_TIM1_CHANNEL0 = 46U, DMA_DRV_REQ_TIM1_CHANNEL1 = 47U, DMA_DRV_REQ_TIM1_CHANNEL2 = 48U, DMA_DRV_REQ_TIM1_CHANNEL3 = 49U, DMA_DRV_REQ_TIM1_CHANNEL4 = 50U, DMA_DRV_REQ_TIM1_CHANNEL5 = 51U, DMA_DRV_REQ_TIM1_CHANNEL6 = 52U, DMA_DRV_REQ_TIM1_CHANNEL7 = 53U, DMA_DRV_REQ_TIM2_CHANNEL0 = 54U, DMA_DRV_REQ_TIM2_CHANNEL1 = 55U, DMA_DRV_REQ_TIM2_CHANNEL2 = 56U, DMA_DRV_REQ_TIM2_CHANNEL3 = 57U, DMA_DRV_REQ_TIM2_CHANNEL4 = 58U, DMA_DRV_REQ_TIM2_CHANNEL5 = 59U, DMA_DRV_REQ_TIM2_CHANNEL6 = 60U, DMA_DRV_REQ_TIM2_CHANNEL7 = 61U, DMA_DRV_REQ_TIM3_CHANNEL0 = 62U, DMA_DRV_REQ_TIM3_CHANNEL1 = 63U, DMA_DRV_REQ_TIM3_CHANNEL2 = 64U, DMA_DRV_REQ_TIM3_CHANNEL3 = 65U, DMA_DRV_REQ_TIM3_CHANNEL4 = 66U, DMA_DRV_REQ_TIM3_CHANNEL5 = 67U, DMA_DRV_REQ_TIM3_CHANNEL6 = 68U, DMA_DRV_REQ_TIM3_CHANNEL7 = 69U, DMA_DRV_REQ_MCPWM0_CHANNEL0 = 70U, DMA_DRV_REQ_MCPWM0_CHANNEL1 = 71U, DMA_DRV_REQ_MCPWM0_CHANNEL2 = 72U, DMA_DRV_REQ_MCPWM0_CHANNEL3 = 73U, DMA_DRV_REQ_MCPWM0_CHANNEL4 = 74U, DMA_DRV_REQ_MCPWM0_CHANNEL5 = 75U, DMA_DRV_REQ_MCPWM0_CHANNEL6 = 76U, DMA_DRV_REQ_MCPWM0_CHANNEL7 = 77U, DMA_DRV_REQ_MCPWM1_CHANNEL0 = 78U, DMA_DRV_REQ_MCPWM1_CHANNEL1 = 79U, DMA_DRV_REQ_MCPWM1_CHANNEL2 = 80U, DMA_DRV_REQ_MCPWM1_CHANNEL3 = 81U, DMA_DRV_REQ_MCPWM1_CHANNEL4 = 82U, DMA_DRV_REQ_MCPWM1_CHANNEL5 = 83U, DMA_DRV_REQ_MCPWM1_CHANNEL6 = 84U, DMA_DRV_REQ_MCPWM1_CHANNEL7 = 85U, DMA_DRV_REQ_ADC0 = 88U, DMA_DRV_REQ_ADC1 = 89U, DMA_DRV_REQ_CMP = 90U, DMA_DRV_REQ_PORTA = 91U, DMA_DRV_REQ_PORTB = 92U, DMA_DRV_REQ_PORTC = 93U, DMA_DRV_REQ_PORTD = 94U, DMA_DRV_REQ_PORTE = 95U, DMA_DRV_REQ_DMAMUX_ALWAYS_ENABLED0 = 96U, DMA_DRV_REQ_DMAMUX_ALWAYS_ENABLED1 = 97U, DMA_DRV_REQ_SOFTWARE = 128U } Dma_Drv_RequestSourceType; typedef struct { Dma_Drv_RequestSourceType MuxReqSrc; boolean ReqEn; } Dma_Drv_RequestConfigType; typedef struct { uint8 Priority; boolean PreemptionDis; boolean SuspendEn; } Dma_Drv_PriorityConfigType; typedef struct { boolean ErrIntEn; boolean MajorIntEn; Dma_Drv_RequestConfigType * RequestConfig; Dma_Drv_PriorityConfigType * PriorityConfig; } Dma_Drv_ChannelGlobalConfigType; typedef struct { uint32 Addr; sint16 MinorLoopOffset; sint16 MajorLoopOffset; Dma_Drv_TransferSizeType TransferSize; } Dma_Drv_AddrConfigType; typedef struct { uint32 TransferNum; uint16 MinorLoopCnt; boolean ReqDis; } Dma_Drv_TransferControlConfigType; typedef struct { Dma_Drv_AddrConfigType * SourceConfig; Dma_Drv_AddrConfigType * DestinationConfig; Dma_Drv_TransferControlConfigType * ControlConfig; } Dma_Drv_ChannelTransferConfigType; typedef struct { boolean DebugHalt; boolean RoundRobin; boolean ErrHalt; } Dma_Drv_ConfigType; typedef enum { DMA_DRV_INT_ERROR = 0U, DMA_DRV_INT_DONE, DMA_DRV_INT_ALL } Dma_Drv_IntType; typedef enum { DMA_DRV_HALT_OFF = 0U, DMA_DRV_HALT_ON } Dma_Drv_HaltType; # 29 "../../../mcal/Dma_ZX_K14xM/Inc/CDD_Dma_Types.h" 2 # 87 "../../../mcal/Dma_ZX_K14xM/Inc/CDD_Dma_Types.h" typedef void (*Dma_CallbackType)(uint32 LogicChIndex); typedef enum { DMA_CH_UNINIT_STATE = 0U, DMA_CH_READY_STATE = 1U, DMA_CH_ERROR_STATE = 2U } Dma_ChannelStateType; typedef enum { DMA_TRANSFER_SIZE_1BYTE = 0U, DMA_TRANSFER_SIZE_2BYTE, DMA_TRANSFER_SIZE_4BYTE } Dma_TransferSizeType; typedef enum { DMA_REQ_I2S0 = 0U, DMA_REQ_I2S1 = 1U, DMA_REQ_UART0_TX = 2U, DMA_REQ_UART0_RX = 3U, DMA_REQ_UART1_TX = 4U, DMA_REQ_UART1_RX = 5U, DMA_REQ_UART2_TX = 6U, DMA_REQ_UART2_RX = 7U, DMA_REQ_UART3_TX = 8U, DMA_REQ_UART3_RX = 9U, DMA_REQ_UART4_TX = 10U, DMA_REQ_UART4_RX = 11U, DMA_REQ_UART5_TX = 12U, DMA_REQ_UART5_RX = 13U, DMA_REQ_SPI0_TX = 14U, DMA_REQ_SPI0_RX = 15U, DMA_REQ_SPI1_TX = 16U, DMA_REQ_SPI1_RX = 17U, DMA_REQ_SPI2_TX = 18U, DMA_REQ_SPI2_RX = 19U, DMA_REQ_SPI3_TX = 20U, DMA_REQ_SPI3_RX = 21U, DMA_REQ_STIM0 = 22U, DMA_REQ_STIM1 = 23U, DMA_REQ_STIM2 = 24U, DMA_REQ_STIM3 = 25U, DMA_REQ_I2C0_TX = 26U, DMA_REQ_I2C0_RX = 27U, DMA_REQ_I2C1_TX = 28U, DMA_REQ_I2C1_RX = 29U, DMA_REQ_CAN0 = 30U, DMA_REQ_CAN1 = 31U, DMA_REQ_CAN2 = 32U, DMA_REQ_CAN3 = 33U, DMA_REQ_CAN4 = 34U, DMA_REQ_CAN5 = 35U, DMA_REQ_CAN6 = 36U, DMA_REQ_CAN7 = 37U, DMA_REQ_TIM0_CHANNEL0 = 38U, DMA_REQ_TIM0_CHANNEL1 = 39U, DMA_REQ_TIM0_CHANNEL2 = 40U, DMA_REQ_TIM0_CHANNEL3 = 41U, DMA_REQ_TIM0_CHANNEL4 = 42U, DMA_REQ_TIM0_CHANNEL5 = 43U, DMA_REQ_TIM0_CHANNEL6 = 44U, DMA_REQ_TIM0_CHANNEL7 = 45U, DMA_REQ_TIM1_CHANNEL0 = 46U, DMA_REQ_TIM1_CHANNEL1 = 47U, DMA_REQ_TIM1_CHANNEL2 = 48U, DMA_REQ_TIM1_CHANNEL3 = 49U, DMA_REQ_TIM1_CHANNEL4 = 50U, DMA_REQ_TIM1_CHANNEL5 = 51U, DMA_REQ_TIM1_CHANNEL6 = 52U, DMA_REQ_TIM1_CHANNEL7 = 53U, DMA_REQ_TIM2_CHANNEL0 = 54U, DMA_REQ_TIM2_CHANNEL1 = 55U, DMA_REQ_TIM2_CHANNEL2 = 56U, DMA_REQ_TIM2_CHANNEL3 = 57U, DMA_REQ_TIM2_CHANNEL4 = 58U, DMA_REQ_TIM2_CHANNEL5 = 59U, DMA_REQ_TIM2_CHANNEL6 = 60U, DMA_REQ_TIM2_CHANNEL7 = 61U, DMA_REQ_TIM3_CHANNEL0 = 62U, DMA_REQ_TIM3_CHANNEL1 = 63U, DMA_REQ_TIM3_CHANNEL2 = 64U, DMA_REQ_TIM3_CHANNEL3 = 65U, DMA_REQ_TIM3_CHANNEL4 = 66U, DMA_REQ_TIM3_CHANNEL5 = 67U, DMA_REQ_TIM3_CHANNEL6 = 68U, DMA_REQ_TIM3_CHANNEL7 = 69U, DMA_REQ_MCPWM0_CHANNEL0 = 70U, DMA_REQ_MCPWM0_CHANNEL1 = 71U, DMA_REQ_MCPWM0_CHANNEL2 = 72U, DMA_REQ_MCPWM0_CHANNEL3 = 73U, DMA_REQ_MCPWM0_CHANNEL4 = 74U, DMA_REQ_MCPWM0_CHANNEL5 = 75U, DMA_REQ_MCPWM0_CHANNEL6 = 76U, DMA_REQ_MCPWM0_CHANNEL7 = 77U, DMA_REQ_MCPWM1_CHANNEL0 = 78U, DMA_REQ_MCPWM1_CHANNEL1 = 79U, DMA_REQ_MCPWM1_CHANNEL2 = 80U, DMA_REQ_MCPWM1_CHANNEL3 = 81U, DMA_REQ_MCPWM1_CHANNEL4 = 82U, DMA_REQ_MCPWM1_CHANNEL5 = 83U, DMA_REQ_MCPWM1_CHANNEL6 = 84U, DMA_REQ_MCPWM1_CHANNEL7 = 85U, DMA_REQ_ADC0 = 88U, DMA_REQ_ADC1 = 89U, DMA_REQ_CMP = 90U, DMA_REQ_PORTA = 91U, DMA_REQ_PORTB = 92U, DMA_REQ_PORTC = 93U, DMA_REQ_PORTD = 94U, DMA_REQ_PORTE = 95U, DMA_REQ_DMAMUX_ALWAYS_ENABLED0 = 96U, DMA_REQ_DMAMUX_ALWAYS_ENABLED1 = 97U, DMA_REQ_SOFTWARE = 128U } Dma_RequestSourceType; typedef struct { uint32 Addr; sint16 MinorLoopOffset; sint16 MajorLoopOffset; Dma_TransferSizeType TransferSize; } Dma_AddrConfigType; typedef Dma_Drv_TransferControlConfigType Dma_TransferControlConfigType; typedef struct { Dma_AddrConfigType * SourceConfig; Dma_AddrConfigType * DestinationConfig; Dma_TransferControlConfigType * ControlConfig; } Dma_ChannelTransferConfigType; typedef struct { Dma_RequestSourceType MuxReqSrc; boolean ReqEn; } Dma_RequestConfigType; typedef Dma_Drv_PriorityConfigType Dma_PriorityConfigType; typedef struct { boolean ErrIntEn; boolean MajorIntEn; Dma_RequestConfigType * RequestConfig; Dma_PriorityConfigType * PriorityConfig; } Dma_ChannelGlobalConfigType; typedef struct { uint32 ChErrState; Dma_ChannelStateType ChState; } Dma_ChannelOptStateType; typedef struct { Dma_Drv_ChannelType PhyChId; Dma_CallbackType ErrIntCallback; Dma_CallbackType MajorIntCallback; const Dma_Drv_ChannelGlobalConfigType * ChGlobalCfgPtr; const Dma_Drv_ChannelTransferConfigType * ChTransferCfgPtr; } Dma_ChannelConfigType; typedef struct { const Dma_ChannelConfigType * const * ChCfgArrayPtr; const Dma_Drv_ConfigType * const * ModuleCfgArrayPtr; } Dma_ConfigType; typedef struct { Dma_ChannelStateType State; uint32 Error; # 342 "../../../mcal/Dma_ZX_K14xM/Inc/CDD_Dma_Types.h" boolean Busy; boolean Done; } Dma_ChannelStatusType; typedef struct { uint16 LastErrChStatus; uint16 ChannelsErrStatus; boolean Busy; boolean Halt; } Dma_ModuleStatusType; typedef enum { DMA_INT_ERROR = 0U, DMA_INT_DONE, DMA_INT_ALL } Dma_IntType; typedef enum { DMA_HALT_OFF = 0U, DMA_HALT_ON } Dma_HaltType; # 29 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" 2 # 99 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1 # 848 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 100 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" 2 extern const Dma_ConfigType *const Dma_PreDefinedConfigPtr; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1 # 864 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" #pragma clang section rodata = "" # 105 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" 2 # 123 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" #pragma clang section text = ".mcal_code" # 124 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" 2 # 134 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" void Dma_Init(const Dma_ConfigType * const CfgPtr); # 146 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" void Dma_GetChannelStatus(const uint32 LogicChIndex, Dma_ChannelStatusType * const StatusPtr); # 159 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" void Dma_Halt(Dma_HaltType Cmd); # 173 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" Std_ReturnType Dma_ConfigChannelTransfer(const uint32 LogicChIndex, const Dma_ChannelTransferConfigType *ChConfigPtr); # 188 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" Std_ReturnType Dma_ConfigChannelGlobalParam(const uint32 LogicChIndex, const Dma_ChannelGlobalConfigType *ChConfigPtr); # 201 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" void Dma_EnableChannelHwRequest(const uint32 LogicChIndex, boolean Enable); # 212 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" void Dma_TriggerChannelStartBySw(const uint32 LogicChIndex); # 227 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" void Dma_ClearIntStatus(const uint32 LogicChIndex, Dma_IntType Int); # 238 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" void Dma_GetHwModuleStatus(Dma_ModuleStatusType * const StatusPtr); # 250 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" void Dma_SetSourceAddr(const uint32 LogicChIndex, uint32 Address); # 262 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" void Dma_SetDestAddr(const uint32 LogicChIndex, uint32 Address); # 274 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" void Dma_GetVersionInfo(Std_VersionInfoType * const VersionInfo); # 289 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" Std_ReturnType Dma_GetChannelTransferConfig(const uint32 LogicChIndex, const Dma_ChannelTransferConfigType * ChConfigPtr); # 304 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" Std_ReturnType Dma_GetChannelGlobalParam(const uint32 LogicChIndex, Dma_ChannelGlobalConfigType * ChConfigPtr); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" #pragma clang section text = "" # 309 "../../../mcal/Dma_ZX_K14xM/Inc\\CDD_Dma.h" 2 # 17 "../Src/main.h" 2 # 1 "../../../mcal/Wdg_ZX_K14xM/Inc\\Wdg.h" 1 # 29 "../../../mcal/Wdg_ZX_K14xM/Inc\\Wdg.h" # 1 "../../../mcal/Wdg_ZX_K14xM/Inc/Wdg_Types.h" 1 # 29 "../../../mcal/Wdg_ZX_K14xM/Inc/Wdg_Types.h" # 1 "../Generated/inc\\Wdg_Cfg.h" 1 # 30 "../Generated/inc\\Wdg_Cfg.h" # 1 "../Generated/inc/Wdg_PBcfg.h" 1 # 31 "../Generated/inc\\Wdg_Cfg.h" 2 # 30 "../../../mcal/Wdg_ZX_K14xM/Inc/Wdg_Types.h" 2 # 1 "../../../mcal/Wdg_ZX_K14xM/Inc/Wdg_Drvw_Types.h" 1 # 30 "../../../mcal/Wdg_ZX_K14xM/Inc/Wdg_Drvw_Types.h" # 1 "../../../mcal/Wdg_ZX_K14xM/Inc/Wdog_Drv_Types.h" 1 # 29 "../../../mcal/Wdg_ZX_K14xM/Inc/Wdog_Drv_Types.h" # 1 "../Generated/inc\\Wdog_Drv_Cfg.h" 1 # 29 "../Generated/inc\\Wdog_Drv_Cfg.h" # 1 "../Generated/inc/Wdog_Drv_PBcfg.h" 1 # 30 "../Generated/inc\\Wdog_Drv_Cfg.h" 2 # 30 "../../../mcal/Wdg_ZX_K14xM/Inc/Wdog_Drv_Types.h" 2 # 1 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Wdg.h" 1 # 55 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Wdg.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Rte_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Rte_MemMap.h" #pragma clang section text = ".mcal_code" # 56 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Wdg.h" 2 extern void SchM_Enter_Wdg_ProtectWdgPreviousMode(void); extern void SchM_Exit_Wdg_ProtectWdgPreviousMode(void); extern void SchM_Enter_Wdg_ProtectWdgGptPeriod(void); extern void SchM_Exit_Wdg_ProtectWdgGptPeriod(void); extern void SchM_Enter_Wdg_ProtectWdgTimeoutValue(void); extern void SchM_Exit_Wdg_ProtectWdgTimeoutValue(void); extern void SchM_Enter_Wdg_ProtectWdgState(void); extern void SchM_Exit_Wdg_ProtectWdgState(void); extern void SchM_Enter_Wdg_WriteRegData(void); extern void SchM_Exit_Wdg_WriteRegData(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Rte_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Rte_MemMap.h" #pragma clang section text = "" # 74 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Wdg.h" 2 # 31 "../../../mcal/Wdg_ZX_K14xM/Inc/Wdog_Drv_Types.h" 2 # 87 "../../../mcal/Wdg_ZX_K14xM/Inc/Wdog_Drv_Types.h" typedef void (*Wdog_Drv_CallbackPtrType)(void); typedef enum { WDOG_DRV_CLOCK_LPO = 0x00U, WDOG_DRV_CLOCK_BUS = 0x01U, WDOG_DRV_CLOCK_FIRC = 0x02U, WDOG_DRV_CLOCK_OSC = 0x03U } Wdog_Drv_ClkSourceType; typedef struct { boolean WaitMode; boolean StopMode; boolean DebugMode; } Wdog_Drv_OperationModeType; typedef enum { WDOG_DRV_STATUS_SUCCESS = 0x00, WDOG_DRV_STATUS_ERROR = 0x01, WDOG_DRV_STATUS_TIMEOUT = 0x02 } Wdog_Drv_StatusType; typedef struct { Wdog_Drv_ClkSourceType ClkSource; Wdog_Drv_OperationModeType OpMode; boolean UpdateEnable; boolean IntEnable; boolean WindowEnable; uint32 WindowValue; uint32 TimeoutValue; Wdog_Drv_CallbackPtrType IntCallbackPtr; } Wdog_Drv_ConfigType; # 31 "../../../mcal/Wdg_ZX_K14xM/Inc/Wdg_Drvw_Types.h" 2 # 1 "../Generated/inc\\Wdg_Drvw_Cfg.h" 1 # 29 "../Generated/inc\\Wdg_Drvw_Cfg.h" # 1 "../Generated/inc/Wdg_Drvw_PBcfg.h" 1 # 30 "../Generated/inc\\Wdg_Drvw_Cfg.h" 2 # 32 "../../../mcal/Wdg_ZX_K14xM/Inc/Wdg_Drvw_Types.h" 2 # 1 "../../../mcal/WdgIf_ZX_K14xM/Inc\\WdgIf.h" 1 # 54 "../../../mcal/WdgIf_ZX_K14xM/Inc\\WdgIf.h" typedef enum { WDGIF_OFF_MODE = 0x00U, WDGIF_SLOW_MODE = 0x01U, WDGIF_FAST_MODE = 0x02U } WdgIf_ModeType; # 33 "../../../mcal/Wdg_ZX_K14xM/Inc/Wdg_Drvw_Types.h" 2 # 114 "../../../mcal/Wdg_ZX_K14xM/Inc/Wdg_Drvw_Types.h" typedef struct { uint32 TimerTriggerPeriod; const Wdog_Drv_ConfigType *WdogDrvConfig; } Wdg_Drvw_ModeType; typedef struct { const WdgIf_ModeType DefaultMode; Wdog_Drv_CallbackPtrType CbBeforeRefreshPtr; Wdog_Drv_CallbackPtrType CbAfterRefreshPtr; const Wdg_Drvw_ModeType *const ModeConfigPtr[3]; }Wdg_Drvw_ConfigType; # 31 "../../../mcal/Wdg_ZX_K14xM/Inc/Wdg_Types.h" 2 # 89 "../../../mcal/Wdg_ZX_K14xM/Inc/Wdg_Types.h" typedef struct { const Wdg_Drvw_ConfigType * DrvwConfigPtr; } Wdg_ConfigType; typedef enum { WDG_UNINIT = 0x01, WDG_IDLE = 0x02, WDG_BUSY = 0x03, } Wdg_StateType; # 30 "../../../mcal/Wdg_ZX_K14xM/Inc\\Wdg.h" 2 # 120 "../../../mcal/Wdg_ZX_K14xM/Inc\\Wdg.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Wdg_MemMap.h" 1 # 848 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Wdg_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 121 "../../../mcal/Wdg_ZX_K14xM/Inc\\Wdg.h" 2 extern const Wdg_ConfigType *const Wdg_PreDefinedConfigPtr; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Wdg_MemMap.h" 1 # 864 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Wdg_MemMap.h" #pragma clang section rodata = "" # 126 "../../../mcal/Wdg_ZX_K14xM/Inc\\Wdg.h" 2 # 150 "../../../mcal/Wdg_ZX_K14xM/Inc\\Wdg.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Wdg_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Wdg_MemMap.h" #pragma clang section text = ".mcal_code" # 151 "../../../mcal/Wdg_ZX_K14xM/Inc\\Wdg.h" 2 void Wdg_Init(const Wdg_ConfigType *ConfigPtr); # 174 "../../../mcal/Wdg_ZX_K14xM/Inc\\Wdg.h" Std_ReturnType Wdg_SetMode(WdgIf_ModeType Mode); # 197 "../../../mcal/Wdg_ZX_K14xM/Inc\\Wdg.h" void Wdg_Service(void); # 211 "../../../mcal/Wdg_ZX_K14xM/Inc\\Wdg.h" void Wdg_GetVersionInfo(Std_VersionInfoType *versioninfo); # 232 "../../../mcal/Wdg_ZX_K14xM/Inc\\Wdg.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Wdg_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Wdg_MemMap.h" #pragma clang section text = "" # 233 "../../../mcal/Wdg_ZX_K14xM/Inc\\Wdg.h" 2 # 18 "../Src/main.h" 2 # 1 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" 1 # 29 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" # 1 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Types.h" 1 # 30 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Types.h" # 1 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Drvw_Types.h" 1 # 29 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Drvw_Types.h" # 1 "../Generated/inc\\Pwm_Drvw_Cfg.h" 1 # 29 "../Generated/inc\\Pwm_Drvw_Cfg.h" # 1 "../Generated/inc/Pwm_Drvw_PBcfg.h" 1 # 30 "../Generated/inc\\Pwm_Drvw_Cfg.h" 2 # 30 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Drvw_Types.h" 2 # 1 "../../../mcal/Pwm_ZX_K14xM/Inc/Mcpwm_Pwm_Drv_Types.h" 1 # 30 "../../../mcal/Pwm_ZX_K14xM/Inc/Mcpwm_Pwm_Drv_Types.h" # 1 "../Generated/inc\\Mcpwm_Pwm_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Mcpwm_Pwm_Drv_Cfg.h" # 1 "../Generated/inc/Mcpwm_Pwm_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Mcpwm_Pwm_Drv_Cfg.h" 2 # 31 "../../../mcal/Pwm_ZX_K14xM/Inc/Mcpwm_Pwm_Drv_Types.h" 2 # 108 "../../../mcal/Pwm_ZX_K14xM/Inc/Mcpwm_Pwm_Drv_Types.h" typedef enum { MCPWM_PWM_DRV_STATUS_SUCCESS = 0x00U, MCPWM_PWM_DRV_STATUS_ERROR = 0x01U, MCPWM_PWM_DRV_STATUS_BUSY = 0x002U, MCPWM_PWM_DRV_STATUS_TIMEOUT = 0x003U, MCPWM_PWM_DRV_STATUS_UNSUPPORTED = 0x004U } Mcpwm_Pwm_Drv_StatusType; typedef enum { MCPWM_PWM_DRV_CLK_DISABLE = 0U, MCPWM_PWM_DRV_CLK_SOURCE_SYSTEM = 1U, MCPWM_PWM_DRV_CLK_SOURCE_FUNCTION = 2U, MCPWM_PWM_DRV_CLK_SOURCE_EXTERNAL = 3U } Mcpwm_Pwm_Drv_ClkSourceType; typedef enum { MCPWM_PWM_DRV_CLK_DIVIDE_1 = 0U, MCPWM_PWM_DRV_CLK_DIVIDE_2, MCPWM_PWM_DRV_CLK_DIVIDE_4, MCPWM_PWM_DRV_CLK_DIVIDE_8, MCPWM_PWM_DRV_CLK_DIVIDE_16, MCPWM_PWM_DRV_CLK_DIVIDE_32, MCPWM_PWM_DRV_CLK_DIVIDE_64, MCPWM_PWM_DRV_CLK_DIVIDE_128 } Mcpwm_Pwm_Drv_ClkDivideType; typedef enum { MCPWM_PWM_DRV_COUNTING_UP = 0U, MCPWM_PWM_DRV_COUNTING_UP_AND_DOWN } Mcpwm_Pwm_Drv_CountingModeType; typedef enum { MCPWM_PWM_DRV_LOW_PULSE_POL = 0U, MCPWM_PWM_DRV_HIGH_PULSE_POL } Mcpwm_Pwm_Drv_PulsePolarityType; typedef enum { MCPWM_PWM_DRV_POL_HIGH = 0U, MCPWM_PWM_DRV_POL_LOW } Mcpwm_Pwm_Drv_PolarityType; typedef enum { MCPWM_PWM_DRV_SYMMETRIC = 0U, MCPWM_PWM_DRV_ASYMMETRIC } Mcpwm_Pwm_Drv_AsymType; typedef enum { MCPWM_PWM_DRV_CHANNEL_UNINIT = 0x00U, MCPWM_PWM_DRV_CHANNEL_RUNNING = 0x01U, MCPWM_PWM_DRV_CHANNEL_IDLE = 0x02U, MCPWM_PWM_DRV_CHANNEL_OUTPUT_FORCED = 0x03U } Mcpwm_Pwm_Drv_ChannelStateType; typedef enum { MCPWM_PWM_DRV_OUTPUT_STATE_LOW = 0x00U, MCPWM_PWM_DRV_OUTPUT_STATE_HIGH = 0x01U } Mcpwm_Pwm_Drv_OutputStateType; typedef enum { MCPWM_PWM_DRV_RISING_EDGE = 0U, MCPWM_PWM_DRV_FALLING_EDGE = 1U, MCPWM_PWM_DRV_BOTH_EDGES = 2U } Mcpwm_Pwm_Drv_EdgeNotifType; typedef enum { MCPWM_PWM_DRV_FULL_POWER = 0x00U, MCPWM_PWM_DRV_LOW_POWER = 0x01U, MCPWM_PWM_DRV_NODEFINE_POWER = 0x02U } Mcpwm_Pwm_Drv_PowerStateType; typedef enum { MCPWM_PWM_DRV_MODE_EDGE_ALIGNED = 0x01, MCPWM_PWM_DRV_MODE_CENTER_ALIGNED = 0x02, MCPWM_PWM_DRV_MODE_COMBINE_EDGE_ALIGNED = 0x03, MCPWM_PWM_DRV_MODE_COMBINE_SYM_CENTER_ALIGNED = 0x04, MCPWM_PWM_DRV_MODE_COMBINE_VARIABLE_EDGE_PLACEMENT = 0x06 } Mcpwm_Pwm_Drv_ChannelModeType; typedef uint8 Mcpwm_Pwm_Drv_EdgeInterruptType; typedef void (*Mcpwm_Pwm_Drv_CallbackType)(void); typedef struct { boolean DeadTimeEnable; uint16 PhaseShiftValue; } Mcpwm_Pwm_Drv_PairChannelCfgType; typedef struct { uint8 ChannelId; boolean ChIrqEn; Mcpwm_Pwm_Drv_CallbackType ChannelCb; boolean ChannelOutputEnable; Mcpwm_Pwm_Drv_PolarityType Polarity; Mcpwm_Pwm_Drv_ChannelModeType ChannelMode; uint8 ChannelDither; boolean ChannelMatchTrigEnable; boolean DmaEn; const Mcpwm_Pwm_Drv_PairChannelCfgType *PairCfg; } Mcpwm_Pwm_Drv_ChannelConfigType; typedef struct { uint8 CntId; uint16 PwmPeriod; uint16 PwmPeriodDither; uint16 DeadTimeVal; boolean OverflowIrqEn; Mcpwm_Pwm_Drv_CallbackType OverflowCb; } Mcpwm_Pwm_Drv_CounterType; typedef struct { Mcpwm_Pwm_Drv_ClkSourceType ClkSrc; Mcpwm_Pwm_Drv_ClkDivideType ClkDiv; # 303 "../../../mcal/Pwm_ZX_K14xM/Inc/Mcpwm_Pwm_Drv_Types.h" boolean GlobalCntEn; boolean InitTrigEn; uint8 CounterNum; const Mcpwm_Pwm_Drv_CounterType * const *CounterConfig; } Mcpwm_Pwm_Drv_ConfigType; typedef struct { const Mcpwm_Pwm_Drv_ConfigType *InstanceCfg; const Mcpwm_Pwm_Drv_ChannelConfigType * const *ConfiguredChArray; uint8 NoOfConfiguredCh; } Mcpwm_Pwm_Drv_UserCfgType; # 31 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Drvw_Types.h" 2 # 1 "../../../mcal/Pwm_ZX_K14xM/Inc/Tim_Pwm_Drv_Types.h" 1 # 30 "../../../mcal/Pwm_ZX_K14xM/Inc/Tim_Pwm_Drv_Types.h" # 1 "../Generated/inc\\Tim_Pwm_Drv_Cfg.h" 1 # 30 "../Generated/inc\\Tim_Pwm_Drv_Cfg.h" # 1 "../Generated/inc/Tim_Pwm_Drv_PBcfg.h" 1 # 31 "../Generated/inc\\Tim_Pwm_Drv_Cfg.h" 2 # 31 "../../../mcal/Pwm_ZX_K14xM/Inc/Tim_Pwm_Drv_Types.h" 2 # 107 "../../../mcal/Pwm_ZX_K14xM/Inc/Tim_Pwm_Drv_Types.h" typedef enum { TIM_PWM_DRV_STATUS_SUCCESS = 0x00U, TIM_PWM_DRV_STATUS_ERROR = 0x01U, TIM_PWM_DRV_STATUS_BUSY = 0x002U, TIM_PWM_DRV_STATUS_TIMEOUT = 0x003U, TIM_PWM_DRV_STATUS_UNSUPPORTED = 0x004U } Tim_Pwm_Drv_StatusType; typedef enum { TIM_PWM_DRV_CLK_DISABLE = 0U, TIM_PWM_DRV_CLK_SOURCE_SYSTEM = 1U, TIM_PWM_DRV_CLK_SOURCE_FUNCTION = 2U, TIM_PWM_DRV_CLK_SOURCE_EXTERNAL = 3U } Tim_Pwm_Drv_ClkSourceType; typedef enum { TIM_PWM_DRV_CLK_DIVIDE_1 = 0U, TIM_PWM_DRV_CLK_DIVIDE_2, TIM_PWM_DRV_CLK_DIVIDE_4, TIM_PWM_DRV_CLK_DIVIDE_8, TIM_PWM_DRV_CLK_DIVIDE_16, TIM_PWM_DRV_CLK_DIVIDE_32, TIM_PWM_DRV_CLK_DIVIDE_64, TIM_PWM_DRV_CLK_DIVIDE_128 } Tim_Pwm_Drv_ClkDivideType; typedef enum { TIM_PWM_DRV_COUNTING_UP = 0U, TIM_PWM_DRV_COUNTING_UP_AND_DOWN } Tim_Pwm_Drv_CountingModeType; typedef enum { TIM_PWM_DRV_LOW_PULSE_POL = 1U, TIM_PWM_DRV_HIGH_PULSE_POL } Tim_Pwm_Drv_PulsePolarityType; typedef enum { TIM_PWM_DRV_POL_HIGH = 0U, TIM_PWM_DRV_POL_LOW } Tim_Pwm_Drv_PolarityType; typedef enum { TIM_PWM_DRV_CHANNEL_UNINIT = 0x00U, TIM_PWM_DRV_CHANNEL_RUNNING = 0x01U, TIM_PWM_DRV_CHANNEL_IDLE = 0x02U, TIM_PWM_DRV_CHANNEL_OUTPUT_FORCED = 0x03U } Tim_Pwm_Drv_ChannelStateType; typedef enum { TIM_PWM_DRV_OUTPUT_STATE_LOW = 0x00U, TIM_PWM_DRV_OUTPUT_STATE_HIGH = 0x01U } Tim_Pwm_Drv_OutputStateType; typedef enum { TIM_PWM_DRV_RISING_EDGE = 0U, TIM_PWM_DRV_FALLING_EDGE = 1U, TIM_PWM_DRV_BOTH_EDGES = 2U } Tim_Pwm_Drv_EdgeNotifType; typedef enum { TIM_PWM_DRV_FULL_POWER = 0x00U, TIM_PWM_DRV_LOW_POWER = 0x01U, TIM_PWM_DRV_NODEFINE_POWER = 0x02U } Tim_Pwm_Drv_PowerStateType; typedef enum { TIM_PWM_DRV_MODE_EDGE_ALIGNED = 0x01U, TIM_PWM_DRV_MODE_CENTER_ALIGNED = 0x02U, TIM_PWM_DRV_MODE_COMBINE_VARIABLE_EDGE_PLACEMENT = 0x03U } Tim_Pwm_Drv_ChannelModeType; typedef enum { TIM_PWM_DRV_CLK_DEADTIME_DIVIDE_1 = 0x01U, TIM_PWM_DRV_CLK_DEADTIME_DIVIDE_4 = 0x02U, TIM_PWM_DRV_CLK_DEADTIME_DIVIDE_16 = 0x03U } Tim_Pwm_Drv_DeadTimeDivider; typedef uint8 Tim_Pwm_Drv_EdgeInterruptType; typedef void (*Tim_Pwm_Drv_CallbackType)(void); typedef struct { boolean DeadTimeEnable; uint16 PhaseShiftValue; } Tim_Pwm_Drv_PairChannelCfgType; typedef struct { uint8 ChannelId; boolean ChIrqEn; Tim_Pwm_Drv_CallbackType ChannelCb; boolean ChannelOutputEnable; Tim_Pwm_Drv_PolarityType Polarity; Tim_Pwm_Drv_ChannelModeType ChannelMode; boolean ChannelMatchTrigEnable; boolean DmaEn; const Tim_Pwm_Drv_PairChannelCfgType *PairCfg; } Tim_Pwm_Drv_ChannelConfigType; typedef struct { Tim_Pwm_Drv_ClkSourceType ClkSrc; Tim_Pwm_Drv_ClkDivideType ClkDiv; # 290 "../../../mcal/Pwm_ZX_K14xM/Inc/Tim_Pwm_Drv_Types.h" uint16 PwmPeriod; Tim_Pwm_Drv_CountingModeType PwmCounterMode; Tim_Pwm_Drv_DeadTimeDivider DeadTimeDiv; uint16 DeadTimeVal; boolean InitTrigEn; boolean OverflowIrqEn; Tim_Pwm_Drv_CallbackType OverflowCb; } Tim_Pwm_Drv_ConfigType; typedef struct { const Tim_Pwm_Drv_ConfigType *InstanceCfg; const Tim_Pwm_Drv_ChannelConfigType * const *ConfiguredChArray; uint8 NoOfConfiguredCh; } Tim_Pwm_Drv_UserCfgType; # 32 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Drvw_Types.h" 2 # 104 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Drvw_Types.h" typedef uint8 Pwm_Drvw_ModuleType; typedef enum { PWM_DRVW_HW_NONE = 0x00U, PWM_DRVW_HW_MCPWM = 0x01U, PWM_DRVW_HW_TIM = 0x02U } Pwm_Drvw_HwType; typedef enum { PWM_DRVW_LOW = 0x00U, PWM_DRVW_HIGH } Pwm_Drvw_OutputStateType; typedef uint16 Pwm_Drvw_PeriodType; typedef enum { PWM_DRVW_RISING_EDGE = 0U, PWM_DRVW_FALLING_EDGE, PWM_DRVW_BOTH_EDGE } Pwm_Drvw_EdgeNotificationType; typedef enum { PWM_DRVW_FULL_POWER = 0x00U, PWM_DRVW_LOW_POWER, PWM_DRVW_NODEFINE_POWER } Pwm_Drvw_PowerStateType; typedef struct { const Pwm_Drvw_ModuleType ChnHwId; const Pwm_Drvw_HwType ChnHwType; const uint16 ChannelDutyCycle; const Mcpwm_Pwm_Drv_ChannelConfigType * McpwmChConfig; const Tim_Pwm_Drv_ChannelConfigType * TimChConfig; } Pwm_Drvw_ChannelConfigType; typedef struct { uint8 HwId; const Pwm_Drvw_HwType HwType; const Mcpwm_Pwm_Drv_UserCfgType * McpwmHwConfig; const Tim_Pwm_Drv_UserCfgType * TimHwConfig; } Pwm_Drvw_HwConfigType; # 31 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Types.h" 2 # 1 "../Generated/inc\\Pwm_Cfg.h" 1 # 32 "../Generated/inc\\Pwm_Cfg.h" # 1 "../Generated/inc/Pwm_PBcfg.h" 1 # 52 "../Generated/inc/Pwm_PBcfg.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 53 "../Generated/inc/Pwm_PBcfg.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section rodata = "" # 57 "../Generated/inc/Pwm_PBcfg.h" 2 # 33 "../Generated/inc\\Pwm_Cfg.h" 2 # 32 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Types.h" 2 # 90 "../../../mcal/Pwm_ZX_K14xM/Inc/Pwm_Types.h" typedef uint8 Pwm_ChannelType; typedef uint8 Pwm_HwNumType; typedef Pwm_Drvw_PeriodType Pwm_PeriodType; typedef enum { PWM_LOW = 0x00U, PWM_HIGH } Pwm_OutputStateType; typedef enum { PWM_RISING_EDGE = 0U, PWM_FALLING_EDGE, PWM_BOTH_EDGE } Pwm_EdgeNotificationType; typedef enum { PWM_VARIABLE_PERIOD = 0x00U, PWM_FIXED_PERIOD, PWM_FIXED_PERIOD_SHIFTED } Pwm_ChannelClassType; typedef void (*Pwm_NotifyType)(void); typedef struct { const Pwm_ChannelType ChannelId; const Pwm_ChannelClassType PwmChnClass; const Pwm_Drvw_ChannelConfigType * DrvwChannelCfg; const Pwm_OutputStateType ChannelIdleState; const Pwm_NotifyType PwmChannelNotificationPtr; } Pwm_ChannelConfigType; typedef struct { const Pwm_ChannelType NumChannels; const Pwm_ChannelConfigType (*PwmChannelConfigs)[]; const Pwm_HwNumType NumModules; const Pwm_Drvw_HwConfigType (*PwmHwConfig)[]; } Pwm_ConfigType; typedef enum { PWM_SERVICE_ACCEPTED = 0x00U, PWM_NOT_INIT, PWM_SEQUENCE_ERROR, PWM_HW_FAILURE, PWM_POWER_STATE_NOT_SUPP, PWM_TRANS_NOT_POSSIBLE } Pwm_PowerStateRequestResultType; typedef enum { PWM_FULL_POWER = 0x00U, PWM_LOW_POWER, PWM_NODEFINE_POWER } Pwm_PowerStateType; typedef enum { PWM_STATE_UNINIT = 0x00U, PWM_STATE_IDLE = 0x01U } Pwm_GlobalStateType; typedef struct { Pwm_GlobalStateType PwmGlobalState; Pwm_PowerStateType PwmCurrentPowerState; Pwm_PowerStateType PwmTargetPowerState; } Pwm_DriverStateType; # 30 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" 2 # 320 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 848 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 321 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" 2 extern const Pwm_ConfigType * const Pwm_PreDefinedConfigPtr[(1U)]; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 864 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section rodata = "" # 324 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" 2 # 337 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section text = ".mcal_code" # 338 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" 2 # 350 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_Init(const Pwm_ConfigType * ConfigPtr); # 360 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_DeInit(void); # 372 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_SetDutyCycle(Pwm_ChannelType ChannelNumber, uint16 DutyCycle); # 385 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_SetPeriodAndDuty(Pwm_ChannelType ChannelNumber, Pwm_PeriodType Period, uint16 DutyCycle); # 398 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_SetOutputToIdle(Pwm_ChannelType ChannelNumber); # 411 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" Pwm_OutputStateType Pwm_GetOutputState(Pwm_ChannelType ChannelNumber); # 422 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_DisableNotification(Pwm_ChannelType ChannelNumber); # 435 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_EnableNotification(Pwm_ChannelType ChannelNumber, Pwm_EdgeNotificationType Notification); # 446 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_GetVersionInfo(Std_VersionInfoType * versioninfo); # 461 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" uint16 Pwm_GetChannelDutyCycle(Pwm_ChannelType ChannelNumber); # 473 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_ForceOutputToLowLevel(Pwm_ChannelType ChannelNumber, boolean ForceEnable); # 485 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_SetChannelDeadTimeTicks(Pwm_ChannelType ChannelNumber, uint16 DeadTimeTicks); # 501 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_WriteDutyCycleToBuffer(Pwm_ChannelType ChannelNumber, uint16 DutyCycle); # 517 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_WritePeriodAndDutyToBuffer(Pwm_ChannelType ChannelNumber, Pwm_PeriodType Period, uint16 DutyCycle); # 536 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_WritePhaseShiftTicksToBuffer(Pwm_ChannelType ChannelNumber, Pwm_PeriodType Period, uint16 PhaseShiftTicks); # 548 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_SyncUpdate(uint8 ModuleId); # 562 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_SetPhaseShiftTicks(Pwm_ChannelType ChannelNumber, Pwm_PeriodType Period, uint16 PhaseShiftTicks); # 580 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_SetDutyPhaseShiftTicks(Pwm_ChannelType ChannelNumber, uint16 DutyCycle, uint16 PhaseShiftTicks, boolean SyncUpdate); # 594 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_EnableTriggerOutput(uint8 ModuleId, uint16 TriggerMask); # 606 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_DisableTriggerOutput(uint8 ModuleId, uint16 TriggerMask); # 618 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_MaskOutputs(uint8 ModuleId, uint8 ChannelMask); # 628 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" void Pwm_UnMaskOutputs(uint8 ModuleId, uint8 ChannelMask); # 648 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" Std_ReturnType Pwm_SetPowerState(Pwm_PowerStateRequestResultType * Result); # 663 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" Std_ReturnType Pwm_GetCurrentPowerState(Pwm_PowerStateType * CurrentPowerState, Pwm_PowerStateRequestResultType * Result); # 679 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" Std_ReturnType Pwm_GetTargetPowerState(Pwm_PowerStateType * TargetPowerState, Pwm_PowerStateRequestResultType * Result); # 701 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" Std_ReturnType Pwm_PreparePowerState(Pwm_PowerStateType PowerState, Pwm_PowerStateRequestResultType * Result); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Pwm_MemMap.h" #pragma clang section text = "" # 707 "../../../mcal/Pwm_ZX_K14xM/Inc\\pwm.h" 2 # 19 "../Src/main.h" 2 # 1 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" 1 # 28 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" # 1 "../../../mcal/adc_ZX_K14xM/Inc/Adc_Types.h" 1 # 28 "../../../mcal/adc_ZX_K14xM/Inc/Adc_Types.h" # 1 "../Generated/inc\\Adc_Cfg.h" 1 # 27 "../Generated/inc\\Adc_Cfg.h" # 1 "../Generated/inc/Adc_PBcfg.h" 1 # 28 "../Generated/inc\\Adc_Cfg.h" 2 # 29 "../../../mcal/adc_ZX_K14xM/Inc/Adc_Types.h" 2 # 1 "../../../mcal/adc_ZX_K14xM/Inc/Adc_Drv_Types.h" 1 # 30 "../../../mcal/adc_ZX_K14xM/Inc/Adc_Drv_Types.h" # 1 "../Generated/inc\\Adc_Drv_Cfg.h" 1 # 28 "../Generated/inc\\Adc_Drv_Cfg.h" # 1 "../Generated/inc/Adc_Drv_PBcfg.h" 1 # 72 "../Generated/inc/Adc_Drv_PBcfg.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Adc_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Adc_MemMap.h" #pragma clang section text = ".mcal_code" # 73 "../Generated/inc/Adc_Drv_PBcfg.h" 2 # 83 "../Generated/inc/Adc_Drv_PBcfg.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Adc_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Adc_MemMap.h" #pragma clang section text = "" # 84 "../Generated/inc/Adc_Drv_PBcfg.h" 2 # 29 "../Generated/inc\\Adc_Drv_Cfg.h" 2 # 31 "../../../mcal/adc_ZX_K14xM/Inc/Adc_Drv_Types.h" 2 # 88 "../../../mcal/adc_ZX_K14xM/Inc/Adc_Drv_Types.h" typedef enum { ADC_DRV_RESOLUTION_12BIT = 0x00U, ADC_DRV_RESOLUTION_10BIT = 0x01U, ADC_DRV_RESOLUTION_8BIT = 0x02U } Adc_Drv_ResolutionType; typedef enum { ADC_DRV_AVG_DISABLE = 0x00U, ADC_DRV_AVG_4_CONV = 0x01U, ADC_DRV_AVG_8_CONV = 0x02U, ADC_DRV_AVG_16_CONV = 0x03U, ADC_DRV_AVG_32_CONV = 0x04U } Adc_Drv_AvgSelectType; typedef enum { ADC_DRV_TRIGGER_SOFTWARE = 0x00U, ADC_DRV_TRIGGER_HARDWARE = 0x01U, ADC_DRV_TRIGGER_TDG = 0x02U } Adc_Drv_TriggerType; typedef enum { ADC_DRV_VREF_EXTERNAL = 0x00U, ADC_DRV_VREF_INTERNAL = 0x01U } Adc_Drv_VRefSelType; typedef enum { ADC_DRV_IREF_EXTERNAL = 0U, ADC_DRV_IREF_INTERNAL } Adc_Drv_IRefSelType; typedef enum { ADC_DRV_CONVERSION_SINGLE = 0x00U, ADC_DRV_CONVERSION_CONTINUOUS = 0x01U } ADC_Drv_ConversionType; typedef enum { ADC_DRV_COMPARE_MODE_DISABLED = 0x00U, ADC_DRV_COMPARE_MODE_LESS_CVL, ADC_DRV_COMPARE_MODE_GREATER_CVL, ADC_DRV_COMPARE_MODE_EQUAL_CVL, ADC_DRV_COMPARE_MODE_WITHIN_CVL_CVH, ADC_DRV_COMPARE_MODE_OUT_OF_RANGE_CVL_CVH } ADC_Drv_CompareModeType; typedef enum { ADC_DRV_P_CH0 = 0U, ADC_DRV_P_CH1 = 1U, ADC_DRV_P_CH2 = 2U, ADC_DRV_P_CH3 = 3U, ADC_DRV_P_CH4 = 4U, ADC_DRV_P_CH5 = 5U, ADC_DRV_P_CH6 = 6U, ADC_DRV_P_CH7 = 7U, ADC_DRV_P_CH8 = 8U, ADC_DRV_P_CH9 = 9U, ADC_DRV_P_CH10 = 10U, ADC_DRV_P_CH11 = 11U, ADC_DRV_P_CH12 = 12U, ADC_DRV_P_CH13 = 13U, ADC_DRV_P_CH14 = 14U, ADC_DRV_P_CH15 = 15U, ADC_DRV_P_CH16 = 16U, ADC_DRV_P_CH17 = 17U, ADC_DRV_P_CH18 = 18U, ADC_DRV_P_CH19 = 19U, ADC_DRV_P_CH20 = 20U, ADC_DRV_P_CH25 = 25U, ADC_DRV_P_CH28 = 28U, ADC_DRV_P_CH29 = 29U, ADC_DRV_P_CH30 = 30U } ADC_Drv_PositiveChannelType; typedef enum { ADC_DRV_FWM_INT = 0U, ADC_DRV_FOF_INT = 1U, ADC_DRV_TCOMP_INT = 2U, ADC_DRV_CMP_INT = 3U, ADC_DRV_TC_ERR_INT = 5U } ADC_Drv_InterruptType; typedef enum { ADC_DRV_STATUS_FWM_INT = 0U, ADC_DRV_STATUS_FOF_INT, ADC_DRV_STATUS_TCOMP_INT, ADC_DRV_STATUS_CMP_INT, ADC_DRV_STATUS_DMA_REQ, ADC_DRV_STATUS_FIFO_RDY, ADC_DRV_STATUS_CAL_RDY, ADC_DRV_STATUS_ACTIVE, ADC_DRV_STATUS_LOOP_IDLE, ADC_DRV_STATUS_TC_ERR_INT } ADC_Drv_StatusType; typedef enum { ADC_DRV_LOOP_MODE = 0x00U, ADC_DRV_MAPPING_MODE = 0x01U } ADC_Drv_TdgTriggerModeType; typedef enum { ADC_DRV_CMD_BUFFER_0 = 0x00U, ADC_DRV_CMD_BUFFER_1 = 0x01U, ADC_DRV_CMD_BUFFER_2 = 0x02U, ADC_DRV_CMD_BUFFER_3 = 0x03U, ADC_DRV_CMD_BUFFER_4 = 0x04U, ADC_DRV_CMD_BUFFER_5 = 0x05U } ADC_Drv_CmdBufferType; typedef enum { ADC_DRV_INTERRUPT = 0U, ADC_DRV_DMA } Adc_Drv_TransferModeType; typedef void Adc_Drv_CompleteNotificationType(uint8 Instance); typedef void Adc_Drv_TriggerConflictErrorNotificationType(void); typedef struct { uint8 ChnIdx; ADC_Drv_PositiveChannelType Channel; boolean InterruptEnable; } Adc_Drv_ChannelConfigType; typedef struct { Adc_Drv_AvgSelectType AvgSel; Adc_Drv_ResolutionType Resolution; Adc_Drv_TriggerType TriggerMode; Adc_Drv_VRefSelType VoltageRef; ADC_Drv_ConversionType ConvMode; ADC_Drv_CompareModeType CompareMode; boolean CompareGreaterThanEnable; boolean CompareRangeFuncEnable; uint16 CompVal1; uint16 CompVal2; uint16 UsrCalibrationEnable; uint16 UsrGain; uint16 UsrOffset; const Adc_Drv_ChannelConfigType *ChannelConfigList; const uint8 ConfiguredChannelCount; Adc_Drv_CompleteNotificationType *ConversionCompleteNotification; Adc_Drv_TriggerConflictErrorNotificationType *TriggerErrorNotification; const Adc_Drv_TransferModeType TransferMode; const uint8 DmaChannel; const uint8 WithoutInterrupt; } Adc_Drv_ConfigType; typedef struct { boolean InitFlag; Adc_Drv_CompleteNotificationType *ConversionCompleteNotification; Adc_Drv_TriggerConflictErrorNotificationType *TriggerErrorNotification; } Adc_Drv_StateStructType; typedef struct { const Adc_Drv_AvgSelectType AverageSelect; uint16 StableTime; uint16 SampleTime; ADC_Drv_TdgTriggerModeType TdgTriggerMode; } Adc_Drv_GroupConfigType; # 30 "../../../mcal/adc_ZX_K14xM/Inc/Adc_Types.h" 2 # 1 "../../../mcal/adc_ZX_K14xM/Inc/Tdg_Adc_Drv_Types.h" 1 # 30 "../../../mcal/adc_ZX_K14xM/Inc/Tdg_Adc_Drv_Types.h" # 1 "../Generated/inc\\Tdg_Adc_Drv_Cfg.h" 1 # 28 "../Generated/inc\\Tdg_Adc_Drv_Cfg.h" # 1 "../Generated/inc/Tdg_Adc_Drv_PBcfg.h" 1 # 29 "../Generated/inc\\Tdg_Adc_Drv_Cfg.h" 2 # 31 "../../../mcal/adc_ZX_K14xM/Inc/Tdg_Adc_Drv_Types.h" 2 # 84 "../../../mcal/adc_ZX_K14xM/Inc/Tdg_Adc_Drv_Types.h" typedef enum { TDG_ADC_DRV_COUNT_SINGLE = 0U, TDG_ADC_DRV_COUNT_INFINITY } Tdg_Adc_Drv_CountModeType; typedef enum { TDG_ADC_DRV_TRIG_EXTERNAL = 0U, TDG_ADC_DRV_TRIG_SW } Tdg_Adc_Drv_TriggerSourceType; typedef enum { TDG_ADC_DRV_CLEAR_MODULATOR = 0U, TDG_ADC_DRV_CLEAR_DELAY } Tdg_Adc_Drv_CountClearModeType; typedef enum { TDG_ADC_DRV_CLK_DIVIDE_1 = 0U, TDG_ADC_DRV_CLK_DIVIDE_2, TDG_ADC_DRV_CLK_DIVIDE_4, TDG_ADC_DRV_CLK_DIVIDE_8, TDG_ADC_DRV_CLK_DIVIDE_16, TDG_ADC_DRV_CLK_DIVIDE_32, TDG_ADC_DRV_CLK_DIVIDE_64, TDG_ADC_DRV_CLK_DIVIDE_128 } Tdg_Adc_Drv_ClockDivideType; typedef enum { TDG_ADC_DRV_UPDATE_IMMEDIATELY = 0U, TDG_ADC_DRV_UPDATE_MODULATOR, TDG_ADC_DRV_UPDATE_DELAY } Tdg_Adc_Drv_UpdateModeType; typedef enum { TDG_ADC_DRV_CHANNEL_0 = 0U, TDG_ADC_DRV_CHANNEL_1, TDG_ADC_DRV_CHANNEL_2, TDG_ADC_DRV_CHANNEL_3, TDG_ADC_DRV_CHANNEL_4, TDG_ADC_DRV_CHANNEL_5 } Tdg_Adc_Drv_ChannelIdType; typedef enum { TDG_ADC_DRV_DELAY_OUTPUT_0 = 0U, TDG_ADC_DRV_DELAY_OUTPUT_1, TDG_ADC_DRV_DELAY_OUTPUT_2, TDG_ADC_DRV_DELAY_OUTPUT_3, TDG_ADC_DRV_DELAY_OUTPUT_4, TDG_ADC_DRV_DELAY_OUTPUT_5, TDG_ADC_DRV_DELAY_OUTPUT_6, TDG_ADC_DRV_DELAY_OUTPUT_7 } Tdg_Adc_Drv_DelayOutputIdType; typedef enum { TDG_ADC_DRV_INT_CH0 = 0U, TDG_ADC_DRV_INT_CH1, TDG_ADC_DRV_INT_CH2, TDG_ADC_DRV_INT_CH3, TDG_ADC_DRV_INT_CH4, TDG_ADC_DRV_INT_CH5, TDG_ADC_DRV_INT_RESERVERD_0, TDG_ADC_DRV_INT_RESERVERD_1, TDG_ADC_DRV_INT_ERR } Tdg_Adc_Drv_InterruptType; typedef void Tdg_Adc_Drv_CompDelayOutputNotifType(uint32 ChanIdx); typedef void Tdg_Adc_Drv_ErrorNotifType(void); typedef struct { Tdg_Adc_Drv_UpdateModeType UpdateMode; Tdg_Adc_Drv_ClockDivideType PrescalerDiv; Tdg_Adc_Drv_TriggerSourceType TriggerSource; Tdg_Adc_Drv_CountClearModeType ClearMode; Tdg_Adc_Drv_CountModeType CountMode; uint16 ModValue; Tdg_Adc_Drv_CompDelayOutputNotifType *CompDelayNotifPtr; Tdg_Adc_Drv_ErrorNotifType *ErrorNotifPtr; } Tdg_Adc_Drv_ConfigType; typedef struct { Tdg_Adc_Drv_DelayOutputIdType DelayOutputId; uint16 Offset; boolean Enable; } Tdg_Adc_Drv_DelayOutputConfigType; typedef struct { Tdg_Adc_Drv_ChannelIdType ChannelId; uint16 IntDelayVal; uint8 DelayOutputNum; const Tdg_Adc_Drv_DelayOutputConfigType *DelayOutputConfig; } Tdg_Adc_Drv_ChannelConfigType; typedef struct { boolean InitFlag; Tdg_Adc_Drv_CompDelayOutputNotifType *CompDelayNotifPtr; Tdg_Adc_Drv_ErrorNotifType *ErrorNotifPtr; } Tdg_Adc_Drv_StateStructType; typedef struct { const boolean IsSwTrig; const uint8 NumOfChannel; const Tdg_Adc_Drv_ChannelConfigType ( *TdgChannelConfigArray)[]; } Tdg_Adc_Drv_GroupConfigType; # 31 "../../../mcal/adc_ZX_K14xM/Inc/Adc_Types.h" 2 # 111 "../../../mcal/adc_ZX_K14xM/Inc/Adc_Types.h" typedef enum { ADC_STATE_UNINIT = 0U, ADC_STATE_BUSY, ADC_STATE_IDLE } Adc_GlobalStateType; typedef enum { ADC_NOT_YET_CONVERTED = 0U, ADC_ALREADY_CONVERTED } Adc_GroupConversionStateType; typedef enum { ADC_ACCESS_MODE_SINGLE = 0U, ADC_ACCESS_MODE_STREAMING } Adc_GroupAccessModeType; typedef enum { ADC_CONV_MODE_ONESHOT = 0U, ADC_CONV_MODE_CONTINUOUS } Adc_GroupConvModeType; # 169 "../../../mcal/adc_ZX_K14xM/Inc/Adc_Types.h" typedef enum { ADC_GROUP_REPL_ABORT_RESTART = 0U, ADC_GROUP_REPL_SUSPEND_RESUME # 187 "../../../mcal/adc_ZX_K14xM/Inc/Adc_Types.h" } Adc_GroupReplacementType; typedef enum { ADC_STREAM_BUFFER_LINEAR = 0U, ADC_STREAM_BUFFER_CIRCULAR } Adc_StreamBufferModeType; # 231 "../../../mcal/adc_ZX_K14xM/Inc/Adc_Types.h" typedef enum { ADC_IDLE = 0U, ADC_BUSY, ADC_COMPLETED, ADC_STREAM_COMPLETED } Adc_StatusType; typedef enum { ADC_NOTIFICATION_DISABLED = 0U, ADC_NOTIFICATION_ENABLED } Adc_NotificationType; # 261 "../../../mcal/adc_ZX_K14xM/Inc/Adc_Types.h" typedef enum { ADC_HW_TRIG_RISING_EDGE = 0U, ADC_HW_TRIG_FALLING_EDGE, ADC_HW_TRIG_BOTH_EDGES } Adc_HwTriggerSignalType; typedef enum { ADC_TRIGG_SRC_SW = 0U, ADC_TRIGG_SRC_HW } Adc_TriggerSourceType; typedef enum { ADC_HWTRIGGER_DISABLED = 0U, ADC_HWTRIGGER_ENABLED } Adc_HwTriggeringType; # 318 "../../../mcal/adc_ZX_K14xM/Inc/Adc_Types.h" typedef void (*Adc_NotifyType)(void); typedef uint16 Adc_ValueGroupType; typedef uint8 Adc_ResolutionType; # 344 "../../../mcal/adc_ZX_K14xM/Inc/Adc_Types.h" typedef uint16 Adc_ChannelType; typedef uint16 Adc_GroupType; typedef Adc_ChannelType Adc_GroupDefType; typedef uint8 Adc_PrescaleType; typedef uint8 Adc_SamplingTimeType; typedef uint16 Adc_StreamNumSampleType; typedef uint16 Adc_HwTriggerTimerType; typedef uint16 Adc_ConversionTimeType; typedef uint16 Adc_QueueIndexType; typedef uint8 Adc_HwUnitType; typedef uint8 Adc_ChannelIndexType; # 442 "../../../mcal/adc_ZX_K14xM/Inc/Adc_Types.h" typedef struct { volatile Adc_StatusType ConvStatus; volatile Adc_GroupConversionStateType AlreadyConverted; Adc_HwTriggeringType HwTriggering; Adc_NotificationType Notification; volatile Adc_StreamNumSampleType ResultIndex; } Adc_GroupStatusType; typedef struct { volatile Adc_QueueIndexType SwNormalQueueIndex; volatile Adc_GroupType SwNormalQueue[(5U)]; volatile Adc_GroupType OngoingHwGroup; } Adc_UnitStatusType; typedef struct { const Adc_GroupType GroupNum; const Adc_ChannelType ChannelNum; const uint8 TransferMode; const uint8 DmaChannel; Adc_Drv_ResolutionType Resolution; const boolean WithoutInterrupt; const Adc_Drv_ConfigType *AdcDrvConfigPtr; const Tdg_Adc_Drv_ConfigType *TdgDrvConfigPtr; } Adc_HWUnitConfigType; typedef struct { const Adc_HWUnitConfigType *HWUnitConfigPtr; } Adc_HWUnitConfigListType; typedef struct { const Adc_GroupType GroupId; const Adc_HwUnitType HwUnitId; const Adc_GroupAccessModeType AccessMode; const Adc_GroupConvModeType ConvMode; const Adc_GroupReplacementType ReplacementMode; const Adc_TriggerSourceType TriggerSource; const Adc_TriggerSourceType HwTriggerSource; const Adc_HwTriggerSignalType TriggerEdge; const Adc_NotifyType Notification; Adc_ValueGroupType **ResultsBufferPtr; const Adc_StreamBufferModeType BufferMode; const Adc_StreamNumSampleType NumSamples; const Adc_ChannelIndexType AssignedChannelCount; const ADC_Drv_PositiveChannelType *AssignedChannelList; const Adc_Drv_GroupConfigType *AdcGroupConfigPtr; const Tdg_Adc_Drv_GroupConfigType *TdgGroupConfigPtr; } Adc_GroupConfigType; # 548 "../../../mcal/adc_ZX_K14xM/Inc/Adc_Types.h" typedef struct { const Adc_HWUnitConfigListType *HWUnitConfigList; const Adc_GroupConfigType *GroupConfigList; Adc_GroupType GroupCount; uint32 CoreId; } Adc_ConfigType; # 29 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" 2 # 268 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Adc_MemMap.h" 1 # 1436 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Adc_MemMap.h" #pragma clang section bss = ".mcal_bss" # 269 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" 2 extern Adc_GroupStatusType Adc_GroupStatus[(5U)]; extern Adc_UnitStatusType Adc_UnitStatus[(2U)]; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Adc_MemMap.h" 1 # 1452 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Adc_MemMap.h" #pragma clang section bss = "" # 274 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Adc_MemMap.h" 1 # 848 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Adc_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 278 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" 2 extern const Adc_ConfigType *const Adc_PreDefinedConfigPtr[(1U)]; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Adc_MemMap.h" 1 # 864 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Adc_MemMap.h" #pragma clang section rodata = "" # 281 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" 2 # 297 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Adc_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Adc_MemMap.h" #pragma clang section text = ".mcal_code" # 298 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" 2 extern void Adc0Grp0NotifyFunc(void); extern void Adc1Grp0NotifyFunc(void); extern void Adc1Grp1NotifyFunc(void); # 315 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" void Adc_Init(const Adc_ConfigType *ConfigPtr); # 337 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" Std_ReturnType Adc_SetupResultBuffer(Adc_GroupType Group, Adc_ValueGroupType *const DataBufferPtr); # 348 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" void Adc_DeInit(void); # 362 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" void Adc_StartGroupConversion(Adc_GroupType Group); # 374 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" void Adc_StopGroupConversion(Adc_GroupType Group); # 397 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" Std_ReturnType Adc_ReadGroup(Adc_GroupType Group, Adc_ValueGroupType *DataBufferPtr); # 411 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" void Adc_EnableHardwareTrigger(Adc_GroupType Group); # 423 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" void Adc_DisableHardwareTrigger(Adc_GroupType Group); # 437 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" void Adc_EnableGroupNotification(Adc_GroupType Group); # 449 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" void Adc_DisableGroupNotification(Adc_GroupType Group); # 462 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" Adc_StatusType Adc_GetGroupStatus(Adc_GroupType Group); # 483 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" Adc_StreamNumSampleType Adc_GetStreamLastPointer(Adc_GroupType Group, Adc_ValueGroupType **PtrToSamplePtr); # 497 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" void Adc_GetVersionInfo(Std_VersionInfoType *versioninfo); # 528 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" Std_ReturnType Adc_SelfTest(Adc_HwUnitType Unit); # 608 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Adc_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Adc_MemMap.h" #pragma clang section text = "" # 609 "../../../mcal/adc_ZX_K14xM/Inc\\Adc.h" 2 # 20 "../Src/main.h" 2 # 1 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" 1 # 29 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" # 1 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Types.h" 1 # 28 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Types.h" # 1 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drvw_Types.h" 1 # 28 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drvw_Types.h" # 1 "../Generated/inc\\Spi_Drvw_Cfg.h" 1 # 28 "../Generated/inc\\Spi_Drvw_Cfg.h" # 1 "../Generated/inc/Spi_Drvw_PBcfg.h" 1 # 29 "../Generated/inc\\Spi_Drvw_Cfg.h" 2 # 29 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drvw_Types.h" 2 # 1 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drv_Types.h" 1 # 30 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drv_Types.h" # 1 "../Generated/inc\\Spi_Drv_Cfg.h" 1 # 28 "../Generated/inc\\Spi_Drv_Cfg.h" # 1 "../Generated/inc/Spi_Drv_PBcfg.h" 1 # 29 "../Generated/inc\\Spi_Drv_Cfg.h" 2 # 31 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drv_Types.h" 2 # 84 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drv_Types.h" typedef enum { SPI_DRV_EVENT_SUCCESS = 0U, SPI_DRV_EVENT_FAULT } Spi_Drv_EventType; typedef void (*Spi_Drv_CallbackType)(uint8 Instance, Spi_Drv_EventType Event); typedef enum { SPI_DRV_POLLING = 0U, SPI_DRV_INTERRUPT } Spi_Drv_AsyncModeType; typedef enum { SPI_DRV_UNINIT = 0U, SPI_DRV_IDLE, SPI_DRV_BUSY, SPI_DRV_FAULT } Spi_Drv_StatusType; typedef struct { uint8 FrameSize; boolean Lsb; uint32 DefaultData; } Spi_Drv_DeviceParamType; typedef struct { uint8 Instance; uint8 CsIdentifier; uint8 ClockPhase; uint8 ClockPolarity; uint32 ClockDivider; Spi_Drv_DeviceParamType *DeviceParamPtr; } Spi_Drv_ExternalDeviceType; typedef struct { uint8 Instance; boolean DmaUsed; uint8 TxDmaChannel; uint8 RxDmaChannel; Spi_Drv_AsyncModeType AsyncMode; } Spi_Drv_PhyUnitConfigType; typedef struct { Spi_Drv_AsyncModeType AsyncMode; Spi_Drv_StatusType Status; uint8 *RxBuffer; uint8 *TxBuffer; Spi_Drv_CallbackType Callback; uint16 RxIndex; uint16 TxIndex; uint16 ExpectReadNum; uint16 ExpectWriteNum; boolean ContinueTransferFlag; boolean FirstTransferFlag; const Spi_Drv_PhyUnitConfigType *PhyUnitConfig; const Spi_Drv_ExternalDeviceType *ExternalDevice; uint8 FrameSize; boolean TxLsb; boolean NextTransferConfigAvailable; uint8 CurrentTxFifoSlot; boolean TxDoneFlag; } Spi_Drv_TransferConfigType; # 30 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drvw_Types.h" 2 # 88 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Drvw_Types.h" typedef enum { IB = 0, EB } Spi_Drvw_BufferType; typedef enum { SPI_DRVW_POLLING_MODE = 0, SPI_DRVW_INTERRUPT_MODE } Spi_Drvw_AsyncModeType; typedef uint8 Spi_Drvw_HWUnitType; typedef uint16 Spi_Drvw_NumberOfDataType; typedef uint8 Spi_Drvw_DataBufferType; typedef struct { uint8 Instance; uint32 IsSync; uint32 SpiCoreUse; const Spi_Drv_PhyUnitConfigType *PhyUnitConfigPtr; } Spi_Drvw_HWUnitConfigType; typedef struct { const Spi_Drvw_HWUnitConfigType *DrvwHWUnitConfig; } Spi_Drvw_HWUnitConfigListType; typedef struct { uint8 Instance; uint32 SpiCoreUse; const Spi_Drv_ExternalDeviceType *DrvExternalDeviceConfigPtr; } Spi_Drvw_ExternalDeviceConfigType; typedef struct { const Spi_Drvw_ExternalDeviceConfigType *DrvwExternalDeviceConfigPtr; } Spi_Drvw_ExternalDeviceListType; typedef struct { Spi_Drvw_DataBufferType *TxBuffer; Spi_Drvw_DataBufferType *RxBuffer; } Spi_Drvw_BufferDescriptorType; typedef struct { uint8 Flags; Spi_Drvw_NumberOfDataType Length; } Spi_Drvw_ChannelStateType; typedef struct { Spi_Drvw_BufferType BufferType; uint8 FrameSize; boolean Lsb; uint32 DefaultTransmitValue; Spi_Drvw_NumberOfDataType Length; Spi_Drvw_BufferDescriptorType *BufferDescriptor; uint32 SpiCoreUse; Spi_Drvw_ChannelStateType *ChannelState; } Spi_Drvw_ChannelConfigType; # 29 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Types.h" 2 # 1 "../Generated/inc\\Spi_Cfg.h" 1 # 28 "../Generated/inc\\Spi_Cfg.h" # 1 "../Generated/inc/Spi_PBcfg.h" 1 # 66 "../Generated/inc/Spi_PBcfg.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" #pragma clang section text = ".mcal_code" # 67 "../Generated/inc/Spi_PBcfg.h" 2 extern void Ex_Spi_StpJobStartNotification(void); extern void Ex_Spi_SbcJobStartNotification(void); extern void Ex_Spi_BuckJobStartNotification(void); extern void Ex_Spi_BoostJobStartNotification(void); extern void Ex_Spi_StpJobEndNotification(void); extern void Ex_Spi_SbcJobEndNotification(void); extern void Ex_Spi_BuckJobEndNotification(void); extern void Ex_Spi_BoostJobEndNotification(void); extern void Ex_Spi_StpSequenceEndNotification(void); extern void Ex_Spi_SbcSequenceEndNotification(void); extern void Ex_Spi_BuckSequenceEndNotification(void); extern void Ex_Spi_BoostSequenceEndNotification(void); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" #pragma clang section text = "" # 132 "../Generated/inc/Spi_PBcfg.h" 2 # 29 "../Generated/inc\\Spi_Cfg.h" 2 # 30 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Types.h" 2 # 99 "../../../mcal/Spi_ZX_K14xM/Inc/Spi_Types.h" typedef enum { SPI_UNINIT = 0, SPI_IDLE, SPI_BUSY } Spi_StatusType; typedef enum { SPI_JOB_OK = 0, SPI_JOB_PENDING, SPI_JOB_FAILED, SPI_JOB_QUEUED } Spi_JobResultType; typedef enum { SPI_SEQ_OK = 0, SPI_SEQ_PENDING, SPI_SEQ_FAILED, SPI_SEQ_CANCELLED } Spi_SeqResultType; typedef enum { SPI_POLLING_MODE = 0, SPI_INTERRUPT_MODE } Spi_AsyncModeType; typedef Spi_Drvw_DataBufferType Spi_DataBufferType; typedef Spi_Drvw_NumberOfDataType Spi_NumberOfDataType; typedef uint8 Spi_ChannelType; typedef uint16 Spi_JobType; typedef uint8 Spi_SequenceType; typedef Spi_Drvw_HWUnitType Spi_HWUnitType; typedef uint8 Spi_ExternalDeviceType; typedef void(Spi_NotifyType)(void); typedef struct { Spi_JobType JobNum; uint32 SpiCoreUse; const Spi_JobType *JobIndexList; Spi_NotifyType(*EndNotification); uint8 Interruptible; } Spi_SequenceConfigType; typedef struct { const Spi_SequenceConfigType *SeqConfig; } Spi_SequenceConfigListType; typedef struct { Spi_SeqResultType Result; const Spi_SequenceConfigType *Sequence; const Spi_JobType *CurrentJobIndexPointer; Spi_JobType RemainingJobs; } Spi_SequenceStateType; typedef struct { Spi_JobResultType Result; Spi_SequenceStateType *AsyncSequenceState; Spi_JobType AsyncNextJob; } Spi_JobStateType; typedef struct { Spi_ChannelType ChannelNum; const Spi_ChannelType *ChannelIndexList; Spi_NotifyType(*EndNotification); Spi_NotifyType(*StartNotification); sint8 Priority; uint32 SpiCoreUse; Spi_JobStateType *JobState; Spi_HWUnitType HWUnit; Spi_ExternalDeviceType ExternalDevice; const Spi_Drvw_ExternalDeviceListType *ExternalDeviceConfig; } Spi_JobConfigType; typedef struct { const Spi_JobConfigType *JobConfig; } Spi_JobConfigListType; typedef struct { Spi_JobType ScheduledJobsListHead[(4U)]; Spi_JobType ScheduledJobsListTail[(4U)]; sint8 MaxScheduledPriority; Spi_StatusType Status; Spi_ChannelType Channel; Spi_JobType Job; } Spi_HWUnitQueue; typedef struct { const Spi_Drvw_ChannelConfigType *ChannelConfig; } Spi_ChannelConfigListType; typedef struct { uint16 MaxExternalDevice; Spi_ChannelType SpiMaxChannel; Spi_JobType SpiMaxJob; Spi_SequenceType SpiMaxSequence; uint32 SpiCoreUse; const Spi_ChannelConfigListType *ChannelConfigList; const Spi_JobConfigListType *JobConfigList; const Spi_SequenceConfigListType *SequenceConfigList; const Spi_Drvw_ExternalDeviceListType *ExternalDeviceConfigList; const Spi_Drvw_HWUnitConfigListType *HWUnitConfigList; } Spi_ConfigType; # 30 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" 2 # 296 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" 1 # 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" #pragma clang section rodata = ".mcal_config_data" # 297 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" 2 extern const Spi_ConfigType Spi_Config; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" 1 # 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" #pragma clang section rodata = "" # 304 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" 1 # 1436 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" #pragma clang section bss = ".mcal_bss" # 308 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" 2 extern Spi_JobStateType Spi_JobStateArray[(4U)]; extern Spi_Drvw_ChannelStateType Spi_ChannelStateArray[(4U)]; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" 1 # 1452 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" #pragma clang section bss = "" # 315 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" #pragma clang section text = ".mcal_code" # 324 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" 2 # 335 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" void Spi_Init(const Spi_ConfigType *ConfigPtr); # 348 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" Std_ReturnType Spi_DeInit(void); # 368 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" Std_ReturnType Spi_WriteIB(Spi_ChannelType Channel, const Spi_DataBufferType *DataBufferPtr); # 385 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" Std_ReturnType Spi_AsyncTransmit(Spi_SequenceType Sequence); # 408 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" Std_ReturnType Spi_ReadIB(Spi_ChannelType Channel, Spi_DataBufferType *DataBufferPtr); # 431 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" Std_ReturnType Spi_SetupEB(Spi_ChannelType Channel, Spi_DataBufferType *SrcDataBufferPtr, Spi_DataBufferType *DesDataBufferPtr, Spi_NumberOfDataType Length); # 448 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" Spi_StatusType Spi_GetStatus(void); # 464 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" Spi_JobResultType Spi_GetJobResult(Spi_JobType Job); # 480 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" Spi_SeqResultType Spi_GetSequenceResult(Spi_SequenceType Sequence); # 494 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" void Spi_GetVersionInfo(Std_VersionInfoType *versioninfo); # 511 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" Std_ReturnType Spi_SyncTransmit(Spi_SequenceType Sequence); # 530 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" Spi_StatusType Spi_GetHWUnitStatus(Spi_HWUnitType HWUnit); # 547 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" void Spi_Cancel(Spi_SequenceType Sequence); # 564 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" Std_ReturnType Spi_SetAsyncMode(Spi_AsyncModeType Mode); # 579 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" Std_ReturnType Spi_SetHWUnitAsyncMode(Spi_HWUnitType HWUnit, Spi_AsyncModeType Mode); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Spi_MemMap.h" #pragma clang section text = "" # 584 "../../../mcal/Spi_ZX_K14xM/Inc\\SPI.h" 2 # 21 "../Src/main.h" 2 # 1 "../Src/spidev.h" 1 void InitSPI_Dev(void); # 22 "../Src/main.h" 2 void Startup_Init(void); void Watchdog_Disable(void); # 2 "../Src/can_func.c" 2 # 1 "../Src/can_func.h" 1 # 1 "d:\\Keil\\ARM\\ARMCLANG\\Bin\\..\\include\\stdint.h" 1 3 # 56 "d:\\Keil\\ARM\\ARMCLANG\\Bin\\..\\include\\stdint.h" 3 typedef signed char int8_t; typedef signed short int int16_t; typedef signed int int32_t; typedef signed long long int int64_t; typedef unsigned char uint8_t; typedef unsigned short int uint16_t; typedef unsigned int uint32_t; typedef unsigned long long int uint64_t; typedef signed char int_least8_t; typedef signed short int int_least16_t; typedef signed int int_least32_t; typedef signed long long int int_least64_t; typedef unsigned char uint_least8_t; typedef unsigned short int uint_least16_t; typedef unsigned int uint_least32_t; typedef unsigned long long int uint_least64_t; typedef signed int int_fast8_t; typedef signed int int_fast16_t; typedef signed int int_fast32_t; typedef signed long long int int_fast64_t; typedef unsigned int uint_fast8_t; typedef unsigned int uint_fast16_t; typedef unsigned int uint_fast32_t; typedef unsigned long long int uint_fast64_t; typedef signed int intptr_t; typedef unsigned int uintptr_t; typedef signed long long intmax_t; typedef unsigned long long uintmax_t; # 5 "../Src/can_func.h" 2 # 1 "../../../Package/OS/Task\\pt_thread/pt_header.h" 1 # 1 "../../../Package/OS/Task\\pt_thread/pt_timer.h" 1 # 1 "../../../Package/OS/Task\\pt_thread/pt.h" 1 # 1 "../../../Package/OS/Task\\pt_thread/lc.h" 1 # 1 "../../../Package/OS/Task\\pt_thread/lc-switch.h" 1 typedef unsigned short lc_t; # 9 "../../../Package/OS/Task\\pt_thread/lc.h" 2 # 6 "../../../Package/OS/Task\\pt_thread/pt.h" 2 struct pt { lc_t lc; }; # 4 "../../../Package/OS/Task\\pt_thread/pt_timer.h" 2 struct timer { int start; int interval; }; # 5 "../../../Package/OS/Task\\pt_thread/pt_header.h" 2 # 1 "../../../Package/OS/Task\\pt_thread/pt-sem.h" 1 # 74 "../../../Package/OS/Task\\pt_thread/pt-sem.h" struct pt_sem { unsigned int count; }; # 6 "../../../Package/OS/Task\\pt_thread/pt_header.h" 2 # 6 "../Src/can_func.h" 2 int8_t TaskCAN(struct pt *pt1 ); # 4 "../Src/can_func.c" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1 # 1128 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" #pragma clang section data = ".mcal_data" # 7 "../Src/can_func.c" 2 static boolean Ex_Can_TxFlag = 0U; static boolean Ex_Can_RxFlagCase2 = 0U; static boolean Ex_Can_RxFlagCase3 = 0U; static boolean Ex_Can_FlagCase4 = 0U; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1 # 1144 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" #pragma clang section data = "" # 16 "../Src/can_func.c" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1 # 1156 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" #pragma clang section data = ".mcal_data" # 19 "../Src/can_func.c" 2 static uint8 Ex_Can_PeriodTime = 0; # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1 # 1172 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" #pragma clang section data = "" # 24 "../Src/can_func.c" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" #pragma clang section text = ".mcal_code" # 27 "../Src/can_func.c" 2 static void Ex_Can_CheckDmaRxResult(const Can_HwType *HwObj, const PduInfoType *PduInfoPtr); static void Ex_Can_CheckPollingRxResult(const Can_HwType *HwObj, const PduInfoType *PduInfoPtr); # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1 # 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" #pragma clang section text = "" # 40 "../Src/can_func.c" 2 # 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1 # 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" #pragma clang section text = ".mcal_code" # 43 "../Src/can_func.c" 2 extern void CanIf_ControllerBusOff(uint8 ControllerId) { (void)ControllerId; } void CanIf_ControllerModeIndication(uint8 ControllerId, Can_ControllerStateType ControllerMode) { (void)ControllerId; (void)ControllerMode; } void CanIf_TxConfirmation(PduIdType CanTxPduId) { Ex_Can_TxFlag = 1U; (void)CanTxPduId; (void)Ex_Can_TxFlag; } void CanIf_RxIndication(const Can_HwType *HwObj, const PduInfoType *PduInfoPtr) { Ex_Can_CheckDmaRxResult(HwObj, PduInfoPtr); Ex_Can_CheckPollingRxResult(HwObj, PduInfoPtr); } void Ex_Can_StimCallback(void) { static uint32 interruptCount = 0U; if (++interruptCount == ((0.001F) * 1000)) { interruptCount = 0U; Ex_Can_PeriodTime = 1; } } static void Ex_Can_CheckDmaRxResult(const Can_HwType *HwObj, const PduInfoType *PduInfoPtr) { # 120 "../Src/can_func.c" if ( (0x7df == HwObj->CanId) ||(0x723U == HwObj->CanId) ||(0x724U == HwObj->CanId) ||(0x450U == HwObj->CanId) ||(0x453U == HwObj->CanId) ||(0x454U == HwObj->CanId) ||(0x387U == HwObj->CanId) ||(0x3efU == HwObj->CanId) ) { Ex_Can_RxFlagCase2 = 1U; } } static void Ex_Can_CheckPollingRxResult(const Can_HwType *HwObj, const PduInfoType *PduInfoPtr) { if ((0x80001314 == HwObj->CanId) && (((Can_HwHandleType)1U) == HwObj->Hoh) && (((uint8)0U) == HwObj->ControllerId)) { if ((8U == PduInfoPtr->SduLength) && (0x01 == PduInfoPtr->SduDataPtr[0U]) && (0x02 == PduInfoPtr->SduDataPtr[1U]) && (0x03 == PduInfoPtr->SduDataPtr[2U]) && (0x04 == PduInfoPtr->SduDataPtr[3U]) && (0x05 == PduInfoPtr->SduDataPtr[4U]) && (0x06 == PduInfoPtr->SduDataPtr[5U]) && (0x07 == PduInfoPtr->SduDataPtr[6U]) && (0x08 == PduInfoPtr->SduDataPtr[7U])) { Ex_Can_RxFlagCase3 = 1U; } } } int8_t Ex_Can_UseCase_01(struct pt *pt1 ) { static struct timer input_timer; static Can_PduType PduInfo; static uint8 SendData[] = {0x12, 0x34, 0x56, 0x78, 0x87, 0x65, 0x43, 0x21}; static uint8 Cnt = 0U; { int8_t PT_YIELD_FLAG = 1; switch((pt1)->lc) { case 0:; PduInfo.id = 0x733; PduInfo.sdu = SendData; PduInfo.swPduHandle = 0; PduInfo.length = 8; Can_SetControllerMode(((uint8)0U), CAN_CS_STARTED); Can_EnableControllerInterrupts(((uint8)0U)); Gpt_StopTimer((2U)); Gpt_StartTimer((2U), 3000); while (1U) { do { (pt1)->lc = 183; case 183:; if(!(Ex_Can_PeriodTime==1)) { return 0; } } while(0); { ++Cnt; if (Cnt == 0xffU) { break; } SendData[0]=(uint8)Cnt; Can_Write(((Can_HwHandleType)2U), &PduInfo); uint32 Index = 0; for (Index = 0U; Index < 10000U; ++Index) { } Can_MainFunction_Write(); Ex_Can_PeriodTime = 0; } } }; PT_YIELD_FLAG = 0; (void)(PT_YIELD_FLAG); (pt1)->lc = 0;; return 3; }; } int8_t Ex_Can_UseCase_02(struct pt *pt1 ) { { int8_t PT_YIELD_FLAG = 1; switch((pt1)->lc) { case 0:; Can_SetControllerMode(((uint8)0U), CAN_CS_STARTED); Can_EnableControllerInterrupts(((uint8)0U)); while (1U) { do { (pt1)->lc = 224; case 224:; if(!(Ex_Can_RxFlagCase2==1U)) { return 0; } } while(0); { break; } } }; PT_YIELD_FLAG = 0; (void)(PT_YIELD_FLAG); (pt1)->lc = 0;; return 3; }; } int ReadFunc(void) { Can_MainFunction_Read(); return Ex_Can_RxFlagCase3; } int8_t Ex_Can_UseCase_03(struct pt *pt1 ) { { int8_t PT_YIELD_FLAG = 1; switch((pt1)->lc) { case 0:; Can_SetControllerMode(((uint8)0U), CAN_CS_STARTED); Can_EnableControllerInterrupts(((uint8)0U)); Gpt_StartTimer((2U), 3000); while (1) { do { (pt1)->lc = 254; case 254:; if(!(ReadFunc()==1U)) { return 0; } } while(0); if (1U == Ex_Can_RxFlagCase3) { Ex_Can_RxFlagCase3 = 0U; break; } } }; PT_YIELD_FLAG = 0; (void)(PT_YIELD_FLAG); (pt1)->lc = 0;; return 3; }; } int8_t Ex_Can_UseCase_04(struct pt *pt1 ) { { int8_t PT_YIELD_FLAG = 1; switch((pt1)->lc) { case 0:; Can_SetControllerMode(((uint8)0U), CAN_CS_STARTED); Can_DisableControllerInterrupts(((uint8)0U)); Can_InjectError(((uint8)0U)); while (1) { do { (pt1)->lc = 275; case 275:; if(!(Ex_Can_FlagCase4==1U)) { return 0; } } while(0); { break; } } }; PT_YIELD_FLAG = 0; (void)(PT_YIELD_FLAG); (pt1)->lc = 0;; return 3; }; } int8_t Ex_Can_UseCase_05(struct pt *pt1 ) { static int i = 0; static Can_PduType PduInfo; static uint8 SendData[] = {0x87, 0x65, 0x43, 0x21, 0x12, 0x34, 0x56, 0x78}; PduInfo.id = 0x80001122; PduInfo.sdu = SendData; PduInfo.swPduHandle = 0; PduInfo.length = 8; Can_SetControllerMode(((uint8)0U), CAN_CS_STARTED); Can_EnableControllerInterrupts(((uint8)0U)); Gpt_StartTimer((2U), 3000); { int8_t PT_YIELD_FLAG = 1; switch((pt1)->lc) { case 0:; while (1) { do { (pt1)->lc = 313; case 313:; if(!(Ex_Can_PeriodTime==1)) { return 0; } } while(0); { Can_Write(((Can_HwHandleType)3U), &PduInfo); Ex_Can_PeriodTime = 0; i++; if(i==100) { i = 0; break; } } } }; PT_YIELD_FLAG = 0; (void)(PT_YIELD_FLAG); (pt1)->lc = 0;; return 3; }; } int8_t TaskCAN(struct pt *pt1 ) { static struct pt pt_Ex_Can_UseCase_01, pt_Ex_Can_UseCase_02,pt_Ex_Can_UseCase_03,pt_Ex_Can_UseCase_05,pt_Ex_Can_UseCase_04; { int8_t PT_YIELD_FLAG = 1; switch((pt1)->lc) { case 0:; Gpt_EnableNotification((2U)); while(1) { do { ((&pt_Ex_Can_UseCase_01))->lc = 0;; do { ((((pt1))))->lc = 337; case 337:; if(!(!((((Ex_Can_UseCase_01(&pt_Ex_Can_UseCase_01))) < 2)))) { return 0; } } while(0); } while(0); do { ((&pt_Ex_Can_UseCase_02))->lc = 0;; do { ((((pt1))))->lc = 338; case 338:; if(!(!((((Ex_Can_UseCase_01(&pt_Ex_Can_UseCase_02))) < 2)))) { return 0; } } while(0); } while(0); do { ((&pt_Ex_Can_UseCase_03))->lc = 0;; do { ((((pt1))))->lc = 339; case 339:; if(!(!((((Ex_Can_UseCase_01(&pt_Ex_Can_UseCase_03))) < 2)))) { return 0; } } while(0); } while(0); do { ((&pt_Ex_Can_UseCase_04))->lc = 0;; do { ((((pt1))))->lc = 340; case 340:; if(!(!((((Ex_Can_UseCase_01(&pt_Ex_Can_UseCase_04))) < 2)))) { return 0; } } while(0); } while(0); } }; PT_YIELD_FLAG = 0; (void)(PT_YIELD_FLAG); (pt1)->lc = 0;; return 3; }; } void Can1_ErrNotifyFunc (void) { } void CAN1_FIFO_DMA_ErrNotifyFunc (void) { } boolean CAN_LPduRxFunc(uint8 Hrh, Can_IdType CanId, uint8 CanDataLegth, const uint8* CanSduPtr) { return 1U; } void CanIf_ControllerErrorStatePassive (uint8 ControllerId,uint16 RxErrorCounter,uint16 TxErrorCounter) { } void CanIf_ErrorNotification (uint8 ControllerId,Can_ErrorType CanErrorType) { } void Can1_HostMemNotify(void) { } void Can1_MemNotify(void) { } void Can1_CorrMemNotify(void) { } void BusFault_Handler(void) { if(0x00U == Can_ClearInjectError(0)) { Ex_Can_FlagCase4 = 1U; } }