# 1 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
# 1 "<built-in>" 1
# 1 "<built-in>" 3
# 387 "<built-in>" 3
# 1 "<command line>" 1
# 1 "<built-in>" 2
# 1 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2
# 26 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
# 1 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h" 1
# 29 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
# 1 "../../../mcal/Can_ZX_K14xM/Inc/Can_Drv_Types.h" 1
# 29 "../../../mcal/Can_ZX_K14xM/Inc/Can_Drv_Types.h"
# 1 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 1
# 30 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h"
# 1 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h" 1
# 86 "../../../mcal/Base_ZX_K14xM/Inc/Platform_Types.h"
typedef unsigned char boolean;




typedef unsigned char uint8;




typedef unsigned short uint16;




typedef unsigned int uint32;





typedef unsigned long long uint64;




typedef signed char sint8;




typedef signed short sint16;




typedef signed int sint32;





typedef signed long long sint64;




typedef unsigned long uint8_least;




typedef unsigned long uint16_least;





typedef unsigned long uint32_least;




typedef signed long sint8_least;




typedef signed long sint16_least;




typedef signed long sint32_least;




typedef float float32;





typedef double float64;




typedef void *VoidPtr;




typedef const void *ConstVoidPtr;
# 31 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2
# 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 1
# 31 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h"
# 1 "../../../mcal/Base_ZX_K14xM/Inc/Compiler_Cfg.h" 1
# 32 "../../../mcal/Base_ZX_K14xM/Inc/Compiler.h" 2
# 32 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h" 2
# 63 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h"
typedef unsigned char StatusType;
# 104 "../../../mcal/Base_ZX_K14xM/Inc\\Std_Types.h"
typedef uint8 Std_ReturnType;




typedef uint8 Std_TransformerClass;




typedef uint8 Std_TransformerForwardCode;





typedef uint8 Std_MessageTypeType;





typedef uint8 Std_MessageResultType;





typedef struct
{
    uint16 vendorID;
    uint16 moduleID;
    uint8 sw_major_version;
    uint8 sw_minor_version;
    uint8 sw_patch_version;
} Std_VersionInfoType;




typedef struct
{
    uint8 errorCode;
    Std_TransformerClass transformerClass;
} Std_TransformerError;





typedef struct
{
    Std_TransformerForwardCode errorCode;
    Std_TransformerClass transformerClass;
} Std_TransformerForward;







typedef Std_ReturnType (*Std_ExtractProtocolHeaderFieldsType)(const uint8 *buffer,
                                                              uint32 bufferLength,
                                                              Std_MessageTypeType *messageType,
                                                              Std_MessageResultType *messageResult);
# 30 "../../../mcal/Can_ZX_K14xM/Inc/Can_Drv_Types.h" 2
# 1 "../Generated/inc\\Can_Drv_Cfg.h" 1
# 30 "../Generated/inc\\Can_Drv_Cfg.h"
# 1 "../Generated/inc/Can_Drv_PBcfg.h" 1
# 31 "../Generated/inc\\Can_Drv_Cfg.h" 2
# 31 "../../../mcal/Can_ZX_K14xM/Inc/Can_Drv_Types.h" 2
# 1 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 1
# 29 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
# 1 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 1
# 30 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h"
# 1 "../Generated/inc\\McalLib_Cfg.h" 1
# 31 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h" 2
# 273 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h"
static inline uint32 McalLib_ReadControlReg(void)
{
    uint32 res;

    __asm("MRS %0,CONTROL" : "=r" (res));

    return res;
}
# 290 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h"
static inline uint32 McalLib_ReadIpsrReg(void)
{
    uint32 res;
    __asm("MRS %0,IPSR" : "=r" (res));
    return res;
}
# 305 "../../../mcal/McalLib_ZX_K14xM/Inc/McalLib_Compiler.h"
static inline uint32 McalLib_ReadPriMaskReg(void)
{
    uint32 res;
    __asm("MRS %0,PRIMASK" : "=r" (res));
    return res;
}
# 30 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2
# 184 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
typedef enum
{
    MCALLIB_COUNTER_SOFTWARE,

    MCALLIB_COUNTER_OS,




} McalLib_CounterType;




typedef struct
{
    uint32 CounterId;
    uint32 CounterFreq;
} McalLib_ConfigType;







# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1
# 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h"
#pragma clang section rodata = ".mcal_config_data"
# 211 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2

extern const McalLib_ConfigType *const McalLib_PreDefinedConfigPtr[(1U)];


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1
# 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h"
#pragma clang section rodata = ""
# 216 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2
# 230 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
extern void Sys_SystemReset(void);


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1
# 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h"
#pragma clang section text = ".mcal_code"
# 234 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2







void McalLib_Init(void);
# 254 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
Std_ReturnType McalLib_GetCounterValue(McalLib_CounterType Counter, uint32 *Value);
# 270 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
Std_ReturnType McalLib_GetElapsedValue(McalLib_CounterType Counter, uint32 *const CounterValue,
                                       uint32 *ElapsedValue);
# 282 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
uint32 McalLib_MicroSecToTicks(McalLib_CounterType Counter, uint32 MicroSecond);
# 296 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
void McalLib_SetCounterFreq(McalLib_CounterType Counter, uint32 Freq);
# 309 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
static inline void McalLib_Assert(const uint8 *File, uint32 Line)
{
    (void)File;
    (void)Line;

    for (;;)
    {
    }
}
# 327 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h"
void McalLib_SuspendAllInterrupts(void);







void McalLib_ResumeAllInterrupts(void);


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h" 1
# 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\McalLib_MemMap.h"
#pragma clang section text = ""
# 339 "../../../mcal/McalLib_ZX_K14xM/Inc\\McalLib.h" 2
# 32 "../../../mcal/Can_ZX_K14xM/Inc/Can_Drv_Types.h" 2
# 165 "../../../mcal/Can_ZX_K14xM/Inc/Can_Drv_Types.h"
typedef enum
{
    CAN_DRV_SUCCESS = 0U,
    CAN_DRV_ERROR,
    CAN_DRV_ENTER_BUSY,
    CAN_DRV_NO_TRANSMIT
} Can_Drv_ControllerStatus;




typedef enum
{
    CAN_DRV_ID_0 = 0U,
    CAN_DRV_ID_1 = 1U,
    CAN_DRV_ID_2 = 2U,
    CAN_DRV_ID_3 = 3U,
    CAN_DRV_ID_4 = 4U,
    CAN_DRV_ID_5 = 5U,
    CAN_DRV_ID_6 = 6U,
    CAN_DRV_ID_7 = 7U
} Can_Drv_IdType;




typedef enum
{
    CAN_DRV_CAN_FD_MB_REGION_0 = 0U,
    CAN_DRV_CAN_FD_MB_REGION_1,
    CAN_DRV_CAN_FD_MB_REGION_2,
    CAN_DRV_CAN_FD_MB_REGION_3
} Can_Drv_FdMbRegionType;




typedef enum
{
    CAN_DRV_RX_FIFO_ACCEPTANCE_FORMAT_A = 0U,
    CAN_DRV_RX_FIFO_ACCEPTANCE_FORMAT_B,

    CAN_DRV_RX_FIFO_ACCEPTANCE_FORMAT_C,
    CAN_DRV_RX_FIFO_ACCEPTANCE_FORMAT_D
} Can_Drv_RxAcceptanceType;




typedef enum
{
    CAN_DRV_RX_FIFO_FILTERS_8 = 0x0U,
    CAN_DRV_RX_FIFO_FILTERS_16 = 0x1U,
    CAN_DRV_RX_FIFO_FILTERS_24 = 0x2U,
    CAN_DRV_RX_FIFO_FILTERS_32 = 0x3U,
    CAN_DRV_RX_FIFO_FILTERS_40 = 0x4U,
    CAN_DRV_RX_FIFO_FILTERS_48 = 0x5U,
    CAN_DRV_RX_FIFO_FILTERS_56 = 0x6U,
    CAN_DRV_RX_FIFO_FILTERS_64 = 0x7U,
    CAN_DRV_RX_FIFO_FILTERS_72 = 0x8U,
    CAN_DRV_RX_FIFO_FILTERS_80 = 0x9U,
    CAN_DRV_RX_FIFO_FILTERS_88 = 0xAU,
    CAN_DRV_RX_FIFO_FILTERS_96 = 0xBU,
    CAN_DRV_RX_FIFO_FILTERS_104 = 0xCU,
    CAN_DRV_RX_FIFO_FILTERS_112 = 0xDU,
    CAN_DRV_RX_FIFO_FILTERS_120 = 0xEU,
    CAN_DRV_RX_FIFO_FILTERS_128 = 0xFU
} Can_Drv_RxFifoFilterNumType;




typedef enum
{
    CAN_DRV_RXFIFO_INTERRUPTS = 0U,
    CAN_DRV_RXFIFO_DMA,
    CAN_DRV_RXFIFO_POLLING
} Can_Drv_RxFifoTransferType;




typedef enum
{
    CAN_DRV_OBJECT_PL_8 = 0U,
    CAN_DRV_OBJECT_PL_16,
    CAN_DRV_OBJECT_PL_32,
    CAN_DRV_OBJECT_PL_64
} Can_Drv_FdPayloadLengthType;




typedef struct
{
    Can_Drv_FdPayloadLengthType Block0;
    Can_Drv_FdPayloadLengthType Block1;
    Can_Drv_FdPayloadLengthType Block2;
    Can_Drv_FdPayloadLengthType Block3;
} Can_Drv_FdPayloadBlockType;




typedef enum
{
    CAN_DRV_MODE_NORMAL = 0U,
    CAN_DRV_MODE_LISTEN_ONLY,
    CAN_DRV_MODE_LOOPBACK,
    CAN_DRV_MODE_FREEZE,
    CAN_DRV_MODE_DISABLE
} Can_Drv_ModeType;




typedef enum
{
    CAN_DRV_MSG_ID_STD = 0U,
    CAN_DRV_MSG_ID_EXT
} Can_Drv_MsgIdType;




typedef enum
{
    CAN_DRV_RX_MASK_GLOBAL = 0U,
    CAN_DRV_RX_MASK_INDIVIDUAL
} Can_Drv_RxMaskType;




typedef enum
{
    CAN_DRV_MB_RX_INACTIVE = 0x0,
    CAN_DRV_MB_RX_FULL = 0x2,
    CAN_DRV_MB_RX_EMPTY = 0x4,
    CAN_DRV_MB_RX_OVERRUN = 0x6,
    CAN_DRV_MB_RX_RANSWER = 0xA,

    CAN_DRV_MB_TX_INACTIVE = 0x08,
    CAN_DRV_MB_TX_ABORT = 0x09,
    CAN_DRV_MB_TX_DATA_REMOTE = 0x0C,

    CAN_DRV_MB_TX_TANSWER = 0x0E,

    CAN_DRV_NOT_USED = 0x0F
} Can_Drv_MbCodeType;




typedef enum
{
    CAN_DRV_INT_BUS_OFF = 0U,
    CAN_DRV_INT_ERR = 1U,
    CAN_DRV_INT_TXW = 2U,
    CAN_DRV_INT_RXW = 3U,
    CAN_DRV_INT_BUS_OFF_DONE = 4U,
    CAN_DRV_INT_ERR_FAST = 5U,


    CAN_DRV_INT_SELF_WAKEUP = 6U,
    CAN_DRV_INT_RXFIFO_FRAME = 7U,
    CAN_DRV_INT_RXFIFO_WARNING = 8U,
    CAN_DRV_INT_RXFIFO_OVERFLOW = 9U,
    CAN_DRV_INT_HOST_MEM_ERR = 10U,


    CAN_DRV_INT_MEM_ERR = 11U,


    CAN_DRV_INT_COR_MEM_ERR = 12U,

    CAN_DRV_INT_PN_WAKEUP_MATCH = 13U,
    CAN_DRV_INT_PN_WAKEUP_TIMEOUT = 14U,
    CAN_DRV_INT_MB_RECEIVE = 15U,
    CAN_DRV_MB_TRANSMIT = 16U,

    CAN_DRV_DMA_COMPLETE = 17U,
    CAN_DRV_DMA_ERROR = 18U,

    CAN_DRV_INT_ALL = 19U
} Can_Drv_IntType;




typedef enum
{
    CAN_DRV_STATE_NOT_SYNC = 0U,
    CAN_DRV_STATE_IDLE = 1U,
    CAN_DRV_STATE_TX = 2U,
    CAN_DRV_STATE_RX = 3U,

    CAN_DRV_STATE_DMA_ERROR = 4U,

    CAN_DRV_STATE_INVALID = 5U
} Can_Drv_ControllerStateType;




typedef struct
{
    uint32 PropSeg;
    uint32 PhaseSeg1;
    uint32 PhaseSeg2;
    uint32 PreDivider;
    uint32 RJumpWidth;
} Can_Drv_BitTimingType;




typedef struct
{
    boolean IsRemoteFrame;
    boolean IsExtendedFrame;
    uint32 Id;
} Can_Drv_IdFilterType;




typedef struct
{
    Can_Drv_MsgIdType IdType;
    uint8 DataLen;
    boolean RemoteFlag;
    boolean FdEn;
    uint8 FdPadding;



    boolean BrsEn;
} Can_Drv_MessageInfoType;




typedef struct
{
    uint32 Cs;
    uint32 MsgId;
    uint8 Data[64];
    uint8 DataLen;
    uint32 TimeStamp;
} Can_Drv_MsgBufType;




typedef struct
{
    Can_Drv_MsgBufType *MbMessagePtr;
    boolean IsPolling;
    boolean RemoteFlag;
    uint32 TimeStamp;
    Can_Drv_ControllerStateType State;

    volatile boolean IsDmaBusy;

} Can_Drv_MbHandleType;




typedef struct Can_Drv_State
{
    Can_Drv_MbHandleType Mb[(64)];
    Can_Drv_RxFifoTransferType TransferType;

    boolean RxFifoEn;
    boolean InterEn;
    uint32 MaxMbNumber;
    void (*IrqCallback)(uint8 Id, Can_Drv_IntType InterType, uint32 MbIdx,
                        const struct Can_Drv_State *State);
    void (*ErrCallback)(uint8 Id, Can_Drv_IntType InterType,
                        uint32 Data);

    uint8 RxFifoDMAChannel;

} Can_Drv_StateType;




typedef struct
{
    uint32 MbMaxNum;
    boolean RxFifoEn;
    Can_Drv_RxFifoFilterNumType RxFifoIdFilterNum;

    Can_Drv_RxFifoTransferType TransferType;

    Can_Drv_ModeType Mode;
    boolean BitRateSwitch;
    Can_Drv_BitTimingType BitTiming;

    boolean FdEn;
    Can_Drv_FdPayloadBlockType Payload;

    Can_Drv_BitTimingType
        BitTimingFdData;

    uint32 CtrlConfig;


    uint8 RxFifoDMAChannel;

    void (*IrqCallback)(uint8 Id, Can_Drv_IntType InterType, uint32 MbIdx,
                        const struct Can_Drv_State *State);
    void (*ErrCallback)(uint8 Id, Can_Drv_IntType InterType,
                        uint32 Data);
} Can_Drv_ConfigType;
# 30 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h" 2
# 73 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1
# 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h"
#pragma clang section rodata = ".mcal_config_data"
# 74 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h" 2

extern const Can_Drv_ConfigType Can_Drv_CtrlConfig[1U];


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1
# 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h"
#pragma clang section rodata = ""
# 79 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h" 2







# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1
# 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h"
#pragma clang section text = ".mcal_code"
# 87 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h" 2
# 101 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_AbortTransfer(uint8 Id, uint8 MbIdx);
# 118 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_ConfigRxMb(uint8 Id, uint8 MbIdx, Can_Drv_MsgIdType IdType,
                                            uint32 MsgId);
# 133 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_Init(uint8 Id, Can_Drv_StateType *CanStatePtr,
                                      const Can_Drv_ConfigType *CanConfigPtr);
# 147 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_Deinit(uint8 Id);
# 159 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_DisableMbInterrupts(uint8 Id);
# 174 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_Receive(uint8 Id, uint8 MbIdx, Can_Drv_MsgBufType *DataPtr,
                                         boolean IsPolling);
# 189 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_RxFIFO(uint8 Id, Can_Drv_MsgBufType *DataPtr);
# 200 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
void Can_Drv_ClearErrorStatus(uint8 Id, uint32 Mask);
# 212 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_EnableInterrupts(uint8 Id);
# 224 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_DisableInterrupts(uint8 Id);
# 237 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
uint32 Can_Drv_GetControllerErrorState(uint8 Id);
# 247 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
uint32 Can_Drv_GetControllerRxErrorCounter(uint8 Id);
# 257 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
uint32 Can_Drv_GetControllerTxErrorCounter(uint8 Id);
# 270 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_GetTransferStatus(uint8 Id, uint8 MbIdx);
# 282 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_ManualBusOffRecovery(uint8 Id);
# 293 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
void Can_Drv_WriteMainFunction(uint8 Id, uint8 MbIdx);
# 304 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
void Can_Drv_ReadMainFunction(const uint8 Id, uint8 MbIdx);
# 316 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_BusOffMainFunction(uint8 Id);
# 328 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_WakeupMainFunction(uint8 Id);
# 342 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_ConfigErrorInterrupt(uint8 Id, Can_Drv_IntType IntType, boolean Enable);
# 355 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_SetStdBitTiming(uint8 Id, const Can_Drv_BitTimingType *RatePtr);
# 368 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_SetFdArbBitTiming(uint8 Id, const Can_Drv_BitTimingType *RatePtr);
# 381 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_SetFdDataBitTiming(uint8 Id, const Can_Drv_BitTimingType *RatePtr);
# 394 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_SetRxMaskType(uint8 Id, Can_Drv_RxMaskType MaskType);
# 408 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
boolean Can_Drv_GetMbInterruptFlag(uint8 Id, uint8 MbIdx);
# 419 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
void Can_Drv_ClearMbIntStatus(uint8 Id, uint8 MbIdx);
# 431 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
boolean Can_Drv_CheckStartedMode(uint8 Id);
# 442 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
boolean Can_Drv_CheckStoppedMode(uint8 Id);
# 454 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_SetStartMode(uint8 Id);
# 466 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_SetStopMode(uint8 Id);
# 480 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_ConfigRxFifo(uint8 Id, Can_Drv_RxAcceptanceType Element,
                                              const Can_Drv_IdFilterType *FilterTablePtr);
# 499 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_SendData(uint8 Id, uint8 MbIdx,
                                          const Can_Drv_MessageInfoType *TxInfoPtr,
                                          boolean IsPolling, uint32 MsgId, const uint8 *MsgDataPtr);
# 516 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_SetRxIndividualMask(uint8 Id, Can_Drv_MsgIdType IdType,
                                                     uint32 MbIdx, uint32 Mask);
# 546 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_SetRxFifoGlobalMask(uint8 Id, uint32 Mask);
# 558 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_EnableArbitrationFiledCompare(uint8 Id);
# 593 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_SetRxFifoIndividualMask(uint8 Id, uint32 ElementIdx, uint32 Mask);
# 611 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_SetFdTdc(uint8 Id, boolean Enable, uint8 Offset);
# 624 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_SetTxArbitrationDelay(uint8 Id, uint8 Value);
# 636 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_EnableSelfWakeup(uint8 Id);
# 648 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_DisableSelfWakeup(uint8 Id);
# 660 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_InjectCorrectableAddress(uint8 Id);
# 672 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_InjectAddress(uint8 Id);
# 684 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
Can_Drv_ControllerStatus Can_Drv_ClearInjection(uint8 Id);
# 695 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
void Can_Drv_IntHandler(uint8 Id, uint32 StartMbIdx, uint32 EndMbIdx);
# 705 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
void Can_Drv_BusOffIntHandler(uint8 Id);
# 715 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
void Can_Drv_TxWarnIntHandler(uint8 Id);
# 725 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
void Can_Drv_RxWarnIntHandler(uint8 Id);
# 735 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
void Can_Drv_ErrorIntHandler(uint8 Id);
# 745 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
void Can_Drv_FdErrorIntHandler(uint8 Id);
# 755 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
void Can_Drv_WakeUpIntHandler(uint8 Id);
# 765 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h"
void Can_Drv_EccIntHandler(uint8 Id);


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1
# 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h"
#pragma clang section text = ""
# 769 "../../../mcal/Can_ZX_K14xM/Inc\\Can_Drv.h" 2
# 27 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2
# 1 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices\\Device_Regs.h" 1
# 17 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices\\Device_Regs.h"
# 1 "../Generated/inc\\Device_Cfg.h" 1
# 18 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices\\Device_Regs.h" 2

# 1 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices/Z20K148M.h" 1
# 43 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices/Z20K148M.h"
typedef enum IRQn
{

    NMI_IRQn = -14,
    HardFalut_IRQn = -13,
    MemManageFault_IRQn = -12,
    BusFault_IRQn = -11,
    UsageFault_IRQn = -10,
    SVCall_IRQn = -5,
    DebugMonitor_IRQn = -4,
    PendSV_IRQn = -2,
    SysTick_IRQn = -1,


    DMA_Ch0_IRQn = 0,
    DMA_Ch1_IRQn = 1,
    DMA_Ch2_IRQn = 2,
    DMA_Ch3_IRQn = 3,
    DMA_Ch4_IRQn = 4,
    DMA_Ch5_IRQn = 5,
    DMA_Ch6_IRQn = 6,
    DMA_Ch7_IRQn = 7,
    DMA_Ch8_IRQn = 8,
    DMA_Ch9_IRQn = 9,
    DMA_Ch10_IRQn = 10,
    DMA_Ch11_IRQn = 11,
    DMA_Ch12_IRQn = 12,
    DMA_Ch13_IRQn = 13,
    DMA_Ch14_IRQn = 14,
    DMA_Ch15_IRQn = 15,
    DMA_Err_IRQn = 16,
    FLASH_CmdComplete_IRQn = 17,
    FLASH_Ecc_IRQn = 18,
    PMU_IRQn = 19,
    WDOG_IRQn = 20,
    EWDT_IRQn = 21,
    SRMC_IRQn = 22,
    I2C0_IRQn = 23,
    I2C1_IRQn = 24,
    SPI0_Txe_IRQn = 25,
    SPI0_Txo_IRQn = 26,
    SPI0_Rxf_IRQn = 27,
    SPI0_Rxo_IRQn = 28,
    SPI0_Rxu_IRQn = 29,
    Reserved30_IRQn = 30,
    SPI1_Txe_IRQn = 31,
    SPI1_Txo_IRQn = 32,
    SPI1_Rxf_IRQn = 33,
    SPI1_Rxo_IRQn = 34,
    SPI1_Rxu_IRQn = 35,
    Reserved36_IRQn = 36,
    SPI2_Txe_IRQn = 37,
    SPI2_Txo_IRQn = 38,
    SPI2_Rxf_IRQn = 39,
    SPI2_Rxo_IRQn = 40,
    SPI2_Rxu_IRQn = 41,
    Reserved42_IRQn = 42,
    SPI3_Txe_IRQn = 43,
    SPI3_Txo_IRQn = 44,
    SPI3_Rxf_IRQn = 45,
    SPI3_Rxo_IRQn = 46,
    SPI3_Rxu_IRQn = 47,
    Reserved48_IRQn = 48,
    UART0_IRQn = 49,
    UART1_IRQn = 50,
    UART2_IRQn = 51,
    UART3_IRQn = 52,
    UART4_IRQn = 53,
    UART5_IRQn = 54,
    CAN0_BusOff_IRQn = 55,
    CAN0_TxWarn_IRQn = 56,
    CAN0_RxWarn_IRQn = 57,
    CAN0_Err_IRQn = 58,
    CAN0_ErrFd_IRQn = 59,
    CAN0_PnWake_IRQn = 60,
    CAN0_SelfWakeup_IRQn = 61,
    CAN0_Ecc_IRQn = 62,
    CAN0_Mb0To15_IRQn = 63,
    CAN0_Mb16To31_IRQn = 64,
    CAN0_Mb32To47_IRQn = 65,
    CAN0_Mb48To63_IRQn = 66,
    CAN1_BusOff_IRQn = 67,
    CAN1_TxWarn_IRQn = 68,
    CAN1_RxWarn_IRQn = 69,
    CAN1_Err_IRQn = 70,
    CAN1_ErrFd_IRQn = 71,
    CAN1_PnWake_IRQn = 72,
    CAN1_SelfWakeup_IRQn = 73,
    CAN1_Ecc_IRQn = 74,
    CAN1_Mb0To15_IRQn = 75,
    CAN1_Mb16To31_IRQn = 76,
    CAN1_Mb32To47_IRQn = 77,
    CAN1_Mb48To63_IRQn = 78,
    CAN2_BusOff_IRQn = 79,
    CAN2_TxWarn_IRQn = 80,
    CAN2_RxWarn_IRQn = 81,
    CAN2_Err_IRQn = 82,
    CAN2_ErrFd_IRQn = 83,
    CAN2_PnWake_IRQn = 84,
    CAN2_SelfWakeup_IRQn = 85,
    CAN2_Ecc_IRQn = 86,
    CAN2_Mb0To15_IRQn = 87,
    CAN2_Mb16To31_IRQn = 88,
    CAN2_Mb32To47_IRQn = 89,
    CAN2_Mb48To63_IRQn = 90,
    CAN3_BusOff_IRQn = 91,
    CAN3_TxWarn_IRQn = 92,
    CAN3_RxWarn_IRQn = 93,
    CAN3_Err_IRQn = 94,
    CAN3_ErrFd_IRQn = 95,
    CAN3_PnWake_IRQn = 96,
    CAN3_SelfWakeup_IRQn = 97,
    CAN3_Ecc_IRQn = 98,
    CAN3_Mb0To15_IRQn = 99,
    CAN3_Mb16To31_IRQn = 100,
    CAN3_Mb32To47_IRQn = 101,
    CAN3_Mb48To63_IRQn = 102,
    CAN4_BusOff_IRQn = 103,
    CAN4_TxWarn_IRQn = 104,
    CAN4_RxWarn_IRQn = 105,
    CAN4_Err_IRQn = 106,
    CAN4_ErrFd_IRQn = 107,
    CAN4_PnWake_IRQn = 108,
    CAN4_SelfWakeup_IRQn = 109,
    CAN4_Ecc_IRQn = 110,
    CAN4_Mb0To15_IRQn = 111,
    CAN4_Mb16To31_IRQn = 112,
    CAN4_Mb32To47_IRQn = 113,
    CAN4_Mb48To63_IRQn = 114,
    CAN5_BusOff_IRQn = 115,
    CAN5_TxWarn_IRQn = 116,
    CAN5_RxWarn_IRQn = 117,
    CAN5_Err_IRQn = 118,
    CAN5_ErrFd_IRQn = 119,
    CAN5_PnWake_IRQn = 120,
    CAN5_SelfWakeup_IRQn = 121,
    CAN5_Ecc_IRQn = 122,
    CAN5_Mb0To15_IRQn = 123,
    CAN5_Mb16To31_IRQn = 124,
    CAN5_Mb32To47_IRQn = 125,
    CAN5_Mb48To63_IRQn = 126,
    CAN6_BusOff_IRQn = 127,
    CAN6_TxWarn_IRQn = 128,
    CAN6_RxWarn_IRQn = 129,
    CAN6_Err_IRQn = 130,
    CAN6_ErrFd_IRQn = 131,
    CAN6_PnWake_IRQn = 132,
    CAN6_SelfWakeup_IRQn = 133,
    CAN6_Ecc_IRQn = 134,
    CAN6_Mb0To31_IRQn = 135,
    CAN6_Mb32To63_IRQn = 136,
    CAN6_Mb64To95_IRQn = 137,
    CAN6_Mb96To127_IRQn = 138,
    CAN7_BusOff_IRQn = 139,
    CAN7_TxWarn_IRQn = 140,
    CAN7_RxWarn_IRQn = 141,
    CAN7_Err_IRQn = 142,
    CAN7_ErrFd_IRQn = 143,
    CAN7_PnWake_IRQn = 144,
    CAN7_SelfWakeup_IRQn = 145,
    CAN7_Ecc_IRQn = 146,
    CAN7_Mb0To31_IRQn = 147,
    CAN7_Mb32To63_IRQn = 148,
    CAN7_Mb64To95_IRQn = 149,
    CAN7_Mb96To127_IRQn = 150,
    Reserved151_IRQn = 151,
    Reserved152_IRQn = 152,
    Reserved153_IRQn = 153,
    TIM0_Ch_IRQn = 154,
    TIM0_Fault_IRQn = 155,
    TIM0_Overflow_IRQn = 156,
    TIM0_Rlfl_IRQn = 157,
    TIM1_Ch_IRQn = 158,
    TIM1_Fault_IRQn = 159,
    TIM1_Overflow_IRQn = 160,
    TIM1_Rlfl_IRQn = 161,
    TIM2_Ch_IRQn = 162,
    TIM2_Fault_IRQn = 163,
    TIM2_Overflow_IRQn = 164,
    TIM2_Rlfl_IRQn = 165,
    TIM3_Ch_IRQn = 166,
    TIM3_Fault_IRQn = 167,
    TIM3_Overflow_IRQn = 168,
    TIM3_Rlfl_IRQn = 169,
    TDG0_Tco_IRQn = 170,
    TDG0_Err_IRQn = 171,
    TDG1_Tco_IRQn = 172,
    TDG1_Err_IRQn = 173,
    I2S0_IRQn = 174,
    I2S1_IRQn = 175,
    PORTA_IRQn = 176,
    PORTB_IRQn = 177,
    PORTC_IRQn = 178,
    PORTD_IRQn = 179,
    PORTE_IRQn = 180,
    STIM_IRQn = 181,
    RTC_Alarm_IRQn = 182,
    RTC_Second_IRQn = 183,
    AES_IRQn = 184,
    TRNG_IRQn = 185,
    CMU0_IRQn = 186,
    CMU1_IRQn = 187,
    CMU2_IRQn = 188,
    SERU_ParityErr_IRQn = 189,
    SERU_ChErr_IRQn = 190,
    SCC_IRQn = 191,
    MCPWM0_Ch_IRQn = 192,
    MCPWM0_Fault_IRQn = 193,
    MCPWM0_Overflow_IRQn = 194,
    MCPWM0_Rlfl_IRQn = 195,
    MCPWM1_Ch_IRQn = 196,
    MCPWM1_Fault_IRQn = 197,
    MCPWM1_Overflow_IRQn = 198,
    MCPWM1_Rlfl_IRQn = 199,
    ADC0_IRQn = 200,
    ADC1_IRQn = 201,
    CMP_IRQn = 202,
    FPU_Err_IRQn = 203,
    CACHE_Err_IRQn = 204,
} IRQn_Type;
# 352 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices/Z20K148M.h"
typedef struct
{
    uint32 RESERVED0[1U];
    volatile const uint32 ICTR;
    volatile uint32 ACTLR;
} Z20_SCnSCBType;




typedef struct
{
    volatile const uint32 CPUID;
    volatile uint32 ICSR;
    volatile uint32 VTOR;
    volatile uint32 AIRCR;
    volatile uint32 SCR;
    volatile uint32 CCR;
    volatile uint8
        SHP[12U];
    volatile uint32 SHCSR;
    volatile uint32 CFSR;
    volatile uint32 HFSR;
    volatile uint32 DFSR;
    volatile uint32 MMFAR;
    volatile uint32 BFAR;
    volatile uint32 AFSR;
    volatile const uint32 PFR[2U];
    volatile const uint32 DFR;
    volatile const uint32 ADR;
    volatile const uint32 MMFR[4U];
    volatile const uint32 ISAR[5U];
    uint32 RESERVED0[5U];
    volatile uint32 CPACR;
} Z20_SCBType;




typedef struct
{
    volatile uint32 CTRL;
    volatile uint32 LOAD;
    volatile uint32 VAL;
    volatile const uint32 CALIB;
} Z20_SysTickType;




typedef struct
{
    volatile uint32 ISER[8U];
    uint32 RESERVED0[24U];
    volatile uint32 ICER[8U];
    uint32 RSERVED1[24U];
    volatile uint32 ISPR[8U];
    uint32 RESERVED2[24U];
    volatile uint32 ICPR[8U];
    uint32 RESERVED3[24U];
    volatile uint32 IABR[8U];
    uint32 RESERVED4[56U];
    volatile uint8 IP[240U];
    uint32 RESERVED5[644U];
    volatile uint32 STIR;
} Z20_NVICType;




typedef struct
{
    volatile uint32 CTRL;
    volatile uint32 CYCCNT;
    volatile uint32 CPICNT;
    volatile uint32 EXCCNT;
    volatile uint32 SLEEPCNT;
    volatile uint32 LSUCNT;
    volatile uint32 FOLDCNT;
    volatile const uint32 PCSR;
    volatile uint32 COMP0;
    volatile uint32 MASK0;
    volatile uint32 FUNCTION0;
    uint32 RESERVED0[1U];
    volatile uint32 COMP1;
    volatile uint32 MASK1;
    volatile uint32 FUNCTION1;
    uint32 RESERVED1[1U];
    volatile uint32 COMP2;
    volatile uint32 MASK2;
    volatile uint32 FUNCTION2;
    uint32 RESERVED2[1U];
    volatile uint32 COMP3;
    volatile uint32 MASK3;
    volatile uint32 FUNCTION3;
} Z20_DWTType;




typedef struct
{
    volatile uint32 DHCSR;
    volatile uint32 DCRSR;
    volatile uint32 DCRDR;
    volatile uint32 DEMCR;
} Z20_CoreDebugType;




typedef struct
{
    uint32 RESERVED0[1U];
    volatile uint32 FPCCR;
    volatile uint32 FPCAR;
    volatile uint32 FPDSCR;
    volatile const uint32 MVFR0;
    volatile const uint32 MVFR1;
} Z20_FPUType;
# 496 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices/Z20K148M.h"
struct Reg_Adc_Bf
{

    uint32 zResverd0x000;

    struct
    {
        uint32 RSVD_7_0 : 8;
        uint32 FIFO_SIZE : 8;
        uint32 RSVD_31_16 : 16;
    } ADC_PARAM;


    struct
    {
        uint32 ADC_EN : 1;
        uint32 CAL_REQ : 1;
        uint32 RST : 1;
        uint32 DOZEN : 1;
        uint32 TRIG_MODE_ENABLE : 1;
        uint32 TRIG_MODE : 1;
        uint32 MODE1_RST : 1;
        uint32 LMD : 3;
        uint32 IREF_SEL : 1;
        uint32 STABLE_T : 11;
        uint32 RSVD_31_22 : 10;
    } ADC_CTRL;


    struct
    {
        uint32 FWM_INT : 1;
        uint32 FOF : 1;
        uint32 TCOMP_INT : 1;
        uint32 CMP_INT : 1;
        uint32 DMA_REQ : 1;
        uint32 RDY : 1;
        uint32 CAL_RDY : 1;
        uint32 ADC_ACTIVE : 1;
        uint32 LSI : 1;
        uint32 TC_ERR : 1;
        uint32 RSVD_31_10 : 22;
    } ADC_STAT;


    struct
    {
        uint32 FWM_IE : 1;
        uint32 FOF_IE : 1;
        uint32 TCOM_IE : 1;
        uint32 CMP_IE : 1;
        uint32 FWMDE : 1;
        uint32 ERR_INT_IE : 1;
        uint32 RSVD_31_6 : 26;
    } ADC_IE;


    struct
    {
        uint32 DIFF_MODE : 1;
        uint32 CHSELP : 5;
        uint32 CHSELN : 2;
        uint32 RSVD_10_8 : 3;
        uint32 CTYPE : 1;
        uint32 CMPS : 3;
        uint32 HWT_EN : 1;
        uint32 REF_SEL : 1;
        uint32 RES : 2;
        uint32 AVGS : 3;
        uint32 STS : 10;
    } ADC_CFG;


    struct
    {
        uint32 CVL : 12;
        uint32 RSVD_15_12 : 4;
        uint32 CVH : 12;
        uint32 RSVD_31_28 : 4;
    } ADC_CV;


    uint8 zResverd0x01C[4];


    struct
    {
        uint32 ADC_DATA_RD : 17;
        uint32 RSVD_31_17 : 15;
    } ADC_DATA_RD;


    struct
    {
        uint32 FCOUNT : 5;
        uint32 RSVD_15_5 : 11;
        uint32 FWMARK : 4;
        uint32 FDRD : 5;
        uint32 RSVD_31_25 : 7;
    } ADC_FCTRL;


    struct
    {
        uint32 ADC_SWTRIG : 1;
        uint32 RSVD_31_1 : 31;
    } ADC_SWTRIG;


    struct
    {
        uint32 ADC_CAL_VAL : 13;
        uint32 RSVD_31_13 : 19;
    } ADC_CAL_VAL;


    struct
    {
        uint32 CMD0 : 5;
        uint32 CMD0_INT_EN : 1;
        uint32 RSVD_7_6 : 2;
        uint32 CMD1 : 5;
        uint32 CMD1_INT_EN : 1;
        uint32 RSVD_15_14 : 2;
        uint32 CMD2 : 5;
        uint32 CMD2_INT_EN : 1;
        uint32 RSVD_23_22 : 2;
        uint32 CMD3 : 5;
        uint32 CMD3_INT_EN : 1;
        uint32 RSVD_31_30 : 2;
    } ADC_CMD_BUFF0;


    struct
    {
        uint32 CMD4 : 5;
        uint32 CMD4_INT_EN : 1;
        uint32 RSVD_7_6 : 2;
        uint32 CMD5 : 5;
        uint32 CMD5_INT_EN : 1;
        uint32 RSVD_31_14 : 18;
    } ADC_CMD_BUFF1;

};

struct Reg_Adc_W
{

    uint32 zResverd0x000;

    uint32 ADC_PARAM;

    uint32 ADC_CTRL;

    uint32 ADC_STAT;

    uint32 ADC_IE;

    uint32 ADC_CFG;

    uint32 ADC_CV;

    uint8 zResverd0x01C[4];

    uint32 ADC_DATA_RD;

    uint32 ADC_FCTRL;

    uint32 ADC_SWTRIG;

    uint32 ADC_CAL_VAL;

    uint32 ADC_CMD_BUFF0;

    uint32 ADC_CMD_BUFF1;
};

typedef volatile struct Reg_Adc_Bf Reg_Adc_BfType;
typedef volatile struct Reg_Adc_W Reg_Adc_WType;

struct Reg_Aes_Bf
{

    uint32 zResverd0x0000;

    struct
    {
        uint32 R : 1;
        uint32 ERR : 8;
        uint32 RSVD_31_9 : 23;
    } AES_STATUS;


    struct
    {
        uint32 S : 1;
        uint32 RND : 4;
        uint32 RSVD_31_5 : 27;
    } AES_CONTROL;


    struct
    {
        uint32 CD : 1;
        uint32 KSS : 2;
        uint32 RSVD_3 : 1;
        uint32 RSVD_7_4 : 4;
        uint32 MODE : 8;
        uint32 BS : 8;
        uint32 ALGO : 8;
    } AES_CONFIG;

    uint8 zResverd0x010[12];


    struct
    {
        uint32 DATA_I : 32;
    } AES_DATA_I0;


    struct
    {
        uint32 DATA_I : 32;
    } AES_DATA_I1;


    struct
    {
        uint32 DATA_I : 32;
    } AES_DATA_I2;


    struct
    {
        uint32 DATA_I : 32;
    } AES_DATA_I3;


    struct
    {
        uint32 DATA_O : 32;
    } AES_DATA_O0;


    struct
    {
        uint32 DATA_O : 32;
    } AES_DATA_O1;


    struct
    {
        uint32 DATA_O : 32;
    } AES_DATA_O2;


    struct
    {
        uint32 DATA_O : 32;
    } AES_DATA_O3;


    struct
    {
        uint32 KEY0 : 32;
    } AES_KEY0;


    struct
    {
        uint32 KEY1 : 32;
    } AES_KEY1;


    struct
    {
        uint32 KEY2 : 32;
    } AES_KEY2;


    struct
    {
        uint32 KEY3 : 32;
    } AES_KEY3;

    uint8 zResverd0x04C[16];


    struct
    {
        uint32 IV0 : 32;
    } AES_IV0;


    struct
    {
        uint32 IV1 : 32;
    } AES_IV1;


    struct
    {
        uint32 IV2 : 32;
    } AES_IV2;


    struct
    {
        uint32 IV3 : 32;
    } AES_IV3;

};

struct Reg_Aes_W
{

    uint32 zResverd0x0000;

    uint32 AES_STATUS;

    uint32 AES_CONTROL;

    uint32 AES_CONFIG;
    uint8 zResverd0x010[12];


    uint32 AES_DATA_I0;

    uint32 AES_DATA_I1;

    uint32 AES_DATA_I2;

    uint32 AES_DATA_I3;

    uint32 AES_DATA_O0;

    uint32 AES_DATA_O1;

    uint32 AES_DATA_O2;

    uint32 AES_DATA_O3;

    uint32 AES_KEY0;

    uint32 AES_KEY1;

    uint32 AES_KEY2;

    uint32 AES_KEY3;
    uint8 zResverd0x04C[16];


    uint32 AES_IV0;

    uint32 AES_IV1;

    uint32 AES_IV2;

    uint32 AES_IV3;
};

typedef volatile struct Reg_Aes_Bf Reg_Aes_BfType;
typedef volatile struct Reg_Aes_W Reg_Aes_WType;

struct Reg_Can_Bf
{

    struct
    {
        uint32 MAXMB : 7;
        uint32 RSVD_7 : 1;
        uint32 IDAM : 2;
        uint32 RSVD_10 : 1;
        uint32 FDEN : 1;
        uint32 AEN : 1;
        uint32 LPRIOEN : 1;
        uint32 PNET_EN : 1;
        uint32 DMAE : 1;
        uint32 IRMQ : 1;
        uint32 SRXDIS : 1;
        uint32 DOZE : 1;
        uint32 WAKSRC : 1;
        uint32 LPMACK : 1;
        uint32 WRNEN : 1;
        uint32 SLFWAK : 1;
        uint32 SUPV : 1;
        uint32 FRZACK : 1;
        uint32 SOFTRST : 1;
        uint32 WAKMSK : 1;
        uint32 NOTRDY : 1;
        uint32 HALT : 1;
        uint32 RFEN : 1;
        uint32 FRZ : 1;
        uint32 MDIS : 1;
    } CAN_MCR;


    struct
    {
        uint32 PROPSEG : 3;
        uint32 LOM : 1;
        uint32 LBUF : 1;
        uint32 TSYC : 1;
        uint32 BOFFREC : 1;
        uint32 SMP : 1;
        uint32 RSVD_9_8 : 2;
        uint32 RWRNMSK : 1;
        uint32 TWRNMSK : 1;
        uint32 LPB : 1;
        uint32 RSVD_13 : 1;
        uint32 ERRMSK : 1;
        uint32 BOFFMSK : 1;
        uint32 PSEG2 : 3;
        uint32 PSEG1 : 3;
        uint32 RJW : 2;
        uint32 PRESDIV : 8;
    } CAN_CTRL1;


    struct
    {
        uint32 TIMER : 16;
        uint32 RSVD_31_16 : 16;
    } CAN_TIMER;

    uint8 zResverd0x0C[4];


    struct
    {
        uint32 MG : 32;
    } CAN_RXMGMSK;


    struct
    {
        uint32 RX14M : 32;
    } CAN_RX14MASK;


    struct
    {
        uint32 RX15M : 32;
    } CAN_RX15MASK;


    struct
    {
        uint32 TXERRCNT : 8;
        uint32 RXERRCNT : 8;
        uint32 TX_ERRCNT_FAST : 8;
        uint32 RX_ERRCNT_FAST : 8;
    } CAN_ECR;


    struct
    {
        uint32 WAKINT : 1;
        uint32 ERRINT : 1;
        uint32 BOFFINT : 1;
        uint32 RX : 1;
        uint32 FLTCONF : 2;
        uint32 TX : 1;
        uint32 IDLE : 1;
        uint32 RXWRN : 1;
        uint32 TXWRN : 1;
        uint32 STFERR : 1;
        uint32 FRAMERR : 1;
        uint32 CRCERR : 1;
        uint32 ACKERR : 1;
        uint32 BIT0ERR : 1;
        uint32 BIT1ERR : 1;
        uint32 RWRNINT : 1;
        uint32 TWRNINT : 1;
        uint32 SYNCH : 1;
        uint32 BUSOFFDONEINT : 1;
        uint32 ERRINT_FAST : 1;
        uint32 ERROVR : 1;
        uint32 RSVD_25_22 : 4;
        uint32 STFERR_FAST : 1;
        uint32 FRAMERR_FAST : 1;
        uint32 CRCERR_FAST : 1;
        uint32 RSVD_29 : 1;
        uint32 BIT0ERR_FAST : 1;
        uint32 BIT1ERR_FAST : 1;
    } CAN_ESR1;


    struct
    {
        uint32 BUF63TO32M : 32;
    } CAN_IMASK2;


    struct
    {
        uint32 BUF31TO0M : 32;
    } CAN_IMASK1;


    struct
    {
        uint32 BUF63TO32I : 32;
    } CAN_IFLAG2;


    struct
    {
        uint32 BUF0I : 1;
        uint32 BUF4TO1I : 4;
        uint32 BUF5I : 1;
        uint32 BUF6I : 1;
        uint32 BUF7I : 1;
        uint32 BUF31TO8I : 24;
    } CAN_IFLAG1;


    struct
    {
        uint32 RSVD_10_0 : 11;
        uint32 EDFLTDIS : 1;
        uint32 ISOCANFDEN : 1;
        uint32 RSVD_13 : 1;
        uint32 PREXCEN : 1;
        uint32 TIMER_SRC : 1;
        uint32 EACEN : 1;
        uint32 RRS : 1;
        uint32 MRP : 1;
        uint32 TASD : 5;
        uint32 RFFN : 4;
        uint32 WRMFRZ : 1;
        uint32 ECRWRE : 1;
        uint32 BOFFDONEMSK : 1;
        uint32 ERRMASK_FAST : 1;
    } CAN_CTRL2;


    struct
    {
        uint32 RSVD_12_0 : 13;
        uint32 IMB : 1;
        uint32 VPS : 1;
        uint32 RSVD_15 : 1;
        uint32 LPTM : 7;
        uint32 RSVD_31_23 : 9;
    } CAN_ESR2;

    uint8 zResverd0x03C[8];


    struct
    {
        uint32 TXCRC : 15;
        uint32 RSVD_15 : 1;
        uint32 MBCRC : 7;
        uint32 RSVD_31_23 : 9;
    } CAN_CRCR;


    struct
    {
        uint32 FGM : 32;
    } CAN_RXFGMASK;


    struct
    {
        uint32 IDHIT : 9;
        uint32 RSVD_31_9 : 23;
    } CAN_RXFIR;


    struct
    {
        uint32 EPSEG2 : 5;
        uint32 EPSEG1 : 5;
        uint32 EPROPSEG : 6;
        uint32 ERJW : 5;
        uint32 EPRESDIV : 10;
        uint32 BTF : 1;
    } CAN_CBT;

    uint8 zResverd0x054[20];


    struct
    {
        uint32 BUF127TO96M : 32;
    } CAN_IMASK4;


    struct
    {
        uint32 BUF95TO64M : 32;
    } CAN_IMASK3;


    struct
    {
        uint32 BUF127TO96I : 32;
    } CAN_IFLAG4;


    struct
    {
        uint32 BUF95TO64I : 32;
    } CAN_IFLAG3;

    uint8 zResverd0x078[8];


    struct {
    struct
    {
        uint32 TIME_STAMP : 16;
        uint32 DLC : 4;
        uint32 RTR : 1;
        uint32 IDE : 1;
        uint32 SRR : 1;
        uint32 RSVD_23 : 1;
        uint32 CODE : 4;
        uint32 RSVD_28 : 1;
        uint32 ESI : 1;
        uint32 BRS : 1;
        uint32 EDL : 1;
    } CAN_MB_CS;


    struct
    {
        uint32 ID_EXTEND : 18;
        uint32 ID_STD_EXD : 11;
        uint32 PRIO : 3;
    } CAN_MB_ID;


    struct
    {
        uint32 DATA_BYTE03 : 32;
    } CAN_MB_DATA03;


    struct
    {
        uint32 DATA_BYTE47 : 32;
    } CAN_MB_DATA47;
    } CAN_MB[128];


    struct
    {
        uint32 MI : 32;
    } CAN_RXIMRn[128];

    uint8 zResverd0x0A80[96];


    struct
    {
        uint32 RSVD_6_0 : 7;
        uint32 NCEFAFRZ : 1;
        uint32 ECCDIS : 1;
        uint32 RERRDIS : 1;
        uint32 RSVD_12_10 : 3;
        uint32 EXTERRIE : 1;
        uint32 FAERRIE : 1;
        uint32 HAERRI : 1;
        uint32 CEI_MSK : 1;
        uint32 RSVD_17 : 1;
        uint32 FANCEI_MSK : 1;
        uint32 HANCEI_MSK : 1;
        uint32 RSVD_30_20 : 11;
        uint32 ECRWRDIS : 1;
    } CAN_MECR;


    struct
    {
        uint32 INJADDR_L : 2;
        uint32 INJADDR_H : 12;
        uint32 RSVD_31_14 : 18;
    } CAN_ERRIAR;


    struct
    {
        uint32 DFLIP : 32;
    } CAN_ERRIDPR;


    struct
    {
        uint32 PFLIP0 : 5;
        uint32 RSVD_7_5 : 3;
        uint32 PFLIP1 : 5;
        uint32 RSVD_15_13 : 3;
        uint32 PFLIP2 : 5;
        uint32 RSVD_23_21 : 3;
        uint32 PFLIP3 : 5;
        uint32 RSVD_31_29 : 3;
    } CAN_ERRIPPR;


    struct
    {
        uint32 ERRADDR : 14;
        uint32 RSVD_15_14 : 2;
        uint32 SAID : 3;
        uint32 RSVD_23_19 : 5;
        uint32 NCE : 1;
        uint32 RSVD_31_25 : 7;
    } CAN_RERRAR;


    struct
    {
        uint32 RDATA : 32;
    } CAN_RERRDR;


    struct
    {
        uint32 SYND0 : 5;
        uint32 RSVD_6_5 : 2;
        uint32 BE0 : 1;
        uint32 SYND1 : 5;
        uint32 RSVD_14_13 : 2;
        uint32 BE1 : 1;
        uint32 SYND2 : 5;
        uint32 RSVD_22_21 : 2;
        uint32 BE2 : 1;
        uint32 SYND3 : 5;
        uint32 RSVD_30_29 : 2;
        uint32 BE3 : 1;
    } CAN_RERRSYNR;


    struct
    {
        uint32 CEIOF : 1;
        uint32 RSVD_1 : 1;
        uint32 FANCEIOF : 1;
        uint32 HANCEIOF : 1;
        uint32 RSVD_15_4 : 12;
        uint32 CEIF : 1;
        uint32 RSVD_17 : 1;
        uint32 FANCEIF : 1;
        uint32 HANCEIF : 1;
        uint32 RSVD_31_20 : 12;
    } CAN_ERRSR;


    struct
    {
        uint32 FCS : 2;
        uint32 IDFS : 2;
        uint32 PLFS : 2;
        uint32 RSVD_7_6 : 2;
        uint32 NMATCH : 8;
        uint32 WUMF_MSK : 1;
        uint32 WTOF_MSK : 1;
        uint32 RSVD_31_18 : 14;
    } CAN_CTRL1_PN;


    struct
    {
        uint32 MATCHTO : 16;
        uint32 RSVD_31_16 : 16;
    } CAN_CTRL2_PN;


    struct
    {
        uint32 RSVD_7_0 : 8;
        uint32 MCOUNTER : 8;
        uint32 WUMF : 1;
        uint32 WTOF : 1;
        uint32 RSVD_31_18 : 14;
    } CAN_WU_MTC;


    struct
    {
        uint32 FLT_ID1 : 29;
        uint32 FLT_RTR : 1;
        uint32 FLT_IDE : 1;
        uint32 RSVD_31 : 1;
    } CAN_FLT_ID1;


    struct
    {
        uint32 FLT_DLC_HI : 4;
        uint32 RSVD_15_4 : 12;
        uint32 FLT_DLC_LO : 4;
        uint32 RSVD_31_20 : 12;
    } CAN_FLT_DLC;


    struct
    {
        uint32 DATA_BYTE_3 : 8;
        uint32 DATA_BYTE_2 : 8;
        uint32 DATA_BYTE_1 : 8;
        uint32 DATA_BYTE_0 : 8;
    } CAN_PL1_LO;


    struct
    {
        uint32 DATA_BYTE_7 : 8;
        uint32 DATA_BYTE_6 : 8;
        uint32 DATA_BYTE_5 : 8;
        uint32 DATA_BYTE_4 : 8;
    } CAN_PL1_HI;


    struct
    {
        uint32 FLT_ID2_IDMASK : 29;
        uint32 RTR_MSK : 1;
        uint32 IDE_MSK : 1;
        uint32 RSVD_31 : 1;
    } CAN_FLT_ID2_IDMASK;


    struct
    {
        uint32 DATA_BYTE_3 : 8;
        uint32 DATA_BYTE_2 : 8;
        uint32 DATA_BYTE_1 : 8;
        uint32 DATA_BYTE_0 : 8;
    } CAN_PL2_PLMASK_LO;


    struct
    {
        uint32 DATA_BYTE_7 : 8;
        uint32 DATA_BYTE_6 : 8;
        uint32 DATA_BYTE_5 : 8;
        uint32 DATA_BYTE_4 : 8;
    } CAN_PL2_PLMASK_HI;

    uint8 zResverd0x0B28[24];

    struct {

    struct
    {
        uint32 RSVD_15_0 : 16;
        uint32 DLC : 4;
        uint32 RTR : 1;
        uint32 IDE : 1;
        uint32 SRR : 1;
        uint32 RSVD_31_23 : 9;
    } CAN_WMB_CS;


    struct
    {
        uint32 ID : 29;
        uint32 RSVD_31_29 : 3;
    } CAN_WMB_ID;


    struct
    {
        uint32 DATA_BYTE_3 : 8;
        uint32 DATA_BYTE_2 : 8;
        uint32 DATA_BYTE_1 : 8;
        uint32 DATA_BYTE_0 : 8;
    } CAN_WMB_D03;


    struct
    {
        uint32 DATA_BYTE_7 : 8;
        uint32 DATA_BYTE_6 : 8;
        uint32 DATA_BYTE_5 : 8;
        uint32 DATA_BYTE_4 : 8;
    } CAN_WMB_D47;
    } CAN_WMB[4];

    uint8 zResverd0x0B80[128];


    struct
    {
        uint32 TDCVAL : 6;
        uint32 RSVD_7_6 : 2;
        uint32 TDCOFF : 5;
        uint32 RSVD_13 : 1;
        uint32 TDCFAIL : 1;
        uint32 TDCEN : 1;
        uint32 MBDSR0 : 2;
        uint32 RSVD_18 : 1;
        uint32 MBDSR1 : 2;
        uint32 RSVD_21 : 1;
        uint32 MBDSR2 : 2;
        uint32 RSVD_24 : 1;
        uint32 MBDSR3 : 2;
        uint32 RSVD_30_27 : 4;
        uint32 FD_RATE : 1;
    } CAN_FDCTRL;


    struct
    {
        uint32 FPSEG2 : 3;
        uint32 RSVD_4_3 : 2;
        uint32 FPSEG1 : 3;
        uint32 RSVD_9_8 : 2;
        uint32 FPROPSEG : 5;
        uint32 RSVD_15 : 1;
        uint32 FRJW : 3;
        uint32 RSVD_19 : 1;
        uint32 FPRESDIV : 10;
        uint32 RSVD_31_30 : 2;
    } CAN_FDCBT;


    struct
    {
        uint32 FD_TXCRC : 21;
        uint32 RSVD_23_21 : 3;
        uint32 FD_MBCRC : 7;
        uint32 RSVD_31 : 1;
    } CAN_FDCRC;

};

struct Reg_Can_W
{

    uint32 CAN_MCR;

    uint32 CAN_CTRL1;

    uint32 CAN_TIMER;
    uint8 zResverd0x0C[4];


    uint32 CAN_RXMGMSK;

    uint32 CAN_RX14MASK;

    uint32 CAN_RX15MASK;

    uint32 CAN_ECR;

    uint32 CAN_ESR1;

    uint32 CAN_IMASK2;

    uint32 CAN_IMASK1;

    uint32 CAN_IFLAG2;

    uint32 CAN_IFLAG1;

    uint32 CAN_CTRL2;

    uint32 CAN_ESR2;
    uint8 zResverd0x03C[8];


    uint32 CAN_CRCR;

    uint32 CAN_RXFGMASK;

    uint32 CAN_RXFIR;

    uint32 CAN_CBT;
    uint8 zResverd0x054[20];


    uint32 CAN_IMASK4;

    uint32 CAN_IMASK3;

    uint32 CAN_IFLAG4;

    uint32 CAN_IFLAG3;
    uint8 zResverd0x078[8];

    struct
    {

        uint32 MB0;

        uint32 MB1;

        uint32 MB2;

        uint32 MB3;
    } CAN_MB[128];


    uint32 CAN_RXIMR[128];
    uint8 zResverd0x0A80[96];


    uint32 CAN_MECR;

    uint32 CAN_ERRIAR;

    uint32 CAN_ERRIDPR;

    uint32 CAN_ERRIPPR;

    uint32 CAN_RERRAR;

    uint32 CAN_RERRDR;

    uint32 CAN_RERRSYNR;

    uint32 CAN_ERRSR;

    uint32 CAN_CTRL1_PN;

    uint32 CAN_CTRL2_PN;

    uint32 CAN_WU_MTC;

    uint32 CAN_FLT_ID1;

    uint32 CAN_FLT_DLC;

    uint32 CAN_PL1_LO;

    uint32 CAN_PL1_HI;

    uint32 CAN_FLT_ID2_IDMASK;

    uint32 CAN_PL2_PLMASK_LO;

    uint32 CAN_PL2_PLMASK_HI;
    uint8 zResverd0x0B28[24];

    struct {

    uint32 CAN_WMB_CS;

    uint32 CAN_WMB_ID;

    uint32 CAN_WMB_D03;

    uint32 CAN_WMB_D47;
    } CAN_WMB[4];

    uint8 zResverd0x0B80[128];


    uint32 CAN_FDCTRL;

    uint32 CAN_FDCBT;

    uint32 CAN_FDCRC;
};

typedef volatile struct Reg_Can_Bf Reg_Can_BfType;
typedef volatile struct Reg_Can_W Reg_Can_WType;

struct Reg_Cmp_Bf
{

    uint32 zResverd0x0;

    struct
    {
        uint32 DAC_RES : 4;
        uint32 RSVD_31_4 : 28;
    } CMP_PARAM;


    struct
    {
        uint32 CMP_SEL : 1;
        uint32 CMP_EN : 1;
        uint32 SOC_TRG_EN : 1;
        uint32 STOP_EN : 1;
        uint32 RSVD_31_4 : 28;
    } CMP_CCR0;


    struct
    {
        uint32 WINDOW_EN : 1;
        uint32 SAMPLE_EN : 1;
        uint32 DMA_EN : 1;
        uint32 COUT_INV : 1;
        uint32 COUT_SEL : 1;
        uint32 COUT_PEN : 1;
        uint32 COUT_OWE : 1;
        uint32 COUT_OW : 1;
        uint32 RSVD_15_8 : 8;
        uint32 FILT_CNT : 3;
        uint32 RSVD_23_19 : 5;
        uint32 FILT_PER : 8;
    } CMP_CCR1;


    struct
    {
        uint32 HS_HSTCTR : 2;
        uint32 RSVD_3_2 : 2;
        uint32 LS_HSTCTR : 2;
        uint32 RSVD_15_6 : 10;
        uint32 HS_PSEL : 4;
        uint32 HS_MSEL : 4;
        uint32 LS_PSEL : 4;
        uint32 LS_MSEL : 4;
    } CMP_CCR2;


    struct
    {
        uint32 DAC_EN : 1;
        uint32 DAC_BUFF_EN : 1;
        uint32 RSVD_7_2 : 6;
        uint32 VREF_SEL : 1;
        uint32 RSVD_15_9 : 7;
        uint32 DAC_SEL : 8;
        uint32 RSVD_31_24 : 8;
    } CMP_DCR;


    struct
    {
        uint32 CFR_IE : 1;
        uint32 CFF_IE : 1;
        uint32 RSVD_31_2 : 30;
    } CMP_IER;


    struct
    {
        uint32 CFR : 1;
        uint32 CFF : 1;
        uint32 RSVD_7_2 : 6;
        uint32 COUT : 1;
        uint32 RSVD_31_9 : 23;
    } CMP_CSR;

};

struct Reg_Cmp_W
{

    uint32 zResverd0x0;

    uint32 CMP_PARAM;

    uint32 CMP_CCR0;

    uint32 CMP_CCR1;

    uint32 CMP_CCR2;

    uint32 CMP_DCR;

    uint32 CMP_IER;

    uint32 CMP_CSR;
};

typedef volatile struct Reg_Cmp_Bf Reg_Cmp_BfType;
typedef volatile struct Reg_Cmp_W Reg_Cmp_WType;

struct Reg_Cmu_Bf
{

    uint32 zResverd0x0;

    struct
    {
        uint32 RST_IMP : 1;
        uint32 RSVD_31_1 : 31;
    } CMU_PARAM;


    struct
    {
        uint32 CME : 1;
        uint32 RSVD_3_1 : 3;
        uint32 CMMD : 1;
        uint32 RSVD_7_5 : 3;
        uint32 FAHTRSTE : 1;
        uint32 FBLTRSTE : 1;
        uint32 RSVD_15_10 : 6;
        uint32 FAHTIE : 1;
        uint32 FBLTIE : 1;
        uint32 RSVD_30_18 : 13;
        uint32 LOCK : 1;
    } CMU_CTRL;


    struct
    {
        uint32 MONST : 2;
        uint32 RSVD_3_2 : 2;
        uint32 STARTMEA : 1;
        uint32 RSVD_15_5 : 11;
        uint32 FAHTIF : 1;
        uint32 FBLTIF : 1;
        uint32 RSVD_31_18 : 14;
    } CMU_STAT;


    struct
    {
        uint32 MONWIN : 32;
    } CMU_MONWIN;


    struct
    {
        uint32 HCT4INT : 32;
    } CMU_CUMHCT4INT;


    struct
    {
        uint32 LCT4INT : 32;
    } CMU_CUMLCT4INT;


    struct
    {
        uint32 HCT4RST : 32;
    } CMU_CUMHCT4RST;


    struct
    {
        uint32 LCT4RST : 32;
    } CMU_CUMLCT4RST;


    struct
    {
        uint32 MEARSLT : 32;
    } CMU_CUMMEARSLT;

};

struct Reg_Cmu_W
{

    uint32 zResverd0x0;

    uint32 CMU_PARAM;

    uint32 CMU_CTRL;

    uint32 CMU_STAT;

    uint32 CMU_MONWIN;

    uint32 CMU_CUMHCT4INT;

    uint32 CMU_CUMLCT4INT;

    uint32 CMU_CUMHCT4RST;

    uint32 CMU_CUMLCT4RST;

    uint32 CMU_CUMMEARSLT;
};

typedef volatile struct Reg_Cmu_Bf Reg_Cmu_BfType;
typedef volatile struct Reg_Cmu_W Reg_Cmu_WType;

struct Reg_Crc_Bf
{

    uint32 zResverd0x0;

    struct
    {
        uint32 RSVD_31_0 : 32;
    } CRC_PARAM;


    struct
    {
        uint32 BYTE0 : 8;
        uint32 BYTE1 : 8;
        uint32 BYTE2 : 8;
        uint32 BYTE3 : 8;
    } CRC_DATA;


    struct
    {
        uint32 LPHW : 16;
        uint32 HPHW : 16;
    } CRC_POLY;


    struct
    {
        uint32 MODE : 1;
        uint32 WS : 1;
        uint32 CR : 1;
        uint32 RSVD_3 : 1;
        uint32 RT : 2;
        uint32 WT : 2;
        uint32 RSVD_31_8 : 24;
    } CRC_CTRL;

};

struct Reg_Crc_W
{

    uint32 zResverd0x0;

    uint32 CRC_PARAM;

    uint32 CRC_DATA;

    uint32 CRC_POLY;

    uint32 CRC_CTRL;
};

typedef volatile struct Reg_Crc_Bf Reg_Crc_BfType;
typedef volatile struct Reg_Crc_W Reg_Crc_WType;

struct Reg_Dmamux_Bf
{

    struct
    {
        uint32 ENABLE : 1;
        uint32 SRC_MUX : 7;
        uint32 RSVD_31_8 : 24;
    } DMA_MUX_CH_CFG[16];

};

struct Reg_Dmamux_W
{

    uint32 DMA_MUX_CH_CFG[16];
};

struct Reg_Dma_Bf
{

    struct
    {
        uint32 HALT : 1;
        uint32 HOEE : 1;
        uint32 RRCAE : 1;
        uint32 DBGE : 1;
        uint32 RSVD_5_4 : 2;
        uint32 BUSY : 1;
        uint32 RSVD_31_7 : 25;
    } DMA_CONF;


    struct
    {
        uint32 DMAE0 : 1;
        uint32 DMAE1 : 1;
        uint32 DMAE2 : 1;
        uint32 DMAE3 : 1;
        uint32 DMAE4 : 1;
        uint32 DMAE5 : 1;
        uint32 DMAE6 : 1;
        uint32 DMAE7 : 1;
        uint32 DMAE8 : 1;
        uint32 DMAE9 : 1;
        uint32 DMAE10 : 1;
        uint32 DMAE11 : 1;
        uint32 DMAE12 : 1;
        uint32 DMAE13 : 1;
        uint32 DMAE14 : 1;
        uint32 DMAE15 : 1;
        uint32 RSVD_31_16 : 16;
    } DMA_DMAE;

    uint8 zResverd0x08[4];


    struct
    {
        uint32 EIE0 : 1;
        uint32 EIE1 : 1;
        uint32 EIE2 : 1;
        uint32 EIE3 : 1;
        uint32 EIE4 : 1;
        uint32 EIE5 : 1;
        uint32 EIE6 : 1;
        uint32 EIE7 : 1;
        uint32 EIE8 : 1;
        uint32 EIE9 : 1;
        uint32 EIE10 : 1;
        uint32 EIE11 : 1;
        uint32 EIE12 : 1;
        uint32 EIE13 : 1;
        uint32 EIE14 : 1;
        uint32 EIE15 : 1;
        uint32 RSVD_31_16 : 16;
    } DMA_EIE;

    uint8 zResverd0x010[4];


    struct
    {
        uint32 CCDONE : 4;
        uint32 RSVD_5_4 : 2;
        uint32 CACDONE : 1;
        uint32 WPEN0 : 1;
        uint32 SCSTART : 4;
        uint32 RSVD_13_12 : 2;
        uint32 SACSTART : 1;
        uint32 WPEN1 : 1;
        uint32 CCES : 4;
        uint32 RSVD_21_20 : 2;
        uint32 CACES : 1;
        uint32 WPEN2 : 1;
        uint32 CCIS : 4;
        uint32 RSVD_29_28 : 2;
        uint32 CACIS : 1;
        uint32 WPEN3 : 1;
    } DMA_GCC;


    struct
    {
        uint32 DBEF : 1;
        uint32 SBEF : 1;
        uint32 RSVD_2 : 1;
        uint32 NUMEF : 1;
        uint32 DOEF : 1;
        uint32 DAEF : 1;
        uint32 SOEF : 1;
        uint32 SAEF : 1;
        uint32 CHEF : 4;
        uint32 RSVD_12 : 1;
        uint32 PRIEF : 1;
        uint32 RSVD_14 : 1;
        uint32 ERRF : 1;
        uint32 RSVD_31_16 : 16;
    } DMA_ES;


    struct
    {
        uint32 ERR0 : 1;
        uint32 ERR1 : 1;
        uint32 ERR2 : 1;
        uint32 ERR3 : 1;
        uint32 ERR4 : 1;
        uint32 ERR5 : 1;
        uint32 ERR6 : 1;
        uint32 ERR7 : 1;
        uint32 ERR8 : 1;
        uint32 ERR9 : 1;
        uint32 ERR10 : 1;
        uint32 ERR11 : 1;
        uint32 ERR12 : 1;
        uint32 ERR13 : 1;
        uint32 ERR14 : 1;
        uint32 ERR15 : 1;
        uint32 RSVD_31_16 : 16;
    } DMA_CES;


    struct
    {
        uint32 INT0 : 1;
        uint32 INT1 : 1;
        uint32 INT2 : 1;
        uint32 INT3 : 1;
        uint32 INT4 : 1;
        uint32 INT5 : 1;
        uint32 INT6 : 1;
        uint32 INT7 : 1;
        uint32 INT8 : 1;
        uint32 INT9 : 1;
        uint32 INT10 : 1;
        uint32 INT11 : 1;
        uint32 INT12 : 1;
        uint32 INT13 : 1;
        uint32 INT14 : 1;
        uint32 INT15 : 1;
        uint32 RSVD_31_16 : 16;
    } DMA_CIS;


    struct
    {
        uint32 HRS0 : 1;
        uint32 HRS1 : 1;
        uint32 HRS2 : 1;
        uint32 HRS3 : 1;
        uint32 HRS4 : 1;
        uint32 HRS5 : 1;
        uint32 HRS6 : 1;
        uint32 HRS7 : 1;
        uint32 HRS8 : 1;
        uint32 HRS9 : 1;
        uint32 HRS10 : 1;
        uint32 HRS11 : 1;
        uint32 HRS12 : 1;
        uint32 HRS13 : 1;
        uint32 HRS14 : 1;
        uint32 HRS15 : 1;
        uint32 RSVD_31_16 : 16;
    } DMA_CHRS;


    struct
    {
        uint32 CPRI3 : 4;
        uint32 RSVD_5_4 : 2;
        uint32 CPDIS3 : 1;
        uint32 CSE3 : 1;
        uint32 CPRI2 : 4;
        uint32 RSVD_13_12 : 2;
        uint32 CPDIS2 : 1;
        uint32 CSE2 : 1;
        uint32 CPRI1 : 4;
        uint32 RSVD_21_20 : 2;
        uint32 CPDIS1 : 1;
        uint32 CSE1 : 1;
        uint32 CPRI0 : 4;
        uint32 RSVD_29_28 : 2;
        uint32 CPDIS0 : 1;
        uint32 CSE0 : 1;
    } DMA_CPRI0;


    struct
    {
        uint32 CPRI7 : 4;
        uint32 RSVD_5_4 : 2;
        uint32 CPDIS7 : 1;
        uint32 CSE7 : 1;
        uint32 CPRI6 : 4;
        uint32 RSVD_13_12 : 2;
        uint32 CPDIS6 : 1;
        uint32 CSE6 : 1;
        uint32 CPRI5 : 4;
        uint32 RSVD_21_20 : 2;
        uint32 CPDIS5 : 1;
        uint32 CSE5 : 1;
        uint32 CPRI4 : 4;
        uint32 RSVD_29_28 : 2;
        uint32 CPDIS4 : 1;
        uint32 CSE4 : 1;
    } DMA_CPRI1;


    struct
    {
        uint32 CPRI11 : 4;
        uint32 RSVD_5_4 : 2;
        uint32 CPDIS11 : 1;
        uint32 CSE11 : 1;
        uint32 CPRI10 : 4;
        uint32 RSVD_13_12 : 2;
        uint32 CPDIS10 : 1;
        uint32 CSE10 : 1;
        uint32 CPRI9 : 4;
        uint32 RSVD_21_20 : 2;
        uint32 CPDIS9 : 1;
        uint32 CSE9 : 1;
        uint32 CPRI8 : 4;
        uint32 RSVD_29_28 : 2;
        uint32 CPDIS8 : 1;
        uint32 CSE8 : 1;
    } DMA_CPRI2;


    struct
    {
        uint32 CPRI15 : 4;
        uint32 RSVD_5_4 : 2;
        uint32 CPDIS15 : 1;
        uint32 CSE15 : 1;
        uint32 CPRI14 : 4;
        uint32 RSVD_13_12 : 2;
        uint32 CPDIS14 : 1;
        uint32 CSE14 : 1;
        uint32 CPRI13 : 4;
        uint32 RSVD_21_20 : 2;
        uint32 CPDIS13 : 1;
        uint32 CSE13 : 1;
        uint32 CPRI12 : 4;
        uint32 RSVD_29_28 : 2;
        uint32 CPDIS12 : 1;
        uint32 CSE12 : 1;
    } DMA_CPRI3;

    uint8 zResverd0x038[456];

    struct
    {

        struct
        {
            uint32 SADDR : 32;
        } DMA_SADDR;


        struct
        {
            uint32 DADDR : 32;
        } DMA_DADDR;


        struct
        {
            sint32 SAOFF : 16;
            sint32 DAOFF : 16;
        } DMA_AOFF;


        struct
        {
            sint32 MLSAOFF : 16;
            sint32 MLDAOFF : 16;
        } DMA_MLAOFF;


        struct
        {
            uint32 NUM : 32;
        } DMA_NUM;


        struct
        {
            uint32 MLITER : 16;
            uint32 MLSTA : 16;
        } DMA_ITER;


        struct
        {
            uint32 START : 1;
            uint32 INTE : 1;
            uint32 RSVD_2 : 1;
            uint32 REQDIS : 1;
            uint32 RSVD_5_4 : 2;
            uint32 BUSY : 1;
            uint32 DONE : 1;
            uint32 RSVD_15_8 : 8;
            uint32 DSIZE : 2;
            uint32 RSVD_23_18 : 6;
            uint32 SSIZE : 2;
            uint32 RSVD_31_26 : 6;
        } DMA_CS;

        uint8 zResverd[4];
    } DMA_CH_CONFIG[16];
};

struct Reg_Dma_W
{

    uint32 DMA_CONF;

    uint32 DMA_DMAE;
    uint8 zResverd0x08[4];


    uint32 DMA_EIE;
    uint8 zResverd0x010[4];


    uint32 DMA_GCC;

    uint32 DMA_ES;

    uint32 DMA_CES;

    uint32 DMA_CIS;

    uint32 DMA_CHRS;

    uint32 DMA_CPRI0;

    uint32 DMA_CPRI1;

    uint32 DMA_CPRI2;

    uint32 DMA_CPRI3;
    uint8 zResverd0x038[456];

    struct
    {

        uint32 DMA_SADDR;

        uint32 DMA_DADDR;

        uint32 DMA_AOFF;

        uint32 DMA_MLAOFF;

        uint32 DMA_NUM;

        uint32 DMA_ITER;

        uint32 DMA_CS;

        uint8 zResverd[4];
    } DMA_CH_CONFIG[16];
};

typedef volatile struct Reg_Dmamux_Bf Reg_Dmamux_BfType;
typedef volatile struct Reg_Dmamux_W Reg_Dmamux_WType;

typedef volatile struct Reg_Dma_Bf Reg_Dma_BfType;
typedef volatile struct Reg_Dma_W Reg_Dma_WType;

struct Reg_Eiru_Bf
{

    struct
    {
        uint32 SRAM0_ER_DIS : 1;
        uint32 SRAM0_EW_DIS : 1;
        uint32 SRAM0_ESB_DIS : 1;
        uint32 SRAM0_EMB_DIS : 1;
        uint32 SRAM0_EEI_EN : 1;
        uint32 RSVD_7_5 : 3;
        uint32 SRAM1_ER_DIS : 1;
        uint32 SRAM1_EW_DIS : 1;
        uint32 SRAM1_ESB_DIS : 1;
        uint32 SRAM1_EMB_DIS : 1;
        uint32 SRAM1_EEI_EN : 1;
        uint32 RSVD_30_13 : 18;
        uint32 LOCK : 1;
    } EIRU_CR;


    struct
    {
        uint32 RSVD_1_0 : 2;
        uint32 EEIADDR : 30;
    } EIRU_EEIADDR;

    uint8 zResverd0x08[8];
    struct
    {

        struct
        {
            uint32 EFPROT : 4;
            uint32 EFSIZE : 3;
            uint32 RSVD_7 : 1;
            uint32 EFMST : 8;
            uint32 RSVD_28_16 : 13;
            uint32 SBERR : 1;
            uint32 MBERR : 1;
            uint32 OVERRUN : 1;
        } EIRU_SRAMn_EESR;


        struct
        {
            uint32 EFADDR : 32;
        } EIRU_SRAMn_FADDR;


        struct
        {
            uint32 EFDATA : 32;
        } EIRU_SRAMn_FDATA;


        struct
        {
            uint32 ECCMASK : 7;
            uint32 RSVD_31_7 : 25;
        } EIRU_SRAMn_ECCMASK;


        struct
        {
            uint32 DATAMASK : 32;
        } EIRU_SRAMn_DATAMASK;
        uint8 zResverd0x024[12];
    } EIRU_SRAMn_SC[2];
};

struct Reg_Eiru_W
{

    uint32 EIRU_CR;

    uint32 EIRU_EEIADDR;
    uint8 zResverd0x08[8];
    struct
    {

        uint32 EIRU_SRAMn_EESR;

        uint32 EIRU_SRAMn_FADDR;

        uint32 EIRU_SRAMn_FDATA;

        uint32 EIRU_SRAMn_ECCMASK;

        uint32 EIRU_SRAMn_DATAMASK;
        uint8 zResverd0x024[12];
    } EIRU_SRAMn_SC[2];
};

typedef volatile struct Reg_Eiru_Bf Reg_Eiru_BfType;
typedef volatile struct Reg_Eiru_W Reg_Eiru_WType;

struct Reg_Ewdt_Bf
{

    uint32 zResverd0x0;

    struct
    {
        uint32 RSVD_31_0 : 32;
    } EWDT_PARAM;


    struct
    {
        uint32 EWDTE : 1;
        uint32 DEBUGE : 1;
        uint32 WAITE : 1;
        uint32 RSVD_3 : 1;
        uint32 INTE : 1;
        uint32 INPE : 1;
        uint32 INPP : 1;
        uint32 RSVD_23_7 : 17;
        uint32 INTF : 1;
        uint32 RSVD_31_25 : 7;
    } EWDT_CS;


    struct
    {
        uint32 COMPH : 32;
    } EWDT_COMPH;


    struct
    {
        uint32 COMPL : 32;
    } EWDT_COMPL;


    struct
    {
        uint32 CNT : 32;
    } EWDT_CNT;

};

struct Reg_Ewdt_W
{

    uint32 zResverd0x0;

    uint32 EWDT_PARAM;

    uint32 EWDT_CS;

    uint32 EWDT_COMPH;

    uint32 EWDT_COMPL;

    uint32 EWDT_CNT;
};

typedef volatile struct Reg_Ewdt_Bf Reg_Ewdt_BfType;
typedef volatile struct Reg_Ewdt_W Reg_Ewdt_WType;

struct Reg_Flash_Bf
{

    struct
    {
        uint32 FAIL : 1;
        uint32 RSVD_1 : 1;
        uint32 CMDABT : 1;
        uint32 RSVD_4_3 : 2;
        uint32 ACCERR : 1;
        uint32 PREABT : 1;
        uint32 CCIF : 1;
        uint32 RSVD_10_8 : 3;
        uint32 CMDWRF : 1;
        uint32 RSVD_15_12 : 4;
        uint32 DFDIF : 1;
        uint32 SFDIF : 1;
        uint32 RSVD_29_18 : 12;
        uint32 DBG_ERSALL_DIS : 1;
        uint32 FSEC : 1;
    } FLASH_FSTAT;


    struct
    {
        uint32 BK_QUERY : 1;
        uint32 RSVD_6_1 : 6;
        uint32 CCIE : 1;
        uint32 DBG_ERS_FLG : 1;
        uint32 RSVD_15_9 : 7;
        uint32 DFDIE : 1;
        uint32 SFDIE : 1;
        uint32 RSVD_31_18 : 14;
    } FLASH_FCNFG;


    struct
    {
        uint32 RWSC : 4;
        uint32 RSVD_7_4 : 4;
        uint32 LSMODE : 1;
        uint32 RSVD_15_9 : 7;
        uint32 FECCF : 1;
        uint32 RSVD_23_17 : 7;
        uint32 ABTREQ : 1;
        uint32 RSVD_31_25 : 7;
    } FLASH_FCTRL;

    uint8 zResverd0x0C[4];


    struct
    {
        uint32 CMDCODE : 8;
        uint32 RSVD_31_8 : 24;
    } FLASH_FCMD;

    uint8 zResverd0x14[4];


    struct
    {
        uint32 CMDADDR : 32;
    } FLASH_FADDR;


    struct
    {
        uint32 CMDADDRE : 32;
    } FLASH_FADDR_END;


    struct
    {
        uint32 CMDDATA0 : 32;
    } FLASH_FDATA0;


    struct
    {
        uint32 CMDDATA1 : 32;
    } FLASH_FDATA1;


    struct
    {
        uint32 CMDDATA2 : 32;
    } FLASH_FDATA2;


    struct
    {
        uint32 CMDDATA3 : 32;
    } FLASH_FDATA3;


    struct
    {
        uint32 RSVD_3_0 : 4;
        uint32 BED_ADDR_STRT : 28;
    } FLASH_BED_ADDR_STRT;


    struct
    {
        uint32 RSVD_3_0 : 4;
        uint32 BED_ADDR_END : 28;
    } FLASH_BED_ADDR_END;


    struct
    {
        uint32 RSVD_3_0 : 4;
        uint32 ECC_IN_ADDR : 28;
    } FLASH_ECC_IN_ADDR;


    struct
    {
        uint32 ECC_9BIT : 9;
        uint32 ECC_IN_EN : 1;
        uint32 RSVD_30_10 : 21;
        uint32 LOCK : 1;
    } FLASH_ECC_IN_CTRL;


    struct
    {
        uint32 MBE_FLAG : 1;
        uint32 MBE_OVERRUN : 1;
        uint32 RSVD_3_2 : 2;
        uint32 MBE_ADDR : 28;
    } FLASH_MBE_STATE;


    struct
    {
        uint32 SBE_FLAG : 1;
        uint32 SBE_OVERRUN : 1;
        uint32 RSVD_3_2 : 2;
        uint32 SBE_ADDR : 28;
    } FLASH_SBE_STATE;

};

struct Reg_Flash_W
{

    uint32 FLASH_FSTAT;

    uint32 FLASH_FCNFG;

    uint32 FLASH_FCTRL;
    uint8 zResverd0x0C[4];


    uint32 FLASH_FCMD;
    uint8 zResverd0x14[4];

    uint32 FLASH_FADDR;

    uint32 FLASH_FADDR_END;

    uint32 FLASH_FDATA0;

    uint32 FLASH_FDATA1;

    uint32 FLASH_FDATA2;

    uint32 FLASH_FDATA3;

    uint32 FLASH_BED_ADDR_STRT;

    uint32 FLASH_BED_ADDR_END;

    uint32 FLASH_ECC_IN_ADDR;

    uint32 FLASH_ECC_IN_CTRL;

    uint32 FLASH_MBE_STATE;

    uint32 FLASH_SBE_STATE;
};

typedef volatile struct Reg_Flash_Bf Reg_Flash_BfType;
typedef volatile struct Reg_Flash_W Reg_Flash_WType;

struct Reg_Gpio_Bf
{

    struct
    {
        uint32 PDO : 32;
    } GPIOx_PDOR;


    struct
    {
        uint32 PSO : 32;
    } GPIOx_PSOR;


    struct
    {
        uint32 PCO : 32;
    } GPIOx_PCOR;


    struct
    {
        uint32 PTO : 32;
    } GPIOx_PTOR;


    struct
    {
        uint32 PDI : 32;
    } GPIOx_PDIR;


    struct
    {
        uint32 PDD : 32;
    } GPIOx_PDDR;

};

struct Reg_Gpio_W
{

    uint32 GPIOx_PDOR;

    uint32 GPIOx_PSOR;

    uint32 GPIOx_PCOR;

    uint32 GPIOx_PTOR;

    uint32 GPIOx_PDIR;

    uint32 GPIOx_PDDR;

};

typedef volatile struct Reg_Gpio_Bf Reg_Gpio_BfType;
typedef volatile struct Reg_Gpio_W Reg_Gpio_WType;

struct Reg_I2c_Bf
{

    uint32 zResverd0x00;

    struct
    {
        uint32 I2C_SUPPORT_SPEED : 2;
        uint32 DMA_SUPPORT : 1;
        uint32 TXFIFO_DEPTH : 4;
        uint32 RXFIFO_DEPTH : 4;
        uint32 RSVD_31_11 : 21;
    } I2C_PARAMETER;


    struct
    {
        uint32 MODULE_EN : 1;
        uint32 SLAVE_ACK_GENCALL : 1;
        uint32 SLAVE_NACK : 1;
        uint32 SDA_RECOVER_EN : 1;
        uint32 MASTER_ABORT : 1;
        uint32 MASTER_BUS_RECOVER_EN : 1;
        uint32 MASTER_BLK_TXFIFO : 1;
        uint32 H_MCODE : 3;
        uint32 RSVD_31_10 : 22;
    } I2C_CONFIG0;


    struct
    {
        uint32 SLAVE_MODE_DIS : 1;
        uint32 MASTER_MODE_EN : 1;
        uint32 MASTER_RESTART_EN : 1;
        uint32 SLAVE_STOP_DET_EN : 1;
        uint32 MASTER_STOP_DET_EN : 1;
        uint32 TXFIFO_EMPTY_EN : 1;
        uint32 SPEED_SEL : 2;
        uint32 HOLD_EN_RXFIFO_FULL : 1;
        uint32 SLAVE_10BIT_ADDR_SEL : 1;
        uint32 MASTER_10BIT_ADDR_SEL : 1;
        uint32 RSVD_31_11 : 21;
    } I2C_CONFIG1;


    struct
    {
        uint32 SDA_SETUP_TIMING : 8;
        uint32 RSVD_31_8 : 24;
    } I2C_SDA_SETUP_TIMING;


    struct
    {
        uint32 SDA_TX_HOLD_TIMING : 16;
        uint32 SDA_RX_HOLD_TIMING : 8;
        uint32 RSVD_31_24 : 8;
    } I2C_SDA_HOLD_TIMING;


    struct
    {
        uint32 RXFIFO_DMA_EN : 1;
        uint32 TXFIFO_DMA_EN : 1;
        uint32 DMA_TXFIFO_WATERMARK : 2;
        uint32 DMA_RXFIFO_WATERMARK : 2;
        uint32 RSVD_31_6 : 26;
    } I2C_DMA_CTRL;


    struct
    {
        uint32 I2C_CALL_IE : 1;
        uint32 I2C_TX_OVF_IE : 1;
        uint32 I2C_ERROR_ABORT_IE : 1;
        uint32 I2C_ACTIVITY_DET_IE : 1;
        uint32 I2C_STOP_DET_IE : 1;
        uint32 I2C_START_DET_IE : 1;
        uint32 RSVD_21_6 : 16;
        uint32 SLAVE_RD_REQ_IE : 1;
        uint32 RX_DONE_IE : 1;
        uint32 RX_UNDER_IE : 1;
        uint32 RX_OVF_IE : 1;
        uint32 RESTART_DET_IE : 1;
        uint32 SCL_STUCK_AT_LOW_IE : 1;
        uint32 RSVD_29_28 : 2;
        uint32 RX_FULL_IE : 1;
        uint32 TX_EMPTY_IE : 1;
    } I2C_INT_ENABLE;


    struct
    {
        uint32 DATA : 8;
        uint32 CMD_MASTER_DIRECTION : 1;
        uint32 CMD_STOP : 1;
        uint32 CMD_RESTART : 1;
        uint32 RSVD_31_11 : 21;
    } I2C_COMMAND_DATA;


    struct
    {
        uint32 DEST_ADDR : 10;
        uint32 MASTER_CMD_SEL : 2;
        uint32 RSVD_31_12 : 20;
    } I2C_DEST_ADDR;


    struct
    {
        uint32 SLV_ADDR : 10;
        uint32 RSVD_31_10 : 22;
    } I2C_SLAVE_ADDR;


    struct
    {
        uint32 STD_SCL_HCNT : 16;
        uint32 RSVD_31_16 : 16;
    } I2C_STD_SCL_HCNT;


    struct
    {
        uint32 STD_SCL_LCNT : 16;
        uint32 RSVD_31_16 : 16;
    } I2C_STD_SCL_LCNT;


    struct
    {
        uint32 FST_SCL_HCNT : 16;
        uint32 RSVD_31_16 : 16;
    } I2C_FST_SCL_HCNT;


    struct
    {
        uint32 FST_SCL_LCNT : 16;
        uint32 RSVD_31_16 : 16;
    } I2C_FST_SCL_LCNT;


    struct
    {
        uint32 HS_SCL_HCNT : 16;
        uint32 RSVD_31_16 : 16;
    } I2C_HS_SCL_HCNT;


    struct
    {
        uint32 HS_SCL_LCNT : 16;
        uint32 RSVD_31_16 : 16;
    } I2C_HS_SCL_LCNT;


    struct
    {
        uint32 RXFIFO_WATER_MARK : 2;
        uint32 RSVD_31_2 : 30;
    } I2C_RXFIFO_WATER_MARK;


    struct
    {
        uint32 TXFIFO_WATER_MARK : 2;
        uint32 RSVD_31_2 : 30;
    } I2C_TXFIFO_WATER_MARK;


    struct
    {
        uint32 TX_FIFO_CNT : 3;
        uint32 RSVD_31_3 : 29;
    } I2C_TX_FIFO_CNT;


    struct
    {
        uint32 RX_FIFO_CNT : 3;
        uint32 RSVD_31_3 : 29;
    } I2C_RX_FIFO_CNT;


    struct
    {
        uint32 FSTD_SPKLEN : 8;
        uint32 RSVD_31_8 : 24;
    } I2C_FSTD_SPKCNT;


    struct
    {
        uint32 HS_SPKLEN : 8;
        uint32 RSVD_31_8 : 24;
    } I2C_HS_SPKCNT;


    struct
    {
        uint32 GENERAL_CALL : 1;
        uint32 TXFIFO_OVERUN : 1;
        uint32 ERROR_ABORT : 1;
        uint32 ACTIVITY : 1;
        uint32 STOP_DETECT : 1;
        uint32 START_DETECT : 1;
        uint32 RSVD_21_6 : 16;
        uint32 SLAVE_READ_REQ : 1;
        uint32 RXFIFO_DONE : 1;
        uint32 RXFIFO_UNDERUN : 1;
        uint32 RXFIFO_OVERUN : 1;
        uint32 RESTART_DET : 1;
        uint32 SCL_STUCK_AT_LOW : 1;
        uint32 RSVD_29_28 : 2;
        uint32 RXFIFO_FULL : 1;
        uint32 TXFIFO_EMPTY : 1;
    } I2C_STATUS0;


    struct
    {
        uint32 MASTER_IS_ACTIVE : 1;
        uint32 SLAVE_IS_ACTIVE : 1;
        uint32 TXFIFO_EMPTY_MASTER_HOLD : 1;
        uint32 TXFIFO_EMPTY_SLAVE_HOLD : 1;
        uint32 RXFIFO_FULL_MASTER_HOLD : 1;
        uint32 RXFIFO_FULL_SLAVE_HOLD : 1;
        uint32 TXFIO_IS_NOT_FULL : 1;
        uint32 TXFIFO_IS_EMPTY : 1;
        uint32 RXFIFO_IS_NOT_EMPTY : 1;
        uint32 RXFIO_IS_FULL : 1;
        uint32 SDA_ERR_RECOVER_STUCK_LOW : 1;
        uint32 SLAVE_IS_DISABLED_UNDER_ACT : 1;
        uint32 SLAVE_RX_DATA_DISCARD : 1;
        uint32 I2C_IS_ENABLE : 1;
        uint32 RSVD_31_14 : 18;
    } I2C_STATUS1;


    struct
    {
        uint32 ERR_GEN_CALL_NO_ACK : 1;
        uint32 ERR_GEN_CALL_READ : 1;
        uint32 ERR_START_BYTE_ACK_DET : 1;
        uint32 ERR_SBYTE_NORSTRT : 1;
        uint32 ERR_H_NO_RSTRT : 1;
        uint32 ERR_H_MCODE_ACK_DET : 1;
        uint32 ERR_7BIT_ADDR_NO_ACK : 1;
        uint32 ERR_10BIT_ADDR1_NO_ACK : 1;
        uint32 ERR_10BIT_ADDR2_NO_ACK : 1;
        uint32 ERR_10BIT_READ_NO_RSTRT : 1;
        uint32 ERR_DATA_NO_ACK : 1;
        uint32 ERR_MASTER_ABRT : 1;
        uint32 ERR_MASTER_DIS : 1;
        uint32 ERR_SLAVE_ARBLOST : 1;
        uint32 ERR_MASTER_LOST : 1;
        uint32 ERR_SLAVE_READ_REQ : 1;
        uint32 ERR_SLAVE_FLUSH_TXFIFO : 1;
        uint32 ERR_SDA_LOW_TIMEOUT : 1;
        uint32 ERR_TXFIFO_FLUSH_CNT : 3;
        uint32 RSVD_31_21 : 11;
    } I2C_ERROR_STATUS;


    struct
    {
        uint32 SCL_LOW_TIMEOUT : 32;
    } I2C_SCL_LOW_TIMEOUT;


    struct
    {
        uint32 SDA_LOW_TIMEOUT : 32;
    } I2C_SDA_LOW_TIMEOUT;


    struct
    {
        uint32 CLR_ERR : 1;
        uint32 RSVD_31_1 : 31;
    } I2C_RD_CLR_ERR_STATUS;

};

struct Reg_I2c_W
{

    uint32 zResverd0x00;

    uint32 I2C_PARAMETER;

    uint32 I2C_CONFIG0;

    uint32 I2C_CONFIG1;

    uint32 I2C_SDA_SETUP_TIMING;

    uint32 I2C_SDA_HOLD_TIMING;

    uint32 I2C_DMA_CTRL;

    uint32 I2C_INT_ENABLE;

    uint32 I2C_COMMAND_DATA;

    uint32 I2C_DEST_ADDR;

    uint32 I2C_SLAVE_ADDR;

    uint32 I2C_STD_SCL_HCNT;

    uint32 I2C_STD_SCL_LCNT;

    uint32 I2C_FST_SCL_HCNT;

    uint32 I2C_FST_SCL_LCNT;

    uint32 I2C_HS_SCL_HCNT;

    uint32 I2C_HS_SCL_LCNT;

    uint32 I2C_RXFIFO_WATER_MARK;

    uint32 I2C_TXFIFO_WATER_MARK;

    uint32 I2C_TX_FIFO_CNT;

    uint32 I2C_RX_FIFO_CNT;

    uint32 I2C_FSTD_SPKCNT;

    uint32 I2C_HS_SPKCNT;

    uint32 I2C_STATUS0;

    uint32 I2C_STATUS1;

    uint32 I2C_ERROR_STATUS;

    uint32 I2C_SCL_LOW_TIMEOUT;

    uint32 I2C_SDA_LOW_TIMEOUT;

    uint32 I2C_RD_CLR_ERR_STATUS;
};

typedef volatile struct Reg_I2c_Bf Reg_I2c_BfType;
typedef volatile struct Reg_I2c_W Reg_I2c_WType;

struct Reg_I2s_Bf
{

    struct
    {
        uint32 I2S_MODULE_EN : 1;
        uint32 I2S_TE : 1;
        uint32 I2S_RE : 1;
        uint32 I2S_TXFIFO_RESET : 1;
        uint32 I2S_RXFIFO_RESET : 1;
        uint32 RSVD_31_5 : 27;
    } I2S_CONTROL;


    struct
    {
        uint32 I2S_MASTER_EN : 1;
        uint32 I2S_NUM_BCLK : 2;
        uint32 RSVD_4_3 : 2;
        uint32 I2S_NUM_BCLK_GATE : 3;
        uint32 MCK_DIV : 8;
        uint32 RSVD_31_16 : 16;
    } I2S_MASTER_CONFIG;


    struct
    {
        struct
        {
            uint32 LEFT_DATA : 32;
        } I2S_CHn_LEFT_DATA;


        struct
        {
            uint32 RIGHT_DATA : 32;
        } I2S_CHn_RIGHT_DATA;


        struct
        {
            uint32 TX_EN : 1;
            uint32 RX_EN : 1;
            uint32 TX_AUDIO_RESOLUTION : 3;
            uint32 RX_AUDIO_RESOLUTION : 3;
            uint32 RSVD_31_8 : 24;
        } I2S_CHn_CFG;


        struct
        {
            uint32 RXFIFO_AVAILABLE_IE : 1;
            uint32 RXFIFO_OVERUN_IE : 1;
            uint32 TXFIFO_EMPTY_IE : 1;
            uint32 TXFIFO_OVERUN_IE : 1;
            uint32 RXFIFO_DAF : 1;
            uint32 RXFIFO_ORF : 1;
            uint32 TXFIFO_EMPTYF : 1;
            uint32 TXFIFO_ORF : 1;
            uint32 RSVD_31_8 : 24;
        } I2S_CHn_INT_CFG;


        struct
        {
            uint32 RXFIFO_FULL_TRIG_LEV : 4;
            uint32 TXFIFO_EMPTY_TRIG_LEV : 4;
            uint32 CH_TXFIFO_RESET : 1;
            uint32 CH_RXFIFO_RESET : 1;
            uint32 RSVD_31_10 : 22;
        } I2S_CHn_TRIGGER_LEVEL_CFG;
    } I2S_CHANNEL_REG[4];


    struct
    {
        uint32 CYCLE_TX_DATA : 32;
    } I2S_CYCLE_TX_DATA;


    struct
    {
        uint32 CYCLE_TX_RESET : 1;
        uint32 RSVD_31_1 : 31;
    } I2S_CYCLE_TX_RESET;


    struct
    {
        uint32 CYCLE_RX_DATA : 32;
    } I2S_CYCLE_RX_DATA;


    struct
    {
        uint32 CYCLE_RX_RESET : 1;
        uint32 RSVD_31_1 : 31;
    } I2S_CYCLE_RX_RESET;

};

struct Reg_I2s_W
{

    uint32 I2S_CONTROL;

    uint32 I2S_MASTER_CONFIG;
    struct
    {

        uint32 I2S_CHn_LEFT_DATA;

        uint32 I2S_CHn_RIGHT_DATA;

        uint32 I2S_CHn_CFG;

        uint32 I2S_CHn_INT_CFG;

        uint32 I2S_CHn_TRIGGER_LEVEL_CFG;
    } I2S_CHANNEL_REG[4];

    uint32 I2S_CYCLE_TX_DATA;

    uint32 I2S_CYCLE_TX_RESET;

    uint32 I2S_CYCLE_RX_DATA;

    uint32 I2S_CYCLE_RX_RESET;

};

typedef volatile struct Reg_I2s_Bf Reg_I2s_BfType;
typedef volatile struct Reg_I2s_W Reg_I2s_WType;

struct Reg_Mcpwm_Bf
{

    struct
    {
        uint32 CKSRC : 2;
        uint32 PSDIV : 3;
        uint32 DBGM : 2;
        uint32 RSVD_31_7 : 25;
    } MCPWM_TIMEBASE;


    struct
    {
        uint32 CNT : 16;
        uint32 RSVD_31_16 : 16;
    } MCPWM_CNTn[4];


    struct
    {
        uint32 MOD : 16;
        uint32 RSVD_31_16 : 16;
    } MCPWM_MODn[4];


    struct
    {
        uint32 DTVAL : 12;
        uint32 RSVD_31_12 : 20;
    } MCPWM_DTVALn[4];


    struct
    {
        uint32 CHOE0 : 1;
        uint32 CHOE1 : 1;
        uint32 CHOE2 : 1;
        uint32 CHOE3 : 1;
        uint32 CHOE4 : 1;
        uint32 CHOE5 : 1;
        uint32 CHOE6 : 1;
        uint32 CHOE7 : 1;
        uint32 CNTM0 : 1;
        uint32 CNTM1 : 1;
        uint32 CNTM2 : 1;
        uint32 CNTM3 : 1;
        uint32 CNTEN0 : 1;
        uint32 CNTEN1 : 1;
        uint32 CNTEN2 : 1;
        uint32 CNTEN3 : 1;
        uint32 RLDIE0 : 1;
        uint32 RLDIE1 : 1;
        uint32 RLDIE2 : 1;
        uint32 RLDIE3 : 1;
        uint32 TOIE0 : 1;
        uint32 TOIE1 : 1;
        uint32 TOIE2 : 1;
        uint32 TOIE3 : 1;
        uint32 RSVD_29_24 : 6;
        uint32 WPEN : 1;
        uint32 GLBCNTEN : 1;
    } MCPWM_GLBCR;


    struct
    {
        uint32 CH0F : 1;
        uint32 CH1F : 1;
        uint32 CH2F : 1;
        uint32 CH3F : 1;
        uint32 CH4F : 1;
        uint32 CH5F : 1;
        uint32 CH6F : 1;
        uint32 CH7F : 1;
        uint32 RLDF0 : 1;
        uint32 RLDF1 : 1;
        uint32 RLDF2 : 1;
        uint32 RLDF3 : 1;
        uint32 TOF0 : 1;
        uint32 TOF1 : 1;
        uint32 TOF2 : 1;
        uint32 TOF3 : 1;
        uint32 WPDIS : 1;
        uint32 RSVD_31_17 : 15;
    } MCPWM_GLBSR;


    struct
    {
        uint32 CPP : 1;
        uint32 RSVD_3_1 : 3;
        uint32 CHIE : 1;
        uint32 CHF : 1;
        uint32 DMA : 1;
        uint32 RSVD_31_7 : 25;
    } MCPWM_CFGn[8];


    struct
    {
        uint32 CV : 16;
        uint32 RSVD_31_16 : 16;
    } MCPWM_CVn[8];


    struct
    {
        uint32 POL0 : 1;
        uint32 POL1 : 1;
        uint32 POL2 : 1;
        uint32 POL3 : 1;
        uint32 POL4 : 1;
        uint32 POL5 : 1;
        uint32 POL6 : 1;
        uint32 POL7 : 1;
        uint32 OFFVAL0 : 1;
        uint32 OFFVAL1 : 1;
        uint32 OFFVAL2 : 1;
        uint32 OFFVAL3 : 1;
        uint32 OFFVAL4 : 1;
        uint32 OFFVAL5 : 1;
        uint32 OFFVAL6 : 1;
        uint32 OFFVAL7 : 1;
        uint32 RSVD_31_16 : 16;
    } MCPWM_OUTCR;


    struct
    {
        uint32 TRIGE0 : 1;
        uint32 TRIGE1 : 1;
        uint32 TRIGE2 : 1;
        uint32 TRIGE3 : 1;
        uint32 TRIGE4 : 1;
        uint32 TRIGE5 : 1;
        uint32 TRIGE6 : 1;
        uint32 TRIGE7 : 1;
        uint32 INITRIGE : 1;
        uint32 TRIGF : 1;
        uint32 RSVD_31_10 : 22;
    } MCPWM_OUTTRIG;


    struct
    {
        uint32 CH0OC : 1;
        uint32 CH1OC : 1;
        uint32 CH2OC : 1;
        uint32 CH3OC : 1;
        uint32 CH4OC : 1;
        uint32 CH5OC : 1;
        uint32 CH6OC : 1;
        uint32 CH7OC : 1;
        uint32 CH0OCV : 1;
        uint32 CH1OCV : 1;
        uint32 CH2OCV : 1;
        uint32 CH3OCV : 1;
        uint32 CH4OCV : 1;
        uint32 CH5OCV : 1;
        uint32 CH6OCV : 1;
        uint32 CH7OCV : 1;
        uint32 RSVD_31_16 : 16;
    } MCPWM_OUTSWCR;


    struct
    {
        uint32 FCTLEN0 : 1;
        uint32 DTEN0 : 1;
        uint32 SYNCEN0 : 1;
        uint32 ASYMEN0 : 1;
        uint32 CVSEL0 : 1;
        uint32 PEC0 : 1;
        uint32 COMB0 : 1;
        uint32 RSVD_7 : 1;
        uint32 FCTLEN1 : 1;
        uint32 DTEN1 : 1;
        uint32 SYNCEN1 : 1;
        uint32 ASYMEN1 : 1;
        uint32 CVSEL1 : 1;
        uint32 PEC1 : 1;
        uint32 COMB1 : 1;
        uint32 RSVD_15 : 1;
        uint32 FCTLEN2 : 1;
        uint32 DTEN2 : 1;
        uint32 SYNCEN2 : 1;
        uint32 ASYMEN2 : 1;
        uint32 CVSEL2 : 1;
        uint32 PEC2 : 1;
        uint32 COMB2 : 1;
        uint32 RSVD_23 : 1;
        uint32 FCTLEN3 : 1;
        uint32 DTEN3 : 1;
        uint32 SYNCEN3 : 1;
        uint32 ASYMEN3 : 1;
        uint32 CVSEL3 : 1;
        uint32 PEC3 : 1;
        uint32 COMB3 : 1;
        uint32 RSVD_31 : 1;
    } MCPWM_PCR;


    struct
    {
        uint32 FIFEN0 : 1;
        uint32 FIFEN1 : 1;
        uint32 FIFEN2 : 1;
        uint32 FIFEN3 : 1;
        uint32 FLTEN0 : 1;
        uint32 FLTEN1 : 1;
        uint32 FLTEN2 : 1;
        uint32 FLTEN3 : 1;
        uint32 FLTPOL0 : 1;
        uint32 FLTPOL1 : 1;
        uint32 FLTPOL2 : 1;
        uint32 FLTPOL3 : 1;
        uint32 FLTIE : 1;
        uint32 FLTCM : 1;
        uint32 RSVD_15_14 : 2;
        uint32 FIFVAL : 4;
        uint32 FSTATE : 1;
        uint32 RSVD_31_21 : 11;
    } MCPWM_FLTCR;


    struct
    {
        uint32 FAULTF0 : 1;
        uint32 FAULTF1 : 1;
        uint32 FAULTF2 : 1;
        uint32 FAULTF3 : 1;
        uint32 FAULTFA : 1;
        uint32 FAULTFB : 1;
        uint32 FAULTINA : 1;
        uint32 FAULTINB : 1;
        uint32 RSVD_31_8 : 24;
    } MCPWM_FLTSR;


    struct
    {
        uint32 FLTASS0 : 1;
        uint32 FLTASS1 : 1;
        uint32 FLTASS2 : 1;
        uint32 FLTASS3 : 1;
        uint32 FLTASS4 : 1;
        uint32 FLTASS5 : 1;
        uint32 FLTASS6 : 1;
        uint32 FLTASS7 : 1;
        uint32 RSVD_31_8 : 24;
    } MCPWM_FLTASS;


    struct
    {
        uint32 FLTBSS0 : 1;
        uint32 FLTBSS1 : 1;
        uint32 FLTBSS2 : 1;
        uint32 FLTBSS3 : 1;
        uint32 FLTBSS4 : 1;
        uint32 FLTBSS5 : 1;
        uint32 FLTBSS6 : 1;
        uint32 FLTBSS7 : 1;
        uint32 RSVD_31_8 : 24;
    } MCPWM_FLTBSS;


    struct
    {
        uint32 SWTRIG : 1;
        uint32 SYNCOSWC : 1;
        uint32 SWWRBUF : 1;
        uint32 SWRSTCNT : 1;
        uint32 RSVD_31_4 : 28;
    } MCPWM_SYNC;


    struct
    {
        uint32 CPWMFCR0 : 1;
        uint32 CPWMFCR1 : 1;
        uint32 CPWMFCR2 : 1;
        uint32 CPWMFCR3 : 1;
        uint32 CPWMHCR0 : 1;
        uint32 CPWMHCR1 : 1;
        uint32 CPWMHCR2 : 1;
        uint32 CPWMHCR3 : 1;
        uint32 LOADEN0 : 1;
        uint32 LOADEN1 : 1;
        uint32 LOADEN2 : 1;
        uint32 LOADEN3 : 1;
        uint32 RSVD_31_12 : 20;
    } MCPWM_RELOAD;


    struct
    {
        uint32 LDFREQ0 : 5;
        uint32 RSVD_7_5 : 3;
        uint32 LDFREQ1 : 5;
        uint32 RSVD_15_13 : 3;
        uint32 LDFREQ2 : 5;
        uint32 RSVD_23_21 : 3;
        uint32 LDFREQ3 : 5;
        uint32 RSVD_31_29 : 3;
    } MCPWM_LDFREQ;

    uint8 zResverd0x0A8[88];


    struct
    {
        uint32 MOD_DITHER : 5;
        uint32 RSVD_31_5 : 27;
    } MCPWM_MODn_DITHER[4];


    struct
    {
        uint32 CV_DITHER : 5;
        uint32 RSVD_31_5 : 27;
    } MCPWM_CVn_DITHER[8];

};

struct Reg_Mcpwm_W
{

    uint32 MCPWM_TIMEBASE;

    uint32 MCPWM_CNTn[4];

    uint32 MCPWM_MODn[4];

    uint32 MCPWM_DTVALn[4];

    uint32 MCPWM_GLBCR;

    uint32 MCPWM_GLBSR;

    uint32 MCPWM_CFGn[8];

    uint32 MCPWM_CVn[8];

    uint32 MCPWM_OUTCR;

    uint32 MCPWM_OUTTRIG;

    uint32 MCPWM_OUTSWCR;

    uint32 MCPWM_PCR;

    uint32 MCPWM_FLTCR;

    uint32 MCPWM_FLTSR;

    uint32 MCPWM_FLTASS;

    uint32 MCPWM_FLTBSS;

    uint32 MCPWM_SYNC;

    uint32 MCPWM_RELOAD;

    uint32 MCPWM_LDFREQ;
    uint8 zResverd0x0A8[88];


    uint32 MCPWM_MODn_DITHER[4];

    uint32 MCPWM_CVn_DITHER[8];
};

typedef volatile struct Reg_Mcpwm_Bf Reg_Mcpwm_BfType;
typedef volatile struct Reg_Mcpwm_W Reg_Mcpwm_WType;

struct Reg_Parcc_Bf
{

    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_15_2 : 14;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_WDOG;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_EWDT;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_STIM;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_TIM0;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_TIM1;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_TIM2;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_TIM3;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_MCPWM0;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_MCPWM1;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_TDG0;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_TDG1;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_CAN0;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_CAN1;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_CAN2;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_CAN3;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_CAN4;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_CAN5;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_CAN6;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_CAN7;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_UART0;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_UART1;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_UART2;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_UART3;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_UART4;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_UART5;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_SPI0;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_SPI1;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_SPI2;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_SPI3;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_I2C0;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_I2C1;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_I2S0;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_I2S1;


    uint32 zResverd0x84;

    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_ADC0;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_ADC1;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_15_2 : 14;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_CMP0;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_15_2 : 14;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_CRC;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_15_2 : 14;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_AES;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_15_2 : 14;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_TRNG;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 RSVD_16 : 1;
        uint32 RSVD_19_17 : 3;
        uint32 RSVD_20 : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_FLASH;


    uint32 zResverd0xA4;

    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_15_2 : 14;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_DMA;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_15_2 : 14;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_DMAMUX;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_PORTA;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_PORTB;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_PORTC;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_PORTD;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_3_2 : 2;
        uint32 CLKMUX : 3;
        uint32 RSVD_7 : 1;
        uint32 CLKDIV : 4;
        uint32 RSVD_15_12 : 4;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_PORTE;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_15_2 : 14;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_TMU;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_15_2 : 14;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_REGFILE;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_15_2 : 14;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_SMPU;


    struct
    {
        uint32 PCKMD : 2;
        uint32 RSVD_15_2 : 14;
        uint32 PWLK : 1;
        uint32 RSVD_19_17 : 3;
        uint32 PSUPVACEN : 1;
        uint32 PRSTB : 1;
        uint32 RSVD_23_22 : 2;
        uint32 PPR : 1;
        uint32 PCLKMUXPR : 1;
        uint32 PCLKDIVPR : 1;
        uint32 PSUPVACPR : 1;
        uint32 RSVD_30_28 : 3;
        uint32 LOCK : 1;
    } PARCC_GPIO;

};

struct Reg_Parcc_W
{

    uint32 PARCC_WDOG;

    uint32 PARCC_EWDT;

    uint32 PARCC_STIM;

    uint32 PARCC_TIM0;

    uint32 PARCC_TIM1;

    uint32 PARCC_TIM2;

    uint32 PARCC_TIM3;

    uint32 PARCC_MCPWM0;

    uint32 PARCC_MCPWM1;

    uint32 PARCC_TDG0;

    uint32 PARCC_TDG1;

    uint32 PARCC_CAN0;

    uint32 PARCC_CAN1;

    uint32 PARCC_CAN2;

    uint32 PARCC_CAN3;

    uint32 PARCC_CAN4;

    uint32 PARCC_CAN5;

    uint32 PARCC_CAN6;

    uint32 PARCC_CAN7;

    uint32 PARCC_UART0;

    uint32 PARCC_UART1;

    uint32 PARCC_UART2;

    uint32 PARCC_UART3;

    uint32 PARCC_UART4;

    uint32 PARCC_UART5;

    uint32 PARCC_SPI0;

    uint32 PARCC_SPI1;

    uint32 PARCC_SPI2;

    uint32 PARCC_SPI3;

    uint32 PARCC_I2C0;

    uint32 PARCC_I2C1;

    uint32 PARCC_I2S0;

    uint32 PARCC_I2S1;

    uint32 zResverd0x84;

    uint32 PARCC_ADC0;

    uint32 PARCC_ADC1;

    uint32 PARCC_CMP0;

    uint32 PARCC_CRC;

    uint32 PARCC_AES;

    uint32 PARCC_TRNG;

    uint32 PARCC_FLASH;

    uint32 zResverd0xA4;

    uint32 PARCC_DMA;

    uint32 PARCC_DMAMUX;

    uint32 PARCC_PORTA;

    uint32 PARCC_PORTB;

    uint32 PARCC_PORTC;

    uint32 PARCC_PORTD;

    uint32 PARCC_PORTE;

    uint32 PARCC_TMU;

    uint32 PARCC_REGFILE;

    uint32 PARCC_SMPU;

    uint32 PARCC_GPIO;
};

typedef volatile struct Reg_Parcc_Bf Reg_Parcc_BfType;
typedef volatile struct Reg_Parcc_W Reg_Parcc_WType;

struct Reg_Pmu_Bf
{

    struct
    {
        uint32 RSVD_30_0 : 31;
        uint32 LOCK : 1;
    } PMU_LOCK;


    struct
    {
        uint32 LPO_CLK_DIS : 1;
        uint32 RSVD_1 : 1;
        uint32 LPO_CLK_READY : 1;
        uint32 RSVD_31_3 : 29;
    } PMU_LPO_32K_CFG;

    uint8 zResverd0x08[4];


    struct
    {
        uint32 ISO_CLR : 1;
        uint32 RSVD_31_1 : 31;
    } PMU_ISO_CLR;


    struct
    {
        uint32 VDD_LVD_LP_EN : 1;
        uint32 VDD_LVD_ACT_EN : 1;
        uint32 VDD_LVD_IE : 1;
        uint32 VDD_LVD_RE : 1;
        uint32 VDD_LVW_EN : 1;
        uint32 VDD_LVW_IE : 1;
        uint32 LVWF_VDD : 1;
        uint32 LVDF_VDD : 1;
        uint32 REF_BUF_1V_EN : 1;
        uint32 RSVD_31_9 : 23;

    } PMU_CSR;


    struct
    {
        uint32 LDO_CORE_EN : 1;
        uint32 LDO_CLOCK_EN : 1;
        uint32 LDO_FLASH_EN : 1;
        uint32 RSVD_3 : 1;
        uint32 LDO_CORE_LPEN : 1;
        uint32 LDO_CLOCK_LPEN : 1;
        uint32 LDO_FLASH_LPEN : 1;
        uint32 RSVD_31_7 : 25;
    } PMU_LDO_EN_CFG;


    struct
    {
        uint32 LVD_CORE_FLAG : 1;
        uint32 LVD_CLOCK_FLAG : 1;
        uint32 LVD_FLASH_FLAG : 1;
        uint32 RSVD_3 : 1;
        uint32 LVD_AOA_FLAG : 1;
        uint32 RSVD_31_5 : 27;
    } PMU_LDO_LVD_STATUS;


    struct
    {
        uint32 LVD_CORE_RE : 1;
        uint32 LVD_CLOCK_RE : 1;
        uint32 LVD_FLASH_RE : 1;
        uint32 RSVD_3 : 1;
        uint32 LVD_AOA_RE : 1;
        uint32 ACT_CORE_LVDE : 1;
        uint32 ACT_CLOCK_LVDE : 1;
        uint32 RSVD_8_7 : 2;
        uint32 ACT_AOA_LVDE : 1;
        uint32 LP_CORE_LVDE : 1;
        uint32 LP_CLOCK_LVDE : 1;
        uint32 RSVD_13_12 : 2;
        uint32 LP_AOA_LVDE : 1;
        uint32 RSVD_31_15 : 17;
    } PMU_LDO_LVD_CFG;

};

struct Reg_Pmu_W
{

    uint32 PMU_LOCK;

    uint32 PMU_LPO_32K_CFG;

    uint8 zResverd0x08[4];

    uint32 PMU_ISO_CLR;

    uint32 PMU_CSR;

    uint32 PMU_LDO_EN_CFG;

    uint32 PMU_LDO_LVD_STATUS;

    uint32 PMU_LDO_LVD_CFG;

};

typedef volatile struct Reg_Pmu_Bf Reg_Pmu_BfType;
typedef volatile struct Reg_Pmu_W Reg_Pmu_WType;

struct Reg_Port_Bf
{

    uint8 zResverd0x0[8];


    struct
    {
        uint32 GPWD : 32;
    } PORTx_GLBDAT;


    struct
    {
        uint32 GPWE : 32;
    } PORTx_GLBCTL;


    struct
    {
        uint32 PS : 1;
        uint32 PE : 1;
        uint32 RSVD_2 : 1;
        uint32 SRE : 1;
        uint32 PFE : 1;
        uint32 ODE : 1;
        uint32 RSVD_7_6 : 2;
        uint32 MUX : 3;
        uint32 RSVD_14_11 : 4;
        uint32 LK : 1;
        uint32 IRQC : 4;
        uint32 RSVD_22_20 : 3;
        uint32 ISF : 1;
        uint32 FLT : 5;
        uint32 RSVD_30_29 : 2;
        uint32 FLTEN : 1;
    } PORTx_PCRn[32];


    struct
    {
        uint32 ISF : 32;
    } PORTx_IRQFLG;

};

struct Reg_Port_W
{

    uint8 zResverd0x0[8];

    uint32 PORTx_GLBDAT;

    uint32 PORTx_GLBCTL;

    uint32 PORTx_PCRn[32];

    uint32 PORTx_IRQFLG;
};

typedef volatile struct Reg_Port_Bf Reg_Port_BfType;
typedef volatile struct Reg_Port_W Reg_Port_WType;

struct Reg_Regfile_Bf
{

    struct
    {
        uint32 DATA : 32;
    } REGFILE_REGn[32];

};

struct Reg_Regfile_W
{

    uint32 REGFILE_REGn[32];
};

typedef volatile struct Reg_Regfile_Bf Reg_Regfile_BfType;
typedef volatile struct Reg_Regfile_W Reg_Regfile_WType;

struct Reg_Rtc_Bf
{

    struct
    {
        uint32 CRYSTAL_EN : 1;
        uint32 CNT_CLK_SEL : 1;
        uint32 CLKOUT_SEL : 1;
        uint32 CLKOUT_PIN_EN : 1;
        uint32 SUP_EN : 1;
        uint32 SW_RST : 1;
        uint32 COUNT_EN : 1;
        uint32 OVF : 1;
        uint32 ALARM_MATCHF : 1;
        uint32 OSC_RDY : 1;
        uint32 EXTAL_32K_EN : 1;
        uint32 SECONDS_INT_FLAG : 1;
        uint32 PERIODIC_CNT_EN : 1;
        uint32 PERIODIC_MATCH_FLG : 1;
        uint32 RSVD_31_14 : 18;
    } RTC_CSR;


    struct
    {
        uint32 SECOND_INT_MUX_SEL : 3;
        uint32 OVFLOW_IE : 1;
        uint32 ALARM_IE : 1;
        uint32 SECONDS_IE : 1;
        uint32 PERIODIC_IE : 1;
        uint32 RSVD_31_7 : 25;
    } RTC_IER;


    struct
    {
        uint32 ALARM_CNT : 32;
    } RTC_ALARM_CNTR;


    struct
    {
        uint32 ONE_SECOND_CNT : 16;
        uint32 RSVD_31_16 : 16;
    } RTC_ONE_SECOND_CNTR;


    struct
    {
        uint32 MATCH_CNT : 32;
    } RTC_MATCH_CNTR;


    struct
    {
        uint32 COMP_CNT : 7;
        uint32 COMP_DIRECTION : 1;
        uint32 DLY : 8;
        uint32 CCOMP_CNT : 8;
        uint32 CDLY : 8;
    } RTC_COMPENSATIONR;


    struct
    {
        uint32 RSVD_30_0 : 31;
        uint32 LOCK : 1;
    } RTC_LOCKR;


    uint8 zResverd0x01C[4];


    struct
    {
        uint32 PERIODIC_TMR_CNT : 32;
    } RTC_PERIODIC_TMR_CNT;


    struct
    {
        uint32 PERIODIC_MATCH_CNT : 32;
    } RTC_PERIODIC_TMR_MATCH_CNT;

};

struct Reg_Rtc_W
{

    uint32 RTC_CSR;

    uint32 RTC_IER;

    uint32 RTC_ALARM_CNTR;

    uint32 RTC_ONE_SECOND_CNTR;

    uint32 RTC_MATCH_CNTR;

    uint32 RTC_COMPENSATIONR;

    uint32 RTC_LOCKR;

    uint8 zResverd0x01C[4];

    uint32 RTC_PERIODIC_TMR_CNT;

    uint32 RTC_PERIODIC_TMR_MATCH_CNT;
};

typedef volatile struct Reg_Rtc_Bf Reg_Rtc_BfType;
typedef volatile struct Reg_Rtc_W Reg_Rtc_WType;

struct Reg_Scc_Bf
{

    uint32 zResverd0x0;


    struct
    {
        uint32 CLKSPRES : 5;
        uint32 RSVD_27_5 : 23;
        uint32 DIVPRES : 3;
        uint32 RSVD_31 : 1;
    } SCC_PARAM;


    struct
    {
        uint32 DIVSLOW : 4;
        uint32 DIVBUS : 4;
        uint32 DIVCORE : 4;
        uint32 RSVD_15_12 : 4;
        uint32 SCS : 3;
        uint32 RSVD_31_19 : 13;
    } SCC_CST;


    struct
    {
        uint32 DIVSLOW : 4;
        uint32 DIVBUS : 4;
        uint32 DIVCORE : 4;
        uint32 RSVD_15_12 : 4;
        uint32 SCS : 3;
        uint32 RSVD_30_19 : 12;
        uint32 LOCK : 1;
    } SCC_CFG;


    struct
    {
        uint32 RSVD_15_0 : 16;
        uint32 CLKOUTSEL : 4;
        uint32 RSVD_31_20 : 12;
    } SCC_CLKOUTCFG;


    struct
    {
        uint32 OSCEN : 1;
        uint32 OSCSTOPEN : 1;
        uint32 RSVD_3_2 : 2;
        uint32 OSCLOCINTEN : 1;
        uint32 RSVD_8_5 : 4;
        uint32 OSCCME : 1;
        uint32 OSCCMRE : 1;
        uint32 RSVD_15_11 : 5;
        uint32 OSCRDY : 1;
        uint32 OSCSELD : 1;
        uint32 OSCLOC : 1;
        uint32 RSVD_30_19 : 12;
        uint32 LOCK : 1;
    } SCC_OSCCS;


    struct
    {
        uint32 EXCLKS : 1;
        uint32 OLMEN : 1;
        uint32 HFREQ : 1;
        uint32 RSVD_7_3 : 5;
        uint32 ITRIM : 2;
        uint32 RSVD_30_10 : 21;
        uint32 LOCK : 1;
    } SCC_OSCCFG;


    struct
    {
        uint32 FIRCEN : 1;
        uint32 FIRCSTOPEN : 1;
        uint32 RSVD_3_2 : 2;
        uint32 FIRCLOCINTEN : 1;
        uint32 RSVD_8_5 : 4;
        uint32 FIRCCME : 1;
        uint32 FIRCCMRE : 1;
        uint32 RSVD_11 : 1;
        uint32 RSVD_12 : 1;
        uint32 RSVD_15_13 : 3;
        uint32 FIRCRDY : 1;
        uint32 FIRCSELD : 1;
        uint32 FIRCLOC : 1;
        uint32 RSVD_30_19 : 12;
        uint32 LOCK : 1;
    } SCC_FIRCCS;

    uint8 zResverd0x020[8];


    struct
    {
        uint32 SPLLEN : 1;
        uint32 SPLLSTOPEN : 1;
        uint32 RSVD_3_2 : 2;
        uint32 RSVD_4 : 1;
        uint32 RSVD_8_5 : 4;
        uint32 RDYEN : 1;
        uint32 RSVD_10 : 1;
        uint32 RSVD_11 : 1;
        uint32 LOCKWIN : 2;
        uint32 RSVD_15_14 : 2;
        uint32 SPLLRDY : 1;
        uint32 SPLLSELD : 1;
        uint32 RSVD_18 : 1;
        uint32 RSVD_24_19 : 6;
        uint32 OUTEN : 1;
        uint32 RSVD_30_26 : 5;
        uint32 LOCK : 1;
    } SCC_SPLLCS;


    struct
    {
        uint32 PREDIV : 2;
        uint32 RSVD_3_2 : 2;
        uint32 FBPRESEN : 1;
        uint32 REFCKS : 1;
        uint32 RSVD_7_6 : 2;
        uint32 MULT : 8;
        uint32 POSTDIV : 3;
        uint32 RSVD_30_19 : 12;
        uint32 LOCK : 1;
    } SCC_SPLLCFG1;


    struct
    {
        uint32 CPIR : 2;
        uint32 CPIC : 2;
        uint32 CS : 2;
        uint32 CAP : 2;
        uint32 RES : 3;
        uint32 KVCO : 1;
        uint32 VCODIV : 1;
        uint32 PFDDIEN : 1;
        uint32 CPISEL : 1;
        uint32 RSVD_15 : 1;
        uint32 RSVD_23_16 : 8;
        uint32 LDOODEN : 1;
        uint32 RSVD_30_25 : 6;
        uint32 LOCK : 1;
    } SCC_SPLLCFG2;
};

struct Reg_Scc_W
{

    uint32 zResverd0x0;

    uint32 SCC_PARAM;

    uint32 SCC_CST;

    uint32 SCC_CFG;

    uint32 SCC_CLKOUTCFG;

    uint32 SCC_OSCCS;

    uint32 SCC_OSCCFG;

    uint32 SCC_FIRCCS;
    uint8 zResverd0x020[8];

    uint32 SCC_SPLLCS;

    uint32 SCC_SPLLCFG1;

    uint32 SCC_SPLLCFG2;
};

typedef volatile struct Reg_Scc_Bf Reg_Scc_BfType;
typedef volatile struct Reg_Scc_W Reg_Scc_WType;

struct Reg_Scm_Bf
{

    struct
    {
        uint32 RSVD_3_0 : 4;
        uint32 CLKOUTSEL : 2;
        uint32 RSVD_7_6 : 2;
        uint32 CLKOUTDIV : 3;
        uint32 CLKOUTEN : 1;
        uint32 RSVD_31_12 : 20;
    } SCM_CHIPCTL;


    struct
    {
        uint32 SWTRIG0 : 1;
        uint32 SWTRIG1 : 1;
        uint32 SWTRIG2 : 1;
        uint32 SWTRIG3 : 1;
        uint32 SRAML_READ_BUFF_EN : 1;
        uint32 SRAMU_READ_BUFF_EN : 1;
        uint32 XBAR_ROUND_ROBIN : 1;
        uint32 RSVD_7 : 1;
        uint32 RSVD_8 : 1;
        uint32 RSVD_9 : 1;
        uint32 RSVD_10 : 1;
        uint32 CCACHE_CLR : 1;
        uint32 CCACHE_PARITY_MISS_EN : 1;
        uint32 CCACHE_PARITY_FAULT_EN : 1;
        uint32 CACHE_DIS : 1;
        uint32 RSVD_15 : 1;
        uint32 CCACHE_BE_INT_EN : 1;
        uint32 RSVD_23_17 : 7;
        uint32 FPU_INEXACT_INT_EN : 1;
        uint32 FPU_OVERFLOW_INT_EN : 1;
        uint32 FPU_UNDERFLOW_INT_EN : 1;
        uint32 FPU_INVALIDOP_INT_EN : 1;
        uint32 FPU_DIVZERO_INT_EN : 1;
        uint32 FPU_DENORMALIN_INT_EN : 1;
        uint32 RSVD_31_30 : 2;
    } SCM_MISCCTL1;

    uint8 zResverd0x08[32];


    struct
    {
        uint32 RSVD_7_0 : 8;
        uint32 MCPWM0_TCLK_SEL : 2;
        uint32 MCPWM1_TCLK_SEL : 2;
        uint32 TIM0_TCLK_SEL : 2;
        uint32 TIM1_TCLK_SEL : 2;
        uint32 TIM2_TCLK_SEL : 2;
        uint32 TIM3_TCLK_SEL : 2;
        uint32 RSVD_23_20 : 4;
        uint32 ADC0_CH8_SEL : 1;
        uint32 ADC0_CH9_SEL : 1;
        uint32 ADC1_CH14_SEL : 1;
        uint32 ADC1_CH15_SEL : 1;
        uint32 RSVD_31_28 : 4;
    } SCM_MISCCTL2;

    uint8 zResverd0x02C[20];


    struct
    {
        uint32 RSVD_14_0 : 15;
        uint32 RSVD_15 : 1;
        uint32 CCACHE_BE_FLAG : 8;
        uint32 FPU_INEXACT_FLAG : 1;
        uint32 FPU_OVERFLOW_FLAG : 1;
        uint32 FPU_UNDERFLOW_FLAG : 1;
        uint32 FPU_INVALIDOP_FLAG : 1;
        uint32 FPU_DIVZERO_FLAG : 1;
        uint32 FPU_DENORMALIN_FLAG : 1;
        uint32 RSVD_31_30 : 2;
    } SCM_MISCSTAT1;


    struct
    {
        uint32 CACHE_BE_ADDR : 32;
    } SCM_MISCDATA1;


    struct
    {
        uint32 CACHE_BE_DATA : 32;
    } SCM_MISCDATA2;

    uint8 zResverd0x04C[180];


    struct
    {
        uint32 CCACHE_DIS_IFR : 1;
        uint32 FPU_DIS : 1;
        uint32 RSVD_31_2 : 30;
    } SCM_CHIPOPT;


    struct
    {
        uint32 RSVD_23_0 : 24;
        uint32 PFSIZE : 4;
        uint32 DFSIZE : 4;
    } SCM_FLSCFG;


    struct
    {
        uint32 CACHESIZE : 4;
        uint32 RSVD_27_4 : 24;
        uint32 RAMSIZE : 4;
    } SCM_RAMCFG;

    uint8 zResverd0x010C[16];


    struct
    {
        uint32 MEMSIZE_ID : 4;
        uint32 SERIES_ID : 3;
        uint32 SUBFAMILY_ID : 5;
        uint32 FAMILY_ID : 4;
        uint32 REV_ID : 4;
        uint32 FEATURE_ID : 7;
        uint32 PACKAGE_ID : 5;
    } SCM_DEVID;


    struct
    {
        uint32 UID_31_0 : 32;
    } SCM_UNIQUE0;


    struct
    {
        uint32 UID_63_32 : 32;
    } SCM_UNIQUE1;


    struct
    {
        uint32 UID_95_64 : 32;
    } SCM_UNIQUE2;


    struct
    {
        uint32 UID_127_96 : 32;
    } SCM_UNIQUE3;

};

struct Reg_Scm_W
{

    uint32 SCM_CHIPCTL;

    uint32 SCM_MISCCTL1;
    uint8 zResverd0x08[32];


    uint32 SCM_MISCCTL2;
    uint8 zResverd0x02C[20];


    uint32 SCM_MISCSTAT1;

    uint32 SCM_MISCDATA1;

    uint32 SCM_MISCDATA2;
    uint8 zResverd0x04C[180];


    uint32 SCM_CHIPOPT;

    uint32 SCM_FLSCFG;

    uint32 SCM_RAMCFG;
    uint8 zResverd0x010C[16];


    uint32 SCM_DEVID;

    uint32 SCM_UNIQUE0;

    uint32 SCM_UNIQUE1;

    uint32 SCM_UNIQUE2;

    uint32 SCM_UNIQUE3;
};

typedef volatile struct Reg_Scm_Bf Reg_Scm_BfType;
typedef volatile struct Reg_Scm_W Reg_Scm_WType;

struct Reg_Seru_Bf
{

    uint32 zResverd0x0;

    struct
    {
        uint32 PARAM : 32;
    } SERU_PARAM;


    struct
    {
        uint32 CRPAR_INT_EN : 1;
        uint32 RSVD_3_1 : 3;
        uint32 EOUT_PS : 1;
        uint32 EOUT0_IO_EN : 1;
        uint32 EOUT1_IO_EN : 1;
        uint32 FFI_EN : 1;
        uint32 CFG_MODE : 1;
        uint32 RSVD_31_9 : 23;
    } SERU_CSR;


    struct
    {
        uint32 S_CRPAR_ERR : 1;
        uint32 RSVD_31_1 : 31;
    } SERU_INTF;


    struct
    {
        uint32 KEY : 32;
    } SERU_CFG_KEY;


    struct
    {
        uint32 CH_FFI_6_0 : 7;
        uint32 RSVD_7 : 1;
        uint32 CH_FFI_14_8 : 7;
        uint32 RSVD_15 : 1;
        uint32 CH_FFI_16 : 1;
        uint32 RSVD_31_17 : 15;
    } SERU_CH_FFI;


    struct
    {
        uint32 SWERR_CH0 : 1;
        uint32 SWERR_CH1 : 1;
        uint32 SWERR_CH2 : 1;
        uint32 RSVD_31_3 : 29;
    } SERU_SWERR_GNT;


    struct
    {
        uint32 CH_FLAG_6_0 : 7;
        uint32 RSVD_7 : 1;
        uint32 CH_FLAG_14_8 : 7;
        uint32 RSVD_15 : 1;
        uint32 CH_FLAG_16 : 1;
        uint32 RSVD_31_17 : 15;
    } SERU_CH_FLAG;


    struct
    {
        uint32 CH_EN : 1;
        uint32 CH_INT_CFG : 1;
        uint32 CH_INT_TYP : 1;
        uint32 CH_EOUT_CFG : 1;
        uint32 CH_RESET_CFG : 1;
        uint32 CH_RESET_TYP : 1;
        uint32 CH_RESET_DLY : 2;
        uint32 CH_FLAG : 1;
        uint32 RSVD_31_9 : 23;
    } SERU_CFG_CHn[17];

};

struct Reg_Seru_W
{

    uint32 zResverd0x0;

    uint32 SERU_PARAM;

    uint32 SERU_CSR;

    uint32 SERU_INTF;

    uint32 SERU_CFG_KEY;

    uint32 SERU_CH_FFI;

    uint32 SERU_SWERR_GNT;

    uint32 SERU_CH_FLAG;

    uint32 SERU_CFG_CHn[17];
};

typedef volatile struct Reg_Seru_Bf Reg_Seru_BfType;
typedef volatile struct Reg_Seru_W Reg_Seru_WType;

struct Reg_Smpu_Bf
{

    uint32 zResverd0x00;

    struct
    {
        uint32 S0ERR : 1;
        uint32 S1ERR : 1;
        uint32 S2ERR : 1;
        uint32 RSVD_3 : 1;
        uint32 RSVD_7_4 : 4;
        uint32 GLBEN : 1;
        uint32 RSVD_31_9 : 23;
    } SMPU_CS;

    uint8 zResverd0x08[8];


    struct
    {
        uint32 EADDR : 32;
    } SMPU_Sn_EA[3];

    uint8 zResverd0x01C[20];


    struct
    {
        uint32 EMRC : 16;
        uint32 RSVD_23_16 : 8;
        uint32 EMN : 4;
        uint32 EATTR : 1;
        uint32 EUS : 1;
        uint32 RSVD_30 : 1;
        uint32 ERW : 1;
    } SMPU_Sn_ES[3];

    uint8 zResverd0x03C[196];
    struct
    {

        struct
        {
            uint32 RSVD_4_0 : 5;
            uint32 SADDR : 27;
        } SMPU_MRCn_W0;


        struct
        {
            uint32 RSVD_4_0 : 5;
            uint32 EADDR : 27;
        } SMPU_MRCn_W1;


        struct
        {
            uint32 M0UX : 1;
            uint32 M0UW : 1;
            uint32 M0UR : 1;
            uint32 M0SM : 2;
            uint32 RSVD_5 : 1;
            uint32 M1UX : 1;
            uint32 M1UW : 1;
            uint32 M1UR : 1;
            uint32 M1SM : 2;
            uint32 RSVD_11 : 1;
            uint32 M2UX : 1;
            uint32 M2UW : 1;
            uint32 M2UR : 1;
            uint32 M2SM : 2;
            uint32 RSVD_31_17 : 15;
        } SMPU_MRCn_W2;


        struct
        {
            uint32 RSVD_15_0 : 16;
            uint32 EN : 1;
            uint32 RSVD_31_17 : 15;
        } SMPU_MRCn_W3;
    } SMPU_MRCn_W[16];
};

struct Reg_Smpu_W
{

    uint32 zResverd0x00;

    uint32 SMPU_CS;
    uint8 zResverd0x08[8];


    uint32 SMPU_Sn_EA[3];
    uint8 zResverd0x01C[20];


    uint32 SMPU_Sn_ES[3];
    uint8 zResverd0x03C[196];
    struct
    {

        uint32 SMPU_MRCn_W0;

        uint32 SMPU_MRCn_W1;

        uint32 SMPU_MRCn_W2;

        uint32 SMPU_MRCn_W3;
    } SMPU_MRCn_W[16];
};

typedef volatile struct Reg_Smpu_Bf Reg_Smpu_BfType;
typedef volatile struct Reg_Smpu_W Reg_Smpu_WType;

struct Reg_Spi_Bf
{

    struct
    {
        uint32 RSVD_5_0 : 6;
        uint32 SCPH : 1;
        uint32 SCPOL : 1;
        uint32 TMOD : 2;
        uint32 RSVD_10 : 1;
        uint32 RSVD_11 : 1;
        uint32 RSVD_15_12 : 4;
        uint32 DFS_32 : 5;
        uint32 MST_MODE : 1;
        uint32 RSVD_22 : 1;
        uint32 RSVD_23 : 1;
        uint32 RSVD_24 : 1;
        uint32 RSVD_31_25 : 7;
    } SPI_CTRLR0;


    struct
    {
        uint32 NDF : 16;
        uint32 RSVD_31_16 : 16;
    } SPI_CTRLR1;


    struct
    {
        uint32 SPI_EN : 1;
        uint32 RSVD_15_1 : 15;
        uint32 SER : 2;
        uint32 RSVD_31_18 : 14;
    } SPI_SSENR;


    struct
    {
        uint32 SCKDV : 16;
        uint32 RSVD_31_16 : 16;
    } SPI_BAUDR;


    struct
    {
        uint32 TFT : 2;
        uint32 RSVD_15_2 : 14;
        uint32 RFT : 2;
        uint32 RSVD_31_18 : 14;
    } SPI_FTLR;


    struct
    {
        uint32 TXTFL : 3;
        uint32 RSVD_15_3 : 13;
        uint32 RXTFL : 3;
        uint32 RSVD_31_19 : 13;
    } SPI_FLR;


    struct
    {
        uint32 BUSY : 1;
        uint32 TFNF : 1;
        uint32 TFE : 1;
        uint32 RFNE : 1;
        uint32 RFF : 1;
        uint32 TXE : 1;
        uint32 RSVD_31_6 : 26;
    } SPI_SR;


    struct
    {
        uint32 TXEIE : 1;
        uint32 TXOIE : 1;
        uint32 RXUIE : 1;
        uint32 RXOIE : 1;
        uint32 RXFIE : 1;
        uint32 RSVD_31_5 : 27;
    } SPI_IER;


    struct
    {
        uint32 TXEIS : 1;
        uint32 TXOIS : 1;
        uint32 RXUIS : 1;
        uint32 RXOIS : 1;
        uint32 RXFIS : 1;
        uint32 RSVD_15_5 : 11;
        uint32 TXEIR : 1;
        uint32 TXOIR : 1;
        uint32 RXUIR : 1;
        uint32 RXOIR : 1;
        uint32 RXFIR : 1;
        uint32 RSVD_31_21 : 11;
    } SPI_ISR;


    struct
    {
        uint32 TXOICR : 1;
        uint32 RSVD_31_1 : 31;
    } SPI_TXOICR;


    struct
    {
        uint32 RXOICR : 1;
        uint32 RSVD_31_1 : 31;
    } SPI_RXOICR;


    struct
    {
        uint32 RXUICR : 1;
        uint32 RSVD_31_1 : 31;
    } SPI_RXUICR;

    uint8 zResverd0x030[4];


    struct
    {
        uint32 ICR : 1;
        uint32 RSVD_31_1 : 31;
    } SPI_ICR;


    struct
    {
        uint32 RDMAE : 1;
        uint32 TDMAE : 1;
        uint32 RSVD_31_2 : 30;
    } SPI_DMACR;


    struct
    {
        uint32 DMATDL : 2;
        uint32 RSVD_31_2 : 30;
    } SPI_DMATDLR;


    struct
    {
        uint32 DMARDL : 2;
        uint32 RSVD_31_2 : 30;
    } SPI_DMARDLR;

    uint8 zResverd0x044[28];


    struct
    {
        uint32 DR : 32;
    } SPI_DR_LOW;

    uint8 zResverd0x064[136];


    struct
    {
        uint32 DR : 32;
    } SPI_DR_HIGH;

};

struct Reg_Spi_W
{

    uint32 SPI_CTRLR0;

    uint32 SPI_CTRLR1;

    uint32 SPI_SSENR;

    uint32 SPI_BAUDR;

    uint32 SPI_FTLR;

    uint32 SPI_FLR;

    uint32 SPI_SR;

    uint32 SPI_IER;

    uint32 SPI_ISR;

    uint32 SPI_TXOICR;

    uint32 SPI_RXOICR;

    uint32 SPI_RXUICR;
    uint8 zResverd0x030[4];


    uint32 SPI_ICR;

    uint32 SPI_DMACR;

    uint32 SPI_DMATDLR;

    uint32 SPI_DMARDLR;

    uint8 zResverd0x044[28];


    uint32 SPI_DR_LOW;
    uint8 zResverd0x064[136];


    uint32 SPI_DR_HIGH;
};

typedef volatile struct Reg_Spi_Bf Reg_Spi_BfType;
typedef volatile struct Reg_Spi_W Reg_Spi_WType;

struct Reg_Srmc_Bf
{

    uint32 zResverd0x00;

    struct
    {
        uint32 EWAKEUP : 1;
        uint32 ELVD : 1;
        uint32 ELOC : 1;
        uint32 RSVD_3 : 1;
        uint32 RSVD_4 : 1;
        uint32 EWDOG : 1;
        uint32 EPIN : 1;
        uint32 EPOR : 1;
        uint32 RSVD_8 : 1;
        uint32 ELOCKUP : 1;
        uint32 ESW : 1;
        uint32 EADM_AP : 1;
        uint32 RSVD_12 : 1;
        uint32 ESACKERR : 1;
        uint32 RSVD_15_14 : 2;
        uint32 ESTB : 1;
        uint32 RSVD_31_17 : 15;
    } SRMC_PARAM;


    struct
    {
        uint32 WAKEUP : 1;
        uint32 LVD : 1;
        uint32 LOC : 1;
        uint32 RSVD_4_3 : 2;
        uint32 WDOG : 1;
        uint32 PIN : 1;
        uint32 POR : 1;
        uint32 RSVD_8 : 1;
        uint32 LOCKUP : 1;
        uint32 SW : 1;
        uint32 ADM_AP : 1;
        uint32 SERU_COLD : 1;
        uint32 SERU_SYS : 1;
        uint32 RSVD_14 : 1;
        uint32 SACKERR : 1;
        uint32 RSVD_31_16 : 16;
    } SRMC_SRS;


    struct
    {
        uint32 RSTFLTSRW : 2;
        uint32 RSTFLTSS : 1;
        uint32 RSVD_7_3 : 5;
        uint32 RSTFLTSEL : 5;
        uint32 RSVD_30_13 : 18;
        uint32 LOCKUP_RST_EN : 1;
    } SRMC_CTRL;

    uint8 zResverd0x010[8];


    struct
    {
        uint32 SWAKEUP : 1;
        uint32 SLVD : 1;
        uint32 SLOC : 1;
        uint32 RSVD_4_3 : 2;
        uint32 SWDOG : 1;
        uint32 SPIN : 1;
        uint32 SPOR : 1;
        uint32 RSVD_8 : 1;
        uint32 SLOCKUP : 1;
        uint32 SSW : 1;
        uint32 SADM_AP : 1;
        uint32 SSERU_COLD : 1;
        uint32 SSERU_SYS : 1;
        uint32 RSVD_14 : 1;
        uint32 SSACKERR : 1;
        uint32 RSVD_31_16 : 16;
    } SRMC_SSRS;


    struct
    {
        uint32 DELAY : 2;
        uint32 LOC : 1;
        uint32 RSVD_4_3 : 2;
        uint32 WDOG : 1;
        uint32 PIN : 1;
        uint32 GIE : 1;
        uint32 RSVD_8 : 1;
        uint32 LOCKUP : 1;
        uint32 SW : 1;
        uint32 RSVD_11 : 1;
        uint32 SERU_COLD : 1;
        uint32 SERU_SYS : 1;
        uint32 RSVD_14 : 1;
        uint32 SACKERR : 1;
        uint32 RSVD_31_16 : 16;
    } SRMC_SRIE;


    struct
    {
        uint32 APD : 1;
        uint32 RSVD_31_1 : 31;
    } SRMC_PMPORT;


    struct
    {
        uint32 DSMC : 2;
        uint32 RSVD_7_2 : 6;
        uint32 DSMACKTMO : 8;
        uint32 RSVD_31_16 : 16;
    } SRMC_PMCTRL;


    struct
    {
        uint32 PMSTAT : 4;
        uint32 RSVD_7_4 : 4;
        uint32 DSMABORT : 1;
        uint32 RSVD_31_9 : 23;
    } SRMC_PMSTAT;


    struct
    {
        uint32 WUPSRC_EN2_0 : 3;
        uint32 RSVD_3 : 1;
        uint32 WUPSRC_EN15_4 : 12;
        uint32 WUPSRC_PL2_0 : 3;
        uint32 RSVD_19 : 1;
        uint32 WUPSRC_PL14_4 : 11;
        uint32 RSVD_31 : 1;
    } SRMC_DSMWUPC1;


    struct
    {
        uint32 WUPSRC_EN16 : 1;
        uint32 RSVD_31_1 : 31;
    } SRMC_DSMWUPC2;


    struct
    {
        uint32 WUPS_2_0 : 3;
        uint32 RSVD_3 : 1;
        uint32 WUPS_16_4 : 13;
        uint32 RSVD_31_17 : 15;
    } SRMC_DSMWUPS;

};

struct Reg_Srmc_W
{

    uint32 zResverd0x00;

    uint32 SRMC_PARAM;

    uint32 SRMC_SRS;

    uint32 SRMC_CTRL;
    uint8 zResverd0x010[8];


    uint32 SRMC_SSRS;

    uint32 SRMC_SRIE;

    uint32 SRMC_PMPORT;

    uint32 SRMC_PMCTRL;

    uint32 SRMC_PMSTAT;

    uint32 SRMC_DSMWUPC1;

    uint32 SRMC_DSMWUPC2;

    uint32 SRMC_DSMWUPS;
};

typedef volatile struct Reg_Srmc_Bf Reg_Srmc_BfType;
typedef volatile struct Reg_Srmc_W Reg_Srmc_WType;

struct Reg_Stim_Bf
{

    uint32 zResverd0x00;

    struct
    {
        uint32 CNT : 32;
    } STIM_CNTn[4];


    struct
    {
        uint32 CV : 32;
    } STIM_CVn[4];


    struct
    {
        uint32 CLKS : 2;
        uint32 PSDIV : 4;
        uint32 PSEN : 1;
        uint32 POL : 1;
        uint32 PSRC : 2;
        uint32 MODE : 1;
        uint32 RSTDIS : 1;
        uint32 DMAE : 1;
        uint32 IE : 1;
        uint32 EN : 1;
        uint32 FLAG : 1;
        uint32 RSVD_31_16 : 16;
    } STIM_SCn[4];

};

struct Reg_Stim_W
{

    uint32 zResverd0x00;

    uint32 STIM_CNTn[4];

    uint32 STIM_CVn[4];

    uint32 STIM_SCn[4];
};

typedef volatile struct Reg_Stim_Bf Reg_Stim_BfType;
typedef volatile struct Reg_Stim_W Reg_Stim_WType;

struct Reg_Tdg_Bf
{

    uint32 zResverd0x0;

    struct
    {
        uint32 DOPNUM : 4;
        uint32 CHNUM : 4;
        uint32 RSVD_31_8 : 24;
    } TDG_PARAM;


    struct
    {
        uint32 TDGEN : 1;
        uint32 RSVD_3_1 : 3;
        uint32 TRIGS : 1;
        uint32 CNTMD : 1;
        uint32 CLRMD : 1;
        uint32 RSVD_7 : 1;
        uint32 PRES : 3;
        uint32 RSVD_15_11 : 5;
        uint32 CFGUP : 1;
        uint32 SWTRG : 1;
        uint32 RSVD_19_18 : 2;
        uint32 UPMD : 2;
        uint32 RSVD_31_22 : 10;
    } TDG_CTRL1;


    struct
    {
        uint32 CDO0IE : 1;
        uint32 CDO1IE : 1;
        uint32 CDO2IE : 1;
        uint32 CDO3IE : 1;
        uint32 CDO4IE : 1;
        uint32 CDO5IE : 1;
        uint32 RSVD_7_6 : 2;
        uint32 ERRIE : 1;
        uint32 RSVD_15_9 : 7;
        uint32 CH0E : 1;
        uint32 CH1E : 1;
        uint32 CH2E : 1;
        uint32 CH3E : 1;
        uint32 CH4E : 1;
        uint32 CH5E : 1;
        uint32 RSVD_31_22 : 10;
    } TDG_CTRL2;


    struct
    {
        uint32 CDO0IF : 1;
        uint32 CDO1IF : 1;
        uint32 CDO2IF : 1;
        uint32 CDO3IF : 1;
        uint32 CDO4IF : 1;
        uint32 CDO5IF : 1;
        uint32 RSVD_7_6 : 2;
        uint32 ERRIF : 1;
        uint32 RSVD_31_9 : 23;
    } TDG_STAT;


    struct
    {
        uint32 MOD : 16;
        uint32 RSVD_31_16 : 16;
    } TDG_MOD;


    struct
    {
        uint32 CNT : 16;
        uint32 RSVD_31_16 : 16;
    } TDG_CNT;

    struct
    {

        struct
        {
            uint32 RSVD_7_0 : 8;
            uint32 DO0E : 1;
            uint32 DO1E : 1;
            uint32 DO2E : 1;
            uint32 DO3E : 1;
            uint32 DO4E : 1;
            uint32 DO5E : 1;
            uint32 DO6E : 1;
            uint32 DO7E : 1;
            uint32 RSVD_31_16 : 16;
        } TDG_CHCTRL;


        struct
        {
            uint32 DO0OFS : 16;
            uint32 RSVD_31_16 : 16;
        } TDG_CHDOOFS[8];


        struct
        {
            uint32 CDOINTDLY : 10;
            uint32 RSVD_15_10 : 6;
            uint32 LDCO : 1;
            uint32 RSVD_31_17 : 15;
        } TDG_CHCDOINTDLY;
    } TDG_CHCFG[6];
};

struct Reg_Tdg_W
{

    uint32 zResverd0x0;

    uint32 TDG_PARAM;

    uint32 TDG_CTRL1;

    uint32 TDG_CTRL2;

    uint32 TDG_STAT;

    uint32 TDG_MOD;

    uint32 TDG_CNT;

    struct
    {

        uint32 TDG_CHCTRL;

        uint32 TDG_CHDOOFS[8];

        uint32 TDG_CHCDOINTDLY;
    } TDG_CHCFG[6];
};

typedef volatile struct Reg_Tdg_Bf Reg_Tdg_BfType;
typedef volatile struct Reg_Tdg_W Reg_Tdg_WType;

struct Reg_Tim_Bf
{

    struct
    {
        uint32 CKSRC : 2;
        uint32 PSDIV : 3;
        uint32 DBGM : 2;
        uint32 RSVD_31_7 : 25;
    } TIM_TIMEBASE;


    struct
    {
        uint32 CNT : 16;
        uint32 RSVD_31_16 : 16;
    } TIM_CNT;


    struct
    {
        uint32 CNTINIT : 16;
        uint32 RSVD_31_16 : 16;
    } TIM_CNTINIT;


    struct
    {
        uint32 MOD : 16;
        uint32 RSVD_31_16 : 16;
    } TIM_MOD;


    struct
    {
        uint32 CHOE0 : 1;
        uint32 CHOE1 : 1;
        uint32 CHOE2 : 1;
        uint32 CHOE3 : 1;
        uint32 CHOE4 : 1;
        uint32 CHOE5 : 1;
        uint32 CHOE6 : 1;
        uint32 CHOE7 : 1;
        uint32 RLDIE : 1;
        uint32 TOIE : 1;
        uint32 CNTMODE : 1;
        uint32 INIT : 1;
        uint32 RSVD_31_12 : 20;
    } TIM_GLBCR;


    struct
    {
        uint32 CH0F : 1;
        uint32 CH1F : 1;
        uint32 CH2F : 1;
        uint32 CH3F : 1;
        uint32 CH4F : 1;
        uint32 CH5F : 1;
        uint32 CH6F : 1;
        uint32 CH7F : 1;
        uint32 RLDF : 1;
        uint32 TOF : 1;
        uint32 WPDIS : 1;
        uint32 RSVD_31_11 : 21;
    } TIM_GLBSR;


    struct
    {
        uint32 ELS : 2;
        uint32 CMS : 2;
        uint32 CHIE : 1;
        uint32 CHF : 1;
        uint32 DMAEN : 1;
        uint32 ICRST : 1;
        uint32 RSVD_31_8 : 24;
    } TIM_CMCn[8];


    struct
    {
        uint32 CCV : 16;
        uint32 RSVD_31_16 : 16;
    } TIM_CCVn[8];


    struct
    {
        uint32 INIT0 : 1;
        uint32 INIT1 : 1;
        uint32 INIT2 : 1;
        uint32 INIT3 : 1;
        uint32 INIT4 : 1;
        uint32 INIT5 : 1;
        uint32 INIT6 : 1;
        uint32 INIT7 : 1;
        uint32 POL0 : 1;
        uint32 POL1 : 1;
        uint32 POL2 : 1;
        uint32 POL3 : 1;
        uint32 POL4 : 1;
        uint32 POL5 : 1;
        uint32 POL6 : 1;
        uint32 POL7 : 1;
        uint32 TRIGE0 : 1;
        uint32 TRIGE1 : 1;
        uint32 TRIGE2 : 1;
        uint32 TRIGE3 : 1;
        uint32 TRIGE4 : 1;
        uint32 TRIGE5 : 1;
        uint32 TRIGE6 : 1;
        uint32 TRIGE7 : 1;
        uint32 INITRIGE : 1;
        uint32 TRIGF : 1;
        uint32 RSVD_31_26 : 6;
    } TIM_OUTCR;


    struct
    {
        uint32 CH0OC : 1;
        uint32 CH1OC : 1;
        uint32 CH2OC : 1;
        uint32 CH3OC : 1;
        uint32 CH4OC : 1;
        uint32 CH5OC : 1;
        uint32 CH6OC : 1;
        uint32 CH7OC : 1;
        uint32 CH0OCV : 1;
        uint32 CH1OCV : 1;
        uint32 CH2OCV : 1;
        uint32 CH3OCV : 1;
        uint32 CH4OCV : 1;
        uint32 CH5OCV : 1;
        uint32 CH6OCV : 1;
        uint32 CH7OCV : 1;
        uint32 RSVD_31_16 : 16;
    } TIM_OUTSWCR;


    struct
    {
        uint32 FCTLEN0 : 1;
        uint32 DTEN0 : 1;
        uint32 COMB0 : 1;
        uint32 SYNCEN0 : 1;
        uint32 DECAPEN0 : 1;
        uint32 DECAP0 : 1;
        uint32 RSVD_7_6 : 2;
        uint32 FCTLEN1 : 1;
        uint32 DTEN1 : 1;
        uint32 COMB1 : 1;
        uint32 SYNCEN1 : 1;
        uint32 DECAPEN1 : 1;
        uint32 DECAP1 : 1;
        uint32 RSVD_15_14 : 2;
        uint32 FCTLEN2 : 1;
        uint32 DTEN2 : 1;
        uint32 COMB2 : 1;
        uint32 SYNCEN2 : 1;
        uint32 DECAPEN2 : 1;
        uint32 DECAP2 : 1;
        uint32 RSVD_23_22 : 2;
        uint32 FCTLEN3 : 1;
        uint32 DTEN3 : 1;
        uint32 COMB3 : 1;
        uint32 SYNCEN3 : 1;
        uint32 DECAPEN3 : 1;
        uint32 DECAP3 : 1;
        uint32 RSVD_31_30 : 2;
    } TIM_PCR;


    struct
    {
        uint32 FILVAL0 : 4;
        uint32 FILVAL1 : 4;
        uint32 FILVAL2 : 4;
        uint32 FILVAL3 : 4;
        uint32 DTPS : 2;
        uint32 DTVAL : 6;
        uint32 RSVD_31_24 : 8;
    } TIM_FILTER;


    struct
    {
        uint32 FAULTEN0 : 1;
        uint32 FIFEN0 : 1;
        uint32 FLTPOL0 : 1;
        uint32 FAULTEN1 : 1;
        uint32 FIFEN1 : 1;
        uint32 FLTPOL1 : 1;
        uint32 FLTIE : 1;
        uint32 FLTCEN : 1;
        uint32 FLTCM : 1;
        uint32 RSVD_10_9 : 2;
        uint32 FIFVAL : 4;
        uint32 FSTATE : 1;
        uint32 RSVD_31_16 : 16;
    } TIM_FLTCR;


    struct
    {
        uint32 FAULTF0 : 1;
        uint32 FAULTF1 : 1;
        uint32 RSVD_3_2 : 2;
        uint32 FAULTF : 1;
        uint32 FAULTIN : 1;
        uint32 WPEN : 1;
        uint32 RSVD_31_7 : 25;
    } TIM_FLTSR;


    struct
    {
        uint32 SWTRIG : 1;
        uint32 RSVD_7_1 : 7;
        uint32 SYNCINIT : 1;
        uint32 SYNCOSWC : 1;
        uint32 RSVD_17_10 : 8;
        uint32 SWWRBUF : 1;
        uint32 SWRSTCNT : 1;
        uint32 RSVD_31_20 : 12;
    } TIM_SYNC;


    struct
    {
        uint32 CH0SEL : 1;
        uint32 CH1SEL : 1;
        uint32 CH2SEL : 1;
        uint32 CH3SEL : 1;
        uint32 CH4SEL : 1;
        uint32 CH5SEL : 1;
        uint32 CH6SEL : 1;
        uint32 CH7SEL : 1;
        uint32 LOADEN : 1;
        uint32 RSVD_10_9 : 2;
        uint32 HCSEL : 1;
        uint32 RSVD_15_12 : 4;
        uint32 LDFREQ : 5;
        uint32 RSVD_31_21 : 11;
    } TIM_RELOAD;


    struct
    {
        uint32 HCV : 16;
        uint32 RSVD_31_16 : 16;
    } TIM_HCV;

};

struct Reg_Tim_W
{

    uint32 TIM_TIMEBASE;

    uint32 TIM_CNT;

    uint32 TIM_CNTINIT;

    uint32 TIM_MOD;

    uint32 TIM_GLBCR;

    uint32 TIM_GLBSR;

    uint32 TIM_CMCn[8];

    uint32 TIM_CCVn[8];

    uint32 TIM_OUTCR;

    uint32 TIM_OUTSWCR;

    uint32 TIM_PCR;

    uint32 TIM_FILTER;

    uint32 TIM_FLTCR;

    uint32 TIM_FLTSR;

    uint32 TIM_SYNC;

    uint32 TIM_RELOAD;

    uint32 TIM_HCV;
};

typedef volatile struct Reg_Tim_Bf Reg_Tim_BfType;
typedef volatile struct Reg_Tim_W Reg_Tim_WType;

struct Reg_Tmu_Bf
{

    struct
    {
        uint32 SEL : 16;
        uint32 EN : 1;
        uint32 RSVD_30_17 : 14;
        uint32 LOCK : 1;
    } TMU_CFGn[40];

};

struct Reg_Tmu_W
{

    uint32 TMU_CFGn[40];
};

typedef volatile struct Reg_Tmu_Bf Reg_Tmu_BfType;
typedef volatile struct Reg_Tmu_W Reg_Tmu_WType;

struct Reg_Trng_Bf
{

    uint32 zResverd0x0000;

    uint32 zResverd0x0004;

    struct
    {
        uint32 RD : 1;
        uint32 IN : 1;
        uint32 TA : 1;
        uint32 CA : 1;
        uint32 RSVD_31_4 : 28;
    } TRNG_STATUS;


    struct
    {
        uint32 EN : 1;
        uint32 SM : 1;
        uint32 RSVD_3_2 : 2;
        uint32 DEC : 10;
        uint32 LP : 5;
        uint32 RSVD_31_19 : 13;
    } TRNG_CONFIG;


    struct
    {
        uint32 GE : 1;
        uint32 IN : 1;
        uint32 HT : 1;
        uint32 UN : 1;
        uint32 RS : 1;
        uint32 AK : 1;
        uint32 RSVD_31_6 : 26;
    } CTR_DRBG_CONTROL;


    struct
    {
        uint32 RS : 12;
        uint32 RP : 20;
    } CTR_DRBG_REQUEST_SIZE;


    struct
    {
        uint32 RP : 32;
    } CTR_DRBG_CONFIG_1;


    struct
    {
        uint32 HTP : 32;
    } CTR_DRBG_CONFIG_2;


    struct
    {
        uint32 AL0 : 1;
        uint32 AL1 : 1;
        uint32 AL2 : 1;
        uint32 AL3 : 1;
        uint32 VA : 1;
        uint32 RSVD_31_5 : 27;
    } TRNG_ALARM;


    struct
    {
        uint32 AL0 : 1;
        uint32 AL1 : 1;
        uint32 AL2 : 1;
        uint32 VA : 1;
        uint32 RSVD_31_4 : 28;
    } CTR_DRBG_ALARM;


    struct
    {
        uint32 FL : 1;
        uint32 RSVD_31_1 : 31;
    } TRNG_RAW_RANDOM_CONTROL;


    struct
    {
        uint32 DATA : 16;
        uint32 VA : 1;
        uint32 RSVD_31_17 : 15;
    } TRNG_RAW_RANDOM_DATA;


    struct
    {
        uint32 DATA : 16;
        uint32 VA : 1;
        uint32 RSVD_31_17 : 15;
    } CTR_DRBG_RANDOM_DATA;


    struct
    {
        uint32 I0 : 1;
        uint32 I1 : 1;
        uint32 I2 : 1;
        uint32 I3 : 1;
        uint32 MC : 1;
        uint32 RE : 1;
        uint32 E0 : 1;
        uint32 E1 : 1;
        uint32 E2 : 1;
        uint32 E3 : 1;
        uint32 SE : 1;
        uint32 RSVD_31_11 : 21;
    } ADDITIONAL_CONFIG_0;


    struct
    {
        uint32 AC1 : 11;
        uint32 RSVD_31_11 : 21;
    } ADDITIONAL_CONFIG_1;


    struct
    {
        uint32 AC2 : 32;
    } ADDITIONAL_CONFIG_2;


    struct
    {
        uint32 NS : 1;
        uint32 RSVD_31_1 : 31;
    } ADDITIONAL_MEAS_CONTROL;


    struct
    {
        uint32 TIME : 30;
        uint32 SEL : 2;
    } ADDITIONAL_MEAS_CONFIG;


    struct
    {
        uint32 RD : 1;
        uint32 OV : 1;
        uint32 RSVD_31_2 : 30;
    } ADDITIONAL_MEAS_STATUS;


    struct
    {
        uint32 D0 : 32;
    } ADDITIONAL_MEAS_DATA_0;


    struct
    {
        uint32 D1 : 32;
    } ADDITIONAL_MEAS_DATA_1;


    struct
    {
        uint32 IS0 : 1;
        uint32 IS1 : 1;
        uint32 IS2 : 1;
        uint32 IS3 : 1;
        uint32 RSVD_31_4 : 28;
    } IRQ_STATUS;


    struct
    {
        uint32 CL0 : 1;
        uint32 CL1 : 1;
        uint32 CL2 : 1;
        uint32 CL3 : 1;
        uint32 RSVD_31_4 : 28;
    } IRQ_CLEAR;


    struct
    {
        uint32 E0 : 1;
        uint32 E1 : 1;
        uint32 E2 : 1;
        uint32 E3 : 1;
        uint32 RSVD_31_4 : 28;
    } IRQ_CONFIG;


    struct
    {
        uint32 TIMEOUT : 32;
    } ERROR_CONFIG;


    struct
    {
        uint32 ST : 1;
        uint32 RSVD_31_1 : 31;
    } ERROR_CONTROL;


    struct
    {
        uint32 RD : 1;
        uint32 OV : 1;
        uint32 TR : 1;
        uint32 RSVD_31_3 : 29;
    } ERROR_STATUS;


    struct
    {
        uint32 MO : 1;
        uint32 RSVD_31_1 : 31;
    } STATS_CONFIG;


    struct
    {
        uint32 CL : 1;
        uint32 RSVD_31_1 : 31;
    } STATS_CONTROL;


    struct
    {
        uint32 EV : 16;
        uint32 PA : 16;
    } STATS_DATA;

};

struct Reg_Trng_W
{

    uint32 zResverd0x0000;

    uint32 zResverd0x0004;

    uint32 TRNG_STATUS;

    uint32 TRNG_CONFIG;

    uint32 CTR_DRBG_CONTROL;

    uint32 CTR_DRBG_REQUEST_SIZE;

    uint32 CTR_DRBG_CONFIG_1;

    uint32 CTR_DRBG_CONFIG_2;

    uint32 TRNG_ALARM;

    uint32 CTR_DRBG_ALARM;

    uint32 TRNG_RAW_RANDOM_CONTROL;

    uint32 TRNG_RAW_RANDOM_DATA;

    uint32 CTR_DRBG_RANDOM_DATA;

    uint32 ADDITIONAL_CONFIG_0;

    uint32 ADDITIONAL_CONFIG_1;

    uint32 ADDITIONAL_CONFIG_2;

    uint32 ADDITIONAL_MEAS_CONTROL;

    uint32 ADDITIONAL_MEAS_CONFIG;

    uint32 ADDITIONAL_MEAS_STATUS;

    uint32 ADDITIONAL_MEAS_DATA_0;

    uint32 ADDITIONAL_MEAS_DATA_1;

    uint32 IRQ_STATUS;

    uint32 IRQ_CLEAR;

    uint32 IRQ_CONFIG;

    uint32 ERROR_CONFIG;

    uint32 ERROR_CONTROL;

    uint32 ERROR_STATUS;

    uint32 STATS_CONFIG;

    uint32 STATS_CONTROL;

    uint32 STATS_DATA;
};

typedef volatile struct Reg_Trng_Bf Reg_Trng_BfType;
typedef volatile struct Reg_Trng_W Reg_Trng_WType;

struct Reg_Uart_Bf
{

    union {
        struct
        {
            uint32 RBR_LSB : 8;
            uint32 RBR_MSB : 1;
            uint32 RSVD_31_9 : 23;
        } UART_RBR;
        struct
        {
            uint32 THR_LSB : 8;
            uint32 THR_MSB : 1;
            uint32 RSVD_31_9 : 23;
        } UART_THR;
        struct
        {
            uint32 DL_L : 8;
            uint32 RSVD_31_8 : 24;
        } UART_DLL;
    } UART_RBR_THR_DLL;


    union {
        struct
        {
            uint32 DL_H : 8;
            uint32 RSVD_31_8 : 24;
        } UART_DLH;
        struct
        {
            uint32 ERBFI : 1;
            uint32 ETBEI : 1;
            uint32 ELSI : 1;
            uint32 EDSSI : 1;
            uint32 RSVD_6_4 : 3;
            uint32 PTIME : 1;
            uint32 HEADER_DONE_INT_EN : 1;
            uint32 RSP_DONE_INT_EN : 1;
            uint32 ASYNC_INT_EN : 1;
            uint32 RSVD_31_11 : 21;
        } UART_IER;
    } UART_DLH_IER;


    union {
        struct
        {
            uint32 IID : 4;
            uint32 RSVD_5_4 : 2;
            uint32 FIFOSE : 2;
            uint32 RSVD_31_8 : 24;
        } UART_IIR;
        struct
        {
            uint32 FIFOE : 1;
            uint32 RFIFOR : 1;
            uint32 XFIFOR : 1;
            uint32 RSVD_3 : 1;
            uint32 TET : 2;
            uint32 RCVR : 2;
            uint32 RSVD_31_8 : 24;
        } UART_FCR;
    } UART_IIR_FCR;


    struct
    {
        uint32 DLS : 2;
        uint32 STOP : 1;
        uint32 PEN : 1;
        uint32 EPS : 1;
        uint32 RSVD_5 : 1;
        uint32 BC : 1;
        uint32 DLAB : 1;
        uint32 LBKEN : 1;
        uint32 LBKM : 5;
        uint32 IDLE_DET_LENGTH : 3;
        uint32 IDLE_DET_EN : 1;
        uint32 AUTO_SYNC_EN : 1;
        uint32 DEBUG_EN : 1;
        uint32 RSVD_31_20 : 12;
    } UART_LCR;


    struct
    {
        uint32 RSVD_0 : 1;
        uint32 RTS : 1;
        uint32 RSVD_2 : 1;
        uint32 RSVD_3 : 1;
        uint32 LB : 1;
        uint32 AFCE : 1;
        uint32 RSVD_6 : 1;
        uint32 RSVD_31_7 : 25;
    } UART_AFCR;


    struct
    {
        uint32 DR : 1;
        uint32 OE : 1;
        uint32 PE : 1;
        uint32 FE : 1;
        uint32 BI : 1;
        uint32 THRE : 1;
        uint32 TEMT : 1;
        uint32 RFE : 1;
        uint32 ADDR_RCVD : 1;
        uint32 ASYNC_INT : 1;
        uint32 SYNC_FIELD_ERROR : 1;
        uint32 PID_ERR : 1;
        uint32 CHECKSUM_ERROR : 1;
        uint32 TO_ERROR : 1;
        uint32 HEADER_OP_DONE : 1;
        uint32 RSP_OP_DONE : 1;
        uint32 RSVD_31_16 : 16;
    } UART_LSR;


    struct
    {
        uint32 RSVD_3_0 : 4;
        uint32 CTS : 1;
        uint32 RSVD_31_5 : 27;
    } UART_MSR;

    uint8 zResverd0x01C[96];


    struct
    {
        uint32 BUSY : 1;
        uint32 RSVD_31_1 : 31;
    } UART_USR;

    uint8 zResverd0x080[40];


    struct
    {
        uint32 RSVD_0 : 1;
        uint32 RSVD_31_1 : 31;
    } UART_DMA_SA;

    uint8 zResverd0x0AC[20];


    struct
    {
        uint32 FD : 4;
        uint32 RSVD_31_4 : 28;
    } UART_FD;


    struct
    {
        uint32 RAR : 8;
        uint32 RSVD_31_8 : 24;
    } UART_RAR;


    struct
    {
        uint32 TAR : 8;
        uint32 RSVD_31_8 : 24;
    } UART_TAR;


    struct
    {
        uint32 DLS_E : 1;
        uint32 ADDR_MATCH : 1;
        uint32 SEND_ADDR : 1;
        uint32 TRANSMIST_MODE : 1;
        uint32 RSVD_31_4 : 28;
    } UART_LCR_EXT;

    uint8 zResverd0x0D0[48];


    struct
    {
        uint32 LIN_MODE : 1;
        uint32 MASTER_MODE : 1;
        uint32 HEADER_OP_START : 1;
        uint32 RSP_OP_START : 1;
        uint32 RSP_DIR : 1;
        uint32 RSVD_31_5 : 27;
    } UART_LIN_CTL;


    struct
    {
        uint32 RSP_LENGTH : 4;
        uint32 RSVD_31_4 : 28;
    } UART_LIN_RSP_LENGTH;


    struct
    {
        uint32 PID : 8;
        uint32 RSVD_31_8 : 24;
    } UART_LIN_PID_VALUE;


    struct
    {
        uint32 CHECKSUM_TYPE : 1;
        uint32 RSVD_7_1 : 7;
        uint32 RSVD_31_8 : 24;
    } UART_LIN_CHECKSUM;


    struct
    {
        uint32 LIN_DEL_LENGTH : 3;
        uint32 RSVD_31_3 : 29;
    } UART_LIN_DEL_LENGTH;


    struct
    {
        uint32 FID0 : 6;
        uint32 RSVD_7_6 : 2;
        uint32 FID1 : 6;
        uint32 RSVD_15_14 : 2;
        uint32 FID2 : 6;
        uint32 RSVD_23_22 : 2;
        uint32 FID3 : 6;
        uint32 RSVD_31_30 : 2;
    } UART_LIN_PID_FILTER_0;


    struct
    {
        uint32 FID4 : 6;
        uint32 RSVD_7_6 : 2;
        uint32 FID5 : 6;
        uint32 RSVD_15_14 : 2;
        uint32 FID6 : 6;
        uint32 RSVD_23_22 : 2;
        uint32 FID7 : 6;
        uint32 RSVD_31_30 : 2;
    } UART_LIN_PID_FILTER_1;


    struct
    {
        uint32 FID8 : 6;
        uint32 RSVD_7_6 : 2;
        uint32 FID9 : 6;
        uint32 RSVD_15_14 : 2;
        uint32 FID10 : 6;
        uint32 RSVD_23_22 : 2;
        uint32 FID11 : 6;
        uint32 RSVD_31_30 : 2;
    } UART_LIN_PID_FILTER_2;


    struct
    {
        uint32 FID12 : 6;
        uint32 RSVD_7_6 : 2;
        uint32 FID13 : 6;
        uint32 RSVD_15_14 : 2;
        uint32 FID14 : 6;
        uint32 RSVD_23_22 : 2;
        uint32 FID15 : 6;
        uint32 RSVD_31_30 : 2;
    } UART_LIN_PID_FILTER_3;


    struct
    {
        uint32 FID_VAGUE : 6;
        uint32 RSVD_31_6 : 26;
    } UART_LIN_PID_FILTER_VAGUE;


    struct
    {
        uint32 FID_MASK : 17;
        uint32 FID_VAGUE_MASK : 6;
        uint32 LIN_FILTER_EN : 1;
        uint32 RSVD_31_24 : 8;
    } UART_LIN_PID_FILTER_CTRL;

};

struct Reg_Uart_W
{

    union {
        uint32 UART_RBR;
        uint32 UART_THR;
        uint32 UART_DLL;
    } UART_RBR_THR_DLL;

    union {
        uint32 UART_DLH;
        uint32 UART_IER;
    } UART_DLH_IER;

    union {
        uint32 UART_IIR;
        uint32 UART_FCR;
    } UART_IIR_FCR;

    uint32 UART_LCR;

    uint32 UART_AFCR;

    uint32 UART_LSR;

    uint32 UART_MSR;
    uint8 zResverd0x01C[96];


    uint32 UART_USR;
    uint8 zResverd0x080[40];


    uint32 UART_DMA_SA;
    uint8 zResverd0x0AC[20];


    uint32 UART_FD;

    uint32 UART_RAR;

    uint32 UART_TAR;

    uint32 UART_LCR_EXT;
    uint8 zResverd0x0D0[48];


    uint32 UART_LIN_CTL;

    uint32 UART_LIN_RSP_LENGTH;

    uint32 UART_LIN_PID_VALUE;

    uint32 UART_LIN_CHECKSUM;

    uint32 UART_LIN_DEL_LENGTH;

    uint32 UART_LIN_PID_FILTER_0;

    uint32 UART_LIN_PID_FILTER_1;

    uint32 UART_LIN_PID_FILTER_2;

    uint32 UART_LIN_PID_FILTER_3;

    uint32 UART_LIN_PID_FILTER_VAGUE;

    uint32 UART_LIN_PID_FILTER_CTRL;
};

typedef volatile struct Reg_Uart_Bf Reg_Uart_BfType;
typedef volatile struct Reg_Uart_W Reg_Uart_WType;

struct Reg_Wdog_Bf
{

    uint32 zResverd0x0;

    struct
    {
        uint32 INT_PRESENT : 1;
        uint32 RSVD_31_1 : 31;
    } WDOG_PARAM;


    struct
    {
        uint32 WDOGE : 1;
        uint32 DEBUGE : 1;
        uint32 WAITE : 1;
        uint32 STOPE : 1;
        uint32 INTE : 1;
        uint32 WINE : 1;
        uint32 CFGUA : 1;
        uint32 RSVD_7 : 1;
        uint32 CLKS : 2;
        uint32 RSVD_15_10 : 6;
        uint32 TSTM : 3;
        uint32 RSVD_23_19 : 5;
        uint32 CFGUF : 1;
        uint32 UNLKF : 1;
        uint32 INTF : 1;
        uint32 RSVD_31_27 : 5;
    } WDOG_CS;


    struct
    {
        uint32 TMO : 32;
    } WDOG_TMO;


    struct
    {
        uint32 WIN : 32;
    } WDOG_WIN;


    struct
    {
        uint32 CNT : 32;
    } WDOG_CNT;

};

struct Reg_Wdog_W
{

    uint32 zResverd0x0;

    uint32 WDOG_PARAM;

    uint32 WDOG_CS;

    uint32 WDOG_TMO;

    uint32 WDOG_WIN;

    uint32 WDOG_CNT;
};

typedef volatile struct Reg_Wdog_Bf Reg_Wdog_BfType;
typedef volatile struct Reg_Wdog_W Reg_Wdog_WType;
# 20 "../../../mcal/McalLib_ZX_K14xM/Inc/Devices\\Device_Regs.h" 2
# 28 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2
# 1 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Can.h" 1
# 59 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Can.h"
# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Rte_MemMap.h" 1
# 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Rte_MemMap.h"
#pragma clang section text = ".mcal_code"
# 60 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Can.h" 2


extern void SchM_Enter_Can_DisableIntGlobal(void);
extern void SchM_Exit_Can_DisableIntGlobal(void);

extern void SchM_Enter_Can_DisableModule(void);
extern void SchM_Exit_Can_DisableModule(void);

extern void SchM_Enter_Can_DisableClock(void);
extern void SchM_Exit_Can_DisableClock(void);

extern void SchM_Enter_Can_SetStandardBitTiming(void);
extern void SchM_Exit_Can_SetStandardBitTiming(void);

extern void SchM_Enter_Can_ConfigFdDataBitTiming(void);
extern void SchM_Exit_Can_ConfigFdDataBitTiming(void);

extern void SchM_Enter_Can_ConfigFdCompensation(void);
extern void SchM_Exit_Can_ConfigFdCompensation(void);

extern void SchM_Enter_Can_SetTxArbitrationDelay(void);
extern void SchM_Exit_Can_SetTxArbitrationDelay(void);

extern void SchM_Enter_Can_InterMaskBuff(void);
extern void SchM_Exit_Can_InterMaskBuff(void);

extern void SchM_Enter_Can_ConfigTimeStamp(void);
extern void SchM_Exit_Can_ConfigTimeStamp(void);

extern void SchM_Enter_Can_RecoveryBusOff(void);
extern void SchM_Exit_Can_RecoveryBusOff(void);

extern void SchM_Enter_Can_CanCtl1Reg(void);
extern void SchM_Exit_Can_CanCtl1Reg(void);

extern void SchM_Enter_Can_CanCtl2Reg(void);
extern void SchM_Exit_Can_CanCtl2Reg(void);

extern void SchM_Enter_Can_CanMcrReg(void);
extern void SchM_Exit_Can_CanMcrReg(void);

extern void SchM_Enter_Can_CanMecrReg(void);
extern void SchM_Exit_Can_CanMecrReg(void);

extern void SchM_Enter_Can_CanRxmgMskReg(void);
extern void SchM_Exit_Can_CanRxmgMskReg(void);

extern void SchM_Enter_Can_SetFdArbitrationBitTiming(void);
extern void SchM_Exit_Can_SetFdArbitrationBitTiming(void);

extern void SchM_Enter_Can_SetSelfWakeup(void);
extern void SchM_Exit_Can_SetSelfWakeup(void);
# 211 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Can.h"
extern void Can_MainFunction_BusOff(void);
# 231 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Can.h"
extern void Can_MainFunction_Mode(void);


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Rte_MemMap.h" 1
# 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Rte_MemMap.h"
#pragma clang section text = ""
# 235 "../../../mcal/Rte_ZX_K14xM/Inc\\SchM_Can.h" 2
# 29 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2


# 1 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h" 1
# 28 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
# 1 "../../../mcal/Dma_ZX_K14xM/Inc/Dma_Drv_Types.h" 1
# 31 "../../../mcal/Dma_ZX_K14xM/Inc/Dma_Drv_Types.h"
# 1 "../Generated/inc\\Dma_Drv_Cfg.h" 1
# 30 "../Generated/inc\\Dma_Drv_Cfg.h"
# 1 "../Generated/inc/Dma_Drv_PBcfg.h" 1
# 31 "../Generated/inc\\Dma_Drv_Cfg.h" 2
# 32 "../../../mcal/Dma_ZX_K14xM/Inc/Dma_Drv_Types.h" 2
# 88 "../../../mcal/Dma_ZX_K14xM/Inc/Dma_Drv_Types.h"
typedef enum
{
    DMA_DRV_PHYS_CH_0 = 0U,
    DMA_DRV_PHYS_CH_1,
    DMA_DRV_PHYS_CH_2,
    DMA_DRV_PHYS_CH_3,
    DMA_DRV_PHYS_CH_4,
    DMA_DRV_PHYS_CH_5,
    DMA_DRV_PHYS_CH_6,
    DMA_DRV_PHYS_CH_7,
    DMA_DRV_PHYS_CH_8,
    DMA_DRV_PHYS_CH_9,
    DMA_DRV_PHYS_CH_10,
    DMA_DRV_PHYS_CH_11,
    DMA_DRV_PHYS_CH_12,
    DMA_DRV_PHYS_CH_13,
    DMA_DRV_PHYS_CH_14,
    DMA_DRV_PHYS_CH_15
} Dma_Drv_ChannelType;




typedef void (*Dma_Drv_CallbackType)(const Dma_Drv_ChannelType Channel);




typedef void (*Dma_Drv_ErrIntCallbackType)(const Dma_Drv_ChannelType Channel);




typedef enum
{
    DMA_DRV_PRIORITY_LEVEL_0 = 0U,
    DMA_DRV_PRIORITY_LEVEL_1,
    DMA_DRV_PRIORITY_LEVEL_2,
    DMA_DRV_PRIORITY_LEVEL_3,
    DMA_DRV_PRIORITY_LEVEL_4,
    DMA_DRV_PRIORITY_LEVEL_5,
    DMA_DRV_PRIORITY_LEVEL_6,
    DMA_DRV_PRIORITY_LEVEL_7,
    DMA_DRV_PRIORITY_LEVEL_8,
    DMA_DRV_PRIORITY_LEVEL_9,
    DMA_DRV_PRIORITY_LEVEL_10,
    DMA_DRV_PRIORITY_LEVEL_11,
    DMA_DRV_PRIORITY_LEVEL_12,
    DMA_DRV_PRIORITY_LEVEL_13,
    DMA_DRV_PRIORITY_LEVEL_14,
    DMA_DRV_PRIORITY_LEVEL_15
} Dma_Drv_ChannelPriorityType;





typedef enum
{
    DMA_DRV_TRANSFER_SIZE_1BYTE = 0U,
    DMA_DRV_TRANSFER_SIZE_2BYTE,
    DMA_DRV_TRANSFER_SIZE_4BYTE
} Dma_Drv_TransferSizeType;






typedef enum
{
    DMA_DRV_REQ_I2S0 = 0U,
    DMA_DRV_REQ_I2S1 = 1U,

    DMA_DRV_REQ_UART0_TX = 2U,
    DMA_DRV_REQ_UART0_RX = 3U,
    DMA_DRV_REQ_UART1_TX = 4U,
    DMA_DRV_REQ_UART1_RX = 5U,
    DMA_DRV_REQ_UART2_TX = 6U,
    DMA_DRV_REQ_UART2_RX = 7U,
    DMA_DRV_REQ_UART3_TX = 8U,
    DMA_DRV_REQ_UART3_RX = 9U,
    DMA_DRV_REQ_UART4_TX = 10U,
    DMA_DRV_REQ_UART4_RX = 11U,
    DMA_DRV_REQ_UART5_TX = 12U,
    DMA_DRV_REQ_UART5_RX = 13U,

    DMA_DRV_REQ_SPI0_TX = 14U,
    DMA_DRV_REQ_SPI0_RX = 15U,
    DMA_DRV_REQ_SPI1_TX = 16U,
    DMA_DRV_REQ_SPI1_RX = 17U,
    DMA_DRV_REQ_SPI2_TX = 18U,
    DMA_DRV_REQ_SPI2_RX = 19U,
    DMA_DRV_REQ_SPI3_TX = 20U,
    DMA_DRV_REQ_SPI3_RX = 21U,

    DMA_DRV_REQ_STIM0 = 22U,
    DMA_DRV_REQ_STIM1 = 23U,
    DMA_DRV_REQ_STIM2 = 24U,
    DMA_DRV_REQ_STIM3 = 25U,

    DMA_DRV_REQ_I2C0_TX = 26U,
    DMA_DRV_REQ_I2C0_RX = 27U,
    DMA_DRV_REQ_I2C1_TX = 28U,
    DMA_DRV_REQ_I2C1_RX = 29U,

    DMA_DRV_REQ_CAN0 = 30U,
    DMA_DRV_REQ_CAN1 = 31U,
    DMA_DRV_REQ_CAN2 = 32U,
    DMA_DRV_REQ_CAN3 = 33U,
    DMA_DRV_REQ_CAN4 = 34U,
    DMA_DRV_REQ_CAN5 = 35U,
    DMA_DRV_REQ_CAN6 = 36U,
    DMA_DRV_REQ_CAN7 = 37U,

    DMA_DRV_REQ_TIM0_CHANNEL0 = 38U,
    DMA_DRV_REQ_TIM0_CHANNEL1 = 39U,
    DMA_DRV_REQ_TIM0_CHANNEL2 = 40U,
    DMA_DRV_REQ_TIM0_CHANNEL3 = 41U,
    DMA_DRV_REQ_TIM0_CHANNEL4 = 42U,
    DMA_DRV_REQ_TIM0_CHANNEL5 = 43U,
    DMA_DRV_REQ_TIM0_CHANNEL6 = 44U,
    DMA_DRV_REQ_TIM0_CHANNEL7 = 45U,
    DMA_DRV_REQ_TIM1_CHANNEL0 = 46U,
    DMA_DRV_REQ_TIM1_CHANNEL1 = 47U,
    DMA_DRV_REQ_TIM1_CHANNEL2 = 48U,
    DMA_DRV_REQ_TIM1_CHANNEL3 = 49U,
    DMA_DRV_REQ_TIM1_CHANNEL4 = 50U,
    DMA_DRV_REQ_TIM1_CHANNEL5 = 51U,
    DMA_DRV_REQ_TIM1_CHANNEL6 = 52U,
    DMA_DRV_REQ_TIM1_CHANNEL7 = 53U,
    DMA_DRV_REQ_TIM2_CHANNEL0 = 54U,
    DMA_DRV_REQ_TIM2_CHANNEL1 = 55U,
    DMA_DRV_REQ_TIM2_CHANNEL2 = 56U,
    DMA_DRV_REQ_TIM2_CHANNEL3 = 57U,
    DMA_DRV_REQ_TIM2_CHANNEL4 = 58U,
    DMA_DRV_REQ_TIM2_CHANNEL5 = 59U,
    DMA_DRV_REQ_TIM2_CHANNEL6 = 60U,
    DMA_DRV_REQ_TIM2_CHANNEL7 = 61U,
    DMA_DRV_REQ_TIM3_CHANNEL0 = 62U,
    DMA_DRV_REQ_TIM3_CHANNEL1 = 63U,
    DMA_DRV_REQ_TIM3_CHANNEL2 = 64U,
    DMA_DRV_REQ_TIM3_CHANNEL3 = 65U,
    DMA_DRV_REQ_TIM3_CHANNEL4 = 66U,
    DMA_DRV_REQ_TIM3_CHANNEL5 = 67U,
    DMA_DRV_REQ_TIM3_CHANNEL6 = 68U,
    DMA_DRV_REQ_TIM3_CHANNEL7 = 69U,

    DMA_DRV_REQ_MCPWM0_CHANNEL0 = 70U,
    DMA_DRV_REQ_MCPWM0_CHANNEL1 = 71U,
    DMA_DRV_REQ_MCPWM0_CHANNEL2 = 72U,
    DMA_DRV_REQ_MCPWM0_CHANNEL3 = 73U,
    DMA_DRV_REQ_MCPWM0_CHANNEL4 = 74U,
    DMA_DRV_REQ_MCPWM0_CHANNEL5 = 75U,
    DMA_DRV_REQ_MCPWM0_CHANNEL6 = 76U,
    DMA_DRV_REQ_MCPWM0_CHANNEL7 = 77U,
    DMA_DRV_REQ_MCPWM1_CHANNEL0 = 78U,
    DMA_DRV_REQ_MCPWM1_CHANNEL1 = 79U,
    DMA_DRV_REQ_MCPWM1_CHANNEL2 = 80U,
    DMA_DRV_REQ_MCPWM1_CHANNEL3 = 81U,
    DMA_DRV_REQ_MCPWM1_CHANNEL4 = 82U,
    DMA_DRV_REQ_MCPWM1_CHANNEL5 = 83U,
    DMA_DRV_REQ_MCPWM1_CHANNEL6 = 84U,
    DMA_DRV_REQ_MCPWM1_CHANNEL7 = 85U,

    DMA_DRV_REQ_ADC0 = 88U,
    DMA_DRV_REQ_ADC1 = 89U,

    DMA_DRV_REQ_CMP = 90U,

    DMA_DRV_REQ_PORTA = 91U,
    DMA_DRV_REQ_PORTB = 92U,
    DMA_DRV_REQ_PORTC = 93U,
    DMA_DRV_REQ_PORTD = 94U,
    DMA_DRV_REQ_PORTE = 95U,

    DMA_DRV_REQ_DMAMUX_ALWAYS_ENABLED0 = 96U,
    DMA_DRV_REQ_DMAMUX_ALWAYS_ENABLED1 = 97U,

    DMA_DRV_REQ_SOFTWARE = 128U
} Dma_Drv_RequestSourceType;




typedef struct
{
    Dma_Drv_RequestSourceType MuxReqSrc;
    boolean ReqEn;


} Dma_Drv_RequestConfigType;




typedef struct
{
    uint8 Priority;
    boolean PreemptionDis;


    boolean SuspendEn;


} Dma_Drv_PriorityConfigType;






typedef struct
{
    boolean ErrIntEn;


    boolean MajorIntEn;


    Dma_Drv_RequestConfigType * RequestConfig;
    Dma_Drv_PriorityConfigType * PriorityConfig;
} Dma_Drv_ChannelGlobalConfigType;




typedef struct
{
    uint32 Addr;
    sint16 MinorLoopOffset;
    sint16 MajorLoopOffset;
    Dma_Drv_TransferSizeType TransferSize;
} Dma_Drv_AddrConfigType;

typedef struct
{
    uint32 TransferNum;
    uint16 MinorLoopCnt;
    boolean ReqDis;


} Dma_Drv_TransferControlConfigType;




typedef struct
{
    Dma_Drv_AddrConfigType * SourceConfig;
    Dma_Drv_AddrConfigType * DestinationConfig;
    Dma_Drv_TransferControlConfigType * ControlConfig;
} Dma_Drv_ChannelTransferConfigType;






typedef struct
{
    boolean DebugHalt;



    boolean RoundRobin;


    boolean ErrHalt;



} Dma_Drv_ConfigType;





typedef enum
{
    DMA_DRV_INT_ERROR = 0U,
    DMA_DRV_INT_DONE,
    DMA_DRV_INT_ALL
} Dma_Drv_IntType;




typedef enum
{
    DMA_DRV_HALT_OFF = 0U,
    DMA_DRV_HALT_ON
} Dma_Drv_HaltType;
# 29 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h" 2
# 67 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 876 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section rodata = ".mcal_config_data"
# 68 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h" 2



extern const Dma_Drv_ConfigType * const Dma_Drv_ModuleCfgArrayPtr[((uint32)1U)]; extern const Dma_Drv_ChannelGlobalConfigType Dma_Drv_ChGlobalCfg0; extern const Dma_Drv_ChannelGlobalConfigType Dma_Drv_ChGlobalCfg1; extern const Dma_Drv_ChannelGlobalConfigType Dma_Drv_ChGlobalCfg2; extern const Dma_Drv_ChannelGlobalConfigType Dma_Drv_ChGlobalCfg3; extern const Dma_Drv_ChannelGlobalConfigType Dma_Drv_ChGlobalCfg4; extern const Dma_Drv_ChannelTransferConfigType Dma_Drv_ChTransferCfg0; extern const Dma_Drv_ChannelTransferConfigType Dma_Drv_ChTransferCfg1; extern const Dma_Drv_ChannelTransferConfigType Dma_Drv_ChTransferCfg2;


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 892 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section rodata = ""
# 75 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h" 2







# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section text = ".mcal_code"
# 83 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h" 2
# 97 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
Dma_Drv_ChannelType Dma_Drv_GetLastErrorChannel(uint16 ErrStateRegVal);
# 108 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_InitDoneIrqHandle(const Dma_Drv_ChannelType Channel, Dma_Drv_CallbackType MajorIntCallback);
# 120 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_HaltControl(Dma_Drv_HaltType Cmd);
# 130 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_EnableChannelRequest(Dma_Drv_ChannelType Channel);
# 140 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_DisableChannelRequest(Dma_Drv_ChannelType Channel);
# 154 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_ClearIntStatus(Dma_Drv_ChannelType Channel, Dma_Drv_IntType IntType);
# 165 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
boolean Dma_Drv_GetBusyStatus(void);
# 177 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
boolean Dma_Drv_GetHaltStatus(void);
# 189 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
boolean Dma_Drv_GetChannelErrorStatus(Dma_Drv_ChannelType Channel);
# 199 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
uint16 Dma_Drv_GetAllChannelsErrorStatus(void);
# 210 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetSourceAddr(Dma_Drv_ChannelType Channel, uint32 Address);
# 221 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetSourceTransferSize(Dma_Drv_ChannelType Channel,
                                                 Dma_Drv_TransferSizeType Size);
# 233 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetDestAddr(Dma_Drv_ChannelType Channel, uint32 Address);
# 244 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetMinorLoopSrcOffset(Dma_Drv_ChannelType Channel, sint16 Offset);
# 255 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetMinorLoopDestOffset(Dma_Drv_ChannelType Channel, sint16 Offset);
# 266 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetMajorLoopSrcOffset(Dma_Drv_ChannelType Channel, sint16 Offset);
# 277 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetMajorLoopDestOffset(Dma_Drv_ChannelType Channel, sint16 Offset);
# 288 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetMinorLoopNum(Dma_Drv_ChannelType Channel, uint16 Num);
# 298 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
uint16 Dma_Drv_GetRestMinorLoopNum(Dma_Drv_ChannelType Channel);
# 309 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetDestTransferSize(Dma_Drv_ChannelType Channel,
                                             Dma_Drv_TransferSizeType Size);
# 321 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetTransferByteNum(Dma_Drv_ChannelType Channel, uint32 Num);
# 334 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetDisableRequestAfterDone(Dma_Drv_ChannelType Channel, boolean Cmd);
# 344 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_TriggerChannelStart(Dma_Drv_ChannelType Channel);
# 356 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
boolean Dma_Drv_GetChannelBusyStatus(Dma_Drv_ChannelType Channel);
# 368 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
boolean Dma_Drv_GetDoneStatus(Dma_Drv_ChannelType Channel);
# 378 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_Init(const Dma_Drv_ConfigType * ModuleCfgPtr);
# 388 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_ClearDoneStatus(Dma_Drv_ChannelType Channel);
# 399 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetChannelTransferConfig(const Dma_Drv_ChannelType Channel,
                                     const Dma_Drv_ChannelTransferConfigType * ChTransCfgPtr);
# 411 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_SetChannelGlobalConfig(const Dma_Drv_ChannelType Channel,
                                     const Dma_Drv_ChannelGlobalConfigType * ChGlobalCfgPtr);
# 422 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
uint16 Dma_Drv_GetLastErrorStatus(void);
# 439 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_ControlInt(Dma_Drv_ChannelType Channel, Dma_Drv_IntType IntType,
                                    boolean Control);
# 450 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_ErrorIntHandler(void);
# 460 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_DoneIntHandler(Dma_Drv_ChannelType Channel);
# 470 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_InstallErrIntCallbackFunc(Dma_Drv_ErrIntCallbackType CbFunPtr);
# 481 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_GetChannelTransferConfig(Dma_Drv_ChannelType Channel,
                                    const Dma_Drv_ChannelTransferConfigType * ChTransCfgPtr);
# 493 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h"
void Dma_Drv_GetChannelGlobalConfig(Dma_Drv_ChannelType Channel,
                                    Dma_Drv_ChannelGlobalConfigType * ChGlobalCfgPtr);


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h" 1
# 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Dma_MemMap.h"
#pragma clang section text = ""
# 498 "../../../mcal/Dma_ZX_K14xM/Inc\\Dma_Drv.h" 2
# 32 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2
# 214 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
typedef enum
{
    CAN_DRV_GET_INT_FLAG = 0U,
    CAN_DRV_GET_INT_STATUS
} Can_Drv_GetIntType;




typedef volatile struct
{
    union {
        struct
        {
            uint32 TIME_STAMP : 16;
            uint32 DLC : 4;
            uint32 RTR : 1;
            uint32 IDE : 1;
            uint32 SRR : 1;
            uint32 RSVD_23 : 1;
            uint32 CODE : 4;
            uint32 RSVD_28 : 1;
            uint32 ESI : 1;
            uint32 BRS : 1;
            uint32 EDL : 1;
        } BF;
        uint32 WORDVAL;
    } Config;


    union {
        struct
        {
            uint32 ID_EXTEND : 18;
            uint32 ID_STANDARD : 11;
            uint32 PRIO : 3;
        } BF;
        uint32 WORDVAL;
    } Id;

    uint32 Data[16];
} Can_Drv_MbType;
# 270 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1
# 1016 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h"
#pragma clang section rodata = ".mcal_const"
# 271 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2



static Reg_Can_BfType *const Can_Drv_CanRegBfPtr[(8U)] = {
    (Reg_Can_BfType *)(((uint32)0x40000000U) + 0x24000UL), (Reg_Can_BfType *)(((uint32)0x40000000U) + 0x25000UL),
    (Reg_Can_BfType *)(((uint32)0x40000000U) + 0x38000UL), (Reg_Can_BfType *)(((uint32)0x40000000U) + 0x39000UL),

    (Reg_Can_BfType *)(((uint32)0x40000000U) + 0x44000UL), (Reg_Can_BfType *)(((uint32)0x40000000U) + 0x45000UL),
    (Reg_Can_BfType *)(((uint32)0x40000000U) + 0x56000UL), (Reg_Can_BfType *)(((uint32)0x40000000U) + 0x57000UL),



};



static Reg_Can_WType *const Can_Drv_CanRegWPtr[(8U)] = {
    (Reg_Can_WType *)(((uint32)0x40000000U) + 0x24000UL), (Reg_Can_WType *)(((uint32)0x40000000U) + 0x25000UL),
    (Reg_Can_WType *)(((uint32)0x40000000U) + 0x38000UL), (Reg_Can_WType *)(((uint32)0x40000000U) + 0x39000UL),

    (Reg_Can_WType *)(((uint32)0x40000000U) + 0x44000UL), (Reg_Can_WType *)(((uint32)0x40000000U) + 0x45000UL),
    (Reg_Can_WType *)(((uint32)0x40000000U) + 0x56000UL), (Reg_Can_WType *)(((uint32)0x40000000U) + 0x57000UL),



};


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1
# 1032 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h"
#pragma clang section rodata = ""
# 300 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1
# 1408 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h"
#pragma clang section bss = ".mcal_bss"
# 303 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2

static Can_Drv_StateType *Can_Drv_StatePtr[(8U)];


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1
# 1424 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h"
#pragma clang section bss = ""
# 308 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1
# 1436 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h"
#pragma clang section bss = ".mcal_bss"
# 311 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2


static Dma_Drv_ChannelTransferConfigType Can_Drv_DmaTransferConfig[(8U)];
static Dma_Drv_AddrConfigType Can_Drv_DmaSourceConfig[(8U)];
static Dma_Drv_AddrConfigType Can_Drv_DmaDestinationConfig[(8U)];
static Dma_Drv_TransferControlConfigType Can_Drv_DmaControlConfig[(8U)];



# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1
# 1452 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h"
#pragma clang section bss = ""
# 321 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1
# 1380 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h"
#pragma clang section bss = ".mcal_bss"
# 324 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2

static volatile uint32 Can_Drv_InterMaskBuff[(8U)][(4U)];


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1
# 1396 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h"
#pragma clang section bss = ""
# 329 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2








# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1
# 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h"
#pragma clang section text = ".mcal_code"
# 338 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2


static void Can_Drv_DmaHandle(uint8 Id);

static void Can_Drv_ConfigDma(uint8 Id);

static void Can_Drv_CallbackForDma(uint8 Id);

static void Can_Drv_ClearOutputRxFIFO(uint8 Id);


static uint8 Can_Drv_GetMbNum(uint8 Id);

static void Can_Drv_CompleteRxFifoData(uint8 Id);

static Can_Drv_ControllerStatus Can_Drv_AbortRxTransfer(uint8 Id, uint8 MbIdx);

static Can_Drv_ControllerStatus Can_Drv_AbortTxTransfer(uint8 Id, uint8 MbIdx);

static Can_Drv_ControllerStatus Can_Drv_CheckMbId(uint8 Id, uint32 MbIdx);

static Can_Drv_ControllerStatus Can_Drv_CheckMbIdRange(uint8 Id, uint32 MbIdx);

static Can_Drv_ControllerStatus Can_Drv_ClearMessageBufferIntFlag(uint8 Id, uint32 MbIdx);

static void Can_Drv_ComputeDlcAndDataSize(uint32 DataLen, uint32 *DlcPtr, uint32 *DataSizePtr);

static uint8 Can_Drv_ComputePayloadSize(uint8 DlcValue);

static Can_Drv_ControllerStatus Can_Drv_Disable(uint8 Id);

static Can_Drv_ControllerStatus Can_Drv_Enable(uint8 Id);

static boolean Can_Drv_GetInterruptInfoFromBlock0(uint8 Id, uint32 MbIdx,
                                                  Can_Drv_GetIntType IntType);

static boolean Can_Drv_GetMbInterruptStateFromBlock0(uint8 Id, uint32 MbIdx);

static boolean Can_Drv_GetMbInterruptStateFromBlock1(uint8 Id, uint32 MbIdx);


static boolean Can_Drv_GetMbInterruptStateFromBlock2(uint8 Id, uint32 MbIdx);



static boolean Can_Drv_GetMbInterruptStateFromBlock3(uint8 Id, uint32 MbIdx);


static boolean Can_Drv_GetInterruptInfoFromBlock1(uint8 Id, uint32 MbIdx,
                                                  Can_Drv_GetIntType IntType);


static boolean Can_Drv_GetInterruptInfoFromBlock2(uint8 Id, uint32 MbIdx,
                                                  Can_Drv_GetIntType IntType);



static boolean Can_Drv_GetInterruptInfoFromBlock3(uint8 Id, uint32 MbIdx,
                                                  Can_Drv_GetIntType IntType);


static boolean Can_Drv_ReadMbInterruptStatus(uint8 Id, uint32 MbIdx);

static boolean Can_Drv_ProcessMbIrqSource(uint8 Id, uint32 StartMbIdx, uint32 EndMbIdx);

static inline boolean Can_Drv_ReadMbInterruptFlag(uint8 Id, uint32 MbIdx);

static Can_Drv_ControllerStatus
Can_Drv_GetMbAddr(uint8 Id, uint8 MbIdx, Can_Drv_FdMbRegionType *Region, Can_Drv_MbType **Addr);

static uint32 Can_Drv_GetTimeStamp(uint8 Id, uint8 MbIdx);

static void Can_Drv_ComputeFifoModeATable(uint8 Id, uint32 Number,
                                          const Can_Drv_IdFilterType *IdFilterTable);

static void Can_Drv_ComputeFifoModeBTable(uint8 Id, uint32 Number,
                                          const Can_Drv_IdFilterType *IdFilterTable);

static void Can_Drv_ComputeFifoModeCTable(uint8 Id, uint32 Number,
                                          const Can_Drv_IdFilterType *IdFilterTable);

static void Can_Drv_ConfigRxFifoFilter(uint8 Id, Can_Drv_RxAcceptanceType Format,
                                       const Can_Drv_IdFilterType *IdFilterTable);

static void Can_Drv_UnmaskInterrupt(uint8 Id);

static void Can_Drv_MaskInterrupt(uint8 Id);

static void Can_Drv_ReadRxFifo(uint8 Id, Can_Drv_MsgBufType *MsgBuf);

static void Can_Drv_GetMsgBuff(uint8 Id, uint8 MbIdx, Can_Drv_MsgBufType *MsgBuf);

static uint32 Can_Drv_GetMsgBuffTimeStamp(uint8 Id, uint8 MbIdx);

static void Can_Drv_ProcessErrorIntConfigure(uint8 Id, uint32 Mask, boolean Enable);
static void Can_Drv_ProcessEccIntConfigure(uint8 Id, uint32 Mask, boolean Enable);
static Can_Drv_ControllerStatus Can_Drv_ExecuteSoftReset(uint8 Id);

static void Can_Drv_ClearRam(uint8 Id);

static inline void Can_Drv_ResetConfiguration(uint8 Id);

static void Can_Drv_ConfigMbInterruptBlock0(uint8 Id, uint8 MbIdx, boolean Enable,
                                            boolean IsActive);

static void Can_Drv_ConfigMbInterruptBlock1(uint8 Id, uint8 MbIdx, boolean Enable,
                                            boolean IsActive);


static void Can_Drv_ConfigMbInterruptBlock2(uint8 Id, uint8 MbIdx, boolean Enable,
                                            boolean IsActive);



static void Can_Drv_ConfigMbInterruptBlock3(uint8 Id, uint8 MbIdx, boolean Enable,
                                            boolean IsActive);


static void Can_Drv_ConfigMbInterrupt(uint8 Id, uint8 MbIdx, boolean Enable, boolean IsActive);

static boolean Can_Drv_GetMbInterruptState(uint8 Id, uint8 MbIdx);

static Can_Drv_ControllerStatus Can_Drv_SetErrorInterruptState(uint8 Id, Can_Drv_IntType IntType,
                                                               boolean Enable);

static Can_Drv_ControllerStatus Can_Drv_SetRxMb(uint8 Id, uint8 MbIdx, Can_Drv_MsgIdType IdType,
                                                uint32 MsgId, uint32 Code);

static void Can_Drv_ProcessSetTxMbBuffer(Can_Drv_MbType *MbAddr,
                                         const Can_Drv_MessageInfoType *MessageInfo, uint32 MsgId,
                                         const uint8 *MsgData, uint32 Code, uint8 LocalPrio);

static Can_Drv_ControllerStatus Can_Drv_SetTxMb(uint8 Id, uint8 MbIdx,
                                                const Can_Drv_MessageInfoType *MessageInfo,
                                                uint32 MsgId, const uint8 *MsgData, uint32 Code,
                                                uint8 LocalPrio);

static Can_Drv_ControllerStatus Can_Drv_ProcessTxMb(const Can_Drv_MbType *MbAddr, uint8 Id,
                                                    uint8 MbIdx,
                                                    const Can_Drv_MessageInfoType *TxInfo,
                                                    boolean IsPolling, uint32 MsgId,
                                                    const uint8 *MsgData);

static Can_Drv_ControllerStatus Can_Drv_SetStandardBitTiming(uint8 Id,
                                                             const Can_Drv_BitTimingType *TimeSeg);

static Can_Drv_ControllerStatus
Can_Drv_SetFdArbitrationBitTiming(uint8 Id, const Can_Drv_BitTimingType *TimeSeg);

static Can_Drv_ControllerStatus Can_Drv_ConfigFdDataBitTiming(uint8 Id,
                                                              const Can_Drv_BitTimingType *TimeSeg);

static uint8 Can_Drv_GetPayloadSize(uint8 Id, Can_Drv_FdMbRegionType Region);

static uint8 Can_Drv_GetMaxMbNumLimit(uint8 Id);

static Can_Drv_ControllerStatus Can_Drv_EnterFreezeMode(uint8 Id);

static Can_Drv_ControllerStatus Can_Drv_ExitFreezeMode(uint8 Id);

static Can_Drv_ControllerStatus Can_Drv_SoftResetController(uint8 Id);

static void Can_Drv_SetGlobalConfig(uint8 Id, const Can_Drv_ConfigType *ConfigPtr);

static Can_Drv_ControllerStatus Can_Drv_SetBaudRate(uint8 Id, const Can_Drv_ConfigType *ConfigPtr);

static Can_Drv_ControllerStatus Can_Drv_SetFifoParameter(uint8 Id,
                                                         const Can_Drv_ConfigType *ConfigPtr);

static Can_Drv_ControllerStatus Can_Drv_SetMode(uint8 Id, const Can_Drv_ConfigType *ConfigPtr);

static Can_Drv_ControllerStatus Can_Drv_InitHandle(uint8 Id, const Can_Drv_ConfigType *ConfigPtr);

static Can_Drv_ControllerStatus Can_Drv_SetOperationMode(uint8 Id, Can_Drv_ModeType Mode);

static void Can_Drv_RxFifoIrqHandler(uint8 Id, uint8 MbIdx);

static void Can_Drv_UnlockRxMsgBuff(uint8 Id);

static void Can_Drv_RxMbIrqHandler(uint8 Id, uint8 MbIdx);

static void Can_Drv_TxMbIrqHandler(uint8 Id, uint8 MbIdx);

static void Can_Drv_ProcessMbAbnormalInter(uint8 Id, boolean IsAbnormal, uint32 StartMbIdx,
                                           uint32 EndMbIdx);


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1
# 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h"
#pragma clang section text = ""
# 526 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2








# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1
# 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h"
#pragma clang section text = ".mcal_code"
# 535 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2
# 544 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_DmaHandle(uint8 Id)
{
    Can_Drv_StateType *StatePtr = Can_Drv_StatePtr[Id];
    uint32 Tmp1 = 0U;
    uint32 Tmp2 = 0U;
    Can_Drv_MsgBufType *DmaMessagePtr;

    Dma_Drv_DisableChannelRequest((Dma_Drv_ChannelType)(StatePtr->RxFifoDMAChannel));

    if(1U == Dma_Drv_GetChannelErrorStatus((Dma_Drv_ChannelType)(StatePtr->RxFifoDMAChannel)))
    {
        StatePtr->Mb[(0U)].State = CAN_DRV_STATE_DMA_ERROR;
    }

    if (CAN_DRV_STATE_DMA_ERROR != StatePtr->Mb[(0U)].State)
    {
        DmaMessagePtr = StatePtr->Mb[(0U)].MbMessagePtr;
        Tmp1 = (uint32)((uint32)DmaMessagePtr->Data[0U] | ((uint32)DmaMessagePtr->Data[1U] << 8U) |
                        ((uint32)DmaMessagePtr->Data[2U] << 16U) |
                        ((uint32)DmaMessagePtr->Data[3U] << 24U));

        Tmp2 = (uint32)((uint32)DmaMessagePtr->Data[4U] | ((uint32)DmaMessagePtr->Data[5U] << 8U) |
                        ((uint32)DmaMessagePtr->Data[6U] << 16U) |
                        ((uint32)DmaMessagePtr->Data[7U] << 24U));

        if (0U == ((DmaMessagePtr->Cs) & 0x00200000U))
        {
            DmaMessagePtr->MsgId = (DmaMessagePtr->MsgId >> 18U);
        }


        DmaMessagePtr->DataLen = (uint8)((DmaMessagePtr->Cs & 0x000F0000U) >> 16);

        DmaMessagePtr->TimeStamp = (uint32)(DmaMessagePtr->Cs & 0x0000FFFFU);


        ((Tmp1) = (((Tmp1)&0xFF000000U) >> 24U) | (((Tmp1)&0xFF0000U) >> 8U) | (((Tmp1)&0xFF00U) << 8U) | (((Tmp1)&0xFFU) << 24U));
        DmaMessagePtr->Data[0U] = (uint8)(Tmp1 & 0xFFU);
        DmaMessagePtr->Data[1U] = (uint8)(Tmp1 >> 8U);
        DmaMessagePtr->Data[2U] = (uint8)(Tmp1 >> 16U);
        DmaMessagePtr->Data[3U] = (uint8)(Tmp1 >> 24U);
        ((Tmp2) = (((Tmp2)&0xFF000000U) >> 24U) | (((Tmp2)&0xFF0000U) >> 8U) | (((Tmp2)&0xFF00U) << 8U) | (((Tmp2)&0xFFU) << 24U));
        DmaMessagePtr->Data[4U] = (uint8)(Tmp2 & 0xFFU);
        DmaMessagePtr->Data[5U] = (uint8)(Tmp2 >> 8U);
        DmaMessagePtr->Data[6U] = (uint8)(Tmp2 >> 16U);
        DmaMessagePtr->Data[7U] = (uint8)(Tmp2 >> 24U);
    }
}
# 602 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_ConfigDma(uint8 Id)
{
    const Can_Drv_StateType *StatePtr = Can_Drv_StatePtr[Id];
    Dma_Drv_ChannelTransferConfigType *DmaTransferConfigPtr = &Can_Drv_DmaTransferConfig[Id];
    DmaTransferConfigPtr->SourceConfig = &Can_Drv_DmaSourceConfig[Id];
    DmaTransferConfigPtr->DestinationConfig = &Can_Drv_DmaDestinationConfig[Id];
    DmaTransferConfigPtr->ControlConfig = &Can_Drv_DmaControlConfig[Id];



    DmaTransferConfigPtr->SourceConfig->Addr = (((uint32)Can_Drv_CanRegBfPtr[Id]) + (uint32)0x80UL);

    DmaTransferConfigPtr->SourceConfig->MinorLoopOffset = (sint16)4U;

    DmaTransferConfigPtr->SourceConfig->MajorLoopOffset = (sint16)0U;

    DmaTransferConfigPtr->SourceConfig->TransferSize = DMA_DRV_TRANSFER_SIZE_4BYTE;



    DmaTransferConfigPtr->DestinationConfig->Addr =
        (uint32)(StatePtr->Mb[(0U)].MbMessagePtr);

    DmaTransferConfigPtr->DestinationConfig->MinorLoopOffset = (sint16)4U;

    DmaTransferConfigPtr->DestinationConfig->MajorLoopOffset = (sint16)0U;

    DmaTransferConfigPtr->DestinationConfig->TransferSize = DMA_DRV_TRANSFER_SIZE_4BYTE;

    DmaTransferConfigPtr->ControlConfig->TransferNum = 16U;

    DmaTransferConfigPtr->ControlConfig->MinorLoopCnt = 1U;

    DmaTransferConfigPtr->ControlConfig->ReqDis = (boolean)1U;


    Dma_Drv_SetChannelTransferConfig((Dma_Drv_ChannelType)StatePtr->RxFifoDMAChannel,
                                     (Dma_Drv_ChannelTransferConfigType *)DmaTransferConfigPtr);

    Dma_Drv_EnableChannelRequest((Dma_Drv_ChannelType)StatePtr->RxFifoDMAChannel);
}
# 651 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_CallbackForDma(uint8 Id)
{
    Can_Drv_CompleteRxFifoData(Id);
}
# 664 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_ClearOutputRxFIFO(uint8 Id)
{
    Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    const volatile Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];

    uint8 Index = 0U;

    if (1U == Can_Drv_ReadMbInterruptFlag(Id, (5U)))
    {
        (void)Can_Drv_EnterFreezeMode(Id);

        CanRegisterWPtr->CAN_IFLAG1 = 0x01;

        if (1U == (CanRegisterBfPtr->CAN_MCR.DMAE))
        {
            do
            {

              (void)CanRegisterBfPtr->CAN_MB[0].CAN_MB_DATA47.DATA_BYTE47;
                Index++;
            }
            while ((1U == Can_Drv_ReadMbInterruptFlag(Id, (5U))) &&
                   (Index <= (uint8)12U));
        }

        (void)Can_Drv_ClearMessageBufferIntFlag(Id, (5U));
        (void)Can_Drv_ClearMessageBufferIntFlag(Id, (6U));
        (void)Can_Drv_ClearMessageBufferIntFlag(Id, (7U));


        (void)Can_Drv_ExitFreezeMode(Id);
    }
}
# 707 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static uint8 Can_Drv_GetMbNum(uint8 Id)
{
    uint8 CanMbNumber = 0U;

    if (Id < (uint8)CAN_DRV_ID_6)
    {
        CanMbNumber = (uint8)64U;
    }
    else
    {
        CanMbNumber = (uint8)128U;
    }

    return CanMbNumber;
}
# 732 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_CompleteRxFifoData(uint8 Id)
{
    Can_Drv_StateType *StatePtr;

    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 740); break; };


    StatePtr = Can_Drv_StatePtr[Id];
    if (CAN_DRV_RXFIFO_INTERRUPTS == StatePtr->TransferType)
    {

        Can_Drv_ConfigMbInterrupt(Id, (5U), (boolean)0U,
                                  StatePtr->InterEn);
        Can_Drv_ConfigMbInterrupt(Id, (6U), (boolean)0U, StatePtr->InterEn);
        Can_Drv_ConfigMbInterrupt(Id, (7U), (boolean)0U,
                                  StatePtr->InterEn);
    }


    else if (CAN_DRV_RXFIFO_DMA == StatePtr->TransferType)
    {
        Can_Drv_DmaHandle(Id);
    }
    else
    {

    }


    StatePtr->Mb[(0U)].MbMessagePtr = ((void *)0);


    if (StatePtr->Mb[(0U)].State != CAN_DRV_STATE_DMA_ERROR)
    {
        StatePtr->Mb[(0U)].State = CAN_DRV_STATE_IDLE;
        if ((StatePtr->IrqCallback != ((void *)0)) && (CAN_DRV_RXFIFO_DMA == StatePtr->TransferType))
        {
            StatePtr->IrqCallback(Id, CAN_DRV_DMA_COMPLETE, (0U), StatePtr);
        }
    }
    else
    {
        if (StatePtr->IrqCallback != ((void *)0))
        {
            StatePtr->IrqCallback(Id, CAN_DRV_DMA_ERROR, (0U), StatePtr);
        }
    }





    break; };

}
# 803 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_AbortRxTransfer(uint8 Id, uint8 MbIdx)
{
    const volatile Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Can_Drv_FdMbRegionType Region;
    Can_Drv_MbType *MbAddrPtr;

    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    const Can_Drv_StateType *StatePtr = Can_Drv_StatePtr[Id];

    if (1U == StatePtr->RxFifoEn)
    {

        if (((0U) == MbIdx) && (CAN_DRV_RXFIFO_DMA == StatePtr->TransferType))
        {
            Dma_Drv_DisableChannelRequest((Dma_Drv_ChannelType)(StatePtr->RxFifoDMAChannel));
        }

        if (MbIdx <= (5U + ((((CanRegisterBfPtr->CAN_CTRL2.RFFN) + 1U) * 8U) >> 2U)))
        {
            ReturnValue = CAN_DRV_ERROR;
        }
    }

    if (CAN_DRV_SUCCESS == ReturnValue)
    {
        if (CAN_DRV_ERROR == Can_Drv_GetMbAddr(Id, MbIdx, &Region, &MbAddrPtr))
        {
            ReturnValue = CAN_DRV_ERROR;
        }
        else
        {
            if (CAN_DRV_ERROR == Can_Drv_CheckMbId(Id, MbIdx))
            {
                ReturnValue = CAN_DRV_ERROR;
            }
            else
            {
                MbAddrPtr->Config.BF.CODE = (uint32)CAN_DRV_MB_RX_INACTIVE;
                MbAddrPtr->Config.BF.CODE = (uint32)CAN_DRV_MB_RX_EMPTY;
            }
        }
    }


    (void)Can_Drv_ClearMessageBufferIntFlag(Id, MbIdx);

    return ReturnValue;
}
# 863 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_AbortTxTransfer(uint8 Id, uint8 MbIdx)
{
    Can_Drv_FdMbRegionType Region;
    Can_Drv_MbType *MbAddrPtr;
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    uint32 Code = (uint32)CAN_DRV_MB_TX_INACTIVE;
    uint32 TimeElapsedValue = 0U;
    uint32 TimeCounter = 0U;
    uint32 CurrentValue;
    uint32 CanTimeoutDuration;

    if (CAN_DRV_ERROR == Can_Drv_GetMbAddr(Id, MbIdx, &Region, &MbAddrPtr))
    {
        ReturnValue = CAN_DRV_ERROR;
    }
    else
    {
        if (CAN_DRV_ERROR == Can_Drv_CheckMbId(Id, MbIdx))
        {
            ReturnValue = CAN_DRV_ERROR;
        }
        else
        {
            MbAddrPtr->Config.BF.CODE = (uint32)CAN_DRV_MB_TX_ABORT;
            CanTimeoutDuration =
                McalLib_MicroSecToTicks((MCALLIB_COUNTER_SOFTWARE), (1000000U));

            (void)McalLib_GetCounterValue((MCALLIB_COUNTER_SOFTWARE), &CurrentValue);
            while (0U == Can_Drv_ReadMbInterruptFlag(Id, MbIdx))
            {
                (void)McalLib_GetElapsedValue((MCALLIB_COUNTER_SOFTWARE), &CurrentValue,
                                              &TimeElapsedValue);
                TimeCounter += TimeElapsedValue;
                if (TimeCounter > CanTimeoutDuration)
                {
                    ReturnValue = CAN_DRV_ERROR;
                    break;
                }
            }

            if (CAN_DRV_SUCCESS == ReturnValue)
            {
                Code = MbAddrPtr->Config.BF.CODE;
            }

            if ((uint32)CAN_DRV_MB_TX_INACTIVE == Code)
            {
                ReturnValue = CAN_DRV_ERROR;
            }
            else if ((uint32)CAN_DRV_MB_TX_ABORT == Code)
            {
                ReturnValue = CAN_DRV_SUCCESS;
            }
            else
            {
                ReturnValue = CAN_DRV_SUCCESS;
            }
        }
    }


    (void)Can_Drv_ClearMessageBufferIntFlag(Id, MbIdx);

    return ReturnValue;
}
# 940 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_CheckMbId(uint8 Id, uint32 MbIdx)
{
    const volatile Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    uint8 CanMBNumber = Can_Drv_GetMbNum(Id);

    if ((MbIdx > CanRegisterBfPtr->CAN_MCR.MAXMB) || (MbIdx >= CanMBNumber))
    {
        ReturnValue = CAN_DRV_ERROR;
    }

    if (CanRegisterBfPtr->CAN_MCR.RFEN != 0U)
    {
        if (MbIdx <= (5U + (((((uint32)CanRegisterBfPtr->CAN_CTRL2.RFFN) + 1U) * 8U) >> 2U)))
        {
            ReturnValue = CAN_DRV_ERROR;
        }
    }

    return ReturnValue;
}
# 973 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_CheckMbIdRange(uint8 Id, uint32 MbIdx)
{
    const volatile Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;

    if ((MbIdx > CanRegisterBfPtr->CAN_MCR.MAXMB) || (MbIdx >= Can_Drv_GetMbNum(Id)))
    {
        ReturnValue = CAN_DRV_ERROR;
    }

    return ReturnValue;
}
# 997 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_ClearMessageBufferIntFlag(uint8 Id, uint32 MbIdx)
{
    Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    uint32 Flag = ((uint32)1U << (MbIdx % 32U));

    if (MbIdx < 32U)
    {
        ReturnValue = Can_Drv_EnterFreezeMode(Id);
        if (CAN_DRV_SUCCESS == ReturnValue)
        {
            CanRegisterWPtr->CAN_IFLAG1 = Flag;
            ReturnValue = Can_Drv_ExitFreezeMode(Id);
        }
    }

    else if (MbIdx < 64U)
    {
        CanRegisterWPtr->CAN_IFLAG2 = Flag;
    }


    else if (MbIdx < 96U)
    {
        if (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id))
        {
            CanRegisterWPtr->CAN_IFLAG3 = Flag;
        }
        else
        {
            ReturnValue = CAN_DRV_ERROR;
        }
    }


    else if (MbIdx < 128U)
    {
        if (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id))
        {
            CanRegisterWPtr->CAN_IFLAG4 = Flag;
        }
        else
        {
            ReturnValue = CAN_DRV_ERROR;
        }
    }

    else
    {
        ReturnValue = CAN_DRV_ERROR;
    }

    return ReturnValue;
}
# 1062 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_ComputeDlcAndDataSize(uint32 DataLen, uint32 *DlcPtr, uint32 *DataSizePtr)
{
    uint32 DlcVal = 0U;
    uint32 DataSizeVal = 0U;
# 1109 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
    DlcVal = DataLen;
    DataSizeVal = DataLen;

    if (DlcPtr != ((void *)0))
    {
        *DlcPtr = DlcVal;
    }

    if (DataSizePtr != ((void *)0))
    {
        *DataSizePtr = DataSizeVal;
    }
}
# 1131 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static uint8 Can_Drv_ComputePayloadSize(uint8 DlcValue)
{
    uint8 Ret = 0U;

    if (DlcValue <= 8U)
    {
        Ret = DlcValue;
    }
# 1171 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
    return Ret;
}
# 1184 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_Disable(uint8 Id)
{
    Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    uint32 TimeElapsedValue = 0U;
    uint32 TimeCounter = 0U;
    uint32 CurrentValue;
    uint32 CanTimeoutDuration;

    if (0U == CanRegisterBfPtr->CAN_MCR.MDIS)
    {

        SchM_Enter_Can_DisableModule();

        CanRegisterBfPtr->CAN_MCR.MDIS = 1;

        SchM_Exit_Can_DisableModule();

        CanTimeoutDuration =
            McalLib_MicroSecToTicks((MCALLIB_COUNTER_SOFTWARE), (1000000U));

        (void)McalLib_GetCounterValue((MCALLIB_COUNTER_SOFTWARE), &CurrentValue);
        while (0U == CanRegisterBfPtr->CAN_MCR.LPMACK)
        {
            (void)McalLib_GetElapsedValue((MCALLIB_COUNTER_SOFTWARE), &CurrentValue,
                                          &TimeElapsedValue);
            TimeCounter += TimeElapsedValue;
            if (TimeCounter > CanTimeoutDuration)
            {
                ReturnValue = CAN_DRV_ERROR;
                break;
            }
        }
    }

    return ReturnValue;
}
# 1232 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_Enable(uint8 Id)
{
    Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    uint32 TimeElapsedValue = 0U;
    uint32 TimeCounter = 0U;
    uint32 CurrentValue;
    uint32 CanTimeoutDuration;

    if (CanRegisterBfPtr->CAN_MCR.LPMACK != 0U)
    {

        SchM_Enter_Can_CanMcrReg();
        CanRegisterBfPtr->CAN_MCR.MDIS = 0U;

        SchM_Exit_Can_CanMcrReg();

        CanTimeoutDuration =
            McalLib_MicroSecToTicks((MCALLIB_COUNTER_SOFTWARE), (1000000U));

        (void)McalLib_GetCounterValue((MCALLIB_COUNTER_SOFTWARE), &CurrentValue);

        while (0U != CanRegisterBfPtr->CAN_MCR.LPMACK)
        {
            (void)McalLib_GetElapsedValue((MCALLIB_COUNTER_SOFTWARE), &CurrentValue,
                                          &TimeElapsedValue);
            TimeCounter += TimeElapsedValue;
            if (TimeCounter > CanTimeoutDuration)
            {
                ReturnValue = CAN_DRV_ERROR;
                break;
            }
        }
    }

    return ReturnValue;
}
# 1281 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static boolean Can_Drv_GetInterruptInfoFromBlock0(uint8 Id, uint32 MbIdx,
                                                  Can_Drv_GetIntType IntType)
{
    const volatile Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    boolean RetStatus = 0U;
    uint32 Mask = 0U;

    if (CAN_DRV_GET_INT_STATUS == IntType)
    {
        Mask = CanRegisterWPtr->CAN_IMASK1;
        RetStatus = (((CanRegisterWPtr->CAN_IFLAG1 & Mask) & (1UL << MbIdx)) != 0U) ? 1U : 0U;
    }
    else
    {
        RetStatus = ((CanRegisterWPtr->CAN_IFLAG1 & (1UL << MbIdx)) != 0U) ? 1U : 0U;
    }

    return RetStatus;
}
# 1312 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static boolean Can_Drv_GetMbInterruptStateFromBlock0(uint8 Id, uint32 MbIdx)
{
    const volatile Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    boolean MaskStatus = 0U;

    MaskStatus = ((CanRegisterWPtr->CAN_IMASK1 & (1UL << MbIdx)) != 0U) ? 1U : 0U;

    return MaskStatus;
}
# 1333 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static boolean Can_Drv_GetMbInterruptStateFromBlock1(uint8 Id, uint32 MbIdx)
{
    const volatile Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    boolean MaskStatus = 0U;

    MaskStatus = ((CanRegisterWPtr->CAN_IMASK2 & (1UL << (MbIdx - 32U))) != 0U) ? 1U : 0U;

    return MaskStatus;
}
# 1355 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static boolean Can_Drv_GetMbInterruptStateFromBlock2(uint8 Id, uint32 MbIdx)
{
    const volatile Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    boolean MaskStatus = 0U;

    MaskStatus = ((CanRegisterWPtr->CAN_IMASK3 & (1UL << (MbIdx - 64U))) != 0U) ? 1U : 0U;

    return MaskStatus;
}
# 1378 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static boolean Can_Drv_GetMbInterruptStateFromBlock3(uint8 Id, uint32 MbIdx)
{
    const volatile Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    boolean MaskStatus = 0U;

    MaskStatus = ((CanRegisterWPtr->CAN_IMASK4 & (1UL << (MbIdx - 96U))) != 0U) ? 1U : 0U;

    return MaskStatus;
}
# 1401 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static boolean Can_Drv_GetInterruptInfoFromBlock1(uint8 Id, uint32 MbIdx,
                                                  Can_Drv_GetIntType IntType)
{
    const volatile Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    boolean RetStatus = 0U;
    uint32 Mask = 0U;

    if (CAN_DRV_GET_INT_STATUS == IntType)
    {
        Mask = CanRegisterWPtr->CAN_IMASK2;
        RetStatus =
            (((CanRegisterWPtr->CAN_IFLAG2 & Mask) & (1UL << (MbIdx - 32U))) != 0U) ? 1U : 0U;
    }
    else
    {
        RetStatus = ((CanRegisterWPtr->CAN_IFLAG2 & (1UL << (MbIdx - 32U))) != 0U) ? 1U : 0U;
    }

    return RetStatus;
}
# 1435 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static boolean Can_Drv_GetInterruptInfoFromBlock2(uint8 Id, uint32 MbIdx,
                                                  Can_Drv_GetIntType IntType)
{
    const volatile Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    boolean RetStatus = 0U;
    uint32 Mask = 0U;

    if (CAN_DRV_GET_INT_STATUS == IntType)
    {
        Mask = CanRegisterWPtr->CAN_IMASK3;
        RetStatus =
            (((CanRegisterWPtr->CAN_IFLAG3 & Mask) & (1UL << (MbIdx - 64U))) != 0U) ? 1U : 0U;
    }
    else
    {
        RetStatus = ((CanRegisterWPtr->CAN_IFLAG3 & (1UL << (MbIdx - 64U))) != 0U) ? 1U : 0U;
    }

    return RetStatus;
}
# 1470 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static boolean Can_Drv_GetInterruptInfoFromBlock3(uint8 Id, uint32 MbIdx,
                                                  Can_Drv_GetIntType IntType)
{
    const volatile Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    boolean RetStatus = 0U;
    uint32 Mask = 0U;

    if (CAN_DRV_GET_INT_STATUS == IntType)
    {
        Mask = CanRegisterWPtr->CAN_IMASK4;
        RetStatus =
            (((CanRegisterWPtr->CAN_IFLAG4 & Mask) & (1UL << (MbIdx - 96U))) != 0U) ? 1U : 0U;
    }
    else
    {
        RetStatus = ((CanRegisterWPtr->CAN_IFLAG4 & (1UL << (MbIdx - 96U))) != 0U) ? 1U : 0U;
    }

    return RetStatus;
}
# 1502 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static boolean Can_Drv_ReadMbInterruptStatus(uint8 Id, uint32 MbIdx)
{
    boolean IntStatus = 0U;

    if (MbIdx < 32U)
    {
        IntStatus = Can_Drv_GetInterruptInfoFromBlock0(Id, MbIdx, CAN_DRV_GET_INT_STATUS);
    }

    else if (MbIdx < 64U)
    {
        IntStatus = Can_Drv_GetInterruptInfoFromBlock1(Id, MbIdx, CAN_DRV_GET_INT_STATUS);
    }


    else if ((MbIdx < 96U) && (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id)))
    {
        IntStatus = Can_Drv_GetInterruptInfoFromBlock2(Id, MbIdx, CAN_DRV_GET_INT_STATUS);
    }



    else
    {
        if (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id))
        {
            IntStatus = Can_Drv_GetInterruptInfoFromBlock3(Id, MbIdx, CAN_DRV_GET_INT_STATUS);
        }
    }


    return IntStatus;
}
# 1548 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static boolean Can_Drv_ProcessMbIrqSource(uint8 Id, uint32 StartMbIdx, uint32 EndMbIdx)
{
    uint32 MbIdx = 0U;
    boolean InterFlag = 0;
    const Can_Drv_StateType *StatePtr = Can_Drv_StatePtr[Id];
    boolean IsSpuriousInt = (boolean)1U;

    uint32 MbCounter = EndMbIdx;

    InterFlag = Can_Drv_ReadMbInterruptStatus(Id, MbCounter);

    while ((0U == InterFlag) && (MbCounter > StartMbIdx))
    {
        MbCounter--;
        InterFlag = Can_Drv_ReadMbInterruptStatus(Id, MbCounter);
    }


    if (InterFlag != 0U)
    {

        IsSpuriousInt = (boolean)0U;
        MbIdx = MbCounter;

        if ((1U == StatePtr->RxFifoEn) && (MbCounter <= (7U)))
        {
            Can_Drv_RxFifoIrqHandler(Id, (uint8)MbCounter);
            MbIdx = (uint32)(0U);
        }
        else
        {

            if (CAN_DRV_STATE_RX == StatePtr->Mb[MbIdx].State)
            {
                Can_Drv_RxMbIrqHandler(Id, (uint8)MbCounter);
            }
            else if (CAN_DRV_STATE_TX == StatePtr->Mb[MbIdx].State)
            {

                Can_Drv_TxMbIrqHandler(Id, (uint8)MbCounter);
            }
            else
            {

            }
        }

        InterFlag = Can_Drv_ReadMbInterruptStatus(Id, MbCounter);

        if (InterFlag != 0U)
        {
            if (CAN_DRV_STATE_IDLE == StatePtr->Mb[MbIdx].State)
            {

                (void)Can_Drv_ClearMessageBufferIntFlag(Id, (uint8)MbCounter);
            }
        }
    }

    return IsSpuriousInt;
}
# 1622 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static inline boolean Can_Drv_ReadMbInterruptFlag(uint8 Id, uint32 MbIdx)
{
    boolean IntFlag = 0U;

    if (MbIdx < 32U)
    {
        IntFlag = Can_Drv_GetInterruptInfoFromBlock0(Id, MbIdx, CAN_DRV_GET_INT_FLAG);
    }

    else if (MbIdx < 64U)
    {
        IntFlag = Can_Drv_GetInterruptInfoFromBlock1(Id, MbIdx, CAN_DRV_GET_INT_FLAG);
    }


    else if ((MbIdx < 96U) && (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id)))
    {
        IntFlag = Can_Drv_GetInterruptInfoFromBlock2(Id, MbIdx, CAN_DRV_GET_INT_FLAG);
    }


    else
    {
        if (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id))
        {
            IntFlag = Can_Drv_GetInterruptInfoFromBlock3(Id, MbIdx, CAN_DRV_GET_INT_FLAG);
        }
    }


    return IntFlag;
}
# 1668 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus
Can_Drv_GetMbAddr(uint8 Id, uint8 MbIdx, Can_Drv_FdMbRegionType *Region, Can_Drv_MbType **Addr)
{
    const volatile Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    uint8 PayloadSize;
    uint8 ConfigFieldSize = 8U;
    uint32 RamBlockSize = 512U;
    uint32 RamBlockOffset = 0U;
    uint32 MbSize, RegionMaxMbNum = 0U;
    uint32 MbOffset;
    Can_Drv_FdMbRegionType MaxRegionIndex;
    uint32 MaxRamSize;
    Can_Drv_ControllerStatus Res = CAN_DRV_SUCCESS;
    uint32 Index;

    if (((void *)0) != Region)
    {
        *Region = CAN_DRV_CAN_FD_MB_REGION_0;
    }

    MaxRegionIndex = ((uint32)Id < (uint32)CAN_DRV_ID_6) ? CAN_DRV_CAN_FD_MB_REGION_1
                                                         : CAN_DRV_CAN_FD_MB_REGION_3;

    for (Index = 0U; Index <= (uint32)MaxRegionIndex; Index++)
    {
        MbIdx -= (uint8)RegionMaxMbNum;

        PayloadSize = Can_Drv_GetPayloadSize(Id, (Can_Drv_FdMbRegionType)Index);
        MbSize = (uint32)PayloadSize + (uint32)ConfigFieldSize;
        RegionMaxMbNum = RamBlockSize / MbSize;

        if (((void *)0) != Region)
        {
            *Region = (Can_Drv_FdMbRegionType)Index;
        }

        if (MbIdx < RegionMaxMbNum)
        {

            MbOffset = RamBlockOffset + (uint32)(MbIdx * MbSize);


            *Addr = (Can_Drv_MbType *)((uint32) & (CanRegisterWPtr->CAN_MB[0]) + MbOffset);
            break;
        }
        else
        {
            RamBlockOffset += 512U;
        }
    }
    MaxRamSize = ((uint32)Id < (uint32)CAN_DRV_ID_6) ? 1024U
                                                     : 2048U;
    if (RamBlockOffset >= MaxRamSize)
    {
        Res = CAN_DRV_ERROR;
    }

    return Res;
}
# 1737 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static uint32 Can_Drv_GetTimeStamp(uint8 Id, uint8 MbIdx)
{
    Can_Drv_FdMbRegionType Region;
    Can_Drv_MbType *MbAddr;
    uint32 Temp = 0U;

    if (CAN_DRV_SUCCESS == Can_Drv_GetMbAddr(Id, MbIdx, &Region, &MbAddr))
    {
        Temp = MbAddr->Config.BF.TIME_STAMP;
    }

    return Temp;
}
# 1772 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_ComputeFifoModeATable(uint8 Id, uint32 Number,
                                          const Can_Drv_IdFilterType *IdFilterTable)
{
    uint32 Index;
    uint32 Val;
    Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    volatile uint32 *Table;

    Table = (volatile uint32 *)&(CanRegisterWPtr->CAN_MB[6U].MB0);
    for (Index = 0U; Index < Number; Index++)
    {
        Val = 0U;

        if (1U == IdFilterTable[Index].IsRemoteFrame)
        {
            Val = (uint32)1U << 31U;
        }

        if (1U == IdFilterTable[Index].IsExtendedFrame)
        {
            Val |= (uint32)1U << 30U;
            Table[Index] = Val | ((IdFilterTable[Index].Id << 1U) & 0x3FFFFFFFU);
        }
        else
        {
            Table[Index] = Val | ((IdFilterTable[Index].Id << 19U) & 0x3FFFFFFFU);
        }
    }
}
# 1826 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_ComputeFifoModeBTable(uint8 Id, uint32 Number,
                                          const Can_Drv_IdFilterType *IdFilterTable)
{
    uint32 Index;
    uint32 TableIndex;
    uint32 Val1 = 0;
    uint32 Val2;
    Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    volatile uint32 *Table;
    Table = (volatile uint32 *)&(CanRegisterWPtr->CAN_MB[6].MB0);

    TableIndex = 0U;
    for (Index = 0U; Index < Number; Index++)
    {
        Val1 = 0U;
        Val2 = 0U;

        if (1U == IdFilterTable[TableIndex].IsRemoteFrame)
        {
            Val1 = 1UL << 31U;
        }

        if (1U == IdFilterTable[TableIndex + 1U].IsRemoteFrame)
        {
            Val2 = 1UL << 15U;
        }

        if (1U == IdFilterTable[TableIndex].IsExtendedFrame)
        {
            Val1 |= 1UL << 30U;

            Table[Index] = Val1 | (((IdFilterTable[TableIndex].Id & 0x1FFF8000U) >> 15) << 16);
        }
        else
        {
            Table[Index] = Val1 | ((IdFilterTable[TableIndex].Id & 0x7FFU) << 19);
        }

        if (1U == IdFilterTable[TableIndex + 1U].IsExtendedFrame)
        {
            Val2 |= 1UL << 14U;

            Table[Index] |= Val2 | ((IdFilterTable[TableIndex + 1U].Id & 0x1FFF8000U) >> 15U);
        }
        else
        {
            Table[Index] |= Val2 + ((IdFilterTable[TableIndex + 1U].Id & 0x7FFU) << 3U);
        }

        TableIndex = TableIndex + 2U;
    }
}
# 1901 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_ComputeFifoModeCTable(uint8 Id, uint32 Number,
                                          const Can_Drv_IdFilterType *IdFilterTable)
{
    uint32 Index;
    uint32 TableIndex;
    Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    volatile uint32 *Table;

    Table = (volatile uint32 *)&(CanRegisterWPtr->CAN_MB[6].MB0);
    TableIndex = 0U;
    for (Index = 0U; Index < Number; Index++)
    {
        if (1U == IdFilterTable[TableIndex].IsExtendedFrame)
        {
            Table[Index] |= (((IdFilterTable[TableIndex].Id & 0x1FE00000U) >> 21U) << 24U);
        }
        else
        {
            Table[Index] |= (((IdFilterTable[TableIndex].Id & 0x7F8U) >> 3U) << 24U);
        }

        if (1U == IdFilterTable[TableIndex + 1U].IsExtendedFrame)
        {
            Table[Index] |= (((IdFilterTable[TableIndex + 1U].Id & 0x1FE00000U) >> 21U) << 16U);
        }
        else
        {
            Table[Index] |= (((IdFilterTable[TableIndex + 1U].Id & 0x7F8U) >> 3U) << 16U);
        }

        if (1U == IdFilterTable[TableIndex + 2U].IsExtendedFrame)
        {
            Table[Index] |= (((IdFilterTable[TableIndex + 2U].Id & 0x1FE00000U) >> 21U) << 8U);
        }
        else
        {
            Table[Index] |= (((IdFilterTable[TableIndex + 2U].Id & 0x7F8U) >> 3U) << 8U);
        }

        if (1U == IdFilterTable[TableIndex + 3U].IsExtendedFrame)
        {
            Table[Index] |= ((IdFilterTable[TableIndex + 3U].Id & 0x1FE00000U) >> 21U);
        }
        else
        {
            Table[Index] |= ((IdFilterTable[TableIndex + 3U].Id & 0x7F8U) >> 3U);
        }

        TableIndex = TableIndex + 4U;
    }
}
# 1970 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_ConfigRxFifoFilter(uint8 Id, Can_Drv_RxAcceptanceType Format,
                                       const Can_Drv_IdFilterType *IdFilterTable)
{
    Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    uint8 FilterNum = 0U;
    FilterNum = ((uint8)(CanRegisterBfPtr->CAN_CTRL2.RFFN) + (uint8)1U) << 3u;


    CanRegisterWPtr->CAN_IFLAG1 = 1U;

    switch (Format)
    {
        case CAN_DRV_RX_FIFO_ACCEPTANCE_FORMAT_A:
            SchM_Enter_Can_CanMcrReg();

            CanRegisterBfPtr->CAN_MCR.IDAM = (uint32)Format;
            SchM_Exit_Can_CanMcrReg();
            Can_Drv_ComputeFifoModeATable(Id, FilterNum, IdFilterTable);
            break;
        case CAN_DRV_RX_FIFO_ACCEPTANCE_FORMAT_B:

            SchM_Enter_Can_CanMcrReg();

            CanRegisterBfPtr->CAN_MCR.IDAM = (uint32)Format;
            SchM_Exit_Can_CanMcrReg();
            Can_Drv_ComputeFifoModeBTable(Id, FilterNum, IdFilterTable);
            break;
        case CAN_DRV_RX_FIFO_ACCEPTANCE_FORMAT_C:
            SchM_Enter_Can_CanMcrReg();

            CanRegisterBfPtr->CAN_MCR.IDAM = (uint32)Format;
            SchM_Exit_Can_CanMcrReg();
            Can_Drv_ComputeFifoModeCTable(Id, FilterNum, IdFilterTable);
            break;
        case CAN_DRV_RX_FIFO_ACCEPTANCE_FORMAT_D:
            SchM_Enter_Can_CanMcrReg();

            CanRegisterBfPtr->CAN_MCR.IDAM = (uint32)Format;
            SchM_Exit_Can_CanMcrReg();
            break;
        default:

            break;
    }
}
# 2025 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_UnmaskInterrupt(uint8 Id)
{
    Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];

    CanRegisterWPtr->CAN_IMASK1 = Can_Drv_InterMaskBuff[Id][0U];

    CanRegisterWPtr->CAN_IMASK2 = Can_Drv_InterMaskBuff[Id][1U];



    if (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id))
    {
        CanRegisterWPtr->CAN_IMASK3 = Can_Drv_InterMaskBuff[Id][2U];
    }



    if (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id))
    {
        CanRegisterWPtr->CAN_IMASK4 = Can_Drv_InterMaskBuff[Id][3U];
    }

}
# 2057 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_MaskInterrupt(uint8 Id)
{
    Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];

    CanRegisterWPtr->CAN_IMASK1 = 0U;

    CanRegisterWPtr->CAN_IMASK2 = 0U;



    if (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id))
    {
        CanRegisterWPtr->CAN_IMASK3 = 0U;
    }



    if (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id))
    {
        CanRegisterWPtr->CAN_IMASK4 = 0U;
    }

}
# 2090 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_ReadRxFifo(uint8 Id, Can_Drv_MsgBufType *MsgBuf)
{

    const volatile Reg_Can_WType *CanRegisterWPtr;
    uint8 Index;
    uint32 DataIndex;
    uint8 TmpNum;
    uint8 TmpIndex;
    uint8 PayloadSize;
    const volatile Can_Drv_MbType *MbAddr;
    const volatile uint8 *MbData;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 2107); break; };
    if ((boolean)(MsgBuf != ((void *)0)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 2108); break; };


    CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];


    MbAddr = (Can_Drv_MbType *)(uint32) & (CanRegisterWPtr->CAN_MB[0].MB0);
    PayloadSize = Can_Drv_ComputePayloadSize((uint8)(MbAddr->Config.BF.DLC));
    if (PayloadSize > Can_Drv_GetPayloadSize(Id, CAN_DRV_CAN_FD_MB_REGION_0))
    {
        PayloadSize = Can_Drv_GetPayloadSize(Id, CAN_DRV_CAN_FD_MB_REGION_0);
    }

    MsgBuf->DataLen = PayloadSize;
    MsgBuf->Cs = MbAddr->Config.WORDVAL;
    MsgBuf->TimeStamp = (uint32)(MsgBuf->Cs & 0xFFFFU);
    if (MbAddr->Config.BF.IDE != 0U)
    {
        MsgBuf->MsgId = MbAddr->Id.WORDVAL & 0xDFFFFFFFU;
    }
    else
    {
        MsgBuf->MsgId = MbAddr->Id.BF.ID_STANDARD;
    }

    TmpNum = PayloadSize / 4U;
    for (Index = 0U; Index < TmpNum; Index += 1U)
    {
        DataIndex = (uint32)Index * 4U;
        MsgBuf->Data[DataIndex] = (uint8)((MbAddr->Data[Index] & 0xFF000000U) >> 24U);
        MsgBuf->Data[DataIndex + 1U] = (uint8)((MbAddr->Data[Index] & 0xFF0000U) >> 16U);
        MsgBuf->Data[DataIndex + 2U] = (uint8)((MbAddr->Data[Index] & 0xFF00U) >> 8U);
        MsgBuf->Data[DataIndex + 3U] = (uint8)(MbAddr->Data[Index] & 0xFFU);
    }
    MbData = (const volatile uint8 *)(&MbAddr->Data[0]);
    for (Index = TmpNum * 4U; Index < PayloadSize; Index++)
    {
        TmpIndex = (((Index) & ~3U) + (3U - ((Index)&3U))) & 0x3FU;

        MsgBuf->Data[Index] = MbData[TmpIndex];
    }


    break; };

}
# 2165 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_GetMsgBuff(uint8 Id, uint8 MbIdx, Can_Drv_MsgBufType *MsgBuf)
{
    const volatile Reg_Can_WType *CanRegisterWPtr;
    uint8 Index;
    uint8 DataIndex;
    uint8 TmpNum;
    uint8 TmpIndex;
    uint8 PayloadSize;
    Can_Drv_FdMbRegionType Region;
    Can_Drv_MbType *MbAddr;
    const volatile uint8 *MbData;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 2182); break; };
    if ((boolean)(MsgBuf != ((void *)0)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 2183); break; };


    CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    (void)Can_Drv_GetMbAddr(Id, MbIdx, &Region, &MbAddr);

    MbData = (volatile uint8 *)(&MbAddr->Data[0]);


    (void)(MbAddr->Config.WORDVAL);

    PayloadSize = Can_Drv_ComputePayloadSize((uint8)(MbAddr->Config.BF.DLC));
    if (PayloadSize > Can_Drv_GetPayloadSize(Id, Region))
    {
        PayloadSize = Can_Drv_GetPayloadSize(Id, Region);
    }

    MsgBuf->DataLen = PayloadSize;
    MsgBuf->Cs = MbAddr->Config.WORDVAL;
    MsgBuf->TimeStamp = (uint32)(MsgBuf->Cs & 0x0000FFFFU);

    if (0U != MbAddr->Config.BF.IDE)
    {
        MsgBuf->MsgId = MbAddr->Id.WORDVAL & 0xDFFFFFFFU;
    }
    else
    {
        MsgBuf->MsgId = MbAddr->Id.BF.ID_STANDARD;
    }

    TmpNum = PayloadSize / 4U;
    for (Index = 0U; Index < TmpNum; Index += 1U)
    {
        DataIndex = (Index * 4U);
        MsgBuf->Data[DataIndex] = (uint8)((MbAddr->Data[Index] & 0xFF000000U) >> 24U);
        MsgBuf->Data[DataIndex + 1U] = (uint8)((MbAddr->Data[Index] & 0xFF0000U) >> 16U);
        MsgBuf->Data[DataIndex + 2U] = (uint8)((MbAddr->Data[Index] & 0xFF00U) >> 8U);
        MsgBuf->Data[DataIndex + 3U] = (uint8)(MbAddr->Data[Index] & 0xFFU);
    }

    for (Index = TmpNum * 4U; Index < PayloadSize; Index++)
    {
        TmpIndex = (((Index) & ~3U) + (3U - ((Index)&3U))) & 0x3FU;

        MsgBuf->Data[Index] = MbData[TmpIndex];
    }


    (void)CanRegisterWPtr->CAN_TIMER;


    break; };

}
# 2247 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static uint32 Can_Drv_GetMsgBuffTimeStamp(uint8 Id, uint8 MbIdx)
{
    Can_Drv_FdMbRegionType Region;
    Can_Drv_MbType *MbAddr;
    uint32 TimeStamp = 0U;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 2258); break; };


    (void)Can_Drv_GetMbAddr(Id, MbIdx, &Region, &MbAddr);
    TimeStamp = (uint32)((MbAddr->Config.WORDVAL) & 0x0000FFFFU);


    break; };


    return TimeStamp;
}
# 2281 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_ProcessErrorIntConfigure(uint8 Id, uint32 Mask, boolean Enable)
{
    Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    uint32 Temp = Mask;

    if (1U == Enable)
    {
# 2298 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
        {
            SchM_Enter_Can_CanCtl1Reg();
            (CanRegisterWPtr->CAN_CTRL1) = ((CanRegisterWPtr->CAN_CTRL1) | (Mask));
            SchM_Exit_Can_CanCtl1Reg();
        }
    }
    else
    {
# 2316 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
        {
            Temp = Mask;
            SchM_Enter_Can_CanCtl1Reg();
            (CanRegisterWPtr->CAN_CTRL1) = ((CanRegisterWPtr->CAN_CTRL1) & ~(Temp));
            SchM_Exit_Can_CanCtl1Reg();
        }
    }
}
# 2335 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_ProcessEccIntConfigure(uint8 Id, uint32 Mask, boolean Enable)
{
    Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];

    SchM_Enter_Can_CanCtl2Reg();
    CanRegisterBfPtr->CAN_CTRL2.ECRWRE = 1U;
    SchM_Exit_Can_CanCtl2Reg();

    SchM_Enter_Can_CanMecrReg();
    if (1U == Enable)
    {
        if ((uint32)CAN_DRV_INT_HOST_MEM_ERR == Mask)
        {
            CanRegisterBfPtr->CAN_MECR.ECRWRDIS = 0U;
            CanRegisterWPtr->CAN_MECR |= ((uint32)1U << 19U);
        }
        else if((uint32)CAN_DRV_INT_MEM_ERR == Mask)
        {
            CanRegisterBfPtr->CAN_MECR.ECRWRDIS = 0U;
            CanRegisterWPtr->CAN_MECR |= ((uint32)1U << 18U);
        }
        else
        {
            CanRegisterBfPtr->CAN_MECR.ECRWRDIS = 0U;
            CanRegisterWPtr->CAN_MECR |= ((uint32)1U << 16U);
        }
    }
    else
    {
        if ((uint32)CAN_DRV_INT_HOST_MEM_ERR == Mask)
        {
            CanRegisterBfPtr->CAN_MECR.ECRWRDIS = 0U;
            CanRegisterWPtr->CAN_MECR &= ~((uint32)1U << 19U);
        }
        else if((uint32)CAN_DRV_INT_MEM_ERR == Mask)
        {
            CanRegisterBfPtr->CAN_MECR.ECRWRDIS = 0U;
            CanRegisterWPtr->CAN_MECR &= ~ ((uint32)1U << 18U);
        }
        else
        {
            CanRegisterBfPtr->CAN_MECR.ECRWRDIS = 0U;
            CanRegisterWPtr->CAN_MECR &= ~ ((uint32)1U << 16U);
        }
    }
    SchM_Exit_Can_CanMecrReg();
}
# 2394 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_ExecuteSoftReset(uint8 Id)
{
    Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    uint32 TimeElapsedValue = 0U;
    uint32 TimeCounter = 0U;
    uint32 CurrentValue;
    uint32 CanTimeoutDuration =
        McalLib_MicroSecToTicks((MCALLIB_COUNTER_SOFTWARE), (1000000U));

    SchM_Enter_Can_CanMcrReg();
    CanRegisterBfPtr->CAN_MCR.SOFTRST = 1U;
    SchM_Exit_Can_CanMcrReg();


    (void)McalLib_GetCounterValue((MCALLIB_COUNTER_SOFTWARE), &CurrentValue);
    while (CanRegisterBfPtr->CAN_MCR.SOFTRST != 0U)
    {
        (void)McalLib_GetElapsedValue((MCALLIB_COUNTER_SOFTWARE), &CurrentValue,
                                      &TimeElapsedValue);
        TimeCounter += TimeElapsedValue;
        if (TimeCounter > CanTimeoutDuration)
        {
            ReturnValue = CAN_DRV_ERROR;
            break;
        }
    }

    return ReturnValue;
}
# 2432 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_ClearRam(uint8 Id)
{
    Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    uint32 DataByte;
    uint32 RamSize;
    uint32 RxImrSize;

    volatile uint32 *RAM = &(CanRegisterWPtr->CAN_MB[0].MB0);

    if ((uint32)Id < (uint32)CAN_DRV_ID_6)
    {
        RamSize = (1024U >> 2U);
        RxImrSize = 64U;
    }
    else
    {
        RamSize = (2048U >> 2U);
        RxImrSize = 128U;
    }

    CanRegisterBfPtr->CAN_CTRL2.WRMFRZ = 1;

    for (DataByte = 0U; DataByte < RamSize; DataByte++)
    {
        RAM[DataByte] = 0x0U;
    }

    RAM = &(CanRegisterWPtr->CAN_RXIMR[0]);


    for (DataByte = 0; DataByte < RxImrSize; DataByte++)
    {
        RAM[DataByte] = 0xFFFFFFFFU;
    }


    CanRegisterWPtr->CAN_RXMGMSK = 0xFFFFFFFFU;
    CanRegisterWPtr->CAN_RX14MASK = 0xFFFFFFFFU;
    CanRegisterWPtr->CAN_RX15MASK = 0xFFFFFFFFU;


    CanRegisterWPtr->CAN_RXFGMASK = 0xFFFFFFFFU;



    RAM = (volatile uint32 *)((uint32)Can_Drv_CanRegBfPtr[Id] + 0xA80U);
    for (DataByte = 0U; DataByte < 6U; DataByte++)
    {
        RAM[DataByte] = 0U;
    }



    RAM = (volatile uint32 *)((uint32)Can_Drv_CanRegBfPtr[Id] + 0xAA0U);
    for (DataByte = 0U; DataByte < 4U; DataByte++)
    {
        RAM[DataByte] = 0xFFFFFFFFU;
    }



    RAM = (volatile uint32 *)((uint32)Can_Drv_CanRegBfPtr[Id] + 0xAB0U);
    for (DataByte = 0U; DataByte < 12U; DataByte++)
    {
        RAM[DataByte] = 0U;
    }



    RAM = (volatile uint32 *)((uint32)Can_Drv_CanRegBfPtr[Id] + 0xF28U);
    for (DataByte = 0U; DataByte < 54U; DataByte++)
    {
        RAM[DataByte] = 0U;
    }


    CanRegisterBfPtr->CAN_CTRL2.WRMFRZ = 0U;
}
# 2520 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static inline void Can_Drv_ResetConfiguration(uint8 Id)
{
    Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];

    CanRegisterWPtr->CAN_IMASK1 = 0x00U;
    CanRegisterWPtr->CAN_IFLAG1 = (uint32)(0xFFFFFFFFU);

    CanRegisterWPtr->CAN_IMASK2 = 0x00U;
    CanRegisterWPtr->CAN_IFLAG2 = (uint32)(0xFFFFFFFFU);

    if (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id))
    {

        CanRegisterWPtr->CAN_IMASK3 = 0x00U;
        CanRegisterWPtr->CAN_IFLAG3 = (uint32)(0xFFFFFFFFU);


        CanRegisterWPtr->CAN_IMASK4 = 0x00U;
        CanRegisterWPtr->CAN_IFLAG4 = (uint32)(0xFFFFFFFFU);

    }

    CanRegisterWPtr->CAN_FDCBT = ((uint32)0x00000000U);
    CanRegisterWPtr->CAN_FDCTRL = ((uint32)0x80004100U);
    CanRegisterWPtr->CAN_CBT = ((uint32)0x00000000U);
    SchM_Enter_Can_CanCtl1Reg();
    CanRegisterWPtr->CAN_CTRL1 &= ~(((uint32)1U << 15U) | ((uint32)1U << 14U) | ((uint32)1U << 11U) | ((uint32)1U << 10U));
    SchM_Exit_Can_CanCtl1Reg();

    SchM_Enter_Can_CanCtl2Reg();
    CanRegisterWPtr->CAN_CTRL2 &= ~(((uint32)1U << 30U) | ((uint32)1U << 31U));
    CanRegisterBfPtr->CAN_CTRL2.ECRWRE = 1U;
    SchM_Exit_Can_CanCtl2Reg();
    SchM_Enter_Can_CanMecrReg();
    CanRegisterBfPtr->CAN_MECR.ECRWRDIS = 0U;
    CanRegisterWPtr->CAN_MECR &= ~(((uint32)1U << 19U) | ((uint32)1U << 18U) | ((uint32)1U << 16U));
    SchM_Exit_Can_CanMecrReg();
    SchM_Enter_Can_CanMcrReg();
    CanRegisterBfPtr->CAN_MCR.WAKMSK = 0;
    CanRegisterBfPtr->CAN_MCR.WRNEN = 0U;
    SchM_Exit_Can_CanMcrReg();
    CanRegisterWPtr->CAN_CTRL1_PN &= ~(((uint32)1U << 16U) | ((uint32)1U << 17U));
    CanRegisterWPtr->CAN_CTRL2 = ((uint32)0x00100000U);
    CanRegisterWPtr->CAN_ESR1 = ((uint32)0x0003B006U);
    CanRegisterWPtr->CAN_ECR = ((uint32)0x00000000U);
    CanRegisterWPtr->CAN_TIMER = ((uint32)0x00000000U);
    CanRegisterWPtr->CAN_CTRL1 = ((uint32)0x00000000U);
    CanRegisterWPtr->CAN_MCR = ((uint32)0xD890000FU);
}
# 2582 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_ConfigMbInterruptBlock0(uint8 Id, uint8 MbIdx, boolean Enable, boolean IsActive)
{
    Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    uint32 Temp = 1UL << (MbIdx % 32U);


    SchM_Enter_Can_InterMaskBuff();

    if (1U == Enable)
    {
        Can_Drv_InterMaskBuff[Id][0U] = ((Can_Drv_InterMaskBuff[Id][0U]) | (Temp));
        if (1U == IsActive)
        {
            CanRegisterWPtr->CAN_IMASK1 = Can_Drv_InterMaskBuff[Id][0U];
        }
    }
    else
    {
        Can_Drv_InterMaskBuff[Id][0U] = ((Can_Drv_InterMaskBuff[Id][0U]) & ~(Temp));
        CanRegisterWPtr->CAN_IMASK1 = Can_Drv_InterMaskBuff[Id][0U];
    }

    SchM_Exit_Can_InterMaskBuff();
}
# 2618 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_ConfigMbInterruptBlock1(uint8 Id, uint8 MbIdx, boolean Enable, boolean IsActive)
{
    Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    uint32 Temp = 1UL << (MbIdx % 32U);

    if (1U == Enable)
    {

        SchM_Enter_Can_InterMaskBuff();
        Can_Drv_InterMaskBuff[Id][1U] = ((Can_Drv_InterMaskBuff[Id][1U]) | (Temp));
        if (1U == IsActive)
        {
            CanRegisterWPtr->CAN_IMASK2 = Can_Drv_InterMaskBuff[Id][1U];
        }

        SchM_Exit_Can_InterMaskBuff();
    }
    else
    {

        SchM_Enter_Can_InterMaskBuff();
        Can_Drv_InterMaskBuff[Id][1U] = ((Can_Drv_InterMaskBuff[Id][1U]) & ~(Temp));
        CanRegisterWPtr->CAN_IMASK2 = Can_Drv_InterMaskBuff[Id][1U];

        SchM_Exit_Can_InterMaskBuff();
    }
}
# 2658 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_ConfigMbInterruptBlock2(uint8 Id, uint8 MbIdx, boolean Enable, boolean IsActive)
{
    Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    uint32 Temp = 1UL << (MbIdx % 32U);

    if (1U == Enable)
    {

        SchM_Enter_Can_InterMaskBuff();
        Can_Drv_InterMaskBuff[Id][2U] = ((Can_Drv_InterMaskBuff[Id][2U]) | (Temp));
        if (1U == IsActive)
        {
            CanRegisterWPtr->CAN_IMASK3 = Can_Drv_InterMaskBuff[Id][2U];
        }

        SchM_Exit_Can_InterMaskBuff();
    }
    else
    {

        SchM_Enter_Can_InterMaskBuff();
        Can_Drv_InterMaskBuff[Id][2U] = ((Can_Drv_InterMaskBuff[Id][2U]) & ~(Temp));
        CanRegisterWPtr->CAN_IMASK3 = Can_Drv_InterMaskBuff[Id][2U];

        SchM_Exit_Can_InterMaskBuff();
    }
}
# 2699 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_ConfigMbInterruptBlock3(uint8 Id, uint8 MbIdx, boolean Enable, boolean IsActive)
{
    Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    uint32 Temp = 1UL << (MbIdx % 32U);

    if (1U == Enable)
    {

        SchM_Enter_Can_InterMaskBuff();
        Can_Drv_InterMaskBuff[Id][3U] = ((Can_Drv_InterMaskBuff[Id][3U]) | (Temp));
        if (1U == IsActive)
        {
            CanRegisterWPtr->CAN_IMASK4 = Can_Drv_InterMaskBuff[Id][3U];
        }

        SchM_Exit_Can_InterMaskBuff();
    }
    else
    {

        SchM_Enter_Can_InterMaskBuff();
        Can_Drv_InterMaskBuff[Id][3U] = ((Can_Drv_InterMaskBuff[Id][3U]) & ~(Temp));
        CanRegisterWPtr->CAN_IMASK4 = Can_Drv_InterMaskBuff[Id][3U];

        SchM_Exit_Can_InterMaskBuff();
    }
}
# 2739 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_ConfigMbInterrupt(uint8 Id, uint8 MbIdx, boolean Enable, boolean IsActive)
{
    if (MbIdx < 32U)
    {
        Can_Drv_ConfigMbInterruptBlock0(Id, MbIdx, Enable, IsActive);
    }

    else if (MbIdx < 64U)
    {
        Can_Drv_ConfigMbInterruptBlock1(Id, MbIdx, Enable, IsActive);
    }


    else if ((MbIdx < 96U) && (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id)))
    {
        Can_Drv_ConfigMbInterruptBlock2(Id, MbIdx, Enable, IsActive);
    }


    else if ((MbIdx >= 96U) && (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id)))
    {
        Can_Drv_ConfigMbInterruptBlock3(Id, MbIdx, Enable, IsActive);
    }

    else
    {

    }
}
# 2780 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static boolean Can_Drv_GetMbInterruptState(uint8 Id, uint8 MbIdx)
{
    boolean IntState = 0U;

    if (MbIdx < 32U)
    {
        IntState = Can_Drv_GetMbInterruptStateFromBlock0(Id, MbIdx);
    }

    else if (MbIdx < 64U)
    {
        IntState = Can_Drv_GetMbInterruptStateFromBlock1(Id, MbIdx);
    }


    else if ((MbIdx < 96U) && (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id)))
    {
        IntState = Can_Drv_GetMbInterruptStateFromBlock2(Id, MbIdx);
    }


    else
    {
        if (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id))
        {
            IntState = Can_Drv_GetMbInterruptStateFromBlock3(Id, MbIdx);
        }
    }


    return IntState;
}
# 2825 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_SetErrorInterruptState(uint8 Id, Can_Drv_IntType IntType,
                                                               boolean Enable)
{
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;

    switch (IntType)
    {
        case CAN_DRV_INT_BUS_OFF:
        {
            Can_Drv_ProcessErrorIntConfigure(Id, ((uint32)1U << 15U), Enable);
            break;
        }
        case CAN_DRV_INT_ERR:
        {
            Can_Drv_ProcessErrorIntConfigure(Id, ((uint32)1U << 14U), Enable);
            break;
        }
        case CAN_DRV_INT_ERR_FAST:
        {
            Can_Drv_ProcessErrorIntConfigure(Id, ((uint32)1U << 31U), Enable);
            break;
        }
        case CAN_DRV_INT_HOST_MEM_ERR:
        {
            Can_Drv_ProcessEccIntConfigure(Id, (uint32)CAN_DRV_INT_HOST_MEM_ERR, Enable);
            break;
        }
        case CAN_DRV_INT_MEM_ERR:
        {
            Can_Drv_ProcessEccIntConfigure(Id, (uint32)CAN_DRV_INT_MEM_ERR, Enable);
            break;
        }
        case CAN_DRV_INT_COR_MEM_ERR:
        {
            Can_Drv_ProcessEccIntConfigure(Id, (uint32)CAN_DRV_INT_COR_MEM_ERR, Enable);
            break;
        }
        default:
        {

            break;
        }
    }

    return ReturnValue;
}
# 2886 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_SetRxMb(uint8 Id, uint8 MbIdx, Can_Drv_MsgIdType IdType,
                                                uint32 MsgId, uint32 Code)
{
    Can_Drv_FdMbRegionType Region;
    Can_Drv_MbType *MbAddr;
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;

    if (CAN_DRV_ERROR == Can_Drv_GetMbAddr(Id, MbIdx, &Region, &MbAddr))
    {
        ReturnValue = CAN_DRV_ERROR;
    }
    else
    {
        if (CAN_DRV_ERROR == Can_Drv_CheckMbId(Id, MbIdx))
        {
            ReturnValue = CAN_DRV_ERROR;
        }
        else
        {
            MbAddr->Config.WORDVAL = 0;
            MbAddr->Id.WORDVAL = 0;

            if (CAN_DRV_MSG_ID_EXT == IdType)
            {

                MbAddr->Id.WORDVAL = MsgId & 0xDFFFFFFFU;

                MbAddr->Config.BF.IDE = 1;

                MbAddr->Config.BF.SRR = 0;
            }
            else if (CAN_DRV_MSG_ID_STD == IdType)
            {

                MbAddr->Id.BF.ID_STANDARD = MsgId;

                MbAddr->Config.BF.IDE = 0;

                MbAddr->Config.BF.SRR = 0;
            }
            else
            {

            }

            if (Code != ((uint32)CAN_DRV_NOT_USED))
            {
                MbAddr->Config.BF.CODE = Code;
            }
        }
    }

    return ReturnValue;
}
# 2954 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_ProcessSetTxMbBuffer(Can_Drv_MbType *MbAddr,
                                         const Can_Drv_MessageInfoType *MessageInfo, uint32 MsgId,
                                         const uint8 *MsgData, uint32 Code, uint8 LocalPrio)
{
    uint8 Cnt;
    uint8 DataIndex;
    uint8 TmpNum;
    uint8 TmpIndex;
    uint32 Dlc;
    uint32 DataSize;
    volatile uint8 *MbData;


    MbAddr->Config.BF.CODE = (uint32)CAN_DRV_MB_TX_INACTIVE;
    MbData = (volatile uint8 *)(&MbAddr->Data[0]);

    Can_Drv_ComputeDlcAndDataSize(MessageInfo->DataLen, &Dlc, &DataSize);

    if (MsgData != ((void *)0))
    {
        TmpNum = (uint8)(MessageInfo->DataLen / 4U);
        for (Cnt = 0; Cnt < TmpNum; Cnt += 1U)
        {
            DataIndex = (Cnt * 4U);
            MbAddr->Data[Cnt] =
                ((uint32)MsgData[DataIndex] << 24U) | ((uint32)MsgData[DataIndex + 1U] << 16U) |
                ((uint32)MsgData[DataIndex + 2U] << 8U) | (uint32)MsgData[DataIndex + 3U];
        }

        for (Cnt = TmpNum * 4U; Cnt < MessageInfo->DataLen; Cnt++)
        {
            TmpIndex = (((Cnt) & ~3U) + (3U - ((Cnt)&3U))) & 0x3FU;
            MbData[TmpIndex] = MsgData[Cnt];
        }

        for (Cnt = MessageInfo->DataLen; Cnt < (uint8)DataSize; Cnt++)
        {
            TmpIndex = (((Cnt) & ~3U) + (3U - ((Cnt)&3U))) & 0x3FU;
            MbData[TmpIndex] = MessageInfo->FdPadding;
        }
    }

    MbAddr->Config.WORDVAL = 0;
    MbAddr->Id.WORDVAL = 0;

    MbAddr->Config.BF.DLC = Dlc;


    if (CAN_DRV_MSG_ID_EXT == MessageInfo->IdType)
    {

        MbAddr->Id.WORDVAL = MsgId & 0xDFFFFFFFU;
        MbAddr->Id.BF.PRIO = LocalPrio;

        MbAddr->Config.BF.IDE = 1;

        MbAddr->Config.BF.SRR = 1;
    }
    else if (CAN_DRV_MSG_ID_STD == MessageInfo->IdType)
    {

        MbAddr->Id.BF.ID_STANDARD = MsgId;
        MbAddr->Id.BF.PRIO = LocalPrio;


        MbAddr->Config.BF.IDE = 0;

        MbAddr->Config.BF.SRR = 0;
    }
    else
    {

    }

    if (MessageInfo->RemoteFlag == 1U)
    {

        MbAddr->Config.BF.RTR = 1;
    }


    MbAddr->Config.BF.CODE = 0;

    if (1U == MessageInfo->FdEn)
    {
        MbAddr->Config.BF.EDL = 1;
    }

    MbAddr->Config.BF.BRS = (uint32)(MessageInfo->BrsEn);


    MbAddr->Config.BF.CODE = Code;
}
# 3064 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_SetTxMb(uint8 Id, uint8 MbIdx,
                                                const Can_Drv_MessageInfoType *MessageInfo,
                                                uint32 MsgId, const uint8 *MsgData, uint32 Code,
                                                uint8 LocalPrio)
{
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    uint8 CanPayload;
    Can_Drv_FdMbRegionType Region;
    Can_Drv_MbType *MbAddr;
    Reg_Can_BfType *CanRegisterBfPtr;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 3080); break; };
    if ((boolean)(MessageInfo != ((void *)0)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 3081); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    if (CAN_DRV_ERROR == Can_Drv_GetMbAddr(Id, MbIdx, &Region, &MbAddr))
    {
        ReturnValue = CAN_DRV_ERROR;
    }
    else
    {
        if (MessageInfo->DataLen > 64U)
        {
            ReturnValue = CAN_DRV_ERROR;
        }
        else
        {
            CanPayload = Can_Drv_GetPayloadSize(Id, Region);
            if ((CAN_DRV_SUCCESS == Can_Drv_CheckMbId(Id, MbIdx)) &&
                (MessageInfo->DataLen <= CanPayload))
            {
                if ((CanRegisterBfPtr->CAN_MCR.FDEN != 0U) && (MessageInfo->BrsEn == 1U))
                {
                    CanRegisterBfPtr->CAN_FDCTRL.FD_RATE = 1U;
                }
                Can_Drv_ProcessSetTxMbBuffer(MbAddr, MessageInfo, MsgId, MsgData, Code, LocalPrio);
            }
            else
            {
                ReturnValue = CAN_DRV_ERROR;
            }
        }
    }


    break; };


    return ReturnValue;
}
# 3138 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_ProcessTxMb(const Can_Drv_MbType *MbAddr, uint8 Id,
                                                    uint8 MbIdx,
                                                    const Can_Drv_MessageInfoType *TxInfo,
                                                    boolean IsPolling, uint32 MsgId,
                                                    const uint8 *MsgData)
{
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    Can_Drv_StateType *StatePtr = Can_Drv_StatePtr[Id];
    uint32 Code;


    Code = MbAddr->Config.BF.CODE;
    if ((StatePtr->Mb[MbIdx].State != CAN_DRV_STATE_IDLE) ||
        ((Code != (uint32)CAN_DRV_MB_RX_INACTIVE) && (Code != (uint32)CAN_DRV_MB_TX_INACTIVE) &&
         (Code != (uint32)CAN_DRV_MB_TX_ABORT)))
    {
        ReturnValue = CAN_DRV_ENTER_BUSY;
    }
    else
    {

        (void)Can_Drv_ClearMessageBufferIntFlag(Id, MbIdx);

        StatePtr->Mb[MbIdx].State = CAN_DRV_STATE_TX;
        StatePtr->Mb[MbIdx].RemoteFlag = TxInfo->RemoteFlag;
        StatePtr->Mb[MbIdx].TimeStamp = 0U;
        StatePtr->Mb[MbIdx].IsPolling = IsPolling;

        ReturnValue = Can_Drv_SetTxMb(Id, MbIdx, TxInfo, MsgId, MsgData,
                                      (uint32)CAN_DRV_MB_TX_DATA_REMOTE, 0);

        if ((CAN_DRV_SUCCESS == ReturnValue) && (0U == IsPolling))
        {

            Can_Drv_ConfigMbInterrupt(Id, MbIdx, (boolean)1U, StatePtr->InterEn);
        }

    }

    return ReturnValue;
}
# 3193 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_SetStandardBitTiming(uint8 Id,
                                                             const Can_Drv_BitTimingType *TimeSeg)
{
    Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Can_Drv_ControllerStatus ReturnVal = CAN_DRV_SUCCESS;


    while (1U) {;



    if ((boolean)(TimeSeg != ((void *)0)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 3204); break; };



    if ((0U == TimeSeg->PropSeg) || (0U == TimeSeg->PhaseSeg1) || (TimeSeg->PhaseSeg2 < 1U) ||
        (0U == TimeSeg->PreDivider) || (0U == TimeSeg->RJumpWidth))
    {
        ReturnVal = CAN_DRV_ERROR;
    }
    else
    {

        SchM_Enter_Can_SetStandardBitTiming();
        CanRegisterBfPtr->CAN_CTRL1.PROPSEG = TimeSeg->PropSeg - 1U;
        CanRegisterBfPtr->CAN_CTRL1.PSEG2 = TimeSeg->PhaseSeg2 - 1U;
        CanRegisterBfPtr->CAN_CTRL1.PSEG1 = TimeSeg->PhaseSeg1 - 1U;
        CanRegisterBfPtr->CAN_CTRL1.PRESDIV = TimeSeg->PreDivider - 1U;
        CanRegisterBfPtr->CAN_CTRL1.RJW = TimeSeg->RJumpWidth - 1U;

        SchM_Exit_Can_SetStandardBitTiming();
    }


    break; };


    return ReturnVal;
}
# 3244 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus
Can_Drv_SetFdArbitrationBitTiming(uint8 Id, const Can_Drv_BitTimingType *TimeSeg)
{
    Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Can_Drv_ControllerStatus ReturnVal = CAN_DRV_SUCCESS;


    while (1U) {;



    if ((boolean)(TimeSeg != ((void *)0)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 3255); break; };



    if ((0U == TimeSeg->PropSeg) || (0U == TimeSeg->PhaseSeg1) || (TimeSeg->PhaseSeg2 < 1U) ||
        (0U == TimeSeg->PreDivider) || (0U == TimeSeg->RJumpWidth))
    {
        ReturnVal = CAN_DRV_ERROR;
    }
    else
    {

        SchM_Enter_Can_SetFdArbitrationBitTiming();
        CanRegisterBfPtr->CAN_CBT.EPROPSEG = TimeSeg->PropSeg - 1U;
        CanRegisterBfPtr->CAN_CBT.EPSEG2 = TimeSeg->PhaseSeg2 - 1U;
        CanRegisterBfPtr->CAN_CBT.EPSEG1 = TimeSeg->PhaseSeg1 - 1U;
        CanRegisterBfPtr->CAN_CBT.EPRESDIV = TimeSeg->PreDivider - 1U;
        CanRegisterBfPtr->CAN_CBT.ERJW = TimeSeg->RJumpWidth - 1U;

        SchM_Exit_Can_SetFdArbitrationBitTiming();
    }


    break; };


    return ReturnVal;
}
# 3295 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_ConfigFdDataBitTiming(uint8 Id,
                                                              const Can_Drv_BitTimingType *TimeSeg)
{
    Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Can_Drv_ControllerStatus ReturnVal = CAN_DRV_SUCCESS;


    while (1U) {;



    if ((boolean)(TimeSeg != ((void *)0)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 3306); break; };



    if ((0U == TimeSeg->PropSeg) || (0U == TimeSeg->PhaseSeg1) || (TimeSeg->PhaseSeg2 < 1U) ||
        (0U == TimeSeg->PreDivider) || (0U == TimeSeg->RJumpWidth))
    {
        ReturnVal = CAN_DRV_ERROR;
    }
    else
    {

        SchM_Enter_Can_ConfigFdDataBitTiming();
        CanRegisterBfPtr->CAN_FDCBT.FPROPSEG = TimeSeg->PropSeg;
        CanRegisterBfPtr->CAN_FDCBT.FPSEG2 = TimeSeg->PhaseSeg2 - 1U;
        CanRegisterBfPtr->CAN_FDCBT.FPSEG1 = TimeSeg->PhaseSeg1 - 1U;
        CanRegisterBfPtr->CAN_FDCBT.FPRESDIV = TimeSeg->PreDivider - 1U;
        CanRegisterBfPtr->CAN_FDCBT.FRJW = TimeSeg->RJumpWidth - 1U;

        SchM_Exit_Can_ConfigFdDataBitTiming();
    }


    break; };


    return ReturnVal;
}
# 3344 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static uint8 Can_Drv_GetPayloadSize(uint8 Id, Can_Drv_FdMbRegionType Region)
{
    const volatile Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    uint32 PayloadSize = 0U;


    if (CanRegisterBfPtr->CAN_MCR.FDEN != 0U)
    {
        switch (Region)
        {
            case CAN_DRV_CAN_FD_MB_REGION_0:
                PayloadSize = 1UL << (CanRegisterBfPtr->CAN_FDCTRL.MBDSR0 + 3U);
                break;
            case CAN_DRV_CAN_FD_MB_REGION_1:
                PayloadSize = 1UL << (CanRegisterBfPtr->CAN_FDCTRL.MBDSR1 + 3U);
                break;
            case CAN_DRV_CAN_FD_MB_REGION_2:
                PayloadSize = 1UL << (CanRegisterBfPtr->CAN_FDCTRL.MBDSR2 + 3U);
                break;
            case CAN_DRV_CAN_FD_MB_REGION_3:
                PayloadSize = 1UL << (CanRegisterBfPtr->CAN_FDCTRL.MBDSR3 + 3U);
                break;
            default:

                break;
        }
    }
    else
    {
        PayloadSize = 8U;
    }

    return (uint8)PayloadSize;
}
# 3387 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static uint8 Can_Drv_GetMaxMbNumLimit(uint8 Id)
{
    uint32 PayloadSize;
    uint8 ConfigFieldSize = 8U;
    uint32 RamBlockSize = 512U;
    uint32 MbSize;
    uint32 TotalMbNum;

    PayloadSize = Can_Drv_GetPayloadSize(Id, CAN_DRV_CAN_FD_MB_REGION_0);
    MbSize = PayloadSize + ConfigFieldSize;
    TotalMbNum = RamBlockSize / MbSize;

    PayloadSize = Can_Drv_GetPayloadSize(Id, CAN_DRV_CAN_FD_MB_REGION_1);
    MbSize = PayloadSize + ConfigFieldSize;
    TotalMbNum += (RamBlockSize / MbSize);

    if (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id))
    {
        PayloadSize = Can_Drv_GetPayloadSize(Id, CAN_DRV_CAN_FD_MB_REGION_2);
        MbSize = PayloadSize + ConfigFieldSize;
        TotalMbNum += (RamBlockSize / MbSize);

        PayloadSize = Can_Drv_GetPayloadSize(Id, CAN_DRV_CAN_FD_MB_REGION_3);
        MbSize = PayloadSize + ConfigFieldSize;
        TotalMbNum += (RamBlockSize / MbSize);
    }

    return (uint8)TotalMbNum;
}
# 3427 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_EnterFreezeMode(uint8 Id)
{
    Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    uint32 TimeElapsedValue = 0U;
    uint32 TimeCounter = 0U;
    uint32 CurrentValue;
    uint32 CanTimeoutDuration;

    if (0U == CanRegisterBfPtr->CAN_MCR.FRZACK)
    {
        CanTimeoutDuration =
            McalLib_MicroSecToTicks((MCALLIB_COUNTER_SOFTWARE), (1000000U));


        SchM_Enter_Can_CanMcrReg();
        CanRegisterBfPtr->CAN_MCR.FRZ = 1U;
        CanRegisterBfPtr->CAN_MCR.HALT = 1U;
        if (CanRegisterBfPtr->CAN_MCR.MDIS != 0U)
        {
            CanRegisterBfPtr->CAN_MCR.MDIS = 0U;
        }
        SchM_Exit_Can_CanMcrReg();



        (void)McalLib_GetCounterValue((MCALLIB_COUNTER_SOFTWARE), &CurrentValue);

        while (0U == CanRegisterBfPtr->CAN_MCR.NOTRDY)
        {
            (void)McalLib_GetElapsedValue((MCALLIB_COUNTER_SOFTWARE), &CurrentValue,
                                          &TimeElapsedValue);
            TimeCounter += TimeElapsedValue;
            if (TimeCounter > CanTimeoutDuration)
            {
                ReturnValue = CAN_DRV_ERROR;
                break;
            }
        }

        TimeCounter = 0;

        (void)McalLib_GetCounterValue((MCALLIB_COUNTER_SOFTWARE), &CurrentValue);
        while ((0U == CanRegisterBfPtr->CAN_MCR.FRZACK) && (CAN_DRV_SUCCESS == ReturnValue))
        {
            (void)McalLib_GetElapsedValue((MCALLIB_COUNTER_SOFTWARE), &CurrentValue,
                                          &TimeElapsedValue);
            TimeCounter += TimeElapsedValue;
            if (TimeCounter > CanTimeoutDuration)
            {
                ReturnValue = CAN_DRV_ERROR;
                break;
            }
        }
    }

    return ReturnValue;
}
# 3496 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_ExitFreezeMode(uint8 Id)
{
    Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    uint32 TimeElapsedValue = 0U;
    uint32 TimeCounter = 0U;
    uint32 CurrentValue;
    uint32 CanTimeoutDuration;

    if (1U == CanRegisterBfPtr->CAN_MCR.FRZACK)
    {
        CanTimeoutDuration =
            McalLib_MicroSecToTicks((MCALLIB_COUNTER_SOFTWARE), (1000000U));


        SchM_Enter_Can_CanMcrReg();
        CanRegisterBfPtr->CAN_MCR.HALT = 0U;
        CanRegisterBfPtr->CAN_MCR.FRZ = 0U;

        SchM_Exit_Can_CanMcrReg();


        (void)McalLib_GetCounterValue((MCALLIB_COUNTER_SOFTWARE), &CurrentValue);
        while (1U == CanRegisterBfPtr->CAN_MCR.FRZACK)
        {
            (void)McalLib_GetElapsedValue((MCALLIB_COUNTER_SOFTWARE), &CurrentValue,
                                          &TimeElapsedValue);
            TimeCounter += TimeElapsedValue;
            if (TimeCounter > CanTimeoutDuration)
            {
                ReturnValue = CAN_DRV_ERROR;
                break;
            }
        }
    }

    return ReturnValue;
}
# 3545 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_SoftResetController(uint8 Id)
{
    const volatile Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;


    if (1U == CanRegisterBfPtr->CAN_MCR.MDIS)
    {
        ReturnValue = Can_Drv_Enable(Id);
    }

    if (CAN_DRV_SUCCESS == ReturnValue)
    {
        ReturnValue = Can_Drv_ExecuteSoftReset(Id);
    }

    return ReturnValue;
}
# 3573 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_SetGlobalConfig(uint8 Id, const Can_Drv_ConfigType *ConfigPtr)
{
    Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];


    if (0x00000001U == ((ConfigPtr->CtrlConfig) & 0x00000001U))
    {
        CanRegisterBfPtr->CAN_CTRL2.EDFLTDIS = 1U;
    }
    else
    {
        CanRegisterBfPtr->CAN_CTRL2.EDFLTDIS = 0U;
    }


    if (0x00000002U == ((ConfigPtr->CtrlConfig) & 0x00000002U))
    {
        CanRegisterBfPtr->CAN_CTRL2.ISOCANFDEN = 1U;
    }
    else
    {
        CanRegisterBfPtr->CAN_CTRL2.ISOCANFDEN = 0U;
    }


    if (0x00000004U == ((ConfigPtr->CtrlConfig) & 0x00000004U))
    {
        CanRegisterBfPtr->CAN_CTRL2.PREXCEN = 1U;
    }
    else
    {
        CanRegisterBfPtr->CAN_CTRL2.PREXCEN = 0U;
    }


    CanRegisterBfPtr->CAN_CTRL1.BOFFREC = 1U;


    if (0x00000020U == ((ConfigPtr->CtrlConfig) & 0x00000020U))
    {
        CanRegisterBfPtr->CAN_CTRL1.SMP = 1U;
    }
    else
    {
        CanRegisterBfPtr->CAN_CTRL1.SMP = 0U;
    }


    if (0x00000040U == ((ConfigPtr->CtrlConfig) & 0x00000040U))
    {
        CanRegisterBfPtr->CAN_CTRL1.LBUF = 1U;
    }
    else
    {
        CanRegisterBfPtr->CAN_CTRL1.LBUF = 0U;
    }


    if (ConfigPtr->Mode != CAN_DRV_MODE_LOOPBACK)
    {
        CanRegisterBfPtr->CAN_MCR.SRXDIS = 1U;
    }
}
# 3648 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_SetBaudRate(uint8 Id, const Can_Drv_ConfigType *ConfigPtr)
{
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
# 3686 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
    if (CAN_DRV_ERROR == Can_Drv_SetStandardBitTiming(Id, &(ConfigPtr->BitTiming)))
    {
        ReturnValue = CAN_DRV_ERROR;
    }


    return ReturnValue;
}
# 3706 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_SetFifoParameter(uint8 Id,
                                                         const Can_Drv_ConfigType *ConfigPtr)
{
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];


    Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];

    if (1U == ConfigPtr->RxFifoEn)
    {
        if (1U == ConfigPtr->FdEn)
        {
            ReturnValue = CAN_DRV_ERROR;
        }
        else
        {
            SchM_Enter_Can_CanMcrReg();

            CanRegisterBfPtr->CAN_MCR.RFEN = 1;
            SchM_Exit_Can_CanMcrReg();

            CanRegisterBfPtr->CAN_CTRL2.RFFN = (uint32)(ConfigPtr->RxFifoIdFilterNum);


            if (CAN_DRV_RXFIFO_DMA == ConfigPtr->TransferType)
            {
                SchM_Enter_Can_CanMcrReg();
                CanRegisterBfPtr->CAN_MCR.DMAE = 1;
                SchM_Exit_Can_CanMcrReg();
            }
            else

            {
                SchM_Enter_Can_CanMcrReg();
                CanRegisterBfPtr->CAN_MCR.DMAE = 0;
                SchM_Exit_Can_CanMcrReg();
            }

            CanRegisterWPtr->CAN_RXFGMASK = 0xFFFFFFFFU;
        }
    }
    else
    {
        SchM_Enter_Can_CanMcrReg();

        CanRegisterBfPtr->CAN_MCR.RFEN = 0;
        SchM_Exit_Can_CanMcrReg();
        if (CAN_DRV_RXFIFO_DMA == ConfigPtr->TransferType)
        {
            ReturnValue = CAN_DRV_ERROR;
        }
    }
# 3770 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
    return ReturnValue;
}
# 3784 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_SetMode(uint8 Id, const Can_Drv_ConfigType *ConfigPtr)
{
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];

    if ((ConfigPtr->MbMaxNum > Can_Drv_GetMaxMbNumLimit(Id)) ||
        (ConfigPtr->MbMaxNum > Can_Drv_GetMbNum(Id)))
    {
        ReturnValue = CAN_DRV_ERROR;
    }
    else
    {
        CanRegisterBfPtr->CAN_MCR.MAXMB = ConfigPtr->MbMaxNum - 1U;

        CanRegisterBfPtr->CAN_MCR.DOZE = 1U;
        ReturnValue = Can_Drv_SetOperationMode(Id, ConfigPtr->Mode);

        if (CAN_DRV_SUCCESS == ReturnValue)
        {

            if (ConfigPtr->Mode != CAN_DRV_MODE_FREEZE)
            {
                if (CAN_DRV_SUCCESS != Can_Drv_ExitFreezeMode(Id))
                {
                    ReturnValue = CAN_DRV_ERROR;
                }
            }
        }
    }

    return ReturnValue;
}
# 3828 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_InitHandle(uint8 Id, const Can_Drv_ConfigType *ConfigPtr)
{
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    Reg_Can_WType *CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];

    ReturnValue = Can_Drv_SoftResetController(Id);

    if (CAN_DRV_SUCCESS == ReturnValue)
    {

        CanRegisterBfPtr->CAN_MCR.AEN = 1U;




        Can_Drv_ClearRam(Id);


        CanRegisterWPtr->CAN_IMASK1 = 0U;

        CanRegisterWPtr->CAN_IFLAG1 = 0xFFFFFFFFU;


        CanRegisterWPtr->CAN_IMASK2 = 0U;

        CanRegisterWPtr->CAN_IFLAG2 = 0xFFFFFFFFU;


        if (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id))
        {

            CanRegisterWPtr->CAN_IMASK3 = 0U;

            CanRegisterWPtr->CAN_IFLAG3 = 0xFFFFFFFFU;
        }


        if (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id))
        {

            CanRegisterWPtr->CAN_IMASK4 = 0U;

            CanRegisterWPtr->CAN_IFLAG4 = 0xFFFFFFFFU;
        }



        CanRegisterWPtr->CAN_ESR1 = (((uint32)1U << 2U) | ((uint32)1U << 1U) | ((uint32)1U << 17U) | ((uint32)1U << 16U) | ((uint32)1U << 19U) | ((uint32)1U << 20U) | 1U);
        CanRegisterWPtr->CAN_ERRSR = (((uint32)1U << 19U) | ((uint32)1U << 18U) | ((uint32)1U << 16U));
        CanRegisterWPtr->CAN_WU_MTC = (((uint32)1U << 16U) | ((uint32)1U << 17U));

        CanRegisterWPtr->CAN_CTRL1 = ((uint32)0x00000000U);
        CanRegisterWPtr->CAN_CTRL2 = ((uint32)0x00100000U);
        CanRegisterWPtr->CAN_CBT = ((uint32)0x00000000U);
# 3898 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
        Can_Drv_SetGlobalConfig(Id, ConfigPtr);

        if (CAN_DRV_SUCCESS == Can_Drv_SetBaudRate(Id, ConfigPtr))
        {
            if (CAN_DRV_ERROR == Can_Drv_SetFifoParameter(Id, ConfigPtr))
            {
                ReturnValue = CAN_DRV_ERROR;
            }
            else
            {
                ReturnValue = Can_Drv_SetMode(Id, ConfigPtr);
            }
        }
        else
        {
            ReturnValue = CAN_DRV_ERROR;
        }
    }

    return ReturnValue;
}
# 3931 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static Can_Drv_ControllerStatus Can_Drv_SetOperationMode(uint8 Id, Can_Drv_ModeType Mode)
{
    Reg_Can_BfType *CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;

    switch (Mode)
    {
        case CAN_DRV_MODE_NORMAL:
            CanRegisterBfPtr->CAN_CTRL1.LOM = 0;
            CanRegisterBfPtr->CAN_CTRL1.LPB = 0;
            CanRegisterBfPtr->CAN_MCR.SUPV = 0;
            break;
        case CAN_DRV_MODE_LISTEN_ONLY:
            CanRegisterBfPtr->CAN_CTRL1.LOM = 1;
            break;
        case CAN_DRV_MODE_LOOPBACK:
            CanRegisterBfPtr->CAN_CTRL1.LOM = 0;
            CanRegisterBfPtr->CAN_CTRL1.LPB = 1;
            CanRegisterBfPtr->CAN_MCR.SRXDIS = 0;
            CanRegisterBfPtr->CAN_FDCTRL.TDCEN = 0;
            break;
        case CAN_DRV_MODE_FREEZE:
            if (CAN_DRV_SUCCESS != Can_Drv_EnterFreezeMode(Id))
            {
                ReturnValue = CAN_DRV_ERROR;
            }
            break;
        case CAN_DRV_MODE_DISABLE:
            CanRegisterBfPtr->CAN_MCR.MDIS = 1;
            break;
        default:
            ReturnValue = CAN_DRV_ERROR;
            break;
    }

    return ReturnValue;
}
# 3978 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_RxFifoIrqHandler(uint8 Id, uint8 MbIdx)
{
    Can_Drv_MsgBufType Data;
    Can_Drv_StateType *StatePtr = Can_Drv_StatePtr[Id];

    if (((void *)0) == StatePtr->Mb[(0U)].MbMessagePtr)
    {
        StatePtr->Mb[(0U)].MbMessagePtr = &Data;
    }

    if ((5U) == MbIdx)
    {
        if (CAN_DRV_STATE_RX == StatePtr->Mb[(0U)].State)
        {

            Can_Drv_ReadRxFifo(Id, StatePtr->Mb[(0U)].MbMessagePtr);

            (void)Can_Drv_ClearMessageBufferIntFlag(Id, MbIdx);

            StatePtr->Mb[(0U)].State = CAN_DRV_STATE_IDLE;

            if (StatePtr->IrqCallback != ((void *)0))
            {
                StatePtr->IrqCallback(Id, CAN_DRV_INT_RXFIFO_FRAME, (0U),
                                      StatePtr);
            }

            if (CAN_DRV_STATE_IDLE == StatePtr->Mb[(0U)].State)
            {

                StatePtr->Mb[(0U)].IsPolling = (boolean)1U;

                Can_Drv_CompleteRxFifoData(Id);
            }
        }
    }
    else if ((6U) == MbIdx)
    {

        (void)Can_Drv_ClearMessageBufferIntFlag(Id, MbIdx);

        if (StatePtr->IrqCallback != ((void *)0))
        {
            StatePtr->IrqCallback(Id, CAN_DRV_INT_RXFIFO_WARNING, (0U),
                                  StatePtr);
        }
    }
    else if ((7U) == MbIdx)
    {

        (void)Can_Drv_ClearMessageBufferIntFlag(Id, MbIdx);

        if (StatePtr->IrqCallback != ((void *)0))
        {
            StatePtr->IrqCallback(Id, CAN_DRV_INT_RXFIFO_OVERFLOW, (0U),
                                  StatePtr);
        }
    }
    else
    {

    }
}
# 4050 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_UnlockRxMsgBuff(uint8 Id)
{
    const volatile Reg_Can_WType *CanRegisterWPtr;

    CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];

    (void)CanRegisterWPtr->CAN_TIMER;
}
# 4068 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_RxMbIrqHandler(uint8 Id, uint8 MbIdx)
{
    Can_Drv_MsgBufType Data;
    Can_Drv_StateType *StatePtr = Can_Drv_StatePtr[Id];
    boolean CurInterStatus = (boolean)0U;

    if (((void *)0) == StatePtr->Mb[MbIdx].MbMessagePtr)
    {
        StatePtr->Mb[MbIdx].MbMessagePtr = &Data;
    }


    Can_Drv_GetMsgBuff(Id, MbIdx, StatePtr->Mb[MbIdx].MbMessagePtr);


    (void)Can_Drv_ClearMessageBufferIntFlag(Id, MbIdx);

    StatePtr->Mb[MbIdx].State = CAN_DRV_STATE_IDLE;

    CurInterStatus = StatePtr->Mb[MbIdx].IsPolling;

    if (StatePtr->IrqCallback != ((void *)0))
    {
        StatePtr->IrqCallback(Id, CAN_DRV_INT_MB_RECEIVE, MbIdx, StatePtr);
    }

    if (0U == StatePtr->Mb[MbIdx].IsPolling)
    {
        if (CAN_DRV_STATE_IDLE == StatePtr->Mb[MbIdx].State)
        {
            StatePtr->Mb[MbIdx].IsPolling = (boolean)1U;
            Can_Drv_ConfigMbInterrupt(Id, MbIdx, (boolean)0U, StatePtr->InterEn);
        }
    }
    else
    {
        if (0U == CurInterStatus)
        {
            Can_Drv_ConfigMbInterrupt(Id, MbIdx, (boolean)0U, StatePtr->InterEn);
        }
    }
}
# 4120 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_TxMbIrqHandler(uint8 Id, uint8 MbIdx)
{
    Can_Drv_StateType *StatePtr = Can_Drv_StatePtr[Id];
    boolean CurInterStatus = (boolean)0U;
    Can_Drv_MsgBufType Data;

    if (1U == StatePtr->Mb[MbIdx].RemoteFlag)
    {

        StatePtr->Mb[MbIdx].MbMessagePtr = &Data;
        Can_Drv_GetMsgBuff(Id, MbIdx, StatePtr->Mb[MbIdx].MbMessagePtr);




        if ((uint32)CAN_DRV_MB_RX_EMPTY ==
            (((StatePtr->Mb[MbIdx].MbMessagePtr)->Cs & ((uint32)0x0F000000U)) >>
             24U))
        {
            (void)Can_Drv_ClearMessageBufferIntFlag(Id, MbIdx);
        }
    }
    else
    {
        StatePtr->Mb[MbIdx].TimeStamp = Can_Drv_GetMsgBuffTimeStamp(Id, MbIdx);
        Can_Drv_UnlockRxMsgBuff(Id);
        (void)Can_Drv_ClearMessageBufferIntFlag(Id, MbIdx);
    }

    StatePtr->Mb[MbIdx].State = CAN_DRV_STATE_IDLE;

    CurInterStatus = StatePtr->Mb[MbIdx].IsPolling;

    if (StatePtr->IrqCallback != ((void *)0))
    {
        StatePtr->IrqCallback(Id, CAN_DRV_MB_TRANSMIT, MbIdx, StatePtr);
    }

    if (0U == StatePtr->Mb[MbIdx].IsPolling)
    {
        if (CAN_DRV_STATE_IDLE == StatePtr->Mb[MbIdx].State)
        {
            StatePtr->Mb[MbIdx].IsPolling = (boolean)1U;


            Can_Drv_ConfigMbInterrupt(Id, MbIdx, (boolean)0U, StatePtr->InterEn);
        }
    }
    else
    {
        if (0U == CurInterStatus)
        {
            Can_Drv_ConfigMbInterrupt(Id, MbIdx, (boolean)0U, StatePtr->InterEn);
        }
    }
}
# 4188 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
static void Can_Drv_ProcessMbAbnormalInter(uint8 Id, boolean IsAbnormal, uint32 StartMbIdx,
                                           uint32 EndMbIdx)
{
    uint32 MbCounter = 0;
    uint32 InterFlag = 0;
    boolean CanIntMask = 0U;
    uint32 MbIdx = 0U;
    Can_Drv_StateType *StatePtr = Can_Drv_StatePtr[Id];

    if (1U == IsAbnormal)
    {

        for (MbCounter = StartMbIdx; MbCounter <= EndMbIdx; MbCounter++)
        {
            CanIntMask = Can_Drv_GetMbInterruptState(Id, (uint8)MbCounter);
            InterFlag = Can_Drv_ReadMbInterruptFlag(Id, MbCounter);
            if (((uint8)0U != InterFlag) && (0U == CanIntMask))
            {
                MbIdx = MbCounter;
                if ((1U == StatePtr->RxFifoEn) && (MbCounter <= (7U)))
                {
                    MbIdx = (uint32)(0U);
                }
                if ((0U == StatePtr->Mb[MbIdx].IsPolling))
                {

                    (void)Can_Drv_ClearMessageBufferIntFlag(Id, MbCounter);
                    if (CAN_DRV_STATE_TX == StatePtr->Mb[MbIdx].State)
                    {

                        StatePtr->Mb[MbIdx].State = CAN_DRV_STATE_IDLE;
                        StatePtr->Mb[MbIdx].IsPolling = (boolean)1U;
                    }
                }
            }
        }
    }
}


# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1
# 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h"
#pragma clang section text = ""
# 4229 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2








# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1
# 1072 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h"
#pragma clang section text = ".mcal_code"
# 4238 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2
# 4252 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_AbortTransfer(uint8 Id, uint8 MbIdx)
{
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    Can_Drv_StateType *StatePtr;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 4262); break; };


    StatePtr = Can_Drv_StatePtr[Id];
    if (Can_Drv_CheckMbIdRange(Id, MbIdx) != CAN_DRV_SUCCESS)
    {
        ReturnValue = CAN_DRV_ERROR;
    }
    else
    {
        if (CAN_DRV_STATE_IDLE == StatePtr->Mb[MbIdx].State)
        {
            ReturnValue = CAN_DRV_NO_TRANSMIT;
        }
        else
        {

            Can_Drv_ConfigMbInterrupt(Id, MbIdx, (boolean)0U, StatePtr->InterEn);
            if (CAN_DRV_STATE_TX == StatePtr->Mb[MbIdx].State)
            {
                ReturnValue = Can_Drv_AbortTxTransfer(Id, MbIdx);
            }
            else if (CAN_DRV_STATE_RX == StatePtr->Mb[MbIdx].State)
            {
                (void)Can_Drv_AbortRxTransfer(Id, MbIdx);
            }
            else
            {

            }

            StatePtr->Mb[MbIdx].State = CAN_DRV_STATE_IDLE;
        }
    }


    break; };


    return ReturnValue;
}
# 4319 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_ConfigRxMb(uint8 Id, uint8 MbIdx, Can_Drv_MsgIdType IdType,
                                            uint32 MsgId)
{
    Can_Drv_ControllerStatus Result = CAN_DRV_ERROR;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 4329); break; };



    if (CAN_DRV_SUCCESS == Can_Drv_ClearMessageBufferIntFlag(Id, MbIdx))
    {

        if (CAN_DRV_SUCCESS == Can_Drv_SetRxMb(Id, MbIdx, IdType, MsgId, (uint32)CAN_DRV_NOT_USED))
        {

            if (CAN_DRV_SUCCESS ==
                Can_Drv_SetRxMb(Id, MbIdx, IdType, MsgId, (uint32)CAN_DRV_MB_RX_INACTIVE))
            {

                if (CAN_DRV_SUCCESS == Can_Drv_ClearMessageBufferIntFlag(Id, MbIdx))
                {
                    Result = Can_Drv_SetRxMb(Id, MbIdx, IdType, MsgId, (uint32)CAN_DRV_MB_RX_EMPTY);
                }
            }
        }
    }

    break; };


    return Result;
}
# 4369 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_Init(uint8 Id, Can_Drv_StateType *CanStatePtr,
                                      const Can_Drv_ConfigType *CanConfigPtr)
{
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    const volatile Reg_Can_BfType *CanRegisterBfPtr = ((void *)0);
    uint32 MbIndex;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 4381); break; };
    if ((boolean)(CanStatePtr != ((void *)0)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 4382); break; };
    if ((boolean)(CanConfigPtr != ((void *)0)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 4383); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];

    ReturnValue = Can_Drv_InitHandle(Id, CanConfigPtr);
    if (CAN_DRV_SUCCESS == ReturnValue)
    {
        for (MbIndex = 0; MbIndex <= (uint8)(CanRegisterBfPtr->CAN_MCR.MAXMB); MbIndex++)
        {
            CanStatePtr->Mb[MbIndex].IsPolling = (boolean)1U;
            CanStatePtr->Mb[MbIndex].MbMessagePtr = ((void *)0);
            CanStatePtr->Mb[MbIndex].State = CAN_DRV_STATE_IDLE;
            CanStatePtr->Mb[MbIndex].TimeStamp = 0U;
            CanStatePtr->Mb[MbIndex].RemoteFlag = (boolean)0U;
        }

        CanStatePtr->TransferType = CanConfigPtr->TransferType;

        CanStatePtr->IrqCallback = CanConfigPtr->IrqCallback;
        CanStatePtr->ErrCallback = CanConfigPtr->ErrCallback;
        CanStatePtr->RxFifoEn = CanConfigPtr->RxFifoEn;
        CanStatePtr->MaxMbNumber = CanConfigPtr->MbMaxNum;
        CanStatePtr->InterEn = (boolean)1U;

        CanStatePtr->RxFifoDMAChannel = CanConfigPtr->RxFifoDMAChannel;


        Can_Drv_StatePtr[Id] = CanStatePtr;
    }


    break; };


    return ReturnValue;
}
# 4432 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_Deinit(uint8 Id)
{
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_ERROR;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 4441); break; };


    ReturnValue = Can_Drv_EnterFreezeMode(Id);


    Can_Drv_ResetConfiguration(Id);
    if (CAN_DRV_SUCCESS == ReturnValue)
    {
        ReturnValue = Can_Drv_Disable(Id);

        Can_Drv_StatePtr[Id] = ((void *)0);
    }


    break; };


    return ReturnValue;
}
# 4472 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_DisableMbInterrupts(uint8 Id)
{
    Reg_Can_WType *CanRegisterWPtr;
    const volatile Reg_Can_BfType *CanRegisterBfPtr;
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_ERROR;
    Can_Drv_StateType *StatePtr;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 4484); break; };


    CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    StatePtr = Can_Drv_StatePtr[Id];

    if (0U == CanRegisterBfPtr->CAN_MCR.MDIS)
    {
        CanRegisterWPtr->CAN_IMASK1 = 0U;

        CanRegisterWPtr->CAN_IMASK2 = 0U;



        if (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id))
        {
            CanRegisterWPtr->CAN_IMASK3 = 0U;
        }



        if (((uint8)CAN_DRV_ID_6 == Id) || ((uint8)CAN_DRV_ID_7 == Id))
        {
            CanRegisterWPtr->CAN_IMASK4 = 0U;
        }

        StatePtr->InterEn = (boolean)0U;
        ReturnValue = CAN_DRV_SUCCESS;
    }


    break; };


    return ReturnValue;
}
# 4535 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_Receive(uint8 Id, uint8 MbIdx, Can_Drv_MsgBufType *DataPtr,
                                         boolean IsPolling)
{

    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    Can_Drv_StateType *StatePtr;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 4547); break; };


    StatePtr = Can_Drv_StatePtr[Id];
    if (Can_Drv_CheckMbIdRange(Id, MbIdx) != CAN_DRV_SUCCESS)
    {
        ReturnValue = CAN_DRV_ERROR;
    }
    else
    {
        if (StatePtr->Mb[MbIdx].State != CAN_DRV_STATE_IDLE)
        {
            ReturnValue = (Can_Drv_ControllerStatus)CAN_DRV_ENTER_BUSY;
        }
        else
        {
            StatePtr->Mb[MbIdx].State = CAN_DRV_STATE_RX;
            StatePtr->Mb[MbIdx].MbMessagePtr = DataPtr;
            StatePtr->Mb[MbIdx].IsPolling = IsPolling;
        }
    }


    if ((CAN_DRV_SUCCESS == ReturnValue) && (0U == IsPolling))
    {

        Can_Drv_ConfigMbInterrupt(Id, MbIdx, (boolean)1U, StatePtr->InterEn);
    }



    break; };


    return ReturnValue;
}
# 4596 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_RxFIFO(uint8 Id, Can_Drv_MsgBufType *DataPtr)
{
    Can_Drv_ControllerStatus resultVal = CAN_DRV_ERROR;
    Can_Drv_StateType *StatePtr;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 4606); break; };


    StatePtr = Can_Drv_StatePtr[Id];
    if (1U == StatePtr->RxFifoEn)
    {

        if (CAN_DRV_RXFIFO_DMA == StatePtr->TransferType)
        {
            if (CAN_DRV_STATE_DMA_ERROR == StatePtr->Mb[(0U)].State)
            {
                Can_Drv_ClearOutputRxFIFO(Id);


                StatePtr->Mb[(0U)].State = CAN_DRV_STATE_IDLE;
            }
        }


        if (StatePtr->Mb[(0U)].State != CAN_DRV_STATE_IDLE)
        {
            resultVal = (Can_Drv_ControllerStatus)CAN_DRV_ENTER_BUSY;
        }
        else
        {
            resultVal = CAN_DRV_SUCCESS;
            StatePtr->Mb[(0U)].State = CAN_DRV_STATE_RX;
            StatePtr->Mb[(0U)].MbMessagePtr = DataPtr;
            if (CAN_DRV_RXFIFO_POLLING == StatePtr->TransferType)
            {
                StatePtr->Mb[(0U)].IsPolling = (boolean)1U;
            }
            else if (CAN_DRV_RXFIFO_INTERRUPTS == StatePtr->TransferType)
            {
                StatePtr->Mb[(0U)].IsPolling = (boolean)0U;

                Can_Drv_ConfigMbInterrupt(Id, (5U), (boolean)1U,
                                          StatePtr->InterEn);
                Can_Drv_ConfigMbInterrupt(Id, (6U), (boolean)1U,
                                          StatePtr->InterEn);
                Can_Drv_ConfigMbInterrupt(Id, (7U), (boolean)1U,
                                          StatePtr->InterEn);
            }

            else if (CAN_DRV_RXFIFO_DMA == StatePtr->TransferType)
            {
                Can_Drv_ConfigDma(Id);
            }

            else
            {

            }
        }
    }


    break; };


    return resultVal;
}
# 4678 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
void Can_Drv_ClearErrorStatus(uint8 Id, uint32 Mask)
{
    Reg_Can_WType *CanRegisterWPtr;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 4687); break; };


    CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    CanRegisterWPtr->CAN_ESR1 = Mask;


    break; };

}
# 4708 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_EnableInterrupts(uint8 Id)
{
    const volatile Reg_Can_BfType *CanRegisterBfPtr;
    Can_Drv_ControllerStatus ReturnVal = CAN_DRV_ERROR;
    Can_Drv_StateType *StatePtr;
    uint32 Disable;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 4720); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    StatePtr = Can_Drv_StatePtr[Id];
    Disable = CanRegisterBfPtr->CAN_MCR.MDIS;
    if (0U == Disable)
    {
        Can_Drv_UnmaskInterrupt(Id);
        StatePtr->InterEn = (boolean)1U;
        ReturnVal = CAN_DRV_SUCCESS;
    }


    break; };


    return ReturnVal;
}
# 4750 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_DisableInterrupts(uint8 Id)
{
    const volatile Reg_Can_BfType *CanRegisterBfPtr;
    Can_Drv_StateType *StatePtr;
    uint32 Disable;
    Can_Drv_ControllerStatus ReturnVal = CAN_DRV_ERROR;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 4762); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    StatePtr = Can_Drv_StatePtr[Id];
    Disable = CanRegisterBfPtr->CAN_MCR.MDIS;

    if (0U == Disable)
    {
        Can_Drv_MaskInterrupt(Id);
        StatePtr->InterEn = (boolean)0U;
        ReturnVal = CAN_DRV_SUCCESS;
    }


    break; };


    return ReturnVal;
}
# 4794 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
uint32 Can_Drv_GetControllerErrorState(uint8 Id)
{
    uint32 Temp = 0U;
    const volatile Reg_Can_BfType *CanRegisterBfPtr;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 4804); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Temp = CanRegisterBfPtr->CAN_ESR1.FLTCONF;


    break; };



    return Temp;
}
# 4826 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
uint32 Can_Drv_GetControllerRxErrorCounter(uint8 Id)
{
    const volatile Reg_Can_BfType *CanRegisterBfPtr;
    uint32 Temp = 0U;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 4836); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Temp = (uint32)(CanRegisterBfPtr->CAN_ECR.RXERRCNT);


    break; };


    return Temp;
}
# 4857 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
uint32 Can_Drv_GetControllerTxErrorCounter(uint8 Id)
{
    uint32 Temp = 0U;
    const volatile Reg_Can_BfType *CanRegisterBfPtr;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 4867); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Temp = (uint32)(CanRegisterBfPtr->CAN_ECR.TXERRCNT);


    break; };


    return Temp;
}
# 4891 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_GetTransferStatus(uint8 Id, uint8 MbIdx)
{
    const Can_Drv_StateType *StatePtr;
    Can_Drv_ControllerStatus ReturnVal = CAN_DRV_ERROR;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 4901); break; };


    StatePtr = Can_Drv_StatePtr[Id];

    if (CAN_DRV_ERROR == Can_Drv_CheckMbIdRange(Id, MbIdx))
    {
        ReturnVal = CAN_DRV_ERROR;
    }
    else
    {
        if (CAN_DRV_STATE_IDLE == StatePtr->Mb[MbIdx].State)
        {
            ReturnVal = CAN_DRV_SUCCESS;
        }

        else if (CAN_DRV_STATE_DMA_ERROR == StatePtr->Mb[MbIdx].State)
        {
            ReturnVal = CAN_DRV_ERROR;
        }

        else
        {
            ReturnVal = CAN_DRV_ENTER_BUSY;
        }
    }


    break; };


    return ReturnVal;
}
# 4945 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_ManualBusOffRecovery(uint8 Id)
{
    Reg_Can_BfType *CanRegisterBfPtr;
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    uint32 TimeElapsedValue = 0U;
    uint32 TimeCounter = 0U;
    uint32 CurrentValue;
    uint32 CanTimeoutDuration;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 4959); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];

    if (1U == CanRegisterBfPtr->CAN_CTRL1.BOFFREC)
    {

        if (((CanRegisterBfPtr->CAN_ESR1.FLTCONF) & (0x00000002U)) != 0U)
        {
            SchM_Enter_Can_RecoveryBusOff();


            CanRegisterBfPtr->CAN_CTRL1.BOFFREC = 0U;


            CanRegisterBfPtr->CAN_CTRL1.BOFFREC = 1U;

            SchM_Exit_Can_RecoveryBusOff();

            CanTimeoutDuration =
                McalLib_MicroSecToTicks((MCALLIB_COUNTER_SOFTWARE), (1000000U));

            (void)McalLib_GetCounterValue((MCALLIB_COUNTER_SOFTWARE), &CurrentValue);
            while (((CanRegisterBfPtr->CAN_ESR1.FLTCONF) & (0x00000002U)) != 0U)
            {
                (void)McalLib_GetElapsedValue((MCALLIB_COUNTER_SOFTWARE), &CurrentValue,
                                              &TimeElapsedValue);
                TimeCounter += TimeElapsedValue;
                if (TimeCounter > CanTimeoutDuration)
                {
                    ReturnValue = CAN_DRV_ERROR;
                    break;
                }
            }
        }
    }


    break; };


    return ReturnValue;
}
# 5013 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
void Can_Drv_WriteMainFunction(uint8 Id, uint8 MbIdx)
{
    Can_Drv_StateType *StatePtr;
    const volatile Reg_Can_WType *CanRegisterWPtr;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5023); break; };


    StatePtr = Can_Drv_StatePtr[Id];
    CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    if (1U == Can_Drv_ReadMbInterruptFlag(Id, MbIdx))
    {
        StatePtr->Mb[MbIdx].TimeStamp = Can_Drv_GetTimeStamp(Id, MbIdx);

        (void)CanRegisterWPtr->CAN_TIMER;

        (void)Can_Drv_ClearMessageBufferIntFlag(Id, MbIdx);

        StatePtr->Mb[MbIdx].State = CAN_DRV_STATE_IDLE;
    }


    break; };

}
# 5053 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
void Can_Drv_ReadMainFunction(const uint8 Id, uint8 MbIdx)
{
    const Can_Drv_StateType *StatePtr;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5062); break; };


    StatePtr = Can_Drv_StatePtr[Id];

    if (CAN_DRV_SUCCESS == Can_Drv_CheckMbIdRange(Id, MbIdx))
    {
        if ((1U == StatePtr->RxFifoEn) && (MbIdx <= (7U)))
        {

            if ((uint8)(0U) == MbIdx)
            {
                if (1U == Can_Drv_ReadMbInterruptFlag(Id, (5U)))
                {
                    Can_Drv_RxFifoIrqHandler(Id, (5U));
                }
            }
        }
        else
        {
            if (1U == Can_Drv_ReadMbInterruptFlag(Id, MbIdx))
            {

                if (CAN_DRV_STATE_RX == StatePtr->Mb[MbIdx].State)
                {
                    Can_Drv_RxMbIrqHandler(Id, MbIdx);
                }
            }
        }
    }


    break; };

}
# 5108 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_BusOffMainFunction(uint8 Id)
{
    Reg_Can_WType *CanRegisterWPtr;
    const volatile Reg_Can_BfType *CanRegisterBfPtr;
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_ERROR;
    const Can_Drv_StateType *StatePtr;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5120); break; };


    CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    StatePtr = Can_Drv_StatePtr[Id];
    if (0U != (CanRegisterBfPtr->CAN_ESR1.FLTCONF & 0x02U))
    {
        if (((void *)0) != StatePtr->ErrCallback)
        {
            StatePtr->ErrCallback(Id, CAN_DRV_INT_BUS_OFF, CanRegisterWPtr->CAN_ESR1);
        }

        CanRegisterWPtr->CAN_ESR1 = (uint32)(((uint32)1U << 2U));

        ReturnValue = CAN_DRV_SUCCESS;
    }


    break; };


    return ReturnValue;
}
# 5155 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_WakeupMainFunction(uint8 Id)
{
    Reg_Can_WType *CanRegisterWPtr;
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_ERROR;
    const Can_Drv_StateType *StatePtr;
    uint32 Status;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5167); break; };


    CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    StatePtr = Can_Drv_StatePtr[Id];
    Status = CanRegisterWPtr->CAN_ESR1;

    CanRegisterWPtr->CAN_ESR1 = 1U;

    if (((void *)0) != StatePtr)
    {
        if ((uint32)0U != (Status & ((uint32)1U)))
        {
            if (((void *)0) != StatePtr->ErrCallback)
            {
                StatePtr->ErrCallback(Id, CAN_DRV_INT_SELF_WAKEUP, Status);
            }
            ReturnValue = CAN_DRV_SUCCESS;
        }
    }


    break; };


    return ReturnValue;
}
# 5207 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_ConfigErrorInterrupt(uint8 Id, Can_Drv_IntType IntType,
                                                      boolean Enable)
{
    const volatile Reg_Can_BfType *CanRegisterBfPtr;
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    uint8 Disabled;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5219); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    Disabled = (uint8)CanRegisterBfPtr->CAN_MCR.MDIS;

    if (1U == Disabled)
    {
        ReturnValue = Can_Drv_Enable(Id);
    }

    if (CAN_DRV_SUCCESS == ReturnValue)
    {
        ReturnValue = Can_Drv_SetErrorInterruptState(Id, IntType, Enable);
    }

    if (1U == Disabled)
    {
        if (CAN_DRV_SUCCESS != Can_Drv_Disable(Id))
        {
            ReturnValue = CAN_DRV_ERROR;
        }
    }


    break; };


    return ReturnValue;
}
# 5261 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_SetStdBitTiming(uint8 Id, const Can_Drv_BitTimingType *RatePtr)
{
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5270); break; };
    if ((boolean)(RatePtr != ((void *)0)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5271); break; };


    ReturnValue = Can_Drv_EnterFreezeMode(Id);
    if (CAN_DRV_SUCCESS == ReturnValue)
    {
        (void)Can_Drv_SetStandardBitTiming(Id, RatePtr);

        ReturnValue = Can_Drv_ExitFreezeMode(Id);
    }


    break; };


    return ReturnValue;
}
# 5300 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_SetFdArbBitTiming(uint8 Id, const Can_Drv_BitTimingType *RatePtr)
{
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5309); break; };
    if ((boolean)(RatePtr != ((void *)0)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5310); break; };


    ReturnValue = Can_Drv_EnterFreezeMode(Id);
    if (CAN_DRV_SUCCESS == ReturnValue)
    {
        (void)Can_Drv_SetFdArbitrationBitTiming(Id, RatePtr);

        ReturnValue = Can_Drv_ExitFreezeMode(Id);
    }


    break; };


    return ReturnValue;
}
# 5339 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_SetFdDataBitTiming(uint8 Id, const Can_Drv_BitTimingType *RatePtr)
{
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5348); break; };
    if ((boolean)(RatePtr != ((void *)0)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5349); break; };


    ReturnValue = Can_Drv_EnterFreezeMode(Id);
    if (CAN_DRV_SUCCESS == ReturnValue)
    {
        (void)Can_Drv_ConfigFdDataBitTiming(Id, RatePtr);

        ReturnValue = Can_Drv_ExitFreezeMode(Id);
    }


    break; };


    return ReturnValue;
}
# 5378 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_SetRxMaskType(uint8 Id, Can_Drv_RxMaskType MaskType)
{
    Reg_Can_BfType *CanRegisterBfPtr;
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5388); break; };

    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];

    ReturnValue = Can_Drv_EnterFreezeMode(Id);
    if (CAN_DRV_SUCCESS == ReturnValue)
    {

        SchM_Enter_Can_CanMcrReg();
        CanRegisterBfPtr->CAN_MCR.IRMQ = (uint32)MaskType;

        SchM_Exit_Can_CanMcrReg();

        ReturnValue = Can_Drv_ExitFreezeMode(Id);
    }


    break; };


    return ReturnValue;
}
# 5423 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
boolean Can_Drv_GetMbInterruptFlag(uint8 Id, uint8 MbIdx)
{
    boolean ReturnVal = 1U;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5432); break; };


    ReturnVal = Can_Drv_ReadMbInterruptFlag(Id, MbIdx);


    break; };


    return ReturnVal;
}
# 5453 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
void Can_Drv_ClearMbIntStatus(uint8 Id, uint8 MbIdx)
{

    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5460); break; };


    (void)Can_Drv_ClearMessageBufferIntFlag(Id, MbIdx);


    break; };

}
# 5480 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
boolean Can_Drv_CheckStartedMode(uint8 Id)
{
    const volatile Reg_Can_BfType *CanRegisterBfPtr;
    boolean Temp = (boolean)0U;
    uint8 CanLpmackSts = 0;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5491); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    CanLpmackSts = (uint8)CanRegisterBfPtr->CAN_MCR.LPMACK;
    if ((0U == (CanRegisterBfPtr->CAN_MCR.FRZACK)) && (0U == CanLpmackSts))
    {
        Temp = (boolean)1U;
    }


    break; };


    return Temp;
}
# 5517 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
boolean Can_Drv_CheckStoppedMode(uint8 Id)
{
    const volatile Reg_Can_BfType *CanRegisterBfPtr;
    boolean Temp = (boolean)0U;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5527); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    if (1U == (CanRegisterBfPtr->CAN_MCR.LPMACK))
    {
        Temp = (boolean)1U;
    }


    break; };


    return Temp;
}
# 5553 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_SetStartMode(uint8 Id)
{
    Reg_Can_BfType *CanRegisterBfPtr;
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5563); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];

    SchM_Enter_Can_CanMcrReg();

    CanRegisterBfPtr->CAN_MCR.MDIS = 0U;

    SchM_Exit_Can_CanMcrReg();
    ReturnValue = Can_Drv_ExitFreezeMode(Id);


    break; };


    return ReturnValue;
}
# 5592 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_SetStopMode(uint8 Id)
{
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5601); break; };


    ReturnValue = Can_Drv_EnterFreezeMode(Id);
    if (CAN_DRV_SUCCESS == ReturnValue)
    {
        ReturnValue = Can_Drv_Disable(Id);
    }


    break; };


    return ReturnValue;
}
# 5629 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_ConfigRxFifo(uint8 Id, Can_Drv_RxAcceptanceType Element,
                                              const Can_Drv_IdFilterType *FilterTablePtr)
{
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5639); break; };


    ReturnValue = Can_Drv_EnterFreezeMode(Id);
    if (CAN_DRV_SUCCESS == ReturnValue)
    {
        Can_Drv_ConfigRxFifoFilter(Id, Element, FilterTablePtr);

        ReturnValue = Can_Drv_ExitFreezeMode(Id);
    }


    break; };


    return ReturnValue;
}
# 5673 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_SendData(uint8 Id, uint8 MbIdx,
                                          const Can_Drv_MessageInfoType *TxInfoPtr,
                                          boolean IsPolling, uint32 MsgId, const uint8 *MsgDataPtr)
{
    const volatile Reg_Can_BfType *CanRegisterBfPtr;
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;
    Can_Drv_FdMbRegionType Region;
    Can_Drv_MbType *MbAddrPtr;
    uint32 ListenMode;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5688); break; };
    if ((boolean)(TxInfoPtr != ((void *)0)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5689); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    ListenMode = CanRegisterBfPtr->CAN_CTRL1.LOM;
    if (0U == ListenMode)
    {
        if (CAN_DRV_ERROR == Can_Drv_GetMbAddr(Id, MbIdx, &Region, &MbAddrPtr))
        {
            ReturnValue = CAN_DRV_ERROR;
        }
        else
        {
            if (CAN_DRV_ERROR == Can_Drv_CheckMbId(Id, MbIdx))
            {
                ReturnValue = CAN_DRV_ERROR;
            }
            else
            {
                ReturnValue = Can_Drv_ProcessTxMb(MbAddrPtr, Id, MbIdx, TxInfoPtr, IsPolling, MsgId,
                                                  MsgDataPtr);
            }
        }
    }
    else
    {
        ReturnValue = CAN_DRV_ERROR;
    }


    break; };


    return ReturnValue;
}
# 5738 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_SetRxIndividualMask(uint8 Id, Can_Drv_MsgIdType IdType,
                                                     uint32 MbIdx, uint32 Mask)
{
    Reg_Can_WType *CanRegisterWPtr;
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5749); break; };


    CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    if (Can_Drv_CheckMbId(Id, MbIdx) != CAN_DRV_SUCCESS)
    {
        ReturnValue = CAN_DRV_ERROR;
    }
    else
    {
        ReturnValue = Can_Drv_EnterFreezeMode(Id);

        if (CAN_DRV_SUCCESS == ReturnValue)
        {
            if (IdType == CAN_DRV_MSG_ID_STD)
            {
                CanRegisterWPtr->CAN_RXIMR[MbIdx] = ((Mask)&0xDFFC0000U);
            }
            else
            {
                CanRegisterWPtr->CAN_RXIMR[MbIdx] = ((Mask)&0xDFFFFFFFU);
            }

            ReturnValue = Can_Drv_ExitFreezeMode(Id);
        }
    }


    break; };

    return ReturnValue;
}
# 5809 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_SetRxFifoGlobalMask(uint8 Id, uint32 Mask)
{
    Reg_Can_BfType *CanRegisterBfPtr;
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5819); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    ReturnValue = Can_Drv_EnterFreezeMode(Id);
    if (CAN_DRV_SUCCESS == ReturnValue)
    {
        if (0U != CanRegisterBfPtr->CAN_MCR.RFEN)
        {
            SchM_Enter_Can_CanRxmgMskReg();
            CanRegisterBfPtr->CAN_RXMGMSK.MG = Mask;
            SchM_Exit_Can_CanRxmgMskReg();
        }

        ReturnValue = Can_Drv_ExitFreezeMode(Id);
    }


    break; };


    return ReturnValue;
}
# 5853 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_EnableArbitrationFiledCompare(uint8 Id)
{
    Reg_Can_BfType *CanRegisterBfPtr;
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5863); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    ReturnValue = Can_Drv_EnterFreezeMode(Id);

    if (CAN_DRV_SUCCESS == ReturnValue)
    {
        CanRegisterBfPtr->CAN_CTRL2.EACEN = 1U;

        ReturnValue = Can_Drv_ExitFreezeMode(Id);
    }


    break; };


    return ReturnValue;
}
# 5916 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_SetRxFifoIndividualMask(uint8 Id, uint32 ElementIdx, uint32 Mask)
{
    Reg_Can_WType *CanRegisterWPtr;
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5926); break; };


    CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];

    ReturnValue = Can_Drv_EnterFreezeMode(Id);
    if (CAN_DRV_SUCCESS == ReturnValue)
    {
        CanRegisterWPtr->CAN_RXIMR[ElementIdx] = Mask;

        ReturnValue = Can_Drv_ExitFreezeMode(Id);
    }


    break; };


    return ReturnValue;
}
# 5962 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_SetFdTdc(uint8 Id, boolean Enable, uint8 Offset)
{
    Reg_Can_BfType *CanRegisterBfPtr;
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 5972); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    ReturnValue = Can_Drv_EnterFreezeMode(Id);

    if (CAN_DRV_SUCCESS == ReturnValue)
    {

        SchM_Enter_Can_ConfigFdCompensation();
        CanRegisterBfPtr->CAN_FDCTRL.TDCEN = (uint32)Enable;
        CanRegisterBfPtr->CAN_FDCTRL.TDCOFF = (uint32)Offset;

        SchM_Exit_Can_ConfigFdCompensation();

        ReturnValue = Can_Drv_ExitFreezeMode(Id);
    }


    break; };


    return ReturnValue;
}
# 6008 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_SetTxArbitrationDelay(uint8 Id, uint8 Value)
{
    Reg_Can_BfType *CanRegisterBfPtr;
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 6018); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];
    ReturnValue = Can_Drv_EnterFreezeMode(Id);

    if (CAN_DRV_SUCCESS == ReturnValue)
    {

        SchM_Enter_Can_SetTxArbitrationDelay();
        CanRegisterBfPtr->CAN_CTRL2.TASD = (uint32)Value;

        SchM_Exit_Can_SetTxArbitrationDelay();

        ReturnValue = Can_Drv_ExitFreezeMode(Id);
    }


    break; };


    return ReturnValue;
}
# 6052 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_EnableSelfWakeup(uint8 Id)
{
    Reg_Can_BfType *CanRegisterBfPtr;
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 6062); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];

    ReturnValue = Can_Drv_EnterFreezeMode(Id);
    if (CAN_DRV_SUCCESS == ReturnValue)
    {

        SchM_Enter_Can_SetSelfWakeup();

        CanRegisterBfPtr->CAN_MCR.SLFWAK = 1;
        CanRegisterBfPtr->CAN_MCR.WAKSRC = 1;
        CanRegisterBfPtr->CAN_MCR.WAKMSK = 1;

        SchM_Exit_Can_SetSelfWakeup();

        ReturnValue = Can_Drv_ExitFreezeMode(Id);
    }


    break; };


    return ReturnValue;
}
# 6099 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_DisableSelfWakeup(uint8 Id)
{
    Reg_Can_BfType *CanRegisterBfPtr;
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_SUCCESS;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 6109); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];

    ReturnValue = Can_Drv_EnterFreezeMode(Id);
    if (CAN_DRV_SUCCESS == ReturnValue)
    {

        SchM_Enter_Can_SetSelfWakeup();

        CanRegisterBfPtr->CAN_MCR.SLFWAK = 0;
        CanRegisterBfPtr->CAN_MCR.WAKMSK = 0;

        SchM_Exit_Can_SetSelfWakeup();

        ReturnValue = Can_Drv_ExitFreezeMode(Id);
    }


    break; };


    return ReturnValue;
}
# 6145 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_InjectCorrectableAddress(uint8 Id)
{
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_ERROR;
    Reg_Can_BfType *CanRegisterBfPtr ;
    uint32 const volatile* CanReadRam;
    uint32 CanReadAddr;

    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 6156); break; };


    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];

    CanRegisterBfPtr->CAN_CTRL2.ECRWRE = 1;
    CanRegisterBfPtr->CAN_MECR.ECRWRDIS = 0;


    CanRegisterBfPtr->CAN_MECR.HAERRI = 1;
    CanRegisterBfPtr->CAN_MECR.FAERRIE = 1;


    if(CAN_DRV_SUCCESS == Can_Drv_EnterFreezeMode(Id))
    {

        CanRegisterBfPtr->CAN_CTRL2.WRMFRZ = 1;

        CanRegisterBfPtr->CAN_ERRIAR.INJADDR_H = ( (uint32)0xE0>> 2U);

        CanRegisterBfPtr->CAN_ERRIDPR.DFLIP = (0x00000001U);
        CanReadRam = (uint32 *)((uint32)CanRegisterBfPtr + 0x80U + 0xE0U);
        (void)*CanReadRam;

        if(1U == CanRegisterBfPtr->CAN_ERRSR.CEIF)
        {
            CanReadAddr = CanRegisterBfPtr->CAN_RERRAR.ERRADDR;
            if( 0xE0U == CanReadAddr)
            {

                ReturnValue = CAN_DRV_SUCCESS;
            }
            CanRegisterBfPtr->CAN_ERRSR.CEIF = 1;

        }


        CanRegisterBfPtr->CAN_ERRIDPR.DFLIP = (0x00000000U);

        if(CAN_DRV_SUCCESS == ReturnValue)
        {

            CanRegisterBfPtr->CAN_ERRIPPR.PFLIP0 = (0x00000001U);

            CanReadRam = (uint32 *)((uint32)CanRegisterBfPtr + 0x80U + 0xE0U);
            (void)*CanReadRam;
            ReturnValue = CAN_DRV_ERROR;

            if(1U == CanRegisterBfPtr->CAN_ERRSR.CEIF)
            {
                CanReadAddr = CanRegisterBfPtr->CAN_RERRAR.ERRADDR;
                if( 0xE0U == CanReadAddr)
                {

                    ReturnValue = CAN_DRV_SUCCESS;

                }
                CanRegisterBfPtr->CAN_ERRSR.CEIF = 1;
            }

            CanRegisterBfPtr->CAN_ERRIPPR.PFLIP0 = (0x00000000U);
            CanRegisterBfPtr->CAN_ERRIAR.INJADDR_H = 0U;
        }

        CanRegisterBfPtr->CAN_CTRL2.WRMFRZ = 0;

        CanRegisterBfPtr->CAN_MECR.ECRWRDIS = 0;
        CanRegisterBfPtr->CAN_MECR.HAERRI = 0;
        CanRegisterBfPtr->CAN_MECR.FAERRIE = 0;
        CanRegisterBfPtr->CAN_CTRL2.ECRWRE = 0;
        CanRegisterBfPtr->CAN_MECR.ECRWRDIS = 1;

        if(CAN_DRV_SUCCESS == ReturnValue)
        {
            ReturnValue = Can_Drv_ExitFreezeMode(Id);
        }
        else
        {
            (void)Can_Drv_ExitFreezeMode(Id);
        }

    }


    break; };


    return ReturnValue;

}
# 6257 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_InjectAddress(uint8 Id)
{
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_ERROR;
    Reg_Can_BfType *CanRegisterBfPtr ;
    uint32 const volatile* CanReadRam;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 6268); break; };



    uint32 *const ShcsrAddr = (uint32 *)0xE000ED24U;
    uint32 ShcsrOriginalVal = *ShcsrAddr;


    *ShcsrAddr |= 0x70000U;

    CanRegisterBfPtr = Can_Drv_CanRegBfPtr[Id];

    CanRegisterBfPtr->CAN_CTRL2.ECRWRE = 1;
    CanRegisterBfPtr->CAN_MECR.ECRWRDIS = 0;


    CanRegisterBfPtr->CAN_MECR.HAERRI = 1;
    CanRegisterBfPtr->CAN_MECR.FAERRIE = 1;


    if(CAN_DRV_SUCCESS == Can_Drv_EnterFreezeMode(Id))
    {

        CanRegisterBfPtr->CAN_CTRL2.WRMFRZ = 1;

        CanRegisterBfPtr->CAN_ERRIAR.INJADDR_H = ( (uint32)0xE0>> 2U);

        CanRegisterBfPtr->CAN_ERRIDPR.DFLIP = (0x00000001U);
        CanRegisterBfPtr->CAN_ERRIPPR.PFLIP0 = (0x00000001U);
        CanReadRam = (uint32 *)((uint32)CanRegisterBfPtr + 0x80U + 0xE0U);
        (void)*CanReadRam;


        *ShcsrAddr = ShcsrOriginalVal;

        ReturnValue = Can_Drv_ExitFreezeMode(Id);
    }


    break; };


    return ReturnValue;
}
# 6323 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
Can_Drv_ControllerStatus Can_Drv_ClearInjection(uint8 Id)
{
    Can_Drv_ControllerStatus ReturnValue = CAN_DRV_ERROR;
    Reg_Can_BfType *CanRegisterBfPtr;
    uint32 CanReadAddr;

    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 6333); break; };

    CanRegisterBfPtr =Can_Drv_CanRegBfPtr[Id];


    if((1U == CanRegisterBfPtr->CAN_ERRSR.FANCEIF) ||
    (1U == CanRegisterBfPtr->CAN_ERRSR.HANCEIF))
    {
        CanReadAddr = CanRegisterBfPtr->CAN_RERRAR.ERRADDR;
        if( 0xE0U == CanReadAddr)
        {

            ReturnValue = CAN_DRV_SUCCESS;
        }


        CanRegisterBfPtr->CAN_ERRSR.FANCEIF = 1;
        CanRegisterBfPtr->CAN_ERRSR.HANCEIF = 1;

        CanRegisterBfPtr->CAN_ERRIDPR.DFLIP = (0x00000000U);
        CanRegisterBfPtr->CAN_ERRIPPR.PFLIP0 = (0x00000000U);

        CanRegisterBfPtr->CAN_ERRIAR.INJADDR_H = 0U;
        CanRegisterBfPtr->CAN_CTRL2.WRMFRZ = 0;

        CanRegisterBfPtr->CAN_MECR.ECRWRDIS = 0;
        CanRegisterBfPtr->CAN_MECR.HAERRI = 0;
        CanRegisterBfPtr->CAN_MECR.FAERRIE = 0;
        CanRegisterBfPtr->CAN_CTRL2.ECRWRE = 0;
        CanRegisterBfPtr->CAN_MECR.ECRWRDIS = 1;
    }


    break; };


    return ReturnValue;
}
# 6382 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
void Can_Drv_IntHandler(uint8 Id, uint32 StartMbIdx, uint32 EndMbIdx)
{
    const Can_Drv_StateType *StatePtr;

    boolean IsSpuriousInt = (boolean)1U;
    uint32 MbCounter = EndMbIdx;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 6394); break; };


    StatePtr = Can_Drv_StatePtr[Id];
    if (((void *)0) != StatePtr)
    {

        IsSpuriousInt = Can_Drv_ProcessMbIrqSource(Id, StartMbIdx, EndMbIdx);


        Can_Drv_ProcessMbAbnormalInter(Id, IsSpuriousInt, StartMbIdx, EndMbIdx);
    }
    else
    {

        for (MbCounter = StartMbIdx; MbCounter <= EndMbIdx; MbCounter++)
        {

            (void)Can_Drv_ClearMessageBufferIntFlag(Id, MbCounter);
        }
    }


    break; };

}
# 6429 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
void Can_Drv_BusOffIntHandler(uint8 Id)
{
    const Can_Drv_StateType *StatePtr;
    Reg_Can_WType *CanRegisterWPtr;
    uint32 CanIntMask = 0U;
    uint32 Status;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 6441); break; };


    StatePtr = Can_Drv_StatePtr[Id];
    CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    Status = CanRegisterWPtr->CAN_ESR1;


    CanRegisterWPtr->CAN_ESR1 = (0x4U);

    if (((void *)0) != StatePtr)
    {
        CanIntMask = CanRegisterWPtr->CAN_CTRL1 & ((uint32)(0x8000U));
        if (((uint32)0U != (Status & ((uint32)(0x4U)))) &&
            ((uint32)0U != CanIntMask))
        {
            if (((void *)0) != StatePtr->ErrCallback)
            {
                StatePtr->ErrCallback(Id, CAN_DRV_INT_BUS_OFF, Status);
            }
        }
    }


    break; };

}
# 6477 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
void Can_Drv_TxWarnIntHandler(uint8 Id)
{
    const Can_Drv_StateType *StatePtr;
    Reg_Can_WType *CanRegisterWPtr;
    uint32 Status;
    uint32 CanIntMask = 0U;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 6489); break; };


    StatePtr = Can_Drv_StatePtr[Id];
    CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    Status = CanRegisterWPtr->CAN_ESR1;

    CanRegisterWPtr->CAN_ESR1 = ((uint32)1U << 17U);

    if (((void *)0) != StatePtr)
    {

        CanIntMask = CanRegisterWPtr->CAN_CTRL1 & ((uint32)((uint32)1U << 11U));
        if (((uint32)0U != (Status & ((uint32)((uint32)1U << 17U)))) &&
            ((uint32)0U != CanIntMask))
        {
            if (((void *)0) != StatePtr->ErrCallback)
            {
                StatePtr->ErrCallback(Id, CAN_DRV_INT_TXW, Status);
            }
        }
    }


    break; };

}
# 6525 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
void Can_Drv_RxWarnIntHandler(uint8 Id)
{
    const Can_Drv_StateType *StatePtr;
    Reg_Can_WType *CanRegisterWPtr;
    uint32 Status;
    uint32 CanIntMask = 0U;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 6537); break; };


    StatePtr = Can_Drv_StatePtr[Id];
    CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    Status = CanRegisterWPtr->CAN_ESR1;

    CanRegisterWPtr->CAN_ESR1 = ((uint32)1U << 16U);

    if (((void *)0) != StatePtr)
    {
        CanIntMask = CanRegisterWPtr->CAN_CTRL1 & ((uint32)((uint32)1U << 10U));
        if (((uint32)0U != (Status & ((uint32)((uint32)1U << 16U)))) &&
            ((uint32)0U != CanIntMask))
        {
            if (((void *)0) != StatePtr->ErrCallback)
            {
                StatePtr->ErrCallback(Id, CAN_DRV_INT_RXW, Status);
            }
        }
    }


    break; };

}
# 6572 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
void Can_Drv_ErrorIntHandler(uint8 Id)
{

    const Can_Drv_StateType *StatePtr;
    Reg_Can_WType *CanRegisterWPtr;
    uint32 Status;
    uint32 CanIntMask = 0U;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 6585); break; };


    StatePtr = Can_Drv_StatePtr[Id];
    CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    Status = CanRegisterWPtr->CAN_ESR1;


    CanRegisterWPtr->CAN_ESR1 = ((uint32)1U << 1U);

    if (((void *)0) != StatePtr)
    {
        CanIntMask = CanRegisterWPtr->CAN_CTRL1 & ((uint32)((uint32)1U << 14U));
        if (((uint32)0U != (Status & ((uint32)((uint32)1U << 1U)))) &&
            ((uint32)0U != CanIntMask))
        {
            if (((void *)0) != StatePtr->ErrCallback)
            {
                StatePtr->ErrCallback(Id, CAN_DRV_INT_ERR, Status);
            }
        }
    }


    break; };

}
# 6621 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
void Can_Drv_FdErrorIntHandler(uint8 Id)
{
    const Can_Drv_StateType *StatePtr;
    Reg_Can_WType *CanRegisterWPtr;
    uint32 Status;
    uint32 CanIntMask = 0U;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 6633); break; };


    StatePtr = Can_Drv_StatePtr[Id];
    CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    Status = CanRegisterWPtr->CAN_ESR1;

    CanRegisterWPtr->CAN_ESR1 = ((uint32)1U << 20U);

    if (((void *)0) != StatePtr)
    {
        CanIntMask = CanRegisterWPtr->CAN_CTRL2 & ((uint32)((uint32)1U << 31U));
        if (((uint32)0U != (Status & ((uint32)((uint32)1U << 20U)))) &&
            ((uint32)0U != CanIntMask))
        {
            if (((void *)0) != StatePtr->ErrCallback)
            {
                StatePtr->ErrCallback(Id, CAN_DRV_INT_ERR_FAST, Status);
            }
        }
    }


    break; };

}
# 6668 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
void Can_Drv_WakeUpIntHandler(uint8 Id)
{
    const Can_Drv_StateType *StatePtr;
    Reg_Can_WType *CanRegisterWPtr;
    uint32 Status;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 6679); break; };


    StatePtr = Can_Drv_StatePtr[Id];
    CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    Status = CanRegisterWPtr->CAN_ESR1;

    CanRegisterWPtr->CAN_ESR1 = 1U;

    if (((void *)0) != StatePtr)
    {
        if ((uint32)0U != (Status & ((uint32)1U)))
        {
            if (((void *)0) != StatePtr->ErrCallback)
            {
                StatePtr->ErrCallback(Id, CAN_DRV_INT_SELF_WAKEUP, Status);
            }
        }
    }


    break; };

}
# 6712 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
void Can_Drv_EccIntHandler(uint8 Id)
{
    const Can_Drv_StateType *StatePtr;
    Reg_Can_WType *CanRegisterWPtr;
    uint32 Status;


    while (1U) {;



    if ((boolean)(Id < (8U)) == (boolean)0U) { McalLib_Assert((uint8 *)"../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c", 6723); break; };


    StatePtr = Can_Drv_StatePtr[Id];
    CanRegisterWPtr = Can_Drv_CanRegWPtr[Id];
    Status = CanRegisterWPtr->CAN_ERRSR;

    Status = Status & (CanRegisterWPtr->CAN_MECR & (((uint32)1U << 19U) | ((uint32)1U << 18U) | ((uint32)1U << 16U)));

    CanRegisterWPtr->CAN_ERRSR = Status;


    CanRegisterWPtr->CAN_ERRSR = (Status >> 16U);

    if (((void *)0) != StatePtr)
    {

        if (((uint32)0U != (Status & ((uint32)((uint32)1U << 19U)))))
        {
            if (((void *)0) != StatePtr->ErrCallback)
            {
                StatePtr->ErrCallback(Id, CAN_DRV_INT_HOST_MEM_ERR, Status);
            }
        }

        if (((uint32)0U != (Status & ((uint32)((uint32)1U << 18U)))))
        {
            if (((void *)0) != StatePtr->ErrCallback)
            {
                StatePtr->ErrCallback(Id, CAN_DRV_INT_MEM_ERR, Status);
            }
        }

        if (((uint32)0U != (Status & ((uint32)((uint32)1U << 16U)))))
        {
            if (((void *)0) != StatePtr->ErrCallback)
            {
                StatePtr->ErrCallback(Id, CAN_DRV_INT_COR_MEM_ERR, Status);
            }
        }
    }


    break; };

}
# 6782 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
void Can_Drv_1_IntHandler(void);
# 6812 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
void Can_Drv_1_IntHandler(void)
{
    Can_Drv_CallbackForDma(1);
}
# 6856 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c"
# 1 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h" 1
# 1088 "../../../mcal/Base_ZX_K14xM/Inc/MemMap\\Can_MemMap.h"
#pragma clang section text = ""
# 6857 "../../../mcal/Can_ZX_K14xM/Src/Can_Drv.c" 2