//***************************************************************************** //KOTEI www.kotei.com.cn //----------------------------------------------------------------------------- /// \file Cdd_bd18397.h /// /// \brief API for Cdd_bd18397 /// /// \author No 7945 , Jamewang //----------------------------------------------------------------------------- #include "Platform.h" #include "Spi.h" #ifndef CDD_BD18397_2023_10_09_H_ #define CDD_BD18397_2023_10_09_H_ #define HWUnit 1 #define CDDBD18397RUV_Cfg_NbOfDevices 4 #define CDDBD18397RUV_NbOfChannel 2 #define CDDBD18397RUV_CFG_NUMBER_OF_CHANNELS CDDBD18397RUV_Cfg_NbOfDevices * CDDBD18397RUV_NbOfChannel #define CDDBD18397RUV_SPI_DATA_LENGTH (16U) //16 BYTES /** * @brief definition for Register Address */ #define CDDBD18397RUV_SYSTEM_REGISTER 0x00 #define CDDBD18397RUV_ERRSET1_REGISTER 0x02 #define CDDBD18397RUV_DIMSET_REGISTER 0x03 #define CDDBD18397RUV_ISET1H_REGISTER 0x04 //CH1 #define CDDBD18397RUV_ISET1L_REGISTER 0x05 //CH1 #define CDDBD18397RUV_ISET2H_REGISTER 0x06 //CH2 #define CDDBD18397RUV_ISET2L_REGISTER 0x07 //CH2 #define CDDBD18397RUV_DPWM1H_REGISTER 0x0A //CH1 #define CDDBD18397RUV_DPWM1L_REGISTER 0x0B //CH1 #define CDDBD18397RUV_DPWM2H_REGISTER 0x0C //CH2 #define CDDBD18397RUV_DPWM2L_REGISTER 0x0D //CH2 #define CDDBD18397RUV_DCDCSET1_REGISTER 0x10 //CH1 #define CDDBD18397RUV_DCDCSET2_REGISTER 0x11 //CH2 #define CDDBD18397RUV_DCDCSET4_REGISTER 0x13 #define CDDBD18397RUV_CHEN_REGISTER 0x14 #define CDDBD18397RUV_ADSEL_REGISTER 0x15 #define CDDBD18397RUV_VMONH_REGISTER 0x16 #define CDDBD18397RUV_VMONL_REGISTER 0x17 #define CDDBD18397RUV_ERRSTALL_REGISTER 0x18 #define CDDBD18397RUV_ERRST1_REGISTER 0x19 #define CDDBD18397RUV_ERRST2_REGISTER 0x1A #define CDDBD18397RUV_ReadCmdBit 0x7F // MSB (registor address 8 bit) set to '0' #define CDDBD18397RUV_WriteCmdBit_Tx 0x80 // MSB (registor address 8 bit) set to '1' #define CDDBD18397RUV_REGISTOR_MAX_NUMBER 21 typedef enum { ID_SYSTEM_REGISTER =0, ID_ERRSET1_REGISTER, ID_DIMSET_REGISTER, ID_ISET1H_REGISTER, ID_ISET1L_REGISTER, ID_ISET2H_REGISTER, ID_ISET2L_REGISTER, ID_DPWM1H_REGISTER, ID_DPWM1L_REGISTER, ID_DPWM2H_REGISTER, ID_DPWM2L_REGISTER, ID_DCDCSET1_REGISTER, ID_DCDCSET2_REGISTER, ID_DCDCSET4_REGISTER, ID_CHEN_REGISTER, ID_ADSEL_REGISTER, ID_VMONH_REGISTER, ID_VMONL_REGISTER, ID_ERRSTALL_REGISTER, ID_ERRST1_REGISTER, ID_ERRST2_REGISTER, ID_MAX_REGISTER, }registor_index_t; typedef enum { CDDBD18397RUV_READ_MODE, /*Reg read mode */ CDDBD18397RUV_WRITE_MODE, /*Reg write mode */ }read_write_mode_t; typedef enum { ADSEL_Thermal =0, ADSEL_VIN , ADSEL_V5VEXT, ADSEL_VPIN, ADSEL_VSNSN1, ADSEL_VSNSN2, }BD13897RUV_VMONSEL_mode_t; /* tCdd_BD18397RUV_Registor_Configure User init all register default value define a common spi comunication struct between with BD18397RUV and Z20K14xM */ typedef struct tCdd_BD18397RUV_Registor_Configure { uint8 ucIndex; // index of next schedule table entry uint8 unCmd; // Read/Write Command to send uint8 unAddr; // SPI address (combination of low and high nibble) uint8 value[CDDBD18397RUV_Cfg_NbOfDevices]; // SPI data }tCdd_BD18397RUV_Registor_Configure; /* tCddBD18397RUV_M_Bit_SYSTEM SWRST register return ‘0’ automatically. Hence, this register is “Write only” . Set this register when you want to reset digital circuit. SLEEP This IC has sleep mode which stops internal clock, so this IC is in low “quiescent current” condition. This IC keeps register value when SLEEP = 1. RDMODE This register controls Read protocol. If RDMODE = 1, it outputs Read Data (target address 8-bit + next address bit[1:0]). The detail of protocol can be referred in "SPI Protocol" section. Such as VMON[9:2]+VMON[1:0] ,or VMON[9:2] Signal get such as Temperature VIN and so on WDTEN This register is “Watchdog timer” function enable. If WDTEN = 1, LIMP-HOME function is available by “Watch Dog Timer error” when state is “LEDACTIVE” or “STANDBY” . WLOCK DPWMx registers are split into two register (higher and lower byte). Normally, whenever a byte (higher or lower) is written, it will immediately be reflected in PWM dimming control. If WLOCK function is used, PWM dimming control will not be updated until the two bytes (higher and lower) are written. Note that it doesn't matter whether the higher or lower byte is written first. */ typedef struct tCddBD18397RUV_M_Bit_SYSTEM { uint16 biSWRST : 1 ; /*RESET */ uint16 biRESERVED : 3 ; /*RESERVED */ uint16 biSLEEP : 1 ; /*SLEEP */ uint16 biRDMODE : 1 ; /*RDMODE */ uint16 biWDTEN : 1 ; /*WDTEN */ uint16 biWLOCK : 1 ; /*WLOCK */ }tCddBD18397RUV_M_Bit_SYSCFG1; /* tCddBD18397RUV_M_Bit_ERRSET1 SWOCPLAT The releasing function of “SWx over current error protection” is programmed by this register. If SWOCPLAT = ‘1’, The SWOCPERRx register doesn't become '0' until writing FLTRST = '1'. If SWOCPLAT = '0', The SWOCPERRx becomes '0' by "SWx over current error" released. LEDOCPLAT The releasing function of “LED over current error protection” is programmed by this register. If LEDOCPLAT = ‘1’, The LEDOCPERRx register doesn't become '0' until writing FLTRST = '1'. If LEDOCPLAT = '0', The LEDOCPERRx becomes '0' by "LED over current error" released. FLTRST The error status register are initialized by this register. If each protection is latched, its condition is released. RESERVED :5 bits reserved */ typedef struct tCddBD18397RUV_M_Bit_ERRSET1 { uint16 biSWOCPLAT : 1 ; /*SWOCPLAT*/ uint16 biLEDOCPLAT : 1 ; /*LEDOCPLAT*/ uint16 biFLTRST : 1 ; /*FLTRST*/ uint16 biRESERVED : 5 ; /*RESERVED*/ }tCddBD18397RUV_M_Bit_ERRSET1; /* ISETDIMX This register selects the LED DC current setting data for channel x (x = 1, 2, 3). If ISETDIMx = 1, the ISETx pin setting is available . If ISETDIMx = 0, LED DC current is programmed by ISETx register. PWMDIV The output frequency is programmed for PWM dimming LED by this register. A/D conversion frequency (ADMODE = 1) is also programed by this register. PHEN PWM dimming phase of channel 1 is programmed by this register as No Phase shift PHEN set 0 */ typedef struct tCddBD18397RUV_M_Bit_DIMSET { uint16 biISETDIM1 : 1 ; /*ISETDIM1 */ uint16 biISETDIM2 : 1 ; /*ISETDIM2*/ uint16 biISETDIM3 : 1 ; /*ISETDIM3 support only BD18398RUV */ uint16 biPWMDIV : 4 ; /*PWMDIV*/ uint16 biPHEN : 1 ; /*PHEN*/ }tCddBD18397RUV_M_Bit_DIMSET; /*tCddBD18397RUV_M_Bit_ISETX Set these registers in initial setting. If you want to change value during dimming, WLOCK function can be used. ISET1H [7-0] ISET1L [1-0] ISET2H [7-0] ISET2L [1-0] LED DC current is programmed by this register ILED=(ISET[9-0]*2.5/1024 -0.2v)*(1/(12*RSNSX) */ typedef struct tCddBD18397RUV_M_Bit_ISET1H { uint16 biISET1H : 8 ; /* ISET1H*/ }tCddBD18397RUV_M_Bit_ISET1H; typedef struct tCddBD18397RUV_M_Bit_ISET1L { uint16 biISET1L : 2 ; /* ISET1L */ }tCddBD18397RUV_M_Bit_ISET1L; typedef struct tCddBD18397RUV_M_Bit_ISET2H { uint16 biISET2H : 8 ; /* ISET2H*/ }tCddBD18397RUV_M_Bit_ISET2H; typedef struct tCddBD18397RUV_M_Bit_ISET2L { uint16 biISET2L : 2 ; /* ISET2L */ }tCddBD18397RUV_M_Bit_ISET2L; /*tCddBD18397RUV_M_Bit_DPWMX Set these registers in initial setting. If you want to change value during dimming, WLOCK function can be used. DPWM1H[7-0] DPWM1L[1-0] DPWM2H[7-0] DPWM2L[1-0] LED average current in PWM is programmed by this register. The dimming ratio is calculated as following formula DPWMX =(DPWMX[9:0]+1)/10124 */ typedef struct tCddBD18397RUV_M_Bit_DPWM1H { uint16 biDPWM1H : 8 ; /* DPWM1H*/ }tCddBD18397RUV_M_Bit_DPWM1H; typedef struct tCddBD18397RUV_M_Bit_DPWM1L { uint16 biDPWM1L : 8 ; /* DPWM1L*/ }tCddBD18397RUV_M_Bit_DPWM1L; typedef struct tCddBD18397RUV_M_Bit_DPWM2H { uint16 biDPWM2H : 8 ; /* DPWM2H*/ }tCddBD18397RUV_M_Bit_DPWM2H; typedef struct tCddBD18397RUV_M_Bit_DPWM2L { uint16 biDPWM2L : 8 ; /* DPWM2L*/ }tCddBD18397RUV_M_Bit_DPWM2L; /*tCddBD18397RUV_M_Bit_DCDCSET1 OR tCddBD18397RUV_M_Bit_DCDCSET2 bit[7:6] GM1[1:0] GM Amplifier Gain Setting DC/DC GM Amplifier Trans Conductance Setting GM1[1:0] (Dec) GM Amplifier Gain Setting [µs] 0 1,200 1 750 2 430 3 240 TON1[5:0] DC/DC Frequency Setting for Reference (RTON = 51 kΩ ) OR (RTON = 9.1 kΩ ) It is available to use DC/DC frequency setting under 2.25 MHz. (over 2.25 MHz setting is prohibited.) */ typedef struct tCddBD18397RUV_M_Bit_DCDCSET1 { uint16 biTON1 : 6; /* TON1*/ uint16 biGM1 : 2; /* GM1*/ }tCddBD18397RUV_M_Bit_DCDCSET1; typedef struct tCddBD18397RUV_M_Bit_DCDCSET2 { uint16 biTON2 : 6; /* TON2*/ uint16 biGM2 : 2; /* GM2*/ }tCddBD18397RUV_M_Bit_DCDCSET2; /*tCddBD18397RUV_M_Bit_DCDCSET4 bit[2:0] SSCG[2:0] The modulation DC/DC switching frequency is programmed for all channel by this register. VMODEx “Voltage control mode” for DC/DC is programmed by this register. If 0 Current control mode for channel x If 1 voltage control mode for channel x */ typedef struct tCddBD18397RUV_M_Bit_DCDCSET4 { uint16 biSSCG : 3; /* SSCG*/ uint16 biRESERVED3 : 1; /* RESERVED*/ uint16 biVMODE1 : 1; /* VMODE1*/ uint16 biVMODE2 : 1; /* VMODE2*/ uint16 biVMODE3 : 1; /* VMODE3 support only BD18398RUV */ uint16 biRESERVED7 : 1; /* RESERVED*/ }tCddBD18397RUV_M_Bit_DCDCSET4; /* tCddBD18397RUV_M_Bit_CHEN bit[2:0] CHONx (CHON3 is only used for the BD18398RUV-M) Each channel starts-up by this register. If CHONx = 1, LED dimming is available for channel x . (x = 1, 2, 3) CHONx = 0, LED dimming is not available for channel x . Protection such as “LED short to ground error protection”, “LED open error protection”, “SW Over Current error protection” and “LED Over Current error protection” in the target channel is not available when CHONx = 0. bit[6:4] PWMDIMx The internal PWM dimming duty is programmed by this register. It is available to dim by the DPWMx[9:0] register when the PWMDIMx = 1. The internal PWM duty can be set to 100 % when the PWMDIMx = 0. */ typedef struct tCddBD18397RUV_M_Bit_CHEN { uint16 biCHON1 : 1; /* CHON1 */ uint16 biCHON2 : 1; /* CHON2 */ uint16 biCHON3 : 1; /* CHON3 support only BD18398RUV */ uint16 biRESERVED3 : 1; /* RESERVED*/ uint16 biPWMDIM1 : 1; /* PWMDIM1 */ uint16 biPWMDIM2 : 1; /* PWMDIM2 */ uint16 biPWMDIM3 : 1; /* PWMDIM3 support only BD18398RUV */ uint16 biRESERVED7 : 1; /* RESERVED*/ }tCddBD18397RUV_M_Bit_CHEN; /* tCddBD18397RUV_M_Bit_ADSEL bit[3:0] VMONSEL[3:0] VMON register is shared in for monitoring below node. This register should be programmed before reading VMON register when target node voltage is need. bit[4] ADMODE There are two A/D converting modes. When ADMODE = 1, A/D converter is operated automatically. Conversion frequency is determined by PWMDIV register and is operational only in LEDACTIVE state. When ADMODE = 0, A/D converter is operated manually by ADTRG. A/D converter becomes sleep condition (low current consumption) after 1 conversion. ADTRG A/D starts to convert the data selected by VMONSEL register after writing ADTRG = 1 during ADMODE = 0. This register will return to ‘0’ after writing ‘1’ . Updated data is available less than 24 µs. */ typedef struct tCddBD18397RUV_M_Bit_ADSEL { uint16 biVMONSEL : 4; /* CHON1 */ uint16 biADMODE : 1; /* ADMODE */ uint16 biRESERVED5 : 1; /* RESERVED */ uint16 biRESERVED6 : 1; /* RESERVED*/ uint16 biADTRG : 1; /* biADTRG */ }tCddBD18397RUV_M_Bit_ADSEL; /*This register is used for monitoring the thermal sensor voltage (VTEMP), VISET/PWMx , VIN , V5VEXT , VPIN or VSNSNx node (x = 1, 2, 3). This operation is programmed by VMONSEL register. This data is divided into two register address. If all of 10-bit data is required when ADMODE = 1, or RDMODE function is available. Formula 1 for thermal sensor voltage Thermal sensor voltage ADC read value = 418 @25 deg Thermal sensor voltage ADC read value = 602 @150 deg 1.472 count/temp (1 degree) Formula 2 for external input pin nodes Monitor voltage 1 [V] = “X” x (VMON + 1) / 1024 VIN : “X” = 48, VPIN : “X” = 70, and VSNSNx : “X” = 67.5, V5VEXT : “X” = 5.5, VISET/PWMx : “X” = 2.5 */ typedef struct tCddBD18397RUV_M_Bit_VMONH { uint16 biVMONH : 8; /* VMON*/ }tCddBD18397RUV_M_Bit_VMONH; typedef struct tCddBD18397RUV_M_Bit_VMONL { uint16 biVMONL : 2; /* VMON*/ }tCddBD18397RUV_M_Bit_VMONL; /* bit[2:0] ERRDETx (ERRDET3 is only used for the BD18398RUV-M) This register is error status each channel. Table 26. Error Status of Each Channel ERRDETx Status 0 Normal 1 Detects error LSDx || LODx || SWOCPERRx || LEDOCPERRx (x = 1, 2, 3) bit[4] UVLO This register is error status for UVLO. Table 27. UVLO UVLO Status 0 Normal 1 Detects under voltage error for V5VEXT or V5VREG PINUVLO This register is error status for PINUVLO. Table 28. PINUVLO PINUVLO Status 0 Normal 1 Detects under voltage error for PIN CRCERR This register is error status for CRC. If CRC error is detected, this register becomes 1. This register becomes 0 by FLTRST = 1. If CRC Error occurred to the SPI command sent after to sending FLTRST, this will not be detected, for more details refer to Error sequence for “CRC Error” . Table 29. CRC Error Status CRCERR Status 0 Normal 1 Detects CRC error WDTERR This register is error status for “Watch Dog Timer” . If “Watch Dog Timer error” is detected, this register becomes 1. This register becomes 0 by FLTRST = 1. Table 30. “Watch Dog Timer error” Status WDTERR Status 0 Normal 1 Detects “Watch Dog Timer error” */ typedef struct tCddBD18397RUV_M_Bit_ERRSTALL { uint16 biERRDET1: 1; /* ERRDET1*/ uint16 biERRDET2: 1; /* ERRDET2*/ uint16 biERRDET3: 1; /* ERRDET3 support only BD18398RUV */ uint16 biRESERVED3: 1; /* RESERVED3 */ uint16 biUVLO: 1; /* UVLO*/ uint16 biPINUVLO: 1; /* PINUVLO*/ uint16 biCRCERR: 1; /* CRCERR*/ uint16 biWDTERR: 1; /* WDTERR*/ }tCddBD18397RUV_M_Bit_ERRSTALL; /* The register data is updated to the newest data immediately when the data (“LED open error”, “LED short to ground error”, “SW1 Over Current”, “LED Over Current”) is detected LSD1 OR LSD2 This register is “LED short to ground error” status for channel 1. LSD1 becomes “1” when “LED short to ground error” is detected, and LSD returns “0” when “LED short to ground error” is released. There is filter for detecting (10 ms) and releasing (1 ms) each channel. This filter is shared for “LED short to ground protection” and “LED open protection” . LOD1 OR LOD2 This register is “LED open error” status for channel 1. LOD1 becomes “1” when “LED open error” is detected, and LOD1 returns “0” when “LED open error” is released. There is filter for detecting (10 ms) and releasing (1 ms) each channel. This filter is shared for “LED short to ground protection” and “LED open protection” . SWOCPERR1 OR SWOCPERR2 This register is “SW Over Current error” status for channel 1. If SWOCPLAT = 0, SWOCPERR1 becomes “1” when “SW Over Current” is detected, and SWOCPERR1 returns “0” when “SW Over Current error” is released. If SWOCPLAT = 1, SWOCPERR1 becomes “1” when “SW over current error” is detected, and SWOCPERR1 becomes “0” by FLTRST = 1. LEDOCPERR1 This register is “LED Over Current error” status for channel 1. If LEDOCPLAT = 0, LEDOCPERR1 becomes “1” when “LED Over Current” is detected, and LEDOCPERR1 returns “0” when “LED Over Current error” is released. If LEDOCPLAT = 1, LEDOCPERR1 becomes “1” when “LED over current error” is detected, and LEDOCPERR1 becomes “0” by FLTRST = 1. */ typedef struct tCddBD18397RUV_M_Bit_ERRST1 { uint16 biLSD1: 1; /* LSD1*/ uint16 biLOD1: 1; /* LOD1*/ uint16 biSWOCPERR1: 1; /* SWOCPERR1 */ uint16 biLEDOCPERR1: 1; /* LEDOCPERR1*/ uint16 RESERVED4 : 4; /* RESERVED4 */ } tCddBD18397RUV_M_Bit_ERRST1 ; typedef struct tCddBD18397RUV_M_Bit_ERRST2 { uint16 biLSD2: 1; /* LSD2*/ uint16 biLOD2: 1; /* LOD2*/ uint16 biSWOCPERR2: 1; /* SWOCPERR2 */ uint16 biLEDOCPERR2: 1; /* LEDOCPERR2*/ uint16 RESERVED4 : 4; /* RESERVED4 */ } tCddBD18397RUV_M_Bit_ERRST2 ; void BD18397_RUV_get_registor_read_cmd(uint8 reg_index); void BD18397_RUV_get_registor_data(uint8 index); void BD18397_RUV_set_registor_value(uint8 reg_index,uint8 *reg_value); void BD18397_RUV_set_VMONSEL_mode(uint8 adsel); uint8 BD18397RUV_get_current_register_id(uint8 index); void Cdd_bd18397_RUV_SetCurrent_mA(const uint32 ulChnIdx, const uint16 unCurrent); // ulChnIdx Channel max 8 min is 1 void Cdd_bd18397_RUV_SPI_PWM_Dimming (const uint32 ulChnIdx, const uint16 value); void Cdd_bd18397_SPI_PWM_Dimming (const uint32 ulChnIdx, const uint16 value); void CDDBD18397RUV_Daisy_Device_init(void); void InitSPI_Dev(void); #endif // CDD_BD18397_2023_10_09_H_