CM4 Cortex-M4 (with FPU) r0p0 little true true 4 false Core All CPU Registers 32 RW unsigned int R0 General purpose register 0 0 R1 General purpose register 1 1 R2 General purpose register 2 2 R3 General purpose register 3 3 R4 General purpose register 4 4 R5 General purpose register 5 5 R6 General purpose register 6 6 R7 General purpose register 7 7 R8 General purpose register 8 8 R9 General purpose register 9 9 R10 General purpose register 10 10 R11 General purpose register 11 11 R12 General purpose register 12 12 R13 SP R13 (SP) Stack pointer 13 R14 LR R14 (LR) Link register 14 R15 PC R15 (PC) Program counter 15 xPSR Program status register 16 N Negative flag 31 1 Z Zero flag 30 1 C Carry flag 29 1 V Overflow flag 28 1 Q DSP overflow and saturation flag 27 1 T Thumb state bit 24 1 ICI/IT HighBits Interruptible-continuable instruction bits (high bits) 25 2 ICI/IT LowBits Interruptible-continuable instruction bits (low bits) 10 6 ISR Number Interrupt service routine number 0 9 MSP Main stack pointer 17 PSP Process stack pointer 18 APSR Application program status register 21 N Negative flag 31 1 Z Zero flag 30 1 C Carry flag 29 1 V Overflow flag 28 1 Q DSP overflow and saturation flag 27 1 EPSR Exception program status register 22 ICI/IT HighBits Interruptible-continuable instruction bits (high bits) 25 2 ICI/IT LowBits Interruptible-continuable instruction bits (low bits) 10 6 T Thumb state bit 24 1 IPSR Interrupt program status register 23 ISR Number Interrupt service routine number 0 9 PriMask Priority mask register 24 PriMask Prevent the activation of all exceptions with configurable priority 0 1 BasePri Base priority mask register 88 BasePri Priority mask bits 0 8 FaultMask Fault mask register 89 FaultMask Prevent the activation of all exceptions except for NMI 0 1 Control Control register 90 FPCA Context floating-point active 2 1 SPSEL Active stack pointer 1 1 nPRIV Thread mode privilege level 0 1 CycleCount Cycle count 65 FPU FPU Registers 32 RW float FPSCR unsigned int Floating point status and control register 32 IOC Invalid operation cumulative flag 0 1 DZC Division by zero cumulative flag 1 1 OFC Overflow cumulative flag 2 1 UFC Underflow cumulative flag 3 1 IXC Inexact cumulative flag 4 1 IDC Input subnormal cumulative flag 7 1 IOE Invalid operation exception enable bit 8 1 DZE Division by Zero exception enable bit 9 1 OFE Overflow exception enable bit 10 1 UFE Underflow exception enable bit 11 1 IXE Inexact exception enable bit 12 1 IDE Input Subnormal exception enable bit 13 1 IDE Input Subnormal exception enable bit 13 1 Len Vector length 16 3 Stride Stride control 20 2 R-Mode Rounding mode control 22 2 FZ Flush-to-zero mode enable bit 24 1 DN Default NaN mode enable bit 25 1 QC Saturation cumulative flag 27 1 V Set if comparison produces an unordered result 28 1 C Set if comparison produces an equal, greater than, or unordered result 29 1 Z Set if comparison produces an equal result 30 1 S0 Floating point register 0 33 S1 Floating point register 1 34 S2 Floating point register 2 35 S3 Floating point register 3 36 S4 Floating point register 4 37 S5 Floating point register 5 38 S6 Floating point register 6 39 S7 Floating point register 7 40 S8 Floating point register 8 41 S9 Floating point register 9 42 S10 Floating point register 10 43 S11 Floating point register 11 44 S12 Floating point register 12 45 S13 Floating point register 13 46 S14 Floating point register 14 47 S15 Floating point register 15 48 S16 Floating point register 16 49 S17 Floating point register 17 50 S18 Floating point register 18 51 S19 Floating point register 19 52 S20 Floating point register 20 53 S21 Floating point register 21 54 S22 Floating point register 22 55 S23 Floating point register 23 56 S24 Floating point register 24 57 S25 Floating point register 25 58 S26 Floating point register 26 59 S27 Floating point register 27 60 S28 Floating point register 28 61 S29 Floating point register 29 62 S30 Floating point register 30 63 S31 Floating point register 31 64 Peripherals Memory-Mapped CPU Registers 32 RW unsigned int ITM Instrumentation Macrocell 0xE0000000 0x0 0x1000 registers Stimulus Port Register %s ITM_STIM_%s Provides the interface for generating instrumentation messages 0x0 256 4 read-write STIMULUS Data write to the stimulus port FIFO, for forwarding as a software event packet [31:0] FIFOREADY Indicates whether the stimulus port FIFO can accept data [0:0] Stimulus port FIFO full 0 Stimulus port FIFO can accept at least one word 1 Trace Enable Register %s ITM_TER_%s Provide an individual enable bit for each ITM_STIM register 0xE00 8 4 read-write STIMENA For bit STIMENA[n], in register ITM_TERx [31:0] Stimulus port (32x + n) disabled 0 Stimulus port (32x + n) enabled 1 Trace Privilege Register ITM_TPR Controls which stimulus ports can be accessed by unprivileged code 0xE40 read-write PRIVMASK Bit mask to enable unprivileged access to ITM stimulus ports [31:0] Unprivileged access permitted 0 Privileged access only 1 Trace Control Register ITM_TCR Configures and controls transfers through the ITM interface 0xE80 read-write BUSY Indicates whether the ITM is currently processing events [23:23] ITM is not processing any events 0 ITM events present and being drained 1 TraceBusID Identifier for multi-source trace stream formatting [22:16] GTSFREQ Global timestamp frequency [11:10] Disable generation of global timestamps 0 Generate timestamp request whenever the ITM detects a change in global timestamp counter bits[47:7] 1 Generate timestamp request whenever the ITM detects a change in global timestamp counter bits[47:13] 10 Generate a timestamp after every packet, if the output FIFO is empty 11 TSPrescale Local timestamp prescaler, used with the trace packet reference clock [9:8] No prescaling 0 Divide by 4 1 Divide by 16 10 Divide by 64 11 SWOENA Enables asynchronous clocking of the timestamp counter [4:4] Timestamp counter uses the processor system clock 0 Timestamp counter uses asynchronous clock from the TPIU interface 1 TXENA Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU [3:3] Disabled 0 Enabled 1 SYNCENA Enables Synchronization packet transmission for a synchronous TPIU [2:2] Disabled 0 Enabled 1 TSENA Enables Local timestamp generation [1:1] Disabled 0 Enabled 1 ITMENA Enables the ITM [0:0] DWT Data Watchpoint and Trace 0xE0001000 0x0 0x1000 registers Control register DWT_CTRL Provides configuration and status information for the DWT unit, and used to control features of the unit 0x0 read-write NUMCOMP Number of comparators implemented [31:28] NOTRCPKT Shows whether the implementation supports trace sampling and exception tracing [27:27] Trace sampling and exception tracing supported 0 Trace sampling and exception tracing not supported 1 NOEXTTRIG Shows whether the implementation includes external match signals, CMPMATCH[N] [26:26] CMPMATCH[N] supported 0 CMPMATCH[N] not supported 1 NOCYCCNT Shows whether the implementation supports a cycle counter [25:25] Cycle counter supported 0 Cycle counter not supported 1 NOPRFCNT Shows whether the implementation supports the profiling counters [24:24] Supported 0 Not supported 1 CYCEVTENA Enables POSTCNT underflow Event counter packets generation [22:22] No POSTCNT underflow packets generated 0 POSTCNT underflow packets generated, if PCSAMPLENA set to 0 1 FOLDEVTENA Enables generation of the Folded-instruction counter overflow event [21:21] Disabled 0 Enabled 1 LSUEVTENA Enables generation of the LSU counter overflow event [20:20] Disabled 0 Enabled 1 SLEEPEVTENA Enables generation of the Sleep counter overflow event [19:19] Disabled 0 Enabled 1 EXCEVTENA Enables generation of the Exception overhead counter overflow event [18:18] Disabled 0 Enabled 1 CPIEVTENA Enables generation of the CPI counter overflow event [17:17] Disabled 0 Enabled 1 EXCTRCENA Enables generation of exception trace [16:16] Disabled 0 Enabled 1 PCSAMPLENA Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation [12:12] No Periodic PC sample packets generated 0 Periodic PC sample packets generated 1 SYNCTAP Selects the position of the synchronization packet counter tap on the CYCCNT counter [11:10] Disabled. No Synchronization packets 0 Synchronization counter tap at CYCCNT[26] 10 Synchronization counter tap at CYCCNT[28] 11 CYCTAP Selects the position of the POSTCNT tap on the CYCCNT counter [9:9] POSTCNT tap at CYCCNT[6] 0 POSTCNT tap at CYCCNT[10] 1 POSTINIT Initial value for the POSTCNT counter [8:5] POSTPRESET Reload value for the POSTCNT counter [4:1] CYCCNTENA Enables CYCCNT [0:0] Disabled 0 Enabled 1 Cycle Count register DWT_CYCCNT Shows or sets the value of the processor cycle counter, CYCCNT 0x4 read-write CYCCNT Incrementing cycle counter value [31:0] CPI Count register DWT_CPICNT Counts additional cycles required to execute multi-cycle instructions and instruction fetch stalls 0x8 read-write CPICNT Base instruction overhead counter [7:0] Exception Overhead Count register DWT_EXCCNT Counts the total cycles spent in exception processing 0xC read-write EXCCNT The exception overhead counter [7:0] Sleep Count register DWT_SLEEPCNT Counts the total number of cycles that the processor is sleeping 0x10 read-write SLEEPCNT Sleep counter [7:0] LSU Count register DWT_LSUCNT Increments on the additional cycles required to execute all load or store instructions 0x14 read-write LSUCNT Load-store overhead counter [7:0] Folded-instruction Count register DWT_FOLDCNT Increments on each instruction that takes 0 cycles 0x18 read-write FOLDCNT Folded instruction counter [7:0] Program Counter Sample Register DWT_PCSR Samples the current value of the program counter 0x1C read-only EIASAMPLE Executed Instruction Address sample value [31:0] Comparator register DWT_COMP_%s Provides a reference value for use by comparator n 0x20 read-write 8 4 COMP Reference value for comparison [31:0] Comparator Mask Register %s DWT_MASK_%s Provides the size of the ignore mask applied to the access address for address range matching by comparator n 0x24 read-write 8 4 MASK The size of the ignore mask, 0-31 bits, applied to address range matching [4:0] Comparator Function Register %s DWT_FUNCTION_%s Controls the operation of comparator n 0x28 read-write 8 4 MATCHED Comparator match [24:24] No match 0 Match 1 DATAVADDR1 When the DATAVMATCH and LNK1ENA bits are both 1, this field can hold the comparator number of a second comparator to use for linked address comparison [19:16] DATAVADDR0 When the DATAVMATCH bit is set to 1 this field can hold the comparator number of a comparator to use for linked address comparison [15:12] DATAVSIZE For data value matching, specifies the size of the required data comparison [11:10] Byte 0 Halfword 1 Word 10 LNK1ENA Indicates whether the implementation supports use of a second linked comparator [9:9] Second linked comparator not supported 0 Second linked comparator supported 1 DATAVMATCH Enables data value comparison, if supported [8:8] Perform address comparison 0 Perform data value comparison 1 CYCMATCH DWT_FUNCTION0 only [7:7] No comparison is performed 0 Compare DWT_COMP0 with the cycle counter, DWT_CYCCNT 1 EMITRANGE If the implementation supports trace sampling, enables generation of Data trace address packets, that hold Daddr[15 [5:5] Data trace address packets disabled 0 Enable Data trace address packet generation 1 FUNCTION Selects action taken on comparator match [3:0] = Disabled or LinkAddr(), see LinkAddr support on page C1-789 0 DPB Flash Patch and Breakpoint 0xE0002000 0x0 0x1000 registers FlashPatch Control Register FP_CTRL Provides FPB implementation information, and the global enable for the FPB unit 0x0 read-write REV Flash Patch Breakpoint architecture revision [31:28] Flash Patch Breakpoint version 1 0 Flash Patch Breakpoint version 2 1 NUM_CODE[6:4] Number of comperators 6:4 [14:12] NUM_LIT The number of literal address comparators supported, starting from NUM_CODE upwards [11:8] NUM_CODE[3:0] Number of comperators 3:0 [7:4] KEY On any write to FP_CTRL, this bit must be 1 [1:1] ENABLE Enable bit for the FPB [0:0] Flash Patch Breakpoint disabled 0 Flash Patch Breakpoint enabled 1 FlashPatch Remap register FP_REMAP Indicates whether the implementation supports flash patch remap, and if it does, holds the SRAM address for remap 0x4 read-write RMPSPT Indicates whether the FPB unit supports flash patch remap [29:29] Remapping not supported. The FPB only supports breakpoint functionality 0 Hard-wired remap to SRAM region 1 REMAP If the FPB supports flash patch remap, this field [28:5] FlashPatch Comparator Register %s FP_COMP_%s Holds an address for comparison with addresses in the Code memory region, see The system address map on page B3-648 0x8 read-write 8 4 REPLACE For an instruction address comparator [31:30] Remap to remap address, see FlashPatch Remap register, FP_REMAP on page C1-818 0 Breakpoint on instruction at '000':COMP:'00' 1 Breakpoint on instruction at '000':COMP:'10' 10 Breakpoint on both instructions at '000':COMP:'00' and '000':COMP:'10' 11 COMP Bits[28 [28:2] For a literal address or instruction address remap of the comparison are also zero [1:0] For an instruction address breakpoint of the comparison are encoded by the REPLACE field [1:0] 30 29 28 2 1 0 COMP Reserved REPLACE Reserved ENABLE C1 ARMv7-M Debug C1 31 ENABLE Enable bit for this comparator [0:0] Comparator disabled 0 Comparator enabled 1 BPADDR Breakpoint address [31:1] BE Enable bit for Breakpoint [0:0] Breakpoint disabled 0 Breakpoint enabled 1 DCBA This field is defined depending on the value for Breakpoint Enabled [31:1] BPADDR Breakpoint address [31:1] FE Specifies if Flash Patch enabled [31:31] Flash Patch disabled 0 Flash Patch enabled 1 FPADDR Specifies bits[28 [28:2] BE Breakpoint Enabled bit [0:0] Breakpoint disabled 0 Breakpoint enabled 1 In protocol packets of each byte, including the header byte, but not including the last byte of a 7-byte packet, is a continuation bit, C [7:7] This is the last byte of the packet 0 This is not the last byte of the packet 1 ICB Implementation Control Block 0xE000E004 0x0 0xC registers Interrupt Controller Type Register ICTR Provides information about the interrupt controller 0x0 read-only INTLINESNUM_%s The total number of interrupt lines supported by an implementation, defined in groups of 32 [3:0] 2 16 Auxiliary Control Register ACTLR Provides IMPLEMENTATION DEFINED configuration and control options 0x4 read-write SYSTICK SysTick Timer 0xE000E010 0x0 0x10 registers SysTick Control and Status Register SYST_CSR Controls the system timer and provides status data 0x0 read-write COUNTFLAG Indicates whether the counter has counted to 0 since the last read of this register [16:16] Timer has not counted to 0 0 Timer has counted to 0 1 CLKSOURCE Indicates the SysTick clock source [2:2] SysTick uses the IMPLEMENTATION DEFINED external reference clock 0 SysTick uses the processor clock 1 TICKINT Indicates whether counting to 0 causes the status of the SysTick exception to change to pending [1:1] Count to 0 does not affect the SysTick exception status 0 Count to 0 changes the SysTick exception status to pending 1 ENABLE Indicates the enabled status of the SysTick counter [0:0] Counter is disabled 0 Counter is operating 1 SysTick Reload Value Register SYST_RVR Holds the reload value of the SYST_CVR 0x4 read-write RELOAD The value to load into the SYST_CVR when the counter reaches 0 [23:0] SysTick Current Value Register SYST_CVR Reads or clears the current counter value 0x8 read-write CURRENT Current counter value [31:0] SysTick Calibration value Register SYST_CALIB Reads the calibration value and parameters for SysTick 0xC read-only NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock is implemented [31:31] The reference clock is implemented 0 The reference clock is not implemented 1 SKEW Indicates whether the 10ms calibration value is exact [30:30] 10ms calibration value is exact 0 10ms calibration value is inexact, because of the clock frequency 1 TENMS Optionally, holds a reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors [23:0] NVIC Nested Vectored Interrupt Controller 0xE000E100 0x0 0x4F0 registers Interrupt Set-Enable Register %s NVIC_ISER_%s Enables, or reads the enable state of a group of interrupts 0x0 16 4 read-write SETENA_%s For register NVIC_ISERn, enables or shows the current enabled state of interrupt (m+(32*n)) [0:0] 32 1 On reads, interrupt disabled 0 On reads, interrupt enabled 1 Interrupt Clear-Enable Register %s NVIC_ICER_%s Disables, or reads the enable state of, a group of registers 0x80 16 4 read-write CLRENA_%s For register NVIC_ICERn, disables or shows the current enabled state of interrupt (m+(32*n)) [0:0] 32 1 On reads, interrupt disabled 0 On reads, interrupt enabled 1 Interrupt Set-Pending Register %s NVIC_ISPR_%s For a group of interrupts, changes interrupt status to pending, or shows the current pending status 0x100 16 4 read-write SETPEND_%s For register NVIC_ISPRn, changes the state of interrupt (m+(32*n)) to pending, or shows whether the state of the interrupt is pending [0:0] 32 1 On reads, interrupt is not pending 0 On reads, interrupt is pending 1 Interrupt Clear-Pending Register %s NVIC_ICPR_%s For a group of interrupts, clears the interrupt pending status, or shows the current pending status 0x180 16 4 read-write CLRPEND_%s For register NVIC_ICPRn, clears the pending state of interrupt (m+(32*n)), or shows whether the state of the interrupt is pending [0:0] 32 1 On reads, interrupt is not pending 0 On reads, interrupt is pending 1 Interrupt Active Bit Register %s NVIC_IABR_%s For a group of 32 interrupts, shows whether each interrupt is active 0x200 16 4 read-only ACTIVE_%s For register NVIC_IABRn, shows whether interrupt (m+(32*n)) is active [0:0] 32 1 Interrupt not active 0 Interrupt active 1 Interrupt Priority Register %s NVIC_IPR_%s Sets or reads interrupt priorities 0x300 124 4 read-write PRI_N3 For register NVIC_IPRn, priority of interrupt number 4n+3 [31:24] PRI_N2 For register NVIC_IPRn, priority of interrupt number 4n+2 [23:16] PRI_N1 For register NVIC_IPRn, priority of interrupt number 4n+1 [15:8] PRI_N0 For register NVIC_IPRn, priority of interrupt number 4n [7:0] SCB System Control Block 0xE000ED00 0x0 0x90 registers CPUID Base Register CPUID Provides identification information for the processor 0x0 read-only IMPLEMENTER Implementer code assigned by ARM [31:24] VARIANT IMPLEMENTATION DEFINED variant number [23:20] ARCHITECTURE Reads as 0xF [19:16] PARTNO IMPLEMENTATION DEFINED part number [15:4] REVISION IMPLEMENTATION DEFINED revision number [3:0] Interrupt Control and State Register ICSR Provides software control of the NMI, PendSV, and SysTick exceptions, and provides interrupt status information 0x4 read-write NMIPENDSET On writes, makes the NMI exception active [31:31] On writes, has no effect. On reads, NMI is inactive 0 On writes, make the NMI exception active. On reads, NMI is active 1 PENDSVSET On writes, sets the PendSV exception as pending [28:28] On writes, has no effect. On reads, PendSV is not pending 0 On writes, make PendSV exception pending. On reads, PendSV is pending 1 PENDSVCLR Removes the pending status of the PendSV exception [27:27] No effect 0 Remove pending status 1 PENDSTSET On writes, sets the SysTick exception as pending [26:26] On writes, has no effect. On reads, SysTick is not pending 0 On writes, make SysTick exception pending. On reads, SysTick is pending 1 PENDSTCLR Removes the pending status of the SysTick exception [25:25] No effect 0 Remove pending status 1 ISRPREEMPT Indicates whether a pending exception will be serviced on exit from debug halt state [23:23] Will not service 0 Will service a pending exception 1 ISRPENDING Indicates whether an external interrupt, generated by the NVIC, is pending [22:22] No external interrupt pending 0 External interrupt pending 1 VECTPENDING The exception number of the highest priority pending and enabled interrupt [20:12] RETTOBASE In Handler mode, indicates whether there is an active exception other than the exception indicated by the current value of the IPSR [11:11] There is an active exception other than the exception shown by IPSR 0 There is no active exception other than any exception shown by IPSR 1 VECTACTIVE The exception number of the current executing exception [8:0] Vector Table Offset Register VTOR Holds the vector table address 0x8 read-write TBLOFF Bits[31:7] of the vector table address [31:7] Application Interrupt and Reset Control Register AIRCR Sets or returns interrupt control data 0xC read-write ENDIANNESS Indicates the memory system endianness [15:15] Little endian 0 Big endian 1 PRIGROUP Priority grouping, indicates the binary point position [10:8] SYSRESETREQ System Reset Request [2:2] Do not request a reset 0 Request reset 1 VECTCLRACTIVE Writing 1 to this bit clears all active state information for fixed and configurable exceptions [1:1] VECTRESET Writing 1 to this bit causes a local system reset, see Reset management on page B1-615 for more information [0:0] System Control Register SCR Sets or returns system control data 0x10 read-write SEVONPEND Determines whether an interrupt transition from inactive state to pending state is a wakeup event [4:4] Transitions from inactive to pending are not wakeup events 0 Transitions from inactive to pending are wakeup events 1 SLEEPDEEP Provides a qualifying hint indicating that waking from sleep might take longer [2:2] Selected sleep state is not deep sleep 0 Selected sleep state is deep sleep 1 SLEEPONEXIT Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state [1:1] Do not enter sleep state 0 Enter sleep state 1 Configuration and Control Register CCR Sets or returns configuration and control data, and provides control over caching and branch prediction 0x14 read-write BP Branch prediction enable bit [18:18] Program flow prediction disabled 0 Program flow prediction enabled 1 IC Instruction cache enable bit [17:17] Instruction caches disabled 0 Instruction caches enabled 1 DC Cache enable bit [16:16] Data and unified caches disabled 0 Data and unified caches enabled 1 STKALIGN Determines whether the exception entry sequence guarantees 8-byte stack frame alignment, adjusting the SP if necessary before saving state [9:9] Guaranteed SP alignment is 4-byte, no SP adjustment is performed 0 8-byte alignment guaranteed, SP adjusted if necessary 1 BFHFNMIGN Determines the effect of precise data access faults on handlers running at priority -1 or priority -2 [8:8] Precise data access fault causes a lockup, see Unrecoverable exception cases on page B1-611 0 Handler ignores the fault 1 DIV_0_TRP Controls the trap on divide by 0 [4:4] Trapping disabled 0 Trapping enabled 1 UNALIGN_TRP Controls the trapping of unaligned word or halfword accesses [3:3] Trapping disabled 0 Trapping enabled 1 USERSETMPEND Controls whether unprivileged software can access the STIR [1:1] Unprivileged software cannot access the STIR 0 Unprivileged software can access the STIR 1 NONBASETHRDENA Controls whether the processor can enter Thread mode with exceptions active [0:0] Any attempt to enter Thread mode with exceptions active faults 0 The processor can enter Thread mode with exceptions active because of a controlled return value 1 System Handler Priority Register 1 SHPR1 Sets or returns priority for system handlers 4-7 0x18 read-write PRI_7 Reserved for priority of system handler 7 [31:24] PRI_6 Priority of system handler 6, UsageFault [23:16] PRI_5 Priority of system handler 5, BusFault [15:8] PRI_4 Priority of system handler 4, MemManage [7:0] System Handler Priority Register 2 SHPR2 Sets or returns priority for system handlers 8-11 0x1C read-write PRI_11 Priority of system handler 11, SVCall [31:24] PRI_10 Reserved for priority of system handler 10 [23:16] PRI_9 Reserved for priority of system handler 9 [15:8] PRI_8 Reserved for priority of system handler 8 [7:0] System Handler Priority Register 3 SHPR3 Sets or returns priority for system handlers 12-15 0x20 read-write PRI_15 Priority of system handler 15, SysTick [31:24] PRI_14 Priority of system handler 14, PendSV [23:16] PRI_13 Reserved for priority of system handler 13 [15:8] PRI_12 Priority of system handler 12, DebugMonitor [7:0] System Handler Control and State Register SHCSR Controls and provides the active and pending status of system exceptions 0x24 read-write USGFAULTENA [18:18] Disable UsageFault 0 Enable UsageFault 1 BUSFAULTENA [17:17] Disable BusFault 0 Enable BusFault 1 MEMFAULTENA [16:16] Disable MemManage fault 0 Enable MemManage fault 1 SVCALLPENDED [15:15] SVCall is not pending 0 SVCall is pending 1 BUSFAULTPENDED [14:14] BusFault is not pending 0 BusFault is pending 1 MEMFAULTPENDED [13:13] MemManage is not pending 0 MemManage is pending 1 USGFAULTPENDED [12:12] UsageFault is not pending 0 UsageFault is pending 1 SYSTICKACT [11:11] SysTick is not active 0 SysTick is active 1 PENDSVACT [10:10] PendSV is not active 0 PendSV is active 1 MONITORACT [8:8] Monitor is not active 0 Monitor is active 1 SVCALLACT [7:7] SVCall is not active 0 SVCall is active 1 USGFAULTACT [3:3] UsageFault is not active 0 UsageFault is active 1 BUSFAULTACT [1:1] BusFault is not active 0 BusFault is active 1 MEMFAULTACT [0:0] MemManage is not active 0 MemManage is active 1 Configurable Fault Status Register CFSR Contains the three Configurable Fault Status Registers 0x28 read-write UsageFault Provides information on UsageFault exceptions [31:16] BusFault Provides information on BusFault exceptions [15:8] MemManage Provides information on MemManage exceptions [7:0] HardFault Status Register HFSR Shows the cause of any HardFault 0x2C read-write DEBUGEVT Indicates when a Debug event has occurred [31:31] No Debug event has occurred 0 Debug event has occurred. The Debug Fault Status Register has been updated 1 FORCED Indicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority or because it was disabled [30:30] No priority escalation has occurred 0 Processor has escalated a configurable-priority exception to HardFault 1 VECTTBL Indicates when a fault has occurred because of a vector table read error on exception processing [1:1] No vector table read fault has occurred 0 Vector table read fault has occurred 1 Debug Fault Status Register DFSR Shows which debug event occurred 0x30 read-write EXTERNAL Indicates a debug event generated because of the assertion of an external debug request [4:4] No external debug request debug event 0 External debug request debug event 1 VCATCH Indicates triggering of a Vector catch [3:3] No Vector catch triggered 0 Vector catch triggered 1 DWTTRAP Indicates a debug event generated by the DWT [2:2] No debug events generated by the DWT 0 At least one debug event generated by the DWT 1 BKPT Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB [1:1] No breakpoint debug event 0 At least one breakpoint debug event 1 HALTED Indicates a debug event generated by either [0:0] No halt request debug event 0 Halt request debug event 1 MemManage Fault Address Register MMFAR Shows the address of the memory location that caused an MPU fault 0x34 read-write ADDRESS Data address for an MPU fault [31:0] BusFault Address Register BFAR Shows the address associated with a precise data access fault 0x38 read-write ADDRESS Data address for a precise bus fault [31:0] Auxiliary Fault Status Register AFSR Provides implementation-specific fault status information and control 0x3C read-write Coprocessor Access Control Register CPACR Specifies the access privileges for coprocessors 0x88 read-write CP_%s for n values 0-7, 10 and 11 Access privileges for coprocessor n, see the register diagram [1:0] 16 2 Access denied. Any attempted access generates a NOCP UsageFault 0 Privileged access only. An unprivileged access generates a NOCP UsageFault 1 Reserved 2 Full access 3 Processor Feature Register 0 ID_PFR0 Gives top-level information about the instruction sets supported by the processor 0x40 read-only State3 ARMv7-M reserved [15:12] State2 ARMv7-M reserved [11:8] State1 Thumb instruction set support [7:4] Support for Thumb encoding including Thumb-2 technology, with all basic 16-bit and 32-bit instructions 3 State0 ARM instruction set support [3:0] The processor does not support the ARM instruction set 0 ARMv7-M reserved 1 Processor Feature Register 1 ID_PFR1 Gives top-level information about the instruction sets supported by the processor 0x44 read-only M profile programmers model [11:8] ARMv7-M reserved 0 Reserved 1 Two-stack programmers model supported 2 Debug Feature Register 0 ID_DFR0 Gives top-level information about the debug system used in the processor 0x48 read-only Debug model, M profile Support for memory-mapped debug model for M profile processors [23:20] Not supported 0 Support for M profile Debug architecture, with memory-mapped access 1 Auxiliary Feature Register 0 ID_AFR0 Gives information about the IMPLEMENTATION DEFINED features of a processor implementation 0x4C read-only Memory Model Feature Register 0 ID_MMFR0 Gives information about the implemented memory model and memory management support 0x50 read-only Auxiliary registers Indicates the support for Auxiliary registers [23:20] Not supported 0 Support for Auxiliary Control Register only 1 ARMv7-M reserved 2 TCM support Indicates the support for Tightly Coupled Memory (TCM) [19:16] No tightly coupled memories implemented 0 Tightly coupled memories implemented with IMPLEMENTATION DEFINED control 1 ARMv7-M reserved 2 Shareability levels Indicates the number of shareability levels implemented [15:12] One level of shareability implemented 0 ARMv7-M reserved 1 Outermost shareability Indicates the outermost shareability domain implemented [11:8] Implemented as Non-cacheable 0 ARMv7-M reserved 1 Shareability ignored 15 PMSA support Indicates support for a PMSA [7:4] Not supported 0 PMSAv7, providing support for a base region and subregions 3 Memory Model Feature Register 1 ID_MMFR1 Gives information about the implemented memory model and memory management support 0x54 read-only Memory Model Feature Register 2 ID_MMFR2 Gives information about the implemented memory model and memory management support 0x58 read-only WFI stall Indicates the support for Wait For Interrupt (WFI) stalling [27:24] Not supported 0 Support for WFI stalling 1 Memory Model Feature Register 3 ID_MMFR3 Gives information about the implemented memory model and memory management support 0x5C read-only Instruction Set Attribute Register 0 ID_ISAR0 Gives information about the instruction sets implemented by the processor 0x60 read-only Divide_instrs Indicates the supported Divide instructions [27:24] None supported, ARMv7-M reserved 0 Adds support for the SDIV and UDIV instructions 1 Debug_instrs Indicates the supported Debug instructions [23:20] None supported, ARMv7-M reserved 0 Adds support for the BKPT instruction 1 Coproc_instrs Indicates the supported Coprocessor instructions [19:16] None supported, except for separately attributed architectures, for example the Floating-point extension 0 Adds support for generic CDP, LDC, MCR, MRC, and STC instructions 1 As for 1, and adds support for generic CDP2, LDC2, MCR2, MRC2, and STC2 instructions 2 As for 2, and adds support for generic MCRR and MRRC instructions, 4 As for 3, and adds support for generic MCRR2 and MRRC2 inst 3 CmpBranch_instrs Indicates the supported combined Compare and Branch instructions [15:12] None supported, ARMv7-M reserved 0 Adds support for the CBNZ and CBZ instructions 1 Bitfield_instrs Indicates the supported BitField instructions [11:8] None supported, ARMv7-M reserved 0 Adds support for the BFC, BFI, SBFX, and UBFX instructions 1 BitCount_instrs Indicates the supported Bit Counting instructions [7:4] None supported, ARMv7-M reserved 0 Adds support for the CLZ instruction 1 Instruction Set Attribute Register 1 ID_ISAR1 Gives information about the instruction sets implemented by the processor 0x64 read-only Interwork_instrs Indicates the supported Interworking instructions [27:24] None supported, ARMv7-M reserved 0 Adds support for the BX instruction, and the T bit in the PSR 1 As for 1, and adds support for the BLX instruction, and PC loads have BX-like behavior 2 ARMv7-M reserved 3 Immediate_instrs Indicates the support for data-processing instructions with long immediates [23:20] None supported, ARMv7-M reserved 0 Adds support for the ADDW, MOVW, MOVT, and SUBW instructions 1 IfThen_instrs Indicates the supported IfThen instructions [19:16] None supported, ARMv7-M reserved 0 Adds support for the IT instructions, and for the IT bits in the PSRs 1 Extend_instrs Indicates the supported Extend instructions [15:12] None supported, ARMv7-M reserved 0 Adds support for the SXTB, SXTH, UXTB, and UXTH instructions 1 As for 1, and adds support for the SXTAB, SXTAB16, SXTAH, SXTB16, UXTAB, UXTAB16, UXTAH, and UXTB16 instructions 2 Instruction Set Attribute Register 2 ID_ISAR2 Gives information about the instruction sets implemented by the processor 0x68 read-only Reversal_instrs Indicates the supported Reversal instructions [31:28] None supported, ARMv7-M reserved 0 Adds support for the REV, REV16, and REVSH instructions, ARMv7-M reserved 1 As for 1, and adds support for the RBIT instruction 2 MultU_instrs Indicates the supported advanced unsigned Multiply instructions [23:20] None supported, ARMv7-M reserved 0 Adds support for the UMULL and UMLAL instructions 1 As for 1, and adds support for the UMAAL instruction 2 MultS_instrs Indicates the supported advanced signed Multiply instructions [19:16] None supported, ARMv7-M reserved 0 Adds support for the SMULL and SMLAL instructions 1 As for 1, and adds support for the SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, S 2 As for 2, and adds support for the SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, 3 Mult_instrs Indicates the supported additional Multiply instructions [15:12] None supported. This means only MUL is supported. ARMv7-M reserved 0 Adds support for the MLA instruction, ARMv7-M reserved 1 As for 1, and adds support for the MLS instruction 2 MultiAccessInt_instrs Indicates the support for multi-access interruptible instructions [11:8] None supported. This means the LDM and STM instructions are not interruptible 0 LDM and STM instructions are restartable 1 LDM and STM instructions are continuable 2 MemHint_instrs Indicates the supported Memory Hint instructions [7:4] None supported, ARMv7-M reserved 0 Adds support for the PLD instruction 2 As for 1 or 2, and adds support for the PLI instruction 3 LoadStore_instrs Indicates the supported additional load and store instructions [3:0] None supported, ARMv7-M reserved 0 Adds support for the LDRD and STRD instructions 1 Instruction Set Attribute Register 3 ID_ISAR3 Gives information about the instruction sets implemented by the processor 0x6C read-only TrueNOP_instrs Indicates the support for a true NOP instruction [27:24] None supported, ARMv7-M reserved 0 Adds support for the true NOP instruction 1 ThumbCopy_instrs Indicates the supported non flag-setting MOV instructions [23:20] None supported, ARMv7-M reserved 0 Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register 1 TabBranch_instrs Indicates the supported Table Branch instructions [19:16] None supported, ARMv7-M reserved 0 Adds support for the TBB and TBH instructions 1 SynchPrim_instrs Must be interpreted with the ID_ISAR4 [15:12] SVC_instrs Indicates the supported SVC instructions [11:8] None supported, ARMv7-M reserved 0 Adds support for the SVC instruction 1 SIMD_instrs Indicates the supported SIMD instructions [7:4] None supported, ARMv7-M reserved 0 Adds support for the SSAT and USAT instructions, and for the Q bit in the PSRs 1 Reserved 2 As for 1, and adds support for the PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SH 3 Saturate_instrs Indicates the supported Saturate instructions [3:0] None supported 0 Adds support for the QADD, QDADD, QDSUB, and QSUB instructions, and for the Q bit in the PSRs 1 Instruction Set Attribute Register 4 ID_ISAR4 Gives information about the instruction sets implemented by the processor 0x70 read-only PSR_M_instrs Indicates the supported M profile instructions to modify the PSRs [27:24] None supported, ARMv7-M reserved 0 Adds support for the M-profile forms of the CPS, MRS, and MSR instructions, to access the PSRs 1 SynchPrim_instrs_frac Must be interpreted with the ID_ISAR3 [23:20] Barrier_instrs Indicates the supported Barrier instructions [19:16] None supported, ARMv7-M reserved 0 Adds support for the DMB, DSB, and ISB barrier instructions 1 Writeback_instrs Indicates the support for Writeback addressing modes [11:8] Basic support 0 Adds support for all of the writeback addressing modes defined in the ARMv7-M architecture 1 WithShifts_instrs Indicates the support for instructions with shifts [7:4] Nonzero shifts supported only in MOV and shift instructions 0 Adds support for shifts of loads and stores over the range LSL 0-3 1 Reserved 2 As for 1, and adds support for other constant shift options, on loads, stores, and other instructions 3 ARMv7-M reserved 4 Unpriv_instrs Indicates the supported unprivileged instructions [3:0] None supported, ARMv7-M reserved 0 Adds support for the LDRBT, LDRT, STRBT, and STRT instructions 1 As for 1, and adds support for the LDRHT, LDRSBT, LDRSHT, and STRHT instructions 2 Cache Level ID Register CLIDR The CLIDR identifies: ? The type of cache, or caches, implemented at each level, up to a maximum of seven levels 0x78 read-only LoUU Level of Unification Uniprocessor for the cache hierarchy, see Terminology for Clean, Invalidate, and Clean and Invalidate operations on page B2-631 [29:27] LoC Level of Coherency for the cache hierarchy [26:24] LoUIS Level of Unification Inner Shareable for the cache hierarchy [23:21] CType_%s Indicates the type of cache implemented at each level [1:0] 7 2 No cache 0 Instruction cache only 1 Data cache only 2 Separate instruction and data caches 3 Unified cache 4 Cache Type Register CTR The CTR provides information about the architecture of the caches 0x7C read-only Format Indicates the implemented CTR format [31:29] ARMv7 format. This is the format described in this section 4 CWG Cache Write-back Granule [27:24] ERG Exclusives Reservation Granule [23:20] DminLine Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor [19:16] IminLine Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor [3:0] Cache Size ID Registers CCSIDR The CCSIDR provides information about the architecture of the caches 0x80 read-only WT Indicates whether the cache level supports write-through, see Table B4-4 [31:31] WB Indicates whether the cache level supports write-back, see Table B4-4 [30:30] RA Indicates whether the cache level supports read-allocation, see Table B4-4 [29:29] WA Indicates whether the cache level supports write-allocation, see Table B4-4 [28:28] NumSets (Number of sets in cache)-1, therefore a value of 0 indicates 1 set in the cache [27:13] Associativity (Associativity of cache)-1, therefore a value of 0 indicates an associativity of 1 [12:3] LineSize (Log2(Number of words in cache line))-2 [2:0] Cache Size Selection Register CSSELR The CSSELR selects the current CCSIDR by specifying the required cache level 0x84 read-only Level Cache level of required cache [3:1] InD Instruction not data bit [0:0] Data or unified cache 0 Instruction cache 1 MPU Memory Protection Unit 0xE000ED90 0x0 0x2C registers MPU Type Register MPU_TYPE The MPU Type Register indicates how many regions the MPU support 0x0 read-only IREGION Instruction region [23:16] DREGION Number of regions supported by the MPU [15:8] SEPARATE Indicates support for separate instruction and data address maps. RAZ. ARMv7-M only supports a unified MPU [0:0] MPU Control Register MPU_CTRL Enables the MPU, and when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs 0x4 read-write PRIVDEFENA When the ENABLE bit is set to 1, the meaning of this bit is [2:2] Disables the default memory map 0 Enables the default memory map as a background region for privileged access 1 HFNMIENA When the ENABLE bit is set to 1, controls whether handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled [1:1] Disables the MPU for these handlers 0 Use the MPU for memory accesses by these handlers 1 ENABLE Enables the MPU [0:0] The MPU is disabled 0 The MPU is enabled 1 MPU Region Number Register MPU_RNR Selects the region currently accessed by MPU_RBAR and MPU_RASR 0x8 read-write REGION Indicates the memory region accessed by MPU_RBAR and MPU_RASR [7:0] MPU Region Base Address Register MPU_RBAR Holds the base address of the region identified by MPU_RNR 0xC read-write ADDR Base address of the region [31:5] VALID On writes, indicates whether the region to update is specified by MPU_RNR [4:4] Apply the base address update to the region specified by MPU_RNR.REGION 0 Update MPU_RNR.REGION to the value obtained by zero extending the REGION value specified in this write 1 REGION On writes, can specify the number of the region to update, see VALID field description [3:0] MPU Region Attribute and Size Register MPU_RASR Defines the size and access behavior of the region identified by MPU_RNR, and enables that region 0x10 read-write ATTRS The MPU Region Attribute field [31:16] SRD Subregion Disable [15:8] Subregion enabled 0 Subregion disabled 1 SIZE Indicates the region size [5:1] ENABLE Enables this region [0:0] When the MPU is enabled, this region is disabled 0 When the MPU is enabled, this region is enabled 1 DCB Debug Control Block 0xE000EDF0 0x0 0x10 registers Debug Halting Control and Status Register DHCSR Controls halting debug 0x0 read-write DBGKEY Debug key [31:16] S_RESET_ST Indicates whether the processor has been reset since the last read of DHCSR [25:25] No reset since last DHCSR read 0 At least one reset since last DHCSR read 1 S_RETIRE_ST Set to 1 every time the processor retires one or more instructions [24:24] No instruction retired since last DHCSR read 0 At least one instruction retired since last DHCSR read 1 S_LOCKUP Indicates whether the processor is locked up because of an unrecoverable exception [19:19] Not locked up 0 Locked up 1 S_SLEEP Indicates whether the processor is sleeping [18:18] Not sleeping 0 Sleeping 1 S_HALT Indicates whether the processor is in Debug state [17:17] In Non-debug state 0 In Debug state 1 S_REGRDY A handshake flag for transfers through the DCRDR [16:16] There has been a write to the DCRDR, but the transfer is not complete 0 The transfer to or from the DCRDR is complete 1 C_SNAPSTALL Allow imprecise entry to Debug state [5:5] No action 0 Allow imprecise entry to Debug state, for example by forcing any stalled load or store instruction to complete 1 C_MASKINTS When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts [3:3] Do not mask 0 Mask PendSV, SysTick and external configurable interrupts 1 C_STEP Processor step bit [2:2] No effect 0 Single step enabled 1 C_HALT Processor halt bit [1:1] Causes the processor to leave Debug state, if in Debug state 0 Halt the processor 1 C_DEBUGEN Halting debug enable bit [0:0] Disabled 0 Enabled 1 Debug Core Register Selector Register DCRSR provides debug access to the ARM core registers, special-purpose registers, and Floating-point extension regi 0x4 write-only REGWnR Specifies the access type for the transfer [16:16] Read 0 Write 1 REGSEL Specifies the ARM core register, special-purpose register, or Floating-point extension register, to transfer [6:0] The current SP 13 LR 14 DebugReturnAddress, see The DebugReturnAddress value 15 xPSR 16 Main stack pointer, MSP 17 Process stack pointer, PSP 18 Control, Faultmask, Basepri and Primask 20 Floating-point Status and Control Register, FPSCR 33 Debug Core Register Data Register DCRDR provides debug access to the ARM core registers, special-purpose registers, and Floating-point extensio 0x8 read-write DBGTMP Data temporary cache, for reading and writing the ARM core registers, special-purpose registers, and Floating-point extension registers [31:0] Debug Exception and Monitor Control Register DEMCR Manages vector catch behavior and DebugMonitor handling when debugging 0xC read-write TRCENA Global enable for all DWT and ITM features [24:24] DWT and ITM units disabled 0 DWT and ITM units enabled 1 MON_REQ DebugMonitor semaphore bit [19:19] MON_STEP When MON_EN is set to 0, this feature is disabled and the processor ignores MON_STEP [18:18] Do not step the processor 0 Step the processor 1 MON_PEND Sets or clears the pending state of the DebugMonitor exception [17:17] Clear the status of the DebugMonitor exception to not pending 0 Set the status of the DebugMonitor exception to pending 1 MON_EN Enable the DebugMonitor exception [16:16] DebugMonitor exception disabled 0 DebugMonitor exception enabled 1 VC_HARDERR Enable halting debug trap on a HardFault exception [10:10] Halting debug trap disabled 0 Halting debug trap enabled 1 VC_INTERR Enable halting debug trap on a fault occurring during exception entry or exception return [9:9] Halting debug trap disabled 0 Halting debug trap enabled 1 VC_BUSERR Enable halting debug trap on a BusFault exception [8:8] Halting debug trap disabled 0 Halting debug trap enabled 1 VC_STATERR Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception [7:7] Halting debug trap disabled 0 Halting debug trap enabled 1 VC_CHKERR Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error [6:6] Halting debug trap disabled 0 Halting debug trap enabled 1 VC_NOCPERR Enable halting debug trap on a UsageFault caused by an access to a Coprocessor [5:5] Halting debug trap disabled 0 Halting debug trap enabled 1 VC_MMERR Enable halting debug trap on a MemManage exception [4:4] Halting debug trap disabled 0 Halting debug trap enabled 1 VC_CORERESET Enable Reset Vector Catch [0:0] Reset Vector Catch disabled 0 Reset Vector Catch enabled 1 SIG Software Interrupt Generation 0xE000EF00 0x0 0x4 registers Software Triggered Interrupt Register STIR Provides a mechanism for software to generate an interrupt 0x0 write-only INTID Indicates the interrupt to be triggered [8:0] FP Floating-Point Extension 0xE000EF34 0x0 0x18 registers Floating Point Context Control Register FPCCR Holds control data for the Floating Point Unit 0x0 read-write ASPEN When this bit is set to 1, execution of a floating-point instruction sets the CONTROL [31:31] Executing an FP instruction has no effect on CONTROL.FPCA 0 Executing an FP instruction sets CONTROL.FPCA to 1 1 LSPEN Enables lazy context save of FP state [30:30] Disable automatic lazy context save 0 Enable automatic lazy context save 1 MONRDY Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending [8:8] Not able to set the DebugMonitor exception to pending 0 Able to set the DebugMonitor exception to pending 1 BFRDY Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending [6:6] Not able to set the BusFault exception to pending 0 Able to set the BusFault exception to pending 1 MMRDY Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending [5:5] Not able to set the MemManage exception to pending 0 Able to set the MemManage exception to pending 1 HFRDY Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending [4:4] Not able to set the HardFault exception to pending 0 Able to set the HardFault exception to pending 1 THREAD Indicates the processor mode when it allocated the FP stack frame [3:3] Handler mode 0 Thread mode 1 USER Indicates the privilege level of the software executing when the processor allocated the FP stack frame [1:1] Privileged 0 Unprivileged 1 LSPACT Indicates whether Lazy preservation of the FP state is active [0:0] Lazy state preservation is not active 0 Lazy state preservation is active 1 Floating Point Context Address Register FPCAR Holds the location of the unpopulated floating-point register space allocated on an exception stack frame 0x4 read-write Floating Point Default Status Control Register FPDSCR Holds the default values for the floating-point status control data that the processor assigns to the FPSCR when it creates a new floating-point context 0x8 read-write AHP Default value for FPSCR.AHP [26:26] DN Default value for FPSCR.DN [25:25] FZ Default value for FPSCR.FZ [24:24] RMode Default value for FPSCR.RMode [23:22] Media and FP Feature Register 0 MVFR0 Describes the features provided by the Floating-point extension 0xC read-only FP rounding modes Indicates the rounding modes supported by the FP floating-point hardware [31:28] All rounding modes supported 1 Short vectors Indicates the hardware support for FP short vectors [27:24] Not supported in ARMv7-M 0 Square root Indicates the hardware support for FP square root operations [23:20] Supported 1 Divide Indicates the hardware support for FP divide operations [19:16] Supported 1 FP exception trapping Indicates whether the FP hardware implementation supports exception trapping [15:12] Not supported in ARMv7-M 0 Double-precision Indicates the hardware support for FP double-precision operations [11:8] Not supported 0 Supported 2 Single-precision Indicates the hardware support for FP single-precision operations [7:4] Supported 2 A_SIMD registers Indicates the size of the FP register bank [3:0] Supported, 16 x 64-bit registers 1 Media and FP Feature Register 1 MVFR1 Describes the features provided by the Floating-point extension 0x10 read-only FP fused MAC Indicates whether the FP supports fused multiply accumulate operations [31:28] Supported 1 FP HPFP Floating Point Half-Precision and double-precision [27:24] Supports conversion between half-precision and single precision 1 As for 0b0001, and also supports conversion between half-precision and double-precision 2 D_NaN mode Indicates whether the FP hardware implementation supports only the Default NaN mode [7:4] Hardware supports propagation of NaN values 1 FtZ mode Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation [3:0] Hardware supports full denormalized number arithmetic 1 Media and FP Feature Register 2 MVFR2 Describes the features provided by the floating-point extension 0x14 read-only VFP_Misc Indicates the hardware support for FP miscellaneous features [7:4] No support for miscellaneous features 0 Support for floating-point selection, floating-point conversion to integer with direct rounding modes, floating-point round to i 4 CMO Cache Maintenance Operations 0xE000EF50 0x0 0x2C registers Instruction Cache Invalidate All to PoU ICIALLU Invalidate all instruction caches to PoU 0x0 write-only Ignored The value written to this field is ignored. Ignored [31:0] Instruction Cache line Invalidate by Address to PoU ICIMVAU Invalidate instruction cache line by address to PoU 0x8 write-only ADDRESS Address. Writing to this field initiates the maintenance operation for the address written [31:0] Data Cache line Invalidate by Address to PoC DCIMVAC Invalidate data or unified cache line by address to PoC 0xC write-only ADDRESS Address. Writing to this field initiates the maintenance operation for the address written [31:0] Data Cache line Invalidate by Set/Way DCISW Invalidate data or unified cache line by set/way 0x10 write-only SetWay Cache set/way. Contains two fields: Way, bits[31:32-A], the number of the way to operate on [31:4] Level Cache level. Cache level to operate on, minus 1 [3:1] Data Cache line Clean by address to PoU DCCMVAU Clean data or unified cache line by address to PoU 0x14 write-only ADDRESS Address. Writing to this field initiates the maintenance operation for the address written [31:0] Data Cache line Clean by Address to PoC DCCMVAC Clean data or unified cache line by address to PoC 0x18 write-only ADDRESS Address. Writing to this field initiates the maintenance operation for the address written [31:0] Data Cache Clean line by Set/Way DCCSW Clean data or unified cache line by set/way 0x1C write-only SetWay Cache set/way. Contains two fields: Way, bits [31:32-A], the number of the way to operate on [31:4] Level Cache level. Cache level to operate on, minus 1 [3:1] Data Cache line Clean and Invalidate by Address to PoC DCCIMVAC Clean and invalidate data or unified cache line by address to PoC 0x20 write-only ADDRESS Address. Writing to this field initiates the maintenance operation for the address written [31:0] Data Cache line Clean and Invalidate by Set/Way DCCISW Clean and invalidate data or unified cache line by set/way 0x24 write-only SetWay Cache set/way. Contains two fields: Way, bits[31:32-A], the number of the way to operate on [31:4] Level Cache level. Cache level to operate on, minus 1 [3:1] Branch Predictor Invalidate All BPIALL Invalidate all entries from branch predictors 0x28 write-only Ignored Ignored. The value written to this field is ignored [31:0] TPIU Trace Port Interface Unit 0xE0040000 0x0 0x1000 registers Supported Parallel Port Sizes Register TPIU_SSPSR Indicates the supported parallel trace port sizes 0x0 read-only SWIDTH[31:0] SWIDTH[N] represents a trace port width of (N+1) [31:0] Width (N+1) not supported 0 Width (N+1) supported 1 Current Parallel Port Size Register TPIU_CSPSR Defines the width of the current parallel trace port 0x4 read-write CWIDTH[31:0] CWIDTH[N] represents a trace port width of (N+1) [31:0] Width (N+1) is not the current trace port width 0 Width (N+1) is the current trace port width 1 Asynchronous Clock Prescaler Register TPIU_ACPR Defines a prescaler value for the baud rate of the Serial Wire Output (SWO) 0x10 read-write SWOSCALER SWO baud rate prescaler value [15:0] Selected Pin Protocol Register TPIU_SPPR Selects the protocol used for trace output 0xF0 read-write TXMODE Specifies the protocol for trace output from the TPIU [1:0] Parallel trace port mode 0 Asynchronous SWO, using Manchester encoding 1 Asynchronous SWO, using NRZ encoding 10 TPIU Type register TPIU_TYPE Defines the SWO options supported by the TPIU 0xF00 read-only NRZVALID Indicates support for SWO using UART/NRZ encoding [11:11] Not supported 0 Supported 1 MANCVALID Indicates support for SWO using Manchester encoding [10:10] Not supported 0 Supported 1 PTINVALID Indicates support for parallel trace port operation [9:9] Supported 0 Not supported 1 FIFOSZ Indicates the minimum implemented size of the TPIU output FIFO for trace data [8:6]