// Turn off trace before resetting, because the ETR only works while DRAM is
// properly set up
substitute eval $tracing = %EVAL{target trace_state}

if ($tracing) {
    trace off -no_retrieve
}

// Alternate soft reset through JTAG-AP.
// target jr
// target t 4..7 rw ctiintack 1
// target t 1 rw 2_0 0
// target t 1 rw 2_4 1
// target t 1 rw 2_0 0xd

target tr r
// If the ETR was on, the boot monitor won't run correctly; turn the ETR off and
// reset again.  We don't do this before resetting the ETR registers are not
// nessessarily accessible before resetting.
target etr_ctl = t 15 rr ctl
target if (etr_ctl != 0)
target     t 15 rw ctl 0
target     tr r
target endif
wait -time 3500
target t 4 th

// Use PSCI to turn on the secondary A53s
target t 4 th
target t 4 mw 0x00100000i 0xd2800072 // movz x18, #3
target t 4 mw 0x00100004i 0xd2b88000 // movz x0, #0xc400, lsl #16
target t 4 mw 0x00100008i 0xb2400400 // orr x0, x0, #0x3
target t 4 mw 0x0010000ci 0xaa1203e1 // mov x1, x18
target t 4 mw 0x00100010i 0x100000a2 // adr x2, .+20 (0x100024)
target t 4 mw 0x00100014i 0xd2800003 // movz x3, #0
target t 4 mw 0x00100018i 0xd4000003 // smc #0
target t 4 mw 0x0010001ci 0xf1000652 // subs x18, x18, #1
target t 4 mw 0x00100020i 0x54ffff21 // b.ne .-28 (0x100004)
target t 4 mw 0x00100024i 0x14000000 // b .+0 (0x100024)
target t 4 rw pc 0x00100000
target t 4 tc
wait -time 100
target t 4..7 th

// Set up the A53 cores
target t 4..7 rw pstate 0x000000cc
target t 4..7 rw sctlr_el3 0x00000000
target t 4..7 clop inval i * *
target t 4..7 clop inval d * *
target t 4    clop inval 2 * *
target t 4    mw 8 0x00001000 0x0000000000000661
target t 4    mw 8 0x00001008 0x0000000040000661
target t 4..7 rw vbar_el1 0x00000000
target t 4..7 rw vbar_el2 0x00000000
target t 4..7 rw vbar_el3 0x00000000
target t 4    mf 0x00000000 0x1000 0x14000000
target t 4..7 rw ttbr0_el3 0x00001000
target t 4..7 rw tcr_el3 0x00000021
target t 4..7 rw mair_el3 0x000000ff
target t 4..7 rw sctlr_el3 0x30c51835
target t 4..7 rw trcoslar 0
target t 4..7 rr trcpdsr
target t 4..7 rw scr_el3 0x400

// Turn on the Cortex-R5 cores in lock-step
target t 2 ma 0x80000000 0xffbfffff -
target t 4 mw 0xffff0000pi 0xeafffffe // Put a branch-to-self at the R5 boot address
target t 4 mw 0xFF9A0100p 5 // RPU0_CFG; clear nCPUHALT, enable FIQ masking, high vectors
target t 4 mw 0xFF5E023Cp 0 // CRL_APB; release R5 from reset
target t 2 th
target t 2 rw cpsr 0x1d3
target t 2 rw sctlr 0x00e5187c

// Enable TPIU input clock
// Uncomment this line for FPGA images that have external trace support
// target t 4 mw 0xfd1a0064p 0x01000500 // DBG_TRACE_CTRL

if ($tracing) {
    trace on
}