trcXXXX_YYYY

Applies to ETMv4 cores only.

Specifies the values of trace register capability fields. These options allow you to override the ARM Core TRM-documented values.

trcXXXX is the register name and YYYY is the field name:

• trcidr0_commopt — Sets the value of TRCIDR0.COMMOPT.
  
• trcidr0_condtype — Sets the value of TRCIDR0.CONDTYPE.
  
• trcidr0_instp0 — Sets the value of TRCIDR0.INSTP0.
  
• trcidr0_numevent — Sets the value of TRCIDR0.NUMEVENT.
  
• trcidr0_retstack — Sets the value of TRCIDR0.RETSTACK.
  
• trcidr0_trcbb — Sets the value of TRCIDR0.TRCBB.
  
• trcidr0_trccci — Sets the value of TRCIDR0.TRCCCI.
  
• trcidr0_trccond — Sets the value of TRCIDR0.TRCCOND.
  
• trcidr0_trcdata — Sets the value of TRCIDR0.TRCDATA.
  
• trcidr0_trcexdata — Sets the value of TRCIDR0.TRCEXDATA.
  
• trcidr0_tssize — Sets the value of TRCIDR0.TSSIZE.
  
• trcidr10_nump1key — Sets the value of TRCIDR10.NUMP1KEY.
  
• trcidr11_nump1spc — Sets the value of TRCIDR11.NUMP1SPC.
  
• trcidr12_numcondkey — Sets the value of TRCIDR12.NUMCONDKEY.
  
• trcidr13_numcondspc — Sets the value of TRCIDR13.NUMCONDSPC.
  
• trcidr2_vmidsize — Sets the value of TRCIDR2.VMIDSIZE.
  
• trcidr3_ccitmin — Sets the value of TRCIDR3.CCITMIN.
  
• trcidr3_nooverflow — Sets the value of TRCIDR3.NOOVERFLOW.
  
• trcidr3_stallctl — Sets the value of TRCIDR0.COMMOPT.
  
• trcidr4_numacpairs — Sets the value of TRCIDR4.NUMACPAIRS.
  
• trcidr4_numdvc — Sets the value of TRCIDR4.NUMDVC.
  
• trcidr4_numsscc — Sets the value of TRCIDR4.NUMSSCC.
  
• trcidr5_numcntr — Sets the value of TRCIDR5.NUMCNTR.
  
• trcidr5_numextinsel — Sets the value of TRCIDR5.NUMEXTINSEL.
  
• trcidr5_numseqstate — Sets the value of TRCIDR5.NUMSEQSTATE.
  
• trcidr8_maxspec — Sets the value of TRCIDR8.MAXSPEC.
  
• trcidr9_nump0key — Sets the value of TRCIDR9.NUMP0KEY.
  

The default setting for all trcXXXX_YYYY options is auto. To change the value, use the following syntax:

where trcXXXX is the register name and YYYY is the field name.

• auto — The trace tools use the value documented in the ARM Core TRM. If there are multiple configurations for a given core, they will default to the configuration with the fewest capabilities.
  
• value — The trace tools use value to determine the capabilities specified by the register field.
  

Adjust Large Timestamps WFI

This option requires ETMv4.

Enables a heuristic that adjusts large timestamps occurring near WFI/WFE instructions to align with said instructions.

ASIC Control

Provides a value for the optional ETMASIC Control register. This register is implemented by some ASICs and allows configuration of ASIC-specific features.

Auxilliary Core

This option is supported for ITM cores only.

Specifies the CPU core linked to the ITM. MULTI uses this information to provide the correct executable code to the ITM trace decoder.

Break On Trigger

Enables halting of the target processor when the trigger event occurs. There is some slip between when the trigger occurs and where the target halts. For more information about configuring a trigger event, see the documentation about configuring trace collection.

This option does not support external triggers.

Conditional Instructions

Controls the inclusion of trace information about the execution and condition codes of conditional non-branch instructions.

This option requires ETMv4.

• None — Does not trace conditional execution for non-branch conditional instructions.
  
• Loads — Traces conditional execution for loads.
  
• Stores — Traces conditional execution for stores.
  
• Loads and Stores — Traces conditional execution for loads and stores.
  
• All — Traces conditional execution for all conditional instructions.
  

If data trace is enabled, you must trace conditional instruction information for any instructions generating data trace. For example, if data is traced from loads, you must set this option to Loads, Loads and Stores, or All. For full Time Machine operation, you must trace conditional execution information of All instructions. If conditional execution information for an instruction is not traced, the instruction will show as executed in the Trace List.

CoreSight Source ID

The CoreSight trace source ID of the ETM. Each CoreSight trace source on a system must have a unique ID between 0x1 and 0x6f.

CoreSight Timestamp Clock Frequency

Specifies the speed of the target's timestamp counter clock when Timestamps Source is set to CoreSight. Timestamps are computed using this value and event counts read from the target. Frequencies must be between 10kHz and 4GHz (inclusive), formatted as an integer with GHz/MHz/kHZ/Hz. Providing a frequency that is significantly slower than the actual frequency can lead to timestamp overflows.

This option should be set to the target's CoreSight timestamp clock frequency. Changing this value does not change the target's clocks. The correct value for this option can be determined from the target's documentation and clocking configuration. Alternatively, if your target includes a Timestamp Generator core, the frequency can be measured by sampling the cnt_cv register, or by reading the virtual register freq_hz, which internally samples the cnt_cv register twice and returns the computed frequency in Hertz.

This option has no default value. If no value is provided, an error will appear at the beginning of the trace list.

CoreSight Timestamp Generation Period

When Timestamps Source is set to CoreSight, this option controls the periodic generation of timestamps. The value specifies the number of CPU clock cycles between periodically generated timestamps. Smaller values cause the target to generate more frequent timestamps, which consume more bandwidth and more space in the trace buffer, but allow for more fine-grained time measurements. The correct way to manage this trade-off varies by use-case. Note that if this value is set too small, trace discontinuities may appear due to insufficient bandwidth.

Cycle-accurate trace is better suited for very fine-grained measurements. Values may range from 0x0 to 0xffff. A value of 0x0 will disable periodic timestamp generation. The CoreSight system will still generate timestamps at certain synchronization events. Periodic timestamp generation results in a timestamp request to the target. It is implementation defined whether and when a target will generate a timestamp in response to such a request.

Cycle Accurate

Enables ETM cycle-accurate mode. For ETMv1.x targets, the ETM normally outputs one trace packet every cycle when trace is enabled. Often many of these packets contain no useful information and can be discarded by the trace collection device. When this option is enabled on those targets, no packets will be discarded. For ETMv3.x targets, this option enables cycle-accurate mode in the ETM, which then outputs cycle count data. This allows the trace tools to determine the number of cycles spent executing each instruction, but requires extra space in the trace buffer.

Note: For ETMv1.x targets, the ETM continues to output trace packets even when the processor is stopped at a breakpoint. Therefore it is generally not a good idea to enable Cycle Accurate mode if you will be hitting breakpoints while collecting trace data from an ETMv1.x target.

Cycle Count Threshold

This option is only supported with ETMv4.

Specifies the tradeoff between trace compression efficiency and cycle count precision. Higher values improve efficiency while reducing precision, and vice versa. Acceptable values have an implementation-defined minimum (typically 4) and range to 4000. Cycle count packets are only output when the cycle count is greater than the Cycle Count Threshold. Cycle counts below the threshold are not output when entering debug mode or when trace is disabled.

Data Address/Value

This option is only supported with ETMv4.

Selects the data access information that will be traced. The ETM can either trace data access addresses and values, addresses only, or values only.

Note: To reduce the number of ETMFIFO overflows in your trace data, you can set this option to Address Only. However, this setting reduces the effectiveness of TimeMachine by preventing reconstruction of register and memory values. For more information, see the documentation about incomplete trace data.

Data Analysis Size

This option is only supported with ETMv4.

Indicates the number of instruction trace packets to analyze for correlating data trace with instructions. Smaller values may result in data trace that cannot be correlated with the instruction that output it. Larger values increase trace decoder memory usage and slow decompression speed moderately. Values can be set from 1000 to 5,000,000.

Data Capture

Selects the data access information that will be traced. The ETM can either trace data access addresses and values, addresses only, or values only.

Note: To reduce the number of ETMFIFO overflows in your trace data, you can set this option to Address Only. However, this setting reduces the effectiveness of TimeMachine by preventing reconstruction of register and memory values. For more information, see the documentation about incomplete trace data.

Data Trace

Enables or disables trace of data accesses.

Data Transfer Type

Selects the data transaction types to trace:

• Loads
  
• Stores
  
• Loads and Stores
  

Data Only Trace

Enables data-only mode for ETMv3.0 and greater. In this mode, the target traces data accesses only and does not output PC information.

ETR AXICTL

This option is available if the probe configuration option axictl is set to not_set on the core at connect time. This value is written to the ETR’sAXICTL register. In most cases, the default value, 0x3f, is acceptable. For more information, see CoreSight Trace Memory Controller Technical Reference Manual, ARM DDI 0461B, available from ARM Ltd.

ETR Base Address

This option is available if the probe configuration option buffer_size on the core is 0 at connect time. An ETR saves trace data to the target's memory. Set this option to the word-aligned physical address of a region of memory you want to use. The memory used for the ETR buffer should not overlap with a cache line used by the CPU, or share a cache line with any memory used by the CPU.

ETR Size

This option is available if the probe configuration option buffer_size on the core is 0 at connect time. An ETR saves trace data to the target's memory. Set this option to the size, in bytes, of the region of memory you want to use. The memory used for the ETR buffer should not overlap with a cache line used by the CPU, or share a cache line with any memory used by the CPU.

Filter Trace of Coprocessor Registers

Applies ETM data trace filtering to coprocessor register transfers. For more information about trace data filters, see the documentation about the Data Trace event in the Set Triggers window.

This option is only available when the Trace Coprocessor Registers option is enabled.

Half Rate Clocking

Enables ETM half rate clocking mode. In this mode, trace packets are output on both the rising and falling edges of the trace clock. This allows the trace clock to run at half the speed of the core clock.

Note: Some targets do not support half rate clocking and some targets only support half rate clocking. If your target only supports one clocking mode, the Half Rate Clocking option is disabled and the appropriate clocking mode is selected automatically.

Note: This option is not available with ETMv3.x targets because trace data is always output on both clock edges with ETMv3.x.

Infer Branch Target

Controls the circumstances in which the target emits a branch's target address instead of requiring the decoder to infer the address. Trace data is more compact when the decoder infers more branch targets, while the decoder is more resilient to errors in the collected trace data when fewer branches must be inferred. There are three choices:

• Never — The PTM emits the target address for all branches, and the decoder never needs to infer the target.
  
• Direct Branches — The PTM does not emit the target address for direct branches; the decoder must infer them instead.
  
• Direct Branches and Return Addresses — The PTM does not emit the target address for direct branches or for some indirect branches that return from a function; the decoder must infer them instead. Use this option if you are uncertain which option is most appropriate.
  

Instructions After WFI

This option requires ETMv4.

Sets the maximum number of instructions a post-WFI/WFE large timestamp will be shifted to be on a WFI/WFE instruction.

Instructions Before WFI

This option requires ETMv4.

Sets the maximum number of instructions a pre-WFI/WFE large timestamp will be shifted to be on a WFI/WFE instruction.

No Path To Sink

Trace of this core is disabled because the Trace Sink you have selected cannot receive trace from it.

Overflow Threshold

Some ETM targets can stall the CPU or suppress data trace to prevent a FIFO overflow when the ETM FIFO is close to full. This option specifies the number of bytes remaining in the FIFO when that action will be done. Setting this option to 0 disables overflow prevention.

When using this option with Prevent Overflow by Stalling CPU, setting a value greater than or equal to the size of your FIFO may cause errors when running or single-stepping (because the CPU is constantly stalled). FIFO sizes are implementation defined, but are often around 16 to 32 bytes. For more information, see the Prevent Overflow by option.

Note: The ETM FIFO (a part of the ETM) should not be confused with an ETF (Embedded Trace FIFO), a CoreSight trace component. For more information, see the ARM Embedded Trace Macrocell Architecture Specification, section 3.5.14.

PMU Event 0-3

This option is not currently supported. Contact Green Hills Support if you require this feature.

Selects events to trace from the Performance Monitoring Unit. Up to four events may be selected, depending on hardware support. PMU events use the same hardware resources as trigger events, so each event may be configured as either a trigger event or a PMU event (the trigger is event 0).

A list of events may be found in the TRM for your target hardware.

Port Mode

Selects the ETM clocking mode used on the target system.

There are three choices for ETMv1.x targets:

• Normal — Most targets only support this mode.
  
• Multiplexed — Uses half as many pins to output trace information, but twice the clock rate.
  
• Demultiplexed — Uses twice as many pins and half the clock rate. This mode typically requires a special adapter with dual Mictor connectors.
  

Multiplexed and Demultiplexed modes were eliminated with ETMv3.x. However, many ETMv3.x targets support several ETM clock multipliers relative to the processor core clock. All of the ETMv3.x clocking modes are listed below. Note that the ratios are of ETM data rate to core clock speed. The ETM data rate is twice the ETM clock speed because ETMv3.x always outputs data on both clock edges.

• 2:1
  
• 1:1
  
• 1:2
  
• 1:3
  
• 1:4
  
• Implementation Defined
  
• Dynamic
  

Port Size/CoreSight Port Size

Selects the ETM port size. This corresponds to the number of bits that will be drained from the ETMFIFO each cycle. Larger port sizes mean that more data can be generated without causing an overflow. It is generally desirable to use the largest port size supported by the target system.

For CoreSight targets, this option displays as CoreSight Port Size.

Prioritize Instruction Trace

This option is only supported with ETMv4.

When enabled, enables the ETM to prioritize Instruction Trace over Data Trace when near overflow. The operation of this option is dependent on Trace Invasiveness Level.

Prevent Overflow by

Enables the ETMFIFOFull mechanism. The amount of data output by the ETM varies depending on the code being executed and the trace configuration. Code with a large number of indirect branches and data accesses (if data trace is enabled) may generate so much data that the ETMFIFO overflows. Trace data is lost when this happens. If this option is enabled, the ETM attempts to prevent FIFO overflows by using the selected method:

• Stalling CPU — Attempts to stall the target processor when the FIFO is close to overflowing. This slows execution of code on the target, but can be very helpful in reducing the number of gaps in the trace data.
  
• Suppressing Data Trace — Suppresses data trace when the FIFO is close to overflowing. This method is only available with ETMv3.x targets. Suppressing data trace is less effective at preventing the FIFO from overflowing than stalling the CPU, but has no impact on the speed of execution.
  

To configure the overflow threshold, see the Overflow Threshold option.

For more information, see the documentation about incomplete trace data.

Note: The ETMFIFOFull mechanism is not supported by some targets. The above methods of preventing overflow are also target specific. Additionally, the ETM FIFO (a part of the ETM) should not be confused with an ETF (Embedded Trace FIFO), a CoreSight trace component. For more information, see the ARM Embedded Trace Macrocell Architecture Specification, section 3.5.14.

Return Stack

This option is only supported with ETMv4.

Controls whether to remove inferred return addresses from the trace stream. When this option is enabled, some return addresses can be inferred from the rest of trace and are not output. This improves trace compression efficiency.

Smooth Cycle Count

This option is only supported with ETMv4.

Controls whether cycle counts are output immediately, or smoothed by dividing them as evenly as possible among intervening instructions. Because ETMv4 cycle count packets are not assignable to single instructions—or even to single basic blocks—this option should generally be enabled. Note that Smooth Cycle Count must be enabled when Cycle Count Threshold is set to 200 or greater.

Stall CPU for Data Trace

This option is only supported with ETMv4.

When enabled, stalls the CPU when the data trace stream is near overflow. The operation of this option is dependent on Trace Invasiveness Level.

Stall CPU for Instruction Trace

This option is only supported with ETMv4.

When enabled, stalls the CPU when the instruction trace stream is near overflow. The operation of this option is dependent on Trace Invasiveness Level.

Timestamps

Enables timestamps. When timestamps are enabled, the trace collection device records a timestamp with each packet. Timestamps are displayed in the Trace List and are used by the MULTI Profile window, PathAnalyzer, and EventAnalyzer.

Timestamps Source

Selects which source to use for timestamps.

• None – Does not use timestamps.
  
• Trace Probe – Uses timestamps from a SuperTrace Probe v3 or Green Hills Probe v4. This option requires the probe to be connected to a trace-capable debug port on the target. Note: this option is not available when tracing to an on-target buffer, such as an ETB or ETR.
  
• CoreSight – Uses CoreSight timestamps generated by target hardware. This option is only supported on ETMv4 and requires that all trace capable cores connected to mpserv are ETMv4.
  

Timestamp Threshold

This option requires ETMv4.

A count in picoseconds of the minimum timestamp size that will be adjusted to be on a WFI/WFE instruction.

Trace Coprocessor Registers

Enables data trace of coprocessor register transfers. For more information about the instructions that perform these transfers, see ARM Embedded Trace Macrocell Architecture Specification, section 4.11.3.

Trace Enable (core n)

Enables or disables trace collection on an individual core in the system. This option determines the cores for which trace data is collected when Enable Trace is turned on.

Trace Invasiveness Level

This option is only supported with ETMv4.

Sets a monotonically increasing threshold level that controls how invasive trace is to normal processor operations. 0 is minimally invasive, with a greater chance of overflow. 15 is maximally invasive, enabling stalling, instruction prioritization, and other methods to reduce overflows.

Trace Sink

Chooses which trace sink to use. This option may only be changed if there are more than one supported sinks to choose between.

• Trace Probe — Trace is output to the SuperTrace Probe v3 or Green Hills Probe v4. On CoreSight systems, a Trace Port Interface Unit (TPIU) is used to output trace. On pre-CoreSight systems, the trace macrocell outputs trace directly
  
• On-Chip Buffer — Trace is output to an Embedded Trace Buffer (ETB) or to an Embedded Trace FIFO (ETF) operating in Circular Buffer Mode. Any ETF not being used as a trace sink is placed into Hardware FIFO mode.
  
• Target Memory — Trace is output to an Embedded Trace Router (ETR). An ETR will save trace data to the target’s memory. The options ETR Base Address, ETR Size and ETR AXICTL must also be set correctly.
  

If the target has multiple instances of the same type of trace sink, then they are all listed, and can be distinguished by their APB-AP Index and Address.

Note: If using the MULTI trace set command to set the Trace Sink option, your changes may not be respected unless you also issue the command trace set"Use Trace Sink" On.

Uncorrelated Data

This option is only supported with ETMv4.

Indicates what to do when data trace cannot be correlated with instruction trace:

• Discard — Does not output the uncorrelated data.
  
• Output — Outputs the data as uncorrelated. This means that the Trace List will show the data access, but it will not be used for memory or register reconstruction. Note that this may cause data transfers that never occurred to be output as uncorrelated. This is because the decoder cannot determine whether the data transfers were for canceled instructions.
  
• Error — Outputs an error. This is useful to guarantee that no trace data was uncorrelated.
  

If FIFO overflows are present, uncorrelated data will be discarded regardless of the setting of this option.

Use Embedded Trace Buffer

Enables use of the Embedded Trace Buffer (ETB). This option may only be changed if you use a SuperTrace Probe v3 to connect to a target that has an ETB. If you use a Green Hills Probe to connect to a target with an ETB, the ETB is the only method available for collecting trace.

Cycle Accurate

Enables cycle-accurate mode. Often many trace packets contain no useful information and can be discarded by the trace collection device. When this option is enabled, no packets will be discarded. This allows the trace tools to determine the number of cycles spent executing each instruction, but requires extra space in the trace buffer.

Data Capture

Selects the data access information that will be traced:

• No Data Values (PC Trace Only)
  
• Reads Only
  
• Writes Only
  
• Reads and Writes
  

INTEGRITY Interrupts at Address

Specifies the address that the interrupt vectors are copied to. For most ColdFire cores, this option should be set to 0x0.

INTEGRITY Interrupts at Other Location

Enable this option if you are tracing INTEGRITY and the BSP copies the interrupt handlers to a different address than the .vector section is mapped to.

Timestamps

Enables timestamps. When timestamps are enabled, the trace collection device records a timestamp with each packet. Timestamps are displayed in the Trace List and are used by the MULTI Profile window, PathAnalyzer, and EventAnalyzer.

MDO Data Port Width

Selects the number of pins used to output trace data. Some targets support multiple MDO data port widths. Using a larger port width reduces the chance of a processor stall and/or FIFO overflow. We recommend using the largest port width that your target supports. If you specify an unsupported port width, you may get invalid trace data.

Stall Processor to Avoid Overflows

Enables processor stalling to prevent FIFO overflows. The amount of trace data output by the target varies depending on the code being executed and the trace configuration. Code with a large number of indirect branches and data accesses (if data trace is enabled) may generate so much data that the FIFO overflows. Trace data is lost when this happens. If this option is enabled, the processor stalls when the FIFO starts to fill. This is very effective at preventing FIFO overflows, but does not prevent all overflows. For more information, see the documentation about incomplete trace data.

Note: OS-awareness in TimeMachine requires specific parts of OS execution to be reconstructed. If kernel trace data is lost due to FIFO overflows, MULTI may discard trace data for some tasks. In this case, enabling Stall Processor to Avoid Overflows may improve OS-awareness.

Timestamps

This option is only supported on trace probes.

Enables timestamps. When timestamps are enabled, the trace collection device records a timestamp with each packet. Timestamps are displayed in the Trace List and are used by the MULTI Profile window, PathAnalyzer, and EventAnalyzer.

Trace Clock Multiplier

Specifies the divisor for the trace clock. Not all targets support all divisors listed. In general, a faster trace collect (smaller divisor) allows for more data to be collected and results in fewer FIFO overflows. If you specify a divisor that your target does not support, you may get invalid trace data.

Use Branch History Messages

Enables branch history messaging. Most Nexus targets are capable of generating two different types of Nexus program trace messages. Traditional Nexus program trace messages are generated each time a branch is taken (direct or indirect). Branch history messaging only generates a message when 31 direct branch instructions have been executed (taken or not) or when an indirect branch is taken.

Advantages of Branch History Messages:

• More compact trace data
  
  • Less chance of overflow
    
  • Better utilization of trace buffer space
    

Disadvantages of Branch History Messages:

• More likely to have uncorrelated data trace
  
• More data is lost as a result of an overflow
  
  • Less likely that the tools will be able to reconstruct missing instructions
    
• Less precise filtering
  
• Less accurate timestamps
  
• Less precise reporting of trigger locations
  

Note: ARM mode instructions on Nexus ARM targets (MAC71xx) are always traced with branch history messages.

Branch and link correlation messages

Enables trace messages every time a branch and link occurs. When these messages are enabled, timestamps are more precise, but trace data is less efficient.

CoreNet Trace

Enables trace output from the CoreNet peripheral. This trace output appears in the Trace List, but is not processed in any other way.

Data Path Trace

Enables trace output from the Data Path peripheral. This trace output appears in the Trace List, but is not processed in any other way.

DDR Trace

Enables trace output from the DDR peripheral. This trace output appears in the Trace List, but is not processed in any other way.

Enable/Disable program trace with MSR[PMM]

When used in conjunction with a mechanism in target software that sets and clears the MSR[PMM] bit, this option aids in determining which sections of code are traced. The MSR[PMM] bit is the performance monitor mark bit, used by Nexus to provide execution context filtering.

OCeaN Trace

Enables trace output from the OCeaN peripheral. This trace output appears in the Trace List, but is not processed in any other way.

Stall Processor to Avoid Overflows

Enables processor stalling to prevent FIFO overflows. The amount of trace data output by the target varies depending on the code being executed and the trace configuration. Code with a large number of indirect branches and data accesses (if data trace is enabled) may generate so much data that the FIFO overflows. Trace data is lost when this happens. If this option is enabled, the processor stalls when the FIFO starts to fill. This is very effective at preventing FIFO overflows, but does not prevent all overflows. For more information, see the documentation about incomplete trace data.

Note: OS-awareness in TimeMachine requires specific parts of OS execution to be reconstructed. If kernel trace data is lost due to FIFO overflows, MULTI may discard trace data for some tasks. In this case, enabling Stall Processor to Avoid Overflows may improve OS-awareness.

Stall threshold

When Stall Processor to Avoid Overflows is enabled, indicates a fraction of trace message queue capacity at which the processor should stall. Smaller values result in more frequent stalls, but fewer FIFO overflows.

Timestamps

Enables timestamps. When timestamps are enabled, the trace collection device records a timestamp with each packet. Timestamps are displayed in the Trace List and are used by the MULTI Profile window, PathAnalyzer, and EventAnalyzer.

QorIQ targets buffer Nexus trace data before sending it out over high-speed serial trace (HSST). The buffer creates a variation in the time delta between when the packet is emitted by the core and when it is actually sent over HSST. The size of the delta is inversely proportional to the HSST bandwidth, and varies depending on how full the buffer is. At minimum bandwidth (1 Aurora lane at 2.5 Gbps), the maximum error is approximately 65 us.

Trace core n

Enables or disables trace collection on an individual core in the system. This option determines the cores for which trace data is collected when Enable Trace is turned on.

Cycle Accurate

Enables IBM cycle-accurate mode. Often many trace packets contain no useful information and can be discarded by the trace collection device. When this option is enabled, no packets will be discarded. This allows the trace tools to determine the number of cycles spent executing each instruction, but requires extra space in the trace buffer.

Timestamps

Enables timestamps. When timestamps are enabled, the trace collection device records a timestamp with each packet. Timestamps are displayed in the Trace List and are used by the MULTI Profile window, PathAnalyzer, and EventAnalyzer.