#ifndef __ARM64_IS #ifdef __ghs__ #pragma ghs startnomisra #endif #define __ARM64_IS #ifdef __cplusplus extern "C" { #endif #if defined(__ATTRIBUTES) #define __ARM64SAFE __attribute__((const,pure)) #define __ARM64PURE __attribute__((pure)) #else #define __ARM64SAFE #define __ARM64PURE #endif /* Retrieve address for return from function from link register or frame. */ void * __builtin_return_address(unsigned int level) __ARM64PURE; /* Retrieve frame pointer from frame pointer register or frame. * Requires target walkable stack. */ void * __builtin_frame_address(unsigned int level) __ARM64PURE; /* Return current function's stack pointer. */ void *__get_stack_pointer(void); /* CLZ : Count leading zeros */ unsigned int __CLZ32(unsigned int Rm) __ARM64SAFE; #if defined(__LLONG_BIT) unsigned int __CLZ64(unsigned long long Rm) __ARM64SAFE; #endif /* UMULH, SMULH : High 64 bits of 64x64->128 bit multiply */ #if defined(__LLONG_BIT) unsigned long long __MULUH64(unsigned long long Rm, unsigned long long Rs) __ARM64SAFE; signed long long __MULSH64( signed long long Rm, signed long long Rs) __ARM64SAFE; #endif /* UMULL, SMULL : High 32 bits of 32x32->64 bit multiply */ unsigned int __MULUH(unsigned int Rm, unsigned int Rs) __ARM64SAFE; signed int __MULSH( signed int Rm, signed int Rs) __ARM64SAFE; /* Add with carry */ #if defined(__LLONG_BIT) unsigned long long __ADD_WITH_CARRY64(unsigned long long a, unsigned long long b, unsigned char carry_in, unsigned char *carry_out); #endif /* Byte reverse instructions */ #if defined(__LLONG_BIT) unsigned long long __REV64(unsigned long long Rm) __ARM64SAFE; unsigned long long __REV32(unsigned long long Rm) __ARM64SAFE; unsigned long long __REV16(unsigned long long Rm) __ARM64SAFE; signed int __REVSH(signed int Rm) __ARM64SAFE; #endif /* Bit reverse instruction */ unsigned int __RBIT32(unsigned int Rm) __ARM64SAFE; #if defined(__LLONG_BIT) unsigned long long __RBIT64(unsigned long long Rm) __ARM64SAFE; #endif /* v8 barrier option values to be used with OPT forms of DMB/DSB */ enum { __BARRIER_SY = 15, __BARRIER_ST = 14, __BARRIER_LD = 13, __BARRIER_ISH = 11, __BARRIER_ISHST = 10, __BARRIER_ISHLD = 9, __BARRIER_NSH = 7, __BARRIER_NSHST = 6, __BARRIER_NSHLD = 5, __BARRIER_OSH = 3, __BARRIER_OSHST = 2, __BARRIER_OSHLD = 1 }; /* pstatefield values for __MSR_IMM */ enum { __PSF_SPSel = 0x05, /* 000 101 */ __PSF_DAIFSet = 0x1e, /* 011 110 */ __PSF_DAIFClr = 0x1f, /* 011 111 */ __PSF_PAN = 0x04, /* 000 100 */ __PSF_UAO = 0x03 /* 000 011 */ }; /* Exception mask bits */ enum { __EMB_D = 0x8, /* Debug */ __EMB_A = 0x4, /* SError */ __EMB_I = 0x2, /* IRQ */ __EMB_F = 0x1 /* FIQ */ }; /* Data Memory Barrier */ void __DMB_OPT(__ghs_c_int__ option); #define __DMB() (__DMB_OPT(__BARRIER_SY)) /* Data Synchronization Barrier */ void __DSB_OPT(__ghs_c_int__ option); #define __DSB() (__DSB_OPT(__BARRIER_SY)) /* Instruction Synchronization Barrier */ void __ISB(void); /* Architectural hints */ void __NOP(void); void __YIELD(void); void __WFE(void); void __WFI(void); void __SEV(void); void __CSDB(void); /* Read/write system registers */ #if defined(__LLONG_BIT) unsigned long long __MRS(__ghs_c_int__ regnum); void __MSR(__ghs_c_int__ regnum, unsigned long long Rn); /* Used for providing the regnum argument to the above. * The arguments correspond to the , , , , and * arguments to the MRS and MSR instructions; see the ARM Architecture * Reference Manual for more information about those arguments. */ typedef unsigned int __SYS_REG_TYPE; #define __GENERIC_SYS_REG(__op0, __op1, __CRn, __CRm, __op2) \ ((((__SYS_REG_TYPE)__op0) << 14) | (((__SYS_REG_TYPE)__op1) << 11) | \ (((__SYS_REG_TYPE)__CRn) << 7) | (((__SYS_REG_TYPE)__CRm) << 3) | \ ((__SYS_REG_TYPE)__op2)) /* The following file includes definitions for many of the named system * registers, which can be accessed by __; e.g. __FPCR. For use in * conjunction with the MRS and MSR instructions as with __GENERIC_SYS_REG(). */ #include "arm64_ghs_sprs.h" #endif /* Write immediate value to system register. pstatefield contains the numerical * value used to encode the argument to the MSR (immediate) * instruction. It takes the form: * * pstatefield = (op1 << 3) | op2 * * See the ARM Architecture Reference Manual for more information about * encodings of different s. As an example, DAIFSet is encoded as * op1 = 0b011, op2 = 0b110 * so would correspond to * pstatefield = 0b011110 = 0x1e */ void __MSR_IMM(__ghs_c_int__ pstatefield, __ghs_c_int__ val); /* System instruction */ void __SYS_XZR(__ghs_c_int__ op1, __ghs_c_int__ Cn, __ghs_c_int__ Cm, __ghs_c_int__ op2); #if defined(__LLONG_BIT) void __SYS (__ghs_c_int__ op1, __ghs_c_int__ Cn, __ghs_c_int__ Cm, __ghs_c_int__ op2, unsigned long long Rt); #endif /* __DI/__EI: Disable/enable maskable interrupts */ #define __DI() (__MSR_IMM(__PSF_DAIFSet, __EMB_I | __EMB_F)) #define __EI() (__MSR_IMM(__PSF_DAIFClr, __EMB_I | __EMB_F)) /* __DIR/__EIR: Disable/enable maskable interrupts, and return a key for use * with __RIR */ #if defined(__LLONG_BIT) unsigned long long __DIR(void); unsigned long long __EIR(void); #endif /* __RIR: Restore interrupts to their state prior to a call to __DIR or __EIR */ #if defined(__LLONG_BIT) void __RIR(unsigned long long key); #endif /* __LDXR: Load exclusive register */ unsigned char __LDXR8 (unsigned char *addr); unsigned short __LDXR16(unsigned short *addr); unsigned int __LDXR32(unsigned int *addr); #if defined(__LLONG_BIT) unsigned long long __LDXR64(unsigned long long *addr); #endif /* __STXR: Store exclusive register */ int __STXR8 (unsigned char value, unsigned char *addr); int __STXR16(unsigned short value, unsigned short *addr); int __STXR32(unsigned int value, unsigned int *addr); #if defined(__LLONG_BIT) int __STXR64(unsigned long long value, unsigned long long *addr); #endif #ifdef __cplusplus } #endif #ifdef __ghs__ #pragma ghs endnomisra #endif #endif