# ARM920T Coprocessor 15 (system coprocessor) registers


enum {

    "testcfg_DDCache_streaming" {
        "enable" {value = 0 desc="Enable DCache streaming" }
        "disable" {value = 1 desc="Disable DCache streaming" }
    }
    "testcfg_DICache_streaming" {
        "enable" {value = 0 desc="Enable ICache streaming" }
        "disable" {value = 1 desc="Disable ICache streaming" }
    }
    "testcfg_DDCache_fill" {
        "enable" {value = 0 desc="Enable DCache linefills" }
        "disable" {value = 1 desc="Disable DCache linefills" }
    }
    "testcfg_DICache_fill" {
        "enable" {value = 0 desc="Enable ICache linefills" }
        "disable" {value = 1 desc="Disable ICache linefills" }
    }
    "testcfg_CP15_R1" {
        "enable R1" {value = 0 desc="Enable CP15 R1" }
        "disable R1" {value = 1 desc="Disable CP15 R1" }
    }
    "async_fastbus_mode" {
        "FastBus"      { value = 0 desc="FastBus mode" }
	"Synchronous"  { value = 1 desc="Synchronous mode" }
	"Reserved"     { value = 2 }
	"Asynchronous" { value = 3 desc="Asynchronous mode" }
    }
    "non_cacheable" {
        "Normal"        { value = 0 desc="Normal operation" }
        "Non cacheable" { value = 1 desc="Force noncacheable behavior in cache" }
    }
    "MMU_test" {
        "Normal" {value = 0 desc="Disable auto-increment" }
        "test"   {value = 1 desc="Enable auto-increment" }
    }
    "disable_hw_pgtbl_walk" {
        "normal"     { value = 0 desc="Enable TLB hardware page table walks" }
        "miss abort" { value = 0 desc="Disable TLB hardware page table walks" }
    }
    "testcfg_CP15_interpret" {
        "no CP15 interpret"      { value = 0 desc="Disable CP15 interpret mode" }
        "CP15 in interpret mode" { value = 1 desc="Enable CP15 interpret mode" }
    }
    "testcfg_Test and clean all" {
        "single" { value = 0 ln = "test and clean single entry" }
	"all"    { value = 1 ln = "test and clean all" }
    }

}


bitfield {

testcfg_bitfield {
%if (_TARGET==ARM_920) 
        "Dis DCache streaming" { loc = "12..12" type = "testcfg_DDCache_streaming" desc = "Disable DCache Streaming" }
        "Dis ICache streaming" { loc = "11..11" type = "testcfg_DICache_streaming" desc = "Disable ICache Streaming" }
        "Dis DCache fill" { loc = "10..10" type = "testcfg_DDCache_fill" desc = "Disable DCache linefill" }
        "Dis ICache fill" { loc = "9..9" type = "testcfg_DICache_fill" desc = "Disable ICache linefill" }
        "Dis CP15,c1,bits[31:30]" { loc = "8..8" type = "testcfg_CP15_R1" desc = "Disable R1" }
        "iA,nF async" { loc = "7..6" type = "async_fastbus_mode" desc = "StrongARM compatible async/FastBus select" }
        "D force noncachable" { loc = "5..5" type = "non_cacheable" desc = "Force noncacheable behavior in the DCache" }
        "I force noncachable" { loc = "4..4" type = "non_cacheable" desc = "Force noncacheable behavior in the ICache" }
        "MMU test" { loc = "3..3" type = "MMU_test" desc = "MMU test" }
        "I miss abort" { loc = "2..2" type = "disable_hw_pgtbl_walk" desc = "Disable Instruction TLB hardware page walk" }
        "D miss abort" { loc = "1..1" type = "disable_hw_pgtbl_walk" desc = "Disable Data TLB hardware page walk" }
        "CP15 interpret mode" { loc = "0..0" type = "testcfg_CP15_interpret" desc = "Enable CP15 interpret mode" }
%endif   
}

}

# Register definitions
register {
    id {
	sn="id"
	ln="ID Code Register c0"
	address=177
	type="id_bitfield"
    }
    cachetype {
	sn="cachetype"
	ln="Cache Type Register c0"
	address=179
	type="cachetype_bitfield"
    }
    control {
	sn="control"
	ln="Control Register c1"
	address=178
	type="control_bitfield"
    }
    i_ttbase {
	sn="i_ttbase"
	ln="Instruction Translation Table Base Register c2"
	address=310
	type="ttbase_bitfield"
    }
    d_ttbase {
	sn="d_ttbase"
	ln="Data Translation Table Base Register c2"
	address=311
	type="ttbase_bitfield"
    }
    i_dactl {
	sn="i_dactl"
	ln="Instruction Domain Access Control Register c3"
	address=308
	type="dactl_bitfield"
    }
    d_dactl {
	sn="d_dactl"
	ln="Data Domain Access Control Register c3"
	address=309
	type="dactl_bitfield"
    }
    i_fsr {
	sn="i_fsr"
	ln="Instruction Fault Status Register c5"
	address=312
	type="faultstatus_bitfield"
    }
    d_fsr {
	sn="d_fsr"
	ln="Data Fault Status Register c5"
	address=313
	type="faultstatus_bitfield"
    }
    i_far {
	sn="i_far"
	ln="Instruction Fault Address Register c6"
	desc="Contains the Modified Virtual Address of the access being attempted when a Data Abort occurred."
	address=314
    }
    d_far {
	sn="d_far"
	ln="Data Fault Address Register c6"
	desc="Contains the Modified Virtual Address of the access being attempted when a Data Abort occurred."
	address=315
    }
    ic_lock {
	sn="ic_lock"
	ln="Data Cache Lockdown Register c9"
	address=185
	type="cachelock_bitfield"
    }
    dc_lock {
	sn="dc_lock"
	ln="Instruction Cache Lockdown Register c9"
	address=186
	type="cachelock_bitfield"
    }
    itlb_lock {
	sn="itlb_lock"
	ln="Instruction TLB Lockdown Register c10"
	address=187
	type="tlblock_bitfield"
    }
    dtlb_lock {
	sn="dtlb_lock"
	ln="Data TLB Lockdown Register c10"
	address=188
	type="tlblock_bitfield"
    }
    pid {
	sn="pid"
	ln="Fast Context Switch Extension (FCSE) Process Identifier (PID) Register c13"
	address=189
	type="pid_bitfield"
    }
    test_cfg {
    	sn="test_cfg"
    	address=190
	type="testcfg_bitfield"
    }	      
}

# Group definitions
group {
    arm920_CP15 {
        sn = "CP15"
        top_level_index = 200
        register += {"id", "cachetype", "control"}
	register += {"i_ttbase", "d_ttbase", "i_dactl", "d_dactl"}
	register += {"i_fsr", "d_fsr", "i_far", "d_far"}
	register += {"ic_lock", "dc_lock", "itlb_lock", "dtlb_lock"}
	register += {"pid", "test_cfg"}
    }
}