# arm64_default.grd
#
# Contains register definitions for the ARM 64-bit Aarch64 processor family.
#

%if (_TARGET_COPROCESSOR == 1)
%define ARM64_HAS_FP 0
%else
%define ARM64_HAS_FP 1
%endif

# Enum definitions
enum {
    "stackPointer" {
	"SP0" {value=0}
	"SPX" {value=1}
    }
    "notRegisterWidth" {
	"64" {value=0}
	"32" {value=1}
    }

    
    "overflowBit" {
        "none" {value=0}
        "overflow" {value=1}
    }
    "carryBit" {
        "none" {value=0}
        "carry" {value=1}
    }
    "zeroBit" {
        "none" {value=0}
        "zero" {value=1}
    }
    "negativeBit" {
        "none" {value=0}
        "negative" {value=1}
    }

    "trapExceptionBit" {
        "untrapped" {value=0}
        "trapped" {value=1}
    }
    "enableBit" {
        "disabled" {value=0}
        "enabled" {value=1}
    }    
    "roundingMode" {
        "Nearest" {value=0}
        "Plus Infinity" {value=1}
        "Minus Infinity" {value=2}
        "Zero" {value=3}
    }    
}


# Bitfield definitions
bitfield {
    pstate_struct_bitfield {
        "SP" {
	    loc="0..0";
	    type="stackPointer"
	    desc = "Stack pointer select\n";
	}
        "nRW" {
	    loc="1..1";
	    type="notRegisterWidth"
	    desc = "not Register Width\n";
	}
        "EL" {
	    loc="2..3";
	   # type="exceptionLevel"
	    desc = "Exception Level\n";
	}
        "F" {
	    loc="6..6";
	    desc = "FIQ mask bit\n";
	}
        "I" {
	    loc="7..7";
	    desc = "IRQ mask bit\n";
	}	
        "A" {
	    loc="8..8";
	    desc = "Asynchronous abort mask bit\n";
	}
        "D" {
	    loc="9..9";
	    desc = "Debug mask bit\n";
	}
	"BTYPE" {
	    loc="10..11";
	    desc = "Branch Type Indicator";
	}
	"SSBS" {
	    loc="12..12";
	    desc = "Speculative Store Bypass";
	}
        "IL" {
	    loc="20..20";
	    desc = "Illegal Execution state bit\n";
	}	
        "SS" {
	    loc="21..21";
	    desc = "Software step bit\n";
	}
	"PAN" {
	    loc="22..22";
	    desc = "Privileged Access Never";
	}
	"UAO" {
	    loc="23..23";
	    desc = "User Access Override";
	}
	"DIT" {
	    loc="24..24";
	    desc = "Data Independent Timing";
	}
	"TCO" {
	    loc="25..25";
	    desc = "Tag Check Override";
	}
        "V" {
	    loc="28..28";
	    type="overflowBit"
	    desc = "Overflow flag\n";
	    desc += "\n";
	    desc += "This condition code flag is set if an overflow occurred.\n";
	}
        "C" {
	    loc="29..29";
	    type="carryBit"
	    desc = "Carry flag\n";
	    desc += "\n";
	    desc += "This condition code flag is set if an operation produced a carry.\n";
	}
        "Z" {
	    loc="30..30";
	    type="zeroBit"
	    desc = "Zero flag\n";
	    desc += "\n";
	    desc += "This condition code flag is set if an operation resulted in a zero.\n";
	}
        "N" {
	    loc="31..31";
	    type="negativeBit"
	    desc = "Negative flag\n";
	    desc += "\n";
	    desc += "This condition code flag is set if an operation produced a negative result.\n";
	}
    }

    fpcr_struct_bitfield {
        "IOE" {
	    loc="8..8";
	    type="trapExceptionBit"
	    desc = "Invalid Operation exception trap\n";
	}
        "DZE" {
	    loc="9..9";
	    type="trapExceptionBit"
	    desc = "Division by Zero exception trap\n";
	}
        "OFE" {
	    loc="10..10";
	    type="trapExceptionBit"
	    desc = "Overflow exception trap\n";
	}
        "UFE" {
	    loc="11..11";
	    type="trapExceptionBit"
	    desc = "Underflow exception trap\n";
	}
        "IXE" {
	    loc="12..12";
	    type="trapExceptionBit"
	    desc = "Inexact exception trap\n";
	}
        "IDE" {
	    loc="15..15";
	    type="trapExceptionBit"
	    desc = "Input Denormal exception trap\n";
	}
        "Rmode" {
	    loc="22..23";
	    type="roundingMode"
	    desc = "Rounding Mode\n";
	}
        "FZ" {
	    loc="24..24";
	    type="enableBit"
	    desc = "Flush-to-zero mode\n";
	}
        "DN" {
	    loc="25..25";	    
	    desc = "Default NaN mode\n";
	}
        "AHP" {
	    loc="26..26";	    
	    desc = "Alternative half-precision\n";
	}
    }    

    fpsr_struct_bitfield {
        "IOC" {
	    loc="0..0";
	    desc = "Invalid Operation cumulative exception\n";
	}
        "DZC" {
	    loc="1..1";
	    desc = "Division by Zero cumulative exception\n";
	}
        "OFC" {
	    loc="2..2";
	    desc = "Overflow cumulative exception\n";
	}
        "UFC" {
	    loc="3..3";
	    desc = "Underflow cumulative exception\n";
	}
        "IXC" {
	    loc="4..4";
	    desc = "Inexact cumulative exception\n";
	}
        "IDC" {
	    loc="7..7";
	    desc = "Input Denormal cumulative exception\n";
	}
        "QC" {
	    loc="27..27";
	    desc = "Cumulative saturation\n";
	}
	"V" {
	    loc="28..28";
	    desc = "Overflow condition flag for AArch32 floating-point comparison operations\n";
	}
	"C" {
	    loc="29..29";
	    desc = "Carry condition flag for AArch32 floating-point comparison operations\n";
	}
	"Z" {
	    loc="30..30";
	    desc = "Zero condition flag for AArch32 floating-point comparison operations\n";
	}
	"N" {
	    loc="31..31";
	    desc = "Negative condition flag for AArch32 floating-point comparison operations\n";
	}
    }
}

# Register definitions
register {
    pc   { sn="pc"; desc="Program Counter"; address=192; type="code *" }
    pstate { 
	sn="pstate"
	desc="Process State"
	address=194
	width=32
%if (_MULTI_MAJOR_VERSION > 7 || (_MULTI_MAJOR_VERSION == 7 && _MULTI_MINOR_VERSION > 1) || (_MULTI_MAJOR_VERSION == 7 && _MULTI_MINOR_VERSION == 1 && _MULTI_MICRO_VERSION >= 6))
	# M7.1.4 and older don't support PSTATE bitfields; see MULTI-41926
	type="pstate_struct_bitfield"
%endif
    }

    r0  { sn="r0";  desc="General Register 0";  address=0  }
    r1  { sn="r1";  desc="General Register 1";  address=2  }
    r2  { sn="r2";  desc="General Register 2";  address=4  }
    r3  { sn="r3";  desc="General Register 3";  address=6  }
    r4  { sn="r4";  desc="General Register 4";  address=8  }
    r5  { sn="r5";  desc="General Register 5";  address=10 }
    r6  { sn="r6";  desc="General Register 6";  address=12 }
    r7  { sn="r7";  desc="General Register 7";  address=14 }
    r8  { sn="r8";  desc="General Register 8";  address=16 }
    r9  { sn="r9";  desc="General Register 9";  address=18 }
    r10 { sn="r10"; desc="General Register 10"; address=20 }
    r11 { sn="r11"; desc="General Register 11"; address=22 }
    r12 { sn="r12"; desc="General Register 12"; address=24 }
    r13 { sn="r13"; desc="General Register 13"; address=26 }
    r14 { sn="r14"; desc="General Register 14"; address=28 }
    r15 { sn="r15"; desc="General Register 15"; address=30 }
    r16 { sn="r16"; desc="General Register 16"; address=32 }
    r17 { sn="r17"; desc="General Register 17"; address=34 }
    r18 { sn="r18"; desc="General Register 18"; address=36 }
    r19 { sn="r19"; desc="General Register 19"; address=38 }
    r20 { sn="r20"; desc="General Register 20"; address=40 }
    r21 { sn="r21"; desc="General Register 21"; address=42 }
    r22 { sn="r22"; desc="General Register 22"; address=44 }
    r23 { sn="r23"; desc="General Register 23"; address=46 }
    r24 { sn="r24"; desc="General Register 24"; address=48 }
    r25 { sn="r25"; desc="General Register 25"; address=50 }
    r26 { sn="r26"; desc="General Register 26"; address=52 }
    r27 { sn="r27"; desc="General Register 27"; address=54 }
    r28 { sn="r28"; desc="General Register 28"; address=56 }
    r29 { sn="r29"; desc="General Register 29"; address=58 }
    r30 { sn="r30"; desc="General Register 30"; address=60 }
    sp  { sn="sp"; desc="Stack Pointer"; address=62 }
    ip0 { access="synonym"; address="r16"; hide=true }
    ip1 { access="synonym"; address="r17"; hide=true }
    fp  { access="synonym"; address="r29"; hide=true }
    lr  { access="synonym"; address="r30"; hide=true }
    r31 { access="synonym"; address="sp";  hide=true }
    result { access="synonym"; address="r0"; hide=true}

    x0  { access="synonym"; address="r0";  hide=true }
    x1  { access="synonym"; address="r1";  hide=true }
    x2  { access="synonym"; address="r2";  hide=true }
    x3  { access="synonym"; address="r3";  hide=true }
    x4  { access="synonym"; address="r4";  hide=true }
    x5  { access="synonym"; address="r5";  hide=true }
    x6  { access="synonym"; address="r6";  hide=true }
    x7  { access="synonym"; address="r7";  hide=true }
    x8  { access="synonym"; address="r8";  hide=true }
    x9  { access="synonym"; address="r9";  hide=true }
    x10 { access="synonym"; address="r10"; hide=true }
    x11 { access="synonym"; address="r11"; hide=true }
    x12 { access="synonym"; address="r12"; hide=true }
    x13 { access="synonym"; address="r13"; hide=true }
    x14 { access="synonym"; address="r14"; hide=true }
    x15 { access="synonym"; address="r15"; hide=true }
    x16 { access="synonym"; address="r16"; hide=true }
    x17 { access="synonym"; address="r17"; hide=true }
    x18 { access="synonym"; address="r18"; hide=true }
    x19 { access="synonym"; address="r19"; hide=true }
    x20 { access="synonym"; address="r20"; hide=true }
    x21 { access="synonym"; address="r21"; hide=true }
    x22 { access="synonym"; address="r22"; hide=true }
    x23 { access="synonym"; address="r23"; hide=true }
    x24 { access="synonym"; address="r24"; hide=true }
    x25 { access="synonym"; address="r25"; hide=true }
    x26 { access="synonym"; address="r26"; hide=true }
    x27 { access="synonym"; address="r27"; hide=true }
    x28 { access="synonym"; address="r28"; hide=true }
    x29 { access="synonym"; address="r29"; hide=true }
    x30 { access="synonym"; address="r30"; hide=true }
    xsp { access="synonym"; address="sp";  hide=true }

    w0  { sn="w0";  desc="Word Register 0";  address=256; width=32; hide=true }
    w1  { sn="w1";  desc="Word Register 1";  address=257; width=32; hide=true }
    w2  { sn="w2";  desc="Word Register 2";  address=258; width=32; hide=true }
    w3  { sn="w3";  desc="Word Register 3";  address=259; width=32; hide=true }
    w4  { sn="w4";  desc="Word Register 4";  address=260; width=32; hide=true }
    w5  { sn="w5";  desc="Word Register 5";  address=261; width=32; hide=true }
    w6  { sn="w6";  desc="Word Register 6";  address=262; width=32; hide=true }
    w7  { sn="w7";  desc="Word Register 7";  address=263; width=32; hide=true }
    w8  { sn="w8";  desc="Word Register 8";  address=264; width=32; hide=true }
    w9  { sn="w9";  desc="Word Register 9";  address=265; width=32; hide=true }
    w10 { sn="w10"; desc="Word Register 10"; address=266; width=32; hide=true }
    w11 { sn="w11"; desc="Word Register 11"; address=267; width=32; hide=true }
    w12 { sn="w12"; desc="Word Register 12"; address=268; width=32; hide=true }
    w13 { sn="w13"; desc="Word Register 13"; address=269; width=32; hide=true }
    w14 { sn="w14"; desc="Word Register 14"; address=270; width=32; hide=true }
    w15 { sn="w15"; desc="Word Register 15"; address=271; width=32; hide=true }
    w16 { sn="w16"; desc="Word Register 16"; address=272; width=32; hide=true }
    w17 { sn="w17"; desc="Word Register 17"; address=273; width=32; hide=true }
    w18 { sn="w18"; desc="Word Register 18"; address=274; width=32; hide=true }
    w19 { sn="w19"; desc="Word Register 19"; address=275; width=32; hide=true }
    w20 { sn="w20"; desc="Word Register 20"; address=276; width=32; hide=true }
    w21 { sn="w21"; desc="Word Register 21"; address=277; width=32; hide=true }
    w22 { sn="w22"; desc="Word Register 22"; address=278; width=32; hide=true }
    w23 { sn="w23"; desc="Word Register 23"; address=279; width=32; hide=true }
    w24 { sn="w24"; desc="Word Register 24"; address=280; width=32; hide=true }
    w25 { sn="w25"; desc="Word Register 25"; address=281; width=32; hide=true }
    w26 { sn="w26"; desc="Word Register 26"; address=282; width=32; hide=true }
    w27 { sn="w27"; desc="Word Register 27"; address=283; width=32; hide=true }
    w28 { sn="w28"; desc="Word Register 28"; address=284; width=32; hide=true }
    w29 { sn="w29"; desc="Word Register 29"; address=285; width=32; hide=true }
    w30 { sn="w30"; desc="Word Register 30"; address=286; width=32; hide=true }
    wsp {sn="wsp"; desc="Word Stack Pointer"; address=287; width=32; hide=true}

%if ARM64_HAS_FP
    v0  { sn="v0";  desc="Vector Register 0";  address=64;  width=128 }
    v1  { sn="v1";  desc="Vector Register 1";  address=68;  width=128 }
    v2  { sn="v2";  desc="Vector Register 2";  address=72;  width=128 }
    v3  { sn="v3";  desc="Vector Register 3";  address=76;  width=128 }
    v4  { sn="v4";  desc="Vector Register 4";  address=80;  width=128 }
    v5  { sn="v5";  desc="Vector Register 5";  address=84;  width=128 }
    v6  { sn="v6";  desc="Vector Register 6";  address=88;  width=128 }
    v7  { sn="v7";  desc="Vector Register 7";  address=92;  width=128 }
    v8  { sn="v8";  desc="Vector Register 8";  address=96;  width=128 }
    v9  { sn="v9";  desc="Vector Register 9";  address=100; width=128 }
    v10 { sn="v10"; desc="Vector Register 10"; address=104; width=128 }
    v11 { sn="v11"; desc="Vector Register 11"; address=108; width=128 }
    v12 { sn="v12"; desc="Vector Register 12"; address=112; width=128 }
    v13 { sn="v13"; desc="Vector Register 13"; address=116; width=128 }
    v14 { sn="v14"; desc="Vector Register 14"; address=120; width=128 }
    v15 { sn="v15"; desc="Vector Register 15"; address=124; width=128 }
    v16 { sn="v16"; desc="Vector Register 16"; address=128; width=128 }
    v17 { sn="v17"; desc="Vector Register 17"; address=132; width=128 }
    v18 { sn="v18"; desc="Vector Register 18"; address=136; width=128 }
    v19 { sn="v19"; desc="Vector Register 19"; address=140; width=128 }
    v20 { sn="v20"; desc="Vector Register 20"; address=144; width=128 }
    v21 { sn="v21"; desc="Vector Register 21"; address=148; width=128 }
    v22 { sn="v22"; desc="Vector Register 22"; address=152; width=128 }
    v23 { sn="v23"; desc="Vector Register 23"; address=156; width=128 }
    v24 { sn="v24"; desc="Vector Register 24"; address=160; width=128 }
    v25 { sn="v25"; desc="Vector Register 25"; address=164; width=128 }
    v26 { sn="v26"; desc="Vector Register 26"; address=168; width=128 }
    v27 { sn="v27"; desc="Vector Register 27"; address=172; width=128 }
    v28 { sn="v28"; desc="Vector Register 28"; address=176; width=128 }
    v29 { sn="v29"; desc="Vector Register 29"; address=180; width=128 }
    v30 { sn="v30"; desc="Vector Register 30"; address=184; width=128 }
    v31 { sn="v31"; desc="Vector Register 31"; address=188; width=128 }

    fpcr {
	sn="FPCR";
	ln = "Floating-Point Control Register";
	address=195;
	width=32;
	type="fpcr_struct_bitfield"
    }
    fpsr {
	sn="FPSR";
	ln = "Floating-Point Status Register";
	address=4724;
	width=32;
	type="fpsr_struct_bitfield"
    }

    q0  { access="synonym"; address="v0";  hide=true }
    q1  { access="synonym"; address="v1";  hide=true }
    q2  { access="synonym"; address="v2";  hide=true }
    q3  { access="synonym"; address="v3";  hide=true }
    q4  { access="synonym"; address="v4";  hide=true }
    q5  { access="synonym"; address="v5";  hide=true }
    q6  { access="synonym"; address="v6";  hide=true }
    q7  { access="synonym"; address="v7";  hide=true }
    q8  { access="synonym"; address="v8";  hide=true }
    q9  { access="synonym"; address="v9";  hide=true }
    q10 { access="synonym"; address="v10"; hide=true }
    q11 { access="synonym"; address="v11"; hide=true }
    q12 { access="synonym"; address="v12"; hide=true }
    q13 { access="synonym"; address="v13"; hide=true }
    q14 { access="synonym"; address="v14"; hide=true }
    q15 { access="synonym"; address="v15"; hide=true }
    q16 { access="synonym"; address="v16"; hide=true }
    q17 { access="synonym"; address="v17"; hide=true }
    q18 { access="synonym"; address="v18"; hide=true }
    q19 { access="synonym"; address="v19"; hide=true }
    q20 { access="synonym"; address="v20"; hide=true }
    q21 { access="synonym"; address="v21"; hide=true }
    q22 { access="synonym"; address="v22"; hide=true }
    q23 { access="synonym"; address="v23"; hide=true }
    q24 { access="synonym"; address="v24"; hide=true }
    q25 { access="synonym"; address="v25"; hide=true }
    q26 { access="synonym"; address="v26"; hide=true }
    q27 { access="synonym"; address="v27"; hide=true }
    q28 { access="synonym"; address="v28"; hide=true }
    q29 { access="synonym"; address="v29"; hide=true }
    q30 { access="synonym"; address="v30"; hide=true }
    q31 { access="synonym"; address="v31"; hide=true }

    d0  { sn="d0";  access="fpu"; desc="Double Register 0";  address=384; width=64 }
    d1  { sn="d1";  access="fpu"; desc="Double Register 1";  address=386; width=64 }
    d2  { sn="d2";  access="fpu"; desc="Double Register 2";  address=388; width=64 }
    d3  { sn="d3";  access="fpu"; desc="Double Register 3";  address=390; width=64 }
    d4  { sn="d4";  access="fpu"; desc="Double Register 4";  address=392; width=64 }
    d5  { sn="d5";  access="fpu"; desc="Double Register 5";  address=394; width=64 }
    d6  { sn="d6";  access="fpu"; desc="Double Register 6";  address=396; width=64 }
    d7  { sn="d7";  access="fpu"; desc="Double Register 7";  address=398; width=64 }
    d8  { sn="d8";  access="fpu"; desc="Double Register 8";  address=400; width=64 }
    d9  { sn="d9";  access="fpu"; desc="Double Register 9";  address=402; width=64 }
    d10 { sn="d10"; access="fpu"; desc="Double Register 10"; address=404; width=64 }
    d11 { sn="d11"; access="fpu"; desc="Double Register 11"; address=406; width=64 }
    d12 { sn="d12"; access="fpu"; desc="Double Register 12"; address=408; width=64 }
    d13 { sn="d13"; access="fpu"; desc="Double Register 13"; address=410; width=64 }
    d14 { sn="d14"; access="fpu"; desc="Double Register 14"; address=412; width=64 }
    d15 { sn="d15"; access="fpu"; desc="Double Register 15"; address=414; width=64 }
    d16 { sn="d16"; access="fpu"; desc="Double Register 16"; address=416; width=64 }
    d17 { sn="d17"; access="fpu"; desc="Double Register 17"; address=418; width=64 }
    d18 { sn="d18"; access="fpu"; desc="Double Register 18"; address=420; width=64 }
    d19 { sn="d19"; access="fpu"; desc="Double Register 19"; address=422; width=64 }
    d20 { sn="d20"; access="fpu"; desc="Double Register 20"; address=424; width=64 }
    d21 { sn="d21"; access="fpu"; desc="Double Register 21"; address=426; width=64 }
    d22 { sn="d22"; access="fpu"; desc="Double Register 22"; address=428; width=64 }
    d23 { sn="d23"; access="fpu"; desc="Double Register 23"; address=430; width=64 }
    d24 { sn="d24"; access="fpu"; desc="Double Register 24"; address=432; width=64 }
    d25 { sn="d25"; access="fpu"; desc="Double Register 25"; address=434; width=64 }
    d26 { sn="d26"; access="fpu"; desc="Double Register 26"; address=436; width=64 }
    d27 { sn="d27"; access="fpu"; desc="Double Register 27"; address=438; width=64 }
    d28 { sn="d28"; access="fpu"; desc="Double Register 28"; address=440; width=64 }
    d29 { sn="d29"; access="fpu"; desc="Double Register 29"; address=442; width=64 }
    d30 { sn="d30"; access="fpu"; desc="Double Register 30"; address=444; width=64 }
    d31 { sn="d31"; access="fpu"; desc="Double Register 31"; address=446; width=64 }

    s0  { sn="s0";  access="fpu"; desc="Single Register 0";  address=352; width=32 }
    s1  { sn="s1";  access="fpu"; desc="Single Register 1";  address=353; width=32 }
    s2  { sn="s2";  access="fpu"; desc="Single Register 2";  address=354; width=32 }
    s3  { sn="s3";  access="fpu"; desc="Single Register 3";  address=355; width=32 }
    s4  { sn="s4";  access="fpu"; desc="Single Register 4";  address=356; width=32 }
    s5  { sn="s5";  access="fpu"; desc="Single Register 5";  address=357; width=32 }
    s6  { sn="s6";  access="fpu"; desc="Single Register 6";  address=358; width=32 }
    s7  { sn="s7";  access="fpu"; desc="Single Register 7";  address=359; width=32 }
    s8  { sn="s8";  access="fpu"; desc="Single Register 8";  address=360; width=32 }
    s9  { sn="s9";  access="fpu"; desc="Single Register 9";  address=361; width=32 }
    s10 { sn="s10"; access="fpu"; desc="Single Register 10"; address=362; width=32 }
    s11 { sn="s11"; access="fpu"; desc="Single Register 11"; address=363; width=32 }
    s12 { sn="s12"; access="fpu"; desc="Single Register 12"; address=364; width=32 }
    s13 { sn="s13"; access="fpu"; desc="Single Register 13"; address=365; width=32 }
    s14 { sn="s14"; access="fpu"; desc="Single Register 14"; address=366; width=32 }
    s15 { sn="s15"; access="fpu"; desc="Single Register 15"; address=367; width=32 }
    s16 { sn="s16"; access="fpu"; desc="Single Register 16"; address=368; width=32 }
    s17 { sn="s17"; access="fpu"; desc="Single Register 17"; address=369; width=32 }
    s18 { sn="s18"; access="fpu"; desc="Single Register 18"; address=370; width=32 }
    s19 { sn="s19"; access="fpu"; desc="Single Register 19"; address=371; width=32 }
    s20 { sn="s20"; access="fpu"; desc="Single Register 20"; address=372; width=32 }
    s21 { sn="s21"; access="fpu"; desc="Single Register 21"; address=373; width=32 }
    s22 { sn="s22"; access="fpu"; desc="Single Register 22"; address=374; width=32 }
    s23 { sn="s23"; access="fpu"; desc="Single Register 23"; address=375; width=32 }
    s24 { sn="s24"; access="fpu"; desc="Single Register 24"; address=376; width=32 }
    s25 { sn="s25"; access="fpu"; desc="Single Register 25"; address=377; width=32 }
    s26 { sn="s26"; access="fpu"; desc="Single Register 26"; address=378; width=32 }
    s27 { sn="s27"; access="fpu"; desc="Single Register 27"; address=379; width=32 }
    s28 { sn="s28"; access="fpu"; desc="Single Register 28"; address=380; width=32 }
    s29 { sn="s29"; access="fpu"; desc="Single Register 29"; address=381; width=32 }
    s30 { sn="s30"; access="fpu"; desc="Single Register 30"; address=382; width=32 }
    s31 { sn="s31"; access="fpu"; desc="Single Register 31"; address=383; width=32 }
%endif

%if !(_IS_RUN_MODE)
%if ARM64_HAS_FP
    h0  { sn="h0";  desc="Half Register 0";  address=320; width=16; hide=true }
    h1  { sn="h1";  desc="Half Register 1";  address=321; width=16; hide=true }
    h2  { sn="h2";  desc="Half Register 2";  address=322; width=16; hide=true }
    h3  { sn="h3";  desc="Half Register 3";  address=323; width=16; hide=true }
    h4  { sn="h4";  desc="Half Register 4";  address=324; width=16; hide=true }
    h5  { sn="h5";  desc="Half Register 5";  address=325; width=16; hide=true }
    h6  { sn="h6";  desc="Half Register 6";  address=326; width=16; hide=true }
    h7  { sn="h7";  desc="Half Register 7";  address=327; width=16; hide=true }
    h8  { sn="h8";  desc="Half Register 8";  address=328; width=16; hide=true }
    h9  { sn="h9";  desc="Half Register 9";  address=329; width=16; hide=true }
    h10 { sn="h10"; desc="Half Register 10"; address=330; width=16; hide=true }
    h11 { sn="h11"; desc="Half Register 11"; address=331; width=16; hide=true }
    h12 { sn="h12"; desc="Half Register 12"; address=332; width=16; hide=true }
    h13 { sn="h13"; desc="Half Register 13"; address=333; width=16; hide=true }
    h14 { sn="h14"; desc="Half Register 14"; address=334; width=16; hide=true }
    h15 { sn="h15"; desc="Half Register 15"; address=335; width=16; hide=true }
    h16 { sn="h16"; desc="Half Register 16"; address=336; width=16; hide=true }
    h17 { sn="h17"; desc="Half Register 17"; address=337; width=16; hide=true }
    h18 { sn="h18"; desc="Half Register 18"; address=338; width=16; hide=true }
    h19 { sn="h19"; desc="Half Register 19"; address=339; width=16; hide=true }
    h20 { sn="h20"; desc="Half Register 20"; address=340; width=16; hide=true }
    h21 { sn="h21"; desc="Half Register 21"; address=341; width=16; hide=true }
    h22 { sn="h22"; desc="Half Register 22"; address=342; width=16; hide=true }
    h23 { sn="h23"; desc="Half Register 23"; address=343; width=16; hide=true }
    h24 { sn="h24"; desc="Half Register 24"; address=344; width=16; hide=true }
    h25 { sn="h25"; desc="Half Register 25"; address=345; width=16; hide=true }
    h26 { sn="h26"; desc="Half Register 26"; address=346; width=16; hide=true }
    h27 { sn="h27"; desc="Half Register 27"; address=347; width=16; hide=true }
    h28 { sn="h28"; desc="Half Register 28"; address=348; width=16; hide=true }
    h29 { sn="h29"; desc="Half Register 29"; address=349; width=16; hide=true }
    h30 { sn="h30"; desc="Half Register 30"; address=350; width=16; hide=true }
    h31 { sn="h31"; desc="Half Register 31"; address=351; width=16; hide=true }

    b0  { sn="b0";  desc="Byte Register 0";  address=288; width=8; hide=true }
    b1  { sn="b1";  desc="Byte Register 1";  address=289; width=8; hide=true }
    b2  { sn="b2";  desc="Byte Register 2";  address=290; width=8; hide=true }
    b3  { sn="b3";  desc="Byte Register 3";  address=291; width=8; hide=true }
    b4  { sn="b4";  desc="Byte Register 4";  address=292; width=8; hide=true }
    b5  { sn="b5";  desc="Byte Register 5";  address=293; width=8; hide=true }
    b6  { sn="b6";  desc="Byte Register 6";  address=294; width=8; hide=true }
    b7  { sn="b7";  desc="Byte Register 7";  address=295; width=8; hide=true }
    b8  { sn="b8";  desc="Byte Register 8";  address=296; width=8; hide=true }
    b9  { sn="b9";  desc="Byte Register 9";  address=297; width=8; hide=true }
    b10 { sn="b10"; desc="Byte Register 10"; address=298; width=8; hide=true }
    b11 { sn="b11"; desc="Byte Register 11"; address=299; width=8; hide=true }
    b12 { sn="b12"; desc="Byte Register 12"; address=300; width=8; hide=true }
    b13 { sn="b13"; desc="Byte Register 13"; address=301; width=8; hide=true }
    b14 { sn="b14"; desc="Byte Register 14"; address=302; width=8; hide=true }
    b15 { sn="b15"; desc="Byte Register 15"; address=303; width=8; hide=true }
    b16 { sn="b16"; desc="Byte Register 16"; address=304; width=8; hide=true }
    b17 { sn="b17"; desc="Byte Register 17"; address=305; width=8; hide=true }
    b18 { sn="b18"; desc="Byte Register 18"; address=306; width=8; hide=true }
    b19 { sn="b19"; desc="Byte Register 19"; address=307; width=8; hide=true }
    b20 { sn="b20"; desc="Byte Register 20"; address=308; width=8; hide=true }
    b21 { sn="b21"; desc="Byte Register 21"; address=309; width=8; hide=true }
    b22 { sn="b22"; desc="Byte Register 22"; address=310; width=8; hide=true }
    b23 { sn="b23"; desc="Byte Register 23"; address=311; width=8; hide=true }
    b24 { sn="b24"; desc="Byte Register 24"; address=312; width=8; hide=true }
    b25 { sn="b25"; desc="Byte Register 25"; address=313; width=8; hide=true }
    b26 { sn="b26"; desc="Byte Register 26"; address=314; width=8; hide=true }
    b27 { sn="b27"; desc="Byte Register 27"; address=315; width=8; hide=true }
    b28 { sn="b28"; desc="Byte Register 28"; address=316; width=8; hide=true }
    b29 { sn="b29"; desc="Byte Register 29"; address=317; width=8; hide=true }
    b30 { sn="b30"; desc="Byte Register 30"; address=318; width=8; hide=true }
    b31 { sn="b31"; desc="Byte Register 31"; address=319; width=8; hide=true }
%endif

%if !_FULL_ARM64_GRD
    SCTLR_EL1 { sn="sctlr_el1"; desc="System Control Register (EL1)";
                address=4406; width=32; }
    SCTLR_EL2 { sn="sctlr_el2"; desc="System Control Register (EL2)";
                address=4408; width=32; }
    SCTLR_EL3 { sn="sctlr_el3"; desc="System Control Register (EL3)";
                address=4410; width=32; }
 %if (defined(_COMP_SEQUENCE) && (_COMP_SEQUENCE >= 2300)) || (defined(_DEBUG_SERVER_IS_SIMULATOR) && !_DEBUG_SERVER_IS_SIMULATOR)
    MAIR_EL1  { sn="mair_el1"; desc="Memory Attribute Indirection Register (EL1)";
                address=4372; width=64; }
    MAIR_EL2  { sn="mair_el2"; desc="Memory Attribute Indirection Register (EL2)";
                address=4374; width=64; }
    MAIR_EL3  { sn="mair_el3"; desc="Memory Attribute Indirection Register (EL3)";
                address=4376; width=64; }
 %endif                
%endif
%endif

%if !(_IS_RUN_MODE) && _INCLUDE_SP_ELx
    # Exception level registers.  These generally aren't available to
    # run-mode debug interfaces.
    sp_el0 { sn="sp_el0"; width=64; desc="EL0 Stack Pointer"; address=198 }
    sp_el1 { sn="sp_el1"; width=64; desc="EL1 Stack Pointer"; address=200 }
    sp_el2 { sn="sp_el2"; width=64; desc="EL2 Stack Pointer"; address=202 }
    sp_el3 { sn="sp_el3"; width=64; desc="EL3 Stack Pointer"; address=204 }

    elr_el1 { sn="elr_el1"; width=64; desc="EL1 Exception Link Register"; address=4722 }
    elr_el2 { sn="elr_el2"; width=64; desc="EL2 Exception Link Register"; address=4728 }
    elr_el3 { sn="elr_el3"; width=64; desc="EL3 Exception Link Register"; address=4740 }
%endif

%if !(_IS_RUN_MODE)
    # Timer registers.
    CNTPCT_EL0 { sn="cntpct_el0"; desc="Counter-timer Physical Count register";
                 address=196; width=64; }
%endif
}

# Group definitions
group {
    status {
	sn = "Status"
	ln = "Status Registers"
	top_level_index = 0
	register += {"pc", "pstate"}
%if ARM64_HAS_FP
	register += {"fpcr", "fpsr"}
%endif
    }
    general {
	sn = "General"
	ln = "General Purpose Registers"
	collapse = false
	top_level_index = 1
	register += {"r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7"}
	register += {"r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15"}
	register += {"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23"}
	register += {"r24", "r25", "r26", "r27", "r28", "r29", "r30", "sp"}
    }
%if ARM64_HAS_FP
    vector {
	sn = "Vector"
	ln = "Floating Point/SIMD Registers"
	top_level_index = 2
	register += {"v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7"}
	register += {"v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15"}
	register += {"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23"}
	register += {"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"}
	register += {"d0",  "d1",  "d2",  "d3",  "d4",  "d5",  "d6",  "d7"}
	register += {"d8",  "d9",  "d10", "d11", "d12", "d13", "d14", "d15"}
	register += {"d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23"}
	register += {"d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31"}
	register += {"s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7"}
	register += {"s8",  "s9",  "s10", "s11", "s12", "s13", "s14", "s15"}
	register += {"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23"}
	register += {"s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31"}
    }
%endif
%if !(_IS_RUN_MODE) && _INCLUDE_SP_ELx
    exception {
	sn = "Exception"
	ln = "Exception Level Registers"
	top_level_index = 3
	register += { "sp_el0", "sp_el1", "sp_el2", "sp_el3"}
	register += { "elr_el1", "elr_el2", "elr_el3"}
    }
%endif
%if !(_IS_RUN_MODE)  && !_FULL_ARM64_GRD
    timer {
	sn = "Timer"
	ln = "Timer Registers"
	top_level_index = 4
	register += { "CNTPCT_EL0" }
    }
    system {
	sn = "System"
	ln = "System Registers"
	top_level_index = 5
	register += { "SCTLR_EL1", "SCTLR_EL2", "SCTLR_EL3" }
# TOOLS-35457: These registers were added to the simulator after 2022.1, but
# we can have the combination of 2022.1 compiler and probe 6.6+ which uses
# post-2022.1 .grd files.
 %if (defined(_COMP_SEQUENCE) && (_COMP_SEQUENCE >= 2300)) || (defined(_DEBUG_SERVER_IS_SIMULATOR) && !_DEBUG_SERVER_IS_SIMULATOR)
	register += { "MAIR_EL1", "MAIR_EL2", "MAIR_EL3" }
 %endif
    }
%endif

}