#ifndef __CM3_CORE_H__ #define __CM3_CORE_H__ #ifdef __cplusplus extern "C" { #endif #define __CM3_CMSIS_VERSION_MAIN (0x01) #define __CM3_CMSIS_VERSION_SUB (0x30) #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) #define __CORTEX_M (0x03) typedef unsigned int uint32_t ; typedef unsigned char uint8_t; /* 仅保留 __CC_ARM 支持 */ #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 4 #endif #ifdef __cplusplus #define __I volatile #else #define __I volatile const #endif #define __O volatile #define __IO volatile typedef struct { __IO uint32_t ISER[8]; uint32_t RESERVED0[24]; __IO uint32_t ICER[8]; uint32_t RSERVED1[24]; __IO uint32_t ISPR[8]; uint32_t RESERVED2[24]; __IO uint32_t ICPR[8]; uint32_t RESERVED3[24]; __IO uint32_t IABR[8]; uint32_t RESERVED4[56]; __IO uint8_t IP[240]; uint32_t RESERVED5[644]; __O uint32_t STIR; } NVIC_Type; typedef enum IRQn { NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, WWDG_IRQn = 0, PVD_IRQn = 1, TAMPER_IRQn = 2, RTC_IRQn = 3, FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7, EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Channel1_IRQn = 11, DMA1_Channel2_IRQn = 12, DMA1_Channel3_IRQn = 13, DMA1_Channel4_IRQn = 14, DMA1_Channel5_IRQn = 15, DMA1_Channel6_IRQn = 16, DMA1_Channel7_IRQn = 17, ADC1_2_IRQn = 18, USB_HP_CAN1_TX_IRQn = 19, USB_LP_CAN1_RX0_IRQn = 20, CAN1_RX1_IRQn = 21, CAN1_SCE_IRQn = 22, EXTI9_5_IRQn = 23, TIM1_BRK_IRQn = 24, TIM1_UP_IRQn = 25, TIM1_TRG_COM_IRQn = 26, TIM1_CC_IRQn = 27, TIM2_IRQn = 28, TIM3_IRQn = 29, TIM4_IRQn = 30, I2C1_EV_IRQn = 31, I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33, I2C2_ER_IRQn = 34, SPI1_IRQn = 35, SPI2_IRQn = 36, USART1_IRQn = 37, USART2_IRQn = 38, USART3_IRQn = 39, EXTI15_10_IRQn = 40, RTCAlarm_IRQn = 41, USBWakeUp_IRQn = 42 } IRQn_Type; typedef struct { __I uint32_t CPUID; __IO uint32_t ICSR; __IO uint32_t VTOR; __IO uint32_t AIRCR; __IO uint32_t SCR; __IO uint32_t CCR; __IO uint8_t SHP[12]; __IO uint32_t SHCSR; __IO uint32_t CFSR; __IO uint32_t HFSR; __IO uint32_t DFSR; __IO uint32_t MMFAR; __IO uint32_t BFAR; __IO uint32_t AFSR; __I uint32_t PFR[2]; __I uint32_t DFR; __I uint32_t ADR; __I uint32_t MMFR[4]; __I uint32_t ISAR[5]; } SCB_Type; #define SCB_CPUID_IMPLEMENTER_Pos 24 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) #define SCB_CPUID_VARIANT_Pos 20 #define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) #define SCB_CPUID_PARTNO_Pos 4 #define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) #define SCB_CPUID_REVISION_Pos 0 #define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) #define SCB_ICSR_NMIPENDSET_Pos 31 #define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) #define SCB_ICSR_PENDSVSET_Pos 28 #define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) #define SCB_ICSR_PENDSVCLR_Pos 27 #define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) #define SCB_ICSR_PENDSTSET_Pos 26 #define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) #define SCB_ICSR_PENDSTCLR_Pos 25 #define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) #define SCB_ICSR_ISRPREEMPT_Pos 23 #define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) #define SCB_ICSR_ISRPENDING_Pos 22 #define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) #define SCB_ICSR_VECTPENDING_Pos 12 #define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) #define SCB_ICSR_RETTOBASE_Pos 11 #define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) #define SCB_ICSR_VECTACTIVE_Pos 0 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) #define SCB_VTOR_TBLBASE_Pos 29 #define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) #define SCB_VTOR_TBLOFF_Pos 7 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) #define SCB_AIRCR_VECTKEY_Pos 16 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) #define SCB_AIRCR_VECTKEYSTAT_Pos 16 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) #define SCB_AIRCR_ENDIANESS_Pos 15 #define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) #define SCB_AIRCR_PRIGROUP_Pos 8 #define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) #define SCB_AIRCR_SYSRESETREQ_Pos 2 #define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) #define SCB_AIRCR_VECTRESET_Pos 0 #define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) #define SCB_SCR_SEVONPEND_Pos 4 #define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) #define SCB_SCR_SLEEPDEEP_Pos 2 #define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) #define SCB_SCR_SLEEPONEXIT_Pos 1 #define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) #define SCB_CCR_STKALIGN_Pos 9 #define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) #define SCB_CCR_BFHFNMIGN_Pos 8 #define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) #define SCB_CCR_DIV_0_TRP_Pos 4 #define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) #define SCB_CCR_UNALIGN_TRP_Pos 3 #define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) #define SCB_CCR_USERSETMPEND_Pos 1 #define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) #define SCB_CCR_NONBASETHRDENA_Pos 0 #define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) #define SCB_SHCSR_USGFAULTENA_Pos 18 #define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) #define SCB_SHCSR_BUSFAULTENA_Pos 17 #define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) #define SCB_SHCSR_MEMFAULTENA_Pos 16 #define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) #define SCB_SHCSR_SVCALLPENDED_Pos 15 #define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) #define SCB_SHCSR_USGFAULTPENDED_Pos 12 #define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) #define SCB_SHCSR_SYSTICKACT_Pos 11 #define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) #define SCB_SHCSR_PENDSVACT_Pos 10 #define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) #define SCB_SHCSR_MONITORACT_Pos 8 #define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) #define SCB_SHCSR_SVCALLACT_Pos 7 #define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) #define SCB_SHCSR_USGFAULTACT_Pos 3 #define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) #define SCB_SHCSR_BUSFAULTACT_Pos 1 #define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) #define SCB_SHCSR_MEMFAULTACT_Pos 0 #define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) #define SCB_CFSR_USGFAULTSR_Pos 16 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) #define SCB_CFSR_BUSFAULTSR_Pos 8 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) #define SCB_CFSR_MEMFAULTSR_Pos 0 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) #define SCB_HFSR_DEBUGEVT_Pos 31 #define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) #define SCB_HFSR_FORCED_Pos 30 #define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) #define SCB_HFSR_VECTTBL_Pos 1 #define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) #define SCB_DFSR_EXTERNAL_Pos 4 #define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) #define SCB_DFSR_VCATCH_Pos 3 #define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) #define SCB_DFSR_DWTTRAP_Pos 2 #define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) #define SCB_DFSR_BKPT_Pos 1 #define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) #define SCB_DFSR_HALTED_Pos 0 #define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) typedef struct { __IO uint32_t CTRL; __IO uint32_t LOAD; __IO uint32_t VAL; __I uint32_t CALIB; } SysTick_Type; #define SysTick_CTRL_COUNTFLAG_Pos 16 #define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) #define SysTick_CTRL_CLKSOURCE_Pos 2 #define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) #define SysTick_CTRL_TICKINT_Pos 1 #define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) #define SysTick_CTRL_ENABLE_Pos 0 #define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) #define SysTick_LOAD_RELOAD_Pos 0 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) #define SysTick_VAL_CURRENT_Pos 0 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) #define SysTick_CALIB_NOREF_Pos 31 #define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) #define SysTick_CALIB_SKEW_Pos 30 #define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) #define SysTick_CALIB_TENMS_Pos 0 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) typedef struct { __O union { __O uint8_t u8; __O uint16_t u16; __O uint32_t u32; } PORT [32]; uint32_t RESERVED0[864]; __IO uint32_t TER; uint32_t RESERVED1[15]; __IO uint32_t TPR; uint32_t RESERVED2[15]; __IO uint32_t TCR; uint32_t RESERVED3[29]; __IO uint32_t IWR; __IO uint32_t IRR; __IO uint32_t IMCR; uint32_t RESERVED4[43]; __IO uint32_t LAR; __IO uint32_t LSR; uint32_t RESERVED5[6]; __I uint32_t PID4; __I uint32_t PID5; __I uint32_t PID6; __I uint32_t PID7; __I uint32_t PID0; __I uint32_t PID1; __I uint32_t PID2; __I uint32_t PID3; __I uint32_t CID0; __I uint32_t CID1; __I uint32_t CID2; __I uint32_t CID3; } ITM_Type; #define ITM_TPR_PRIVMASK_Pos 0 #define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) #define ITM_TCR_BUSY_Pos 23 #define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) #define ITM_TCR_ATBID_Pos 16 #define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) #define ITM_TCR_TSPrescale_Pos 8 #define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) #define ITM_TCR_SWOENA_Pos 4 #define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) #define ITM_TCR_DWTENA_Pos 3 #define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) #define ITM_TCR_SYNCENA_Pos 2 #define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) #define ITM_TCR_TSENA_Pos 1 #define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) #define ITM_TCR_ITMENA_Pos 0 #define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) #define ITM_IWR_ATVALIDM_Pos 0 #define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) #define ITM_IRR_ATREADYM_Pos 0 #define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) #define ITM_IMCR_INTEGRATION_Pos 0 #define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) #define ITM_LSR_ByteAcc_Pos 2 #define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) #define ITM_LSR_Access_Pos 1 #define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) #define ITM_LSR_Present_Pos 0 #define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) typedef struct { uint32_t RESERVED0; __I uint32_t ICTR; #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) __IO uint32_t ACTLR; #else uint32_t RESERVED1; #endif } InterruptType_Type; #define InterruptType_ICTR_INTLINESNUM_Pos 0 #define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) #define InterruptType_ACTLR_DISFOLD_Pos 2 #define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) #define InterruptType_ACTLR_DISDEFWBUF_Pos 1 #define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) #define InterruptType_ACTLR_DISMCYCINT_Pos 0 #define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) typedef struct { __I uint32_t TYPE; __IO uint32_t CTRL; __IO uint32_t RNR; __IO uint32_t RBAR; __IO uint32_t RASR; __IO uint32_t RBAR_A1; __IO uint32_t RASR_A1; __IO uint32_t RBAR_A2; __IO uint32_t RASR_A2; __IO uint32_t RBAR_A3; __IO uint32_t RASR_A3; } MPU_Type; #define MPU_TYPE_IREGION_Pos 16 #define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) #define MPU_TYPE_DREGION_Pos 8 #define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) #define MPU_TYPE_SEPARATE_Pos 0 #define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) #define MPU_CTRL_PRIVDEFENA_Pos 2 #define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) #define MPU_CTRL_HFNMIENA_Pos 1 #define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) #define MPU_CTRL_ENABLE_Pos 0 #define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) #define MPU_RNR_REGION_Pos 0 #define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) #define MPU_RBAR_ADDR_Pos 5 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) #define MPU_RBAR_VALID_Pos 4 #define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) #define MPU_RBAR_REGION_Pos 0 #define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) #define MPU_RASR_XN_Pos 28 #define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) #define MPU_RASR_AP_Pos 24 #define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) #define MPU_RASR_TEX_Pos 19 #define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) #define MPU_RASR_S_Pos 18 #define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) #define MPU_RASR_C_Pos 17 #define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) #define MPU_RASR_B_Pos 16 #define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) #define MPU_RASR_SRD_Pos 8 #define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) #define MPU_RASR_SIZE_Pos 1 #define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) #define MPU_RASR_ENA_Pos 0 #define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) #endif typedef struct { __IO uint32_t DHCSR; __O uint32_t DCRSR; __IO uint32_t DCRDR; __IO uint32_t DEMCR; } CoreDebug_Type; #define CoreDebug_DHCSR_DBGKEY_Pos 16 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) #define CoreDebug_DHCSR_S_SLEEP_Pos 18 #define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) #define CoreDebug_DHCSR_S_HALT_Pos 17 #define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) #define CoreDebug_DHCSR_S_REGRDY_Pos 16 #define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) #define CoreDebug_DHCSR_C_STEP_Pos 2 #define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) #define CoreDebug_DHCSR_C_HALT_Pos 1 #define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) #define CoreDebug_DCRSR_REGWnR_Pos 16 #define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) #define CoreDebug_DCRSR_REGSEL_Pos 0 #define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) #define CoreDebug_DEMCR_TRCENA_Pos 24 #define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) #define CoreDebug_DEMCR_MON_REQ_Pos 19 #define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) #define CoreDebug_DEMCR_MON_STEP_Pos 18 #define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) #define CoreDebug_DEMCR_MON_PEND_Pos 17 #define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) #define CoreDebug_DEMCR_MON_EN_Pos 16 #define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) #define CoreDebug_DEMCR_VC_INTERR_Pos 9 #define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) #define CoreDebug_DEMCR_VC_STATERR_Pos 7 #define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) #define CoreDebug_DEMCR_VC_MMERR_Pos 4 #define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) #define SCS_BASE (0xE000E000) #define ITM_BASE (0xE0000000) #define CoreDebug_BASE (0xE000EDF0) #define SysTick_BASE (SCS_BASE + 0x0010) #define NVIC_BASE (SCS_BASE + 0x0100) #define SCB_BASE (SCS_BASE + 0x0D00) #define InterruptType ((InterruptType_Type *) SCS_BASE) #define SCB ((SCB_Type *) SCB_BASE) #define SysTick ((SysTick_Type *) SysTick_BASE) #define NVIC ((NVIC_Type *) NVIC_BASE) #define ITM ((ITM_Type *) ITM_BASE) #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) #define MPU_BASE (SCS_BASE + 0x0D90) #define MPU ((MPU_Type*) MPU_BASE) #endif typedef struct { __IO uint32_t SR; __IO uint32_t CR1; __IO uint32_t CR2; __IO uint32_t SMPR1; __IO uint32_t SMPR2; __IO uint32_t JOFR1; __IO uint32_t JOFR2; __IO uint32_t JOFR3; __IO uint32_t JOFR4; __IO uint32_t HTR; __IO uint32_t LTR; __IO uint32_t SQR1; __IO uint32_t SQR2; __IO uint32_t SQR3; __IO uint32_t JSQR; __IO uint32_t JDR1; __IO uint32_t JDR2; __IO uint32_t JDR3; __IO uint32_t JDR4; __IO uint32_t DR; } ADC_TypeDef; typedef struct { uint32_t RESERVED0; __IO uint16_t DR1; uint16_t RESERVED1; __IO uint16_t DR2; uint16_t RESERVED2; __IO uint16_t DR3; uint16_t RESERVED3; __IO uint16_t DR4; uint16_t RESERVED4; __IO uint16_t DR5; uint16_t RESERVED5; __IO uint16_t DR6; uint16_t RESERVED6; __IO uint16_t DR7; uint16_t RESERVED7; __IO uint16_t DR8; uint16_t RESERVED8; __IO uint16_t DR9; uint16_t RESERVED9; __IO uint16_t DR10; uint16_t RESERVED10; __IO uint16_t RTCCR; uint16_t RESERVED11; __IO uint16_t CR; uint16_t RESERVED12; __IO uint16_t CSR; uint16_t RESERVED13[5]; __IO uint16_t DR11; uint16_t RESERVED14; __IO uint16_t DR12; uint16_t RESERVED15; __IO uint16_t DR13; uint16_t RESERVED16; __IO uint16_t DR14; uint16_t RESERVED17; __IO uint16_t DR15; uint16_t RESERVED18; __IO uint16_t DR16; uint16_t RESERVED19; __IO uint16_t DR17; uint16_t RESERVED20; __IO uint16_t DR18; uint16_t RESERVED21; __IO uint16_t DR19; uint16_t RESERVED22; __IO uint16_t DR20; uint16_t RESERVED23; __IO uint16_t DR21; uint16_t RESERVED24; __IO uint16_t DR22; uint16_t RESERVED25; __IO uint16_t DR23; uint16_t RESERVED26; __IO uint16_t DR24; uint16_t RESERVED27; __IO uint16_t DR25; uint16_t RESERVED28; __IO uint16_t DR26; uint16_t RESERVED29; __IO uint16_t DR27; uint16_t RESERVED30; __IO uint16_t DR28; uint16_t RESERVED31; __IO uint16_t DR29; uint16_t RESERVED32; __IO uint16_t DR30; uint16_t RESERVED33; __IO uint16_t DR31; uint16_t RESERVED34; __IO uint16_t DR32; uint16_t RESERVED35; __IO uint16_t DR33; uint16_t RESERVED36; __IO uint16_t DR34; uint16_t RESERVED37; __IO uint16_t DR35; uint16_t RESERVED38; __IO uint16_t DR36; uint16_t RESERVED39; __IO uint16_t DR37; uint16_t RESERVED40; __IO uint16_t DR38; uint16_t RESERVED41; __IO uint16_t DR39; uint16_t RESERVED42; __IO uint16_t DR40; uint16_t RESERVED43; __IO uint16_t DR41; uint16_t RESERVED44; __IO uint16_t DR42; uint16_t RESERVED45; } BKP_TypeDef; typedef struct { __IO uint32_t TIR; __IO uint32_t TDTR; __IO uint32_t TDLR; __IO uint32_t TDHR; } CAN_TxMailBox_TypeDef; typedef struct { __IO uint32_t RIR; __IO uint32_t RDTR; __IO uint32_t RDLR; __IO uint32_t RDHR; } CAN_FIFOMailBox_TypeDef; typedef struct { __IO uint32_t FR1; __IO uint32_t FR2; } CAN_FilterRegister_TypeDef; typedef struct { __IO uint32_t MCR; __IO uint32_t MSR; __IO uint32_t TSR; __IO uint32_t RF0R; __IO uint32_t RF1R; __IO uint32_t IER; __IO uint32_t ESR; __IO uint32_t BTR; uint32_t RESERVED0[88]; CAN_TxMailBox_TypeDef sTxMailBox[3]; CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; uint32_t RESERVED1[12]; __IO uint32_t FMR; __IO uint32_t FM1R; uint32_t RESERVED2; __IO uint32_t FS1R; uint32_t RESERVED3; __IO uint32_t FFA1R; uint32_t RESERVED4; __IO uint32_t FA1R; uint32_t RESERVED5[8]; #ifndef STM32F10X_CL CAN_FilterRegister_TypeDef sFilterRegister[14]; #else CAN_FilterRegister_TypeDef sFilterRegister[28]; #endif } CAN_TypeDef; typedef struct { __IO uint32_t CFGR; __IO uint32_t OAR; __IO uint32_t PRES; __IO uint32_t ESR; __IO uint32_t CSR; __IO uint32_t TXD; __IO uint32_t RXD; } CEC_TypeDef; typedef struct { __IO uint32_t DR; __IO uint8_t IDR; uint8_t RESERVED0; uint16_t RESERVED1; __IO uint32_t CR; } CRC_TypeDef; typedef struct { __IO uint32_t CR; __IO uint32_t SWTRIGR; __IO uint32_t DHR12R1; __IO uint32_t DHR12L1; __IO uint32_t DHR8R1; __IO uint32_t DHR12R2; __IO uint32_t DHR12L2; __IO uint32_t DHR8R2; __IO uint32_t DHR12RD; __IO uint32_t DHR12LD; __IO uint32_t DHR8RD; __IO uint32_t DOR1; __IO uint32_t DOR2; #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) __IO uint32_t SR; #endif } DAC_TypeDef; typedef struct { __IO uint32_t IDCODE; __IO uint32_t CR; }DBGMCU_TypeDef; typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; __IO uint32_t CPAR; __IO uint32_t CMAR; } DMA_Channel_TypeDef; typedef struct { __IO uint32_t ISR; __IO uint32_t IFCR; } DMA_TypeDef; typedef struct { __IO uint32_t MACCR; __IO uint32_t MACFFR; __IO uint32_t MACHTHR; __IO uint32_t MACHTLR; __IO uint32_t MACMIIAR; __IO uint32_t MACMIIDR; __IO uint32_t MACFCR; __IO uint32_t MACVLANTR; uint32_t RESERVED0[2]; __IO uint32_t MACRWUFFR; __IO uint32_t MACPMTCSR; uint32_t RESERVED1[2]; __IO uint32_t MACSR; __IO uint32_t MACIMR; __IO uint32_t MACA0HR; __IO uint32_t MACA0LR; __IO uint32_t MACA1HR; __IO uint32_t MACA1LR; __IO uint32_t MACA2HR; __IO uint32_t MACA2LR; __IO uint32_t MACA3HR; __IO uint32_t MACA3LR; uint32_t RESERVED2[40]; __IO uint32_t MMCCR; __IO uint32_t MMCRIR; __IO uint32_t MMCTIR; __IO uint32_t MMCRIMR; __IO uint32_t MMCTIMR; uint32_t RESERVED3[14]; __IO uint32_t MMCTGFSCCR; __IO uint32_t MMCTGFMSCCR; uint32_t RESERVED4[5]; __IO uint32_t MMCTGFCR; uint32_t RESERVED5[10]; __IO uint32_t MMCRFCECR; __IO uint32_t MMCRFAECR; uint32_t RESERVED6[10]; __IO uint32_t MMCRGUFCR; uint32_t RESERVED7[334]; __IO uint32_t PTPTSCR; __IO uint32_t PTPSSIR; __IO uint32_t PTPTSHR; __IO uint32_t PTPTSLR; __IO uint32_t PTPTSHUR; __IO uint32_t PTPTSLUR; __IO uint32_t PTPTSAR; __IO uint32_t PTPTTHR; __IO uint32_t PTPTTLR; uint32_t RESERVED8[567]; __IO uint32_t DMABMR; __IO uint32_t DMATPDR; __IO uint32_t DMARPDR; __IO uint32_t DMARDLAR; __IO uint32_t DMATDLAR; __IO uint32_t DMASR; __IO uint32_t DMAOMR; __IO uint32_t DMAIER; __IO uint32_t DMAMFBOCR; uint32_t RESERVED9[9]; __IO uint32_t DMACHTDR; __IO uint32_t DMACHRDR; __IO uint32_t DMACHTBAR; __IO uint32_t DMACHRBAR; } ETH_TypeDef; typedef struct { __IO uint32_t IMR; __IO uint32_t EMR; __IO uint32_t RTSR; __IO uint32_t FTSR; __IO uint32_t SWIER; __IO uint32_t PR; } EXTI_TypeDef; typedef struct { __IO uint32_t ACR; __IO uint32_t KEYR; __IO uint32_t OPTKEYR; __IO uint32_t SR; __IO uint32_t CR; __IO uint32_t AR; __IO uint32_t RESERVED; __IO uint32_t OBR; __IO uint32_t WRPR; #ifdef STM32F10X_XL uint32_t RESERVED1[8]; __IO uint32_t KEYR2; uint32_t RESERVED2; __IO uint32_t SR2; __IO uint32_t CR2; __IO uint32_t AR2; #endif } FLASH_TypeDef; typedef struct { __IO uint16_t RDP; __IO uint16_t USER; __IO uint16_t Data0; __IO uint16_t Data1; __IO uint16_t WRP0; __IO uint16_t WRP1; __IO uint16_t WRP2; __IO uint16_t WRP3; } OB_TypeDef; typedef struct { __IO uint32_t BTCR[8]; } FSMC_Bank1_TypeDef; typedef struct { __IO uint32_t BWTR[7]; } FSMC_Bank1E_TypeDef; typedef struct { __IO uint32_t PCR2; __IO uint32_t SR2; __IO uint32_t PMEM2; __IO uint32_t PATT2; uint32_t RESERVED0; __IO uint32_t ECCR2; } FSMC_Bank2_TypeDef; typedef struct { __IO uint32_t PCR3; __IO uint32_t SR3; __IO uint32_t PMEM3; __IO uint32_t PATT3; uint32_t RESERVED0; __IO uint32_t ECCR3; } FSMC_Bank3_TypeDef; typedef struct { __IO uint32_t PCR4; __IO uint32_t SR4; __IO uint32_t PMEM4; __IO uint32_t PATT4; __IO uint32_t PIO4; } FSMC_Bank4_TypeDef; typedef struct { __IO uint32_t CRL; __IO uint32_t CRH; __IO uint32_t IDR; __IO uint32_t ODR; __IO uint32_t BSRR; __IO uint32_t BRR; __IO uint32_t LCKR; } GPIO_TypeDef; typedef struct { __IO uint32_t EVCR; __IO uint32_t MAPR; __IO uint32_t EXTICR[4]; uint32_t RESERVED0; __IO uint32_t MAPR2; } AFIO_TypeDef; typedef struct { __IO uint16_t CR1; uint16_t RESERVED0; __IO uint16_t CR2; uint16_t RESERVED1; __IO uint16_t OAR1; uint16_t RESERVED2; __IO uint16_t OAR2; uint16_t RESERVED3; __IO uint16_t DR; uint16_t RESERVED4; __IO uint16_t SR1; uint16_t RESERVED5; __IO uint16_t SR2; uint16_t RESERVED6; __IO uint16_t CCR; uint16_t RESERVED7; __IO uint16_t TRISE; uint16_t RESERVED8; } I2C_TypeDef; typedef struct { __IO uint32_t KR; __IO uint32_t PR; __IO uint32_t RLR; __IO uint32_t SR; } IWDG_TypeDef; typedef struct { __IO uint32_t CR; __IO uint32_t CSR; } PWR_TypeDef; typedef struct { __IO uint32_t CR; __IO uint32_t CFGR; __IO uint32_t CIR; __IO uint32_t APB2RSTR; __IO uint32_t APB1RSTR; __IO uint32_t AHBENR; __IO uint32_t APB2ENR; __IO uint32_t APB1ENR; __IO uint32_t BDCR; __IO uint32_t CSR; #ifdef STM32F10X_CL __IO uint32_t AHBRSTR; __IO uint32_t CFGR2; #endif #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) uint32_t RESERVED0; __IO uint32_t CFGR2; #endif } RCC_TypeDef; typedef struct { __IO uint16_t CRH; uint16_t RESERVED0; __IO uint16_t CRL; uint16_t RESERVED1; __IO uint16_t PRLH; uint16_t RESERVED2; __IO uint16_t PRLL; uint16_t RESERVED3; __IO uint16_t DIVH; uint16_t RESERVED4; __IO uint16_t DIVL; uint16_t RESERVED5; __IO uint16_t CNTH; uint16_t RESERVED6; __IO uint16_t CNTL; uint16_t RESERVED7; __IO uint16_t ALRH; uint16_t RESERVED8; __IO uint16_t ALRL; uint16_t RESERVED9; } RTC_TypeDef; typedef struct { __IO uint32_t POWER; __IO uint32_t CLKCR; __IO uint32_t ARG; __IO uint32_t CMD; __I uint32_t RESPCMD; __I uint32_t RESP1; __I uint32_t RESP2; __I uint32_t RESP3; __I uint32_t RESP4; __IO uint32_t DTIMER; __IO uint32_t DLEN; __IO uint32_t DCTRL; __I uint32_t DCOUNT; __I uint32_t STA; __IO uint32_t ICR; __IO uint32_t MASK; uint32_t RESERVED0[2]; __I uint32_t FIFOCNT; uint32_t RESERVED1[13]; __IO uint32_t FIFO; } SDIO_TypeDef; typedef struct { __IO uint16_t CR1; uint16_t RESERVED0; __IO uint16_t CR2; uint16_t RESERVED1; __IO uint16_t SR; uint16_t RESERVED2; __IO uint16_t DR; uint16_t RESERVED3; __IO uint16_t CRCPR; uint16_t RESERVED4; __IO uint16_t RXCRCR; uint16_t RESERVED5; __IO uint16_t TXCRCR; uint16_t RESERVED6; __IO uint16_t I2SCFGR; uint16_t RESERVED7; __IO uint16_t I2SPR; uint16_t RESERVED8; } SPI_TypeDef; typedef struct { __IO uint16_t CR1; uint16_t RESERVED0; __IO uint16_t CR2; uint16_t RESERVED1; __IO uint16_t SMCR; uint16_t RESERVED2; __IO uint16_t DIER; uint16_t RESERVED3; __IO uint16_t SR; uint16_t RESERVED4; __IO uint16_t EGR; uint16_t RESERVED5; __IO uint16_t CCMR1; uint16_t RESERVED6; __IO uint16_t CCMR2; uint16_t RESERVED7; __IO uint16_t CCER; uint16_t RESERVED8; __IO uint16_t CNT; uint16_t RESERVED9; __IO uint16_t PSC; uint16_t RESERVED10; __IO uint16_t ARR; uint16_t RESERVED11; __IO uint16_t RCR; uint16_t RESERVED12; __IO uint16_t CCR1; uint16_t RESERVED13; __IO uint16_t CCR2; uint16_t RESERVED14; __IO uint16_t CCR3; uint16_t RESERVED15; __IO uint16_t CCR4; uint16_t RESERVED16; __IO uint16_t BDTR; uint16_t RESERVED17; __IO uint16_t DCR; uint16_t RESERVED18; __IO uint16_t DMAR; uint16_t RESERVED19; } TIM_TypeDef; typedef struct { __IO uint16_t SR; uint16_t RESERVED0; __IO uint16_t DR; uint16_t RESERVED1; __IO uint16_t BRR; uint16_t RESERVED2; __IO uint16_t CR1; uint16_t RESERVED3; __IO uint16_t CR2; uint16_t RESERVED4; __IO uint16_t CR3; uint16_t RESERVED5; __IO uint16_t GTPR; uint16_t RESERVED6; } USART_TypeDef; typedef struct { __IO uint32_t CR; __IO uint32_t CFR; __IO uint32_t SR; } WWDG_TypeDef; #define FLASH_BASE ((uint32_t)0x08000000) #define SRAM_BASE ((uint32_t)0x20000000) #define PERIPH_BASE ((uint32_t)0x40000000) #define SRAM_BB_BASE ((uint32_t)0x22000000) #define PERIPH_BB_BASE ((uint32_t)0x42000000) #define FSMC_R_BASE ((uint32_t)0xA0000000) #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) #define TIM12_BASE (APB1PERIPH_BASE + 0x1800) #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) #define TIM14_BASE (APB1PERIPH_BASE + 0x2000) #define RTC_BASE (APB1PERIPH_BASE + 0x2800) #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) #define USART2_BASE (APB1PERIPH_BASE + 0x4400) #define USART3_BASE (APB1PERIPH_BASE + 0x4800) #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) #define UART5_BASE (APB1PERIPH_BASE + 0x5000) #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) #define CAN2_BASE (APB1PERIPH_BASE + 0x6800) #define BKP_BASE (APB1PERIPH_BASE + 0x6C00) #define PWR_BASE (APB1PERIPH_BASE + 0x7000) #define DAC_BASE (APB1PERIPH_BASE + 0x7400) #define CEC_BASE (APB1PERIPH_BASE + 0x7800) #define AFIO_BASE (APB2PERIPH_BASE + 0x0000) #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) #define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) #define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) #define ADC1_BASE (APB2PERIPH_BASE + 0x2400) #define ADC2_BASE (APB2PERIPH_BASE + 0x2800) #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) #define TIM8_BASE (APB2PERIPH_BASE + 0x3400) #define USART1_BASE (APB2PERIPH_BASE + 0x3800) #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) #define TIM15_BASE (APB2PERIPH_BASE + 0x4000) #define TIM16_BASE (APB2PERIPH_BASE + 0x4400) #define TIM17_BASE (APB2PERIPH_BASE + 0x4800) #define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) #define TIM10_BASE (APB2PERIPH_BASE + 0x5000) #define TIM11_BASE (APB2PERIPH_BASE + 0x5400) #define SDIO_BASE (PERIPH_BASE + 0x18000) #define DMA1_BASE (AHBPERIPH_BASE + 0x0000) #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) #define DMA2_BASE (AHBPERIPH_BASE + 0x0400) #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) #define RCC_BASE (AHBPERIPH_BASE + 0x1000) #define CRC_BASE (AHBPERIPH_BASE + 0x3000) #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) #define OB_BASE ((uint32_t)0x1FFFF800) #define ETH_BASE (AHBPERIPH_BASE + 0x8000) #define ETH_MAC_BASE (ETH_BASE) #define ETH_MMC_BASE (ETH_BASE + 0x0100) #define ETH_PTP_BASE (ETH_BASE + 0x0700) #define ETH_DMA_BASE (ETH_BASE + 0x1000) #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) #define DBGMCU_BASE ((uint32_t)0xE0042000) #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) #define TIM5 ((TIM_TypeDef *) TIM5_BASE) #define TIM6 ((TIM_TypeDef *) TIM6_BASE) #define TIM7 ((TIM_TypeDef *) TIM7_BASE) #define TIM12 ((TIM_TypeDef *) TIM12_BASE) #define TIM13 ((TIM_TypeDef *) TIM13_BASE) #define TIM14 ((TIM_TypeDef *) TIM14_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define WWDG ((WWDG_TypeDef *) WWDG_BASE) #define IWDG ((IWDG_TypeDef *) IWDG_BASE) #define SPI2 ((SPI_TypeDef *) SPI2_BASE) #define SPI3 ((SPI_TypeDef *) SPI3_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) #define USART3 ((USART_TypeDef *) USART3_BASE) #define UART4 ((USART_TypeDef *) UART4_BASE) #define UART5 ((USART_TypeDef *) UART5_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define CAN2 ((CAN_TypeDef *) CAN2_BASE) #define BKP ((BKP_TypeDef *) BKP_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define DAC ((DAC_TypeDef *) DAC_BASE) #define CEC ((CEC_TypeDef *) CEC_BASE) #define AFIO ((AFIO_TypeDef *) AFIO_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC2 ((ADC_TypeDef *) ADC2_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define TIM8 ((TIM_TypeDef *) TIM8_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define ADC3 ((ADC_TypeDef *) ADC3_BASE) #define TIM15 ((TIM_TypeDef *) TIM15_BASE) #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define TIM9 ((TIM_TypeDef *) TIM9_BASE) #define TIM10 ((TIM_TypeDef *) TIM10_BASE) #define TIM11 ((TIM_TypeDef *) TIM11_BASE) #define SDIO ((SDIO_TypeDef *) SDIO_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define OB ((OB_TypeDef *) OB_BASE) #define ETH ((ETH_TypeDef *) ETH_BASE) #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) #if defined ( __CC_ARM ) #define __ASM __asm #define __INLINE __inline #endif #if defined ( __CC_ARM ) #define __enable_fault_irq __enable_fiq #define __disable_fault_irq __disable_fiq #define __NOP __nop #define __WFI __wfi #define __WFE __wfe #define __SEV __sev #define __ISB() __isb(0) #define __DSB() __dsb(0) #define __DMB() __dmb(0) #define __REV __rev #define __RBIT __rbit #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) #define __STREXB(value, ptr) __strex(value, ptr) #define __STREXH(value, ptr) __strex(value, ptr) #define __STREXW(value, ptr) __strex(value, ptr) extern uint32_t __get_PSP(void); extern void __set_PSP(uint32_t topOfProcStack); extern uint32_t __get_MSP(void); extern void __set_MSP(uint32_t topOfMainStack); extern uint32_t __REV16(uint16_t value); extern int32_t __REVSH(int16_t value); #if (__ARMCC_VERSION < 400000) extern void __CLREX(void); extern uint32_t __get_BASEPRI(void); extern void __set_BASEPRI(uint32_t basePri); extern uint32_t __get_PRIMASK(void); extern void __set_PRIMASK(uint32_t priMask); extern uint32_t __get_FAULTMASK(void); extern void __set_FAULTMASK(uint32_t faultMask); extern uint32_t __get_CONTROL(void); extern void __set_CONTROL(uint32_t control); #else #define __CLREX __clrex static __INLINE uint32_t __get_BASEPRI(void) { register uint32_t __regBasePri __ASM("basepri"); return(__regBasePri); } static __INLINE void __set_BASEPRI(uint32_t basePri) { register uint32_t __regBasePri __ASM("basepri"); __regBasePri = (basePri & 0xff); } static __INLINE uint32_t __get_PRIMASK(void) { register uint32_t __regPriMask __ASM("primask"); return(__regPriMask); } static __INLINE void __set_PRIMASK(uint32_t priMask) { register uint32_t __regPriMask __ASM("primask"); __regPriMask = (priMask); } static __INLINE uint32_t __get_FAULTMASK(void) { register uint32_t __regFaultMask __ASM("faultmask"); return(__regFaultMask); } static __INLINE void __set_FAULTMASK(uint32_t faultMask) { register uint32_t __regFaultMask __ASM("faultmask"); __regFaultMask = (faultMask & 1); } static __INLINE uint32_t __get_CONTROL(void) { register uint32_t __regControl __ASM("control"); return(__regControl); } static __INLINE void __set_CONTROL(uint32_t control) { register uint32_t __regControl __ASM("control"); __regControl = control; } #endif /* 仅保留 __CC_ARM 支持 */ /* 仅保留 __CC_ARM 支持 */ #endif static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); reg_value = SCB->AIRCR; reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); reg_value = (reg_value | (0x5FA << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8)); SCB->AIRCR = reg_value; } static __INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); } static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); } static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); } static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); } static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); } static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); } static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); } static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if(IRQn < 0) { SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } else { NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } } static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { if(IRQn < 0) { return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } else { return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } } static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; return ( ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | ((SubPriority & ((1 << (SubPriorityBits )) - 1))) ); } static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); } #if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) static __INLINE uint32_t SysTick_Config(uint32_t ticks) { if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); SysTick->VAL = 0; SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; return (0); } #endif static __INLINE void NVIC_SystemReset(void) { SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); while(1); } extern volatile int ITM_RxBuffer; #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 static __INLINE uint32_t ITM_SendChar (uint32_t ch) { if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && (ITM->TCR & ITM_TCR_ITMENA_Msk) && (ITM->TER & (1ul << 0) ) ) { while (ITM->PORT[0].u32 == 0); ITM->PORT[0].u8 = (uint8_t) ch; } return (ch); } static __INLINE int ITM_ReceiveChar (void) { int ch = -1; if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; } return (ch); } static __INLINE int ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); } else { return (1); } } /* STM32F10x Peripheral Structures */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t SR; __IO uint32_t CR1; __IO uint32_t CR2; __IO uint32_t SMPR1; __IO uint32_t SMPR2; __IO uint32_t JOFR1; __IO uint32_t JOFR2; __IO uint32_t JOFR3; __IO uint32_t JOFR4; __IO uint32_t HTR; __IO uint32_t LTR; __IO uint32_t SQR1; __IO uint32_t SQR2; __IO uint32_t SQR3; __IO uint32_t JSQR; __IO uint32_t JDR1; __IO uint32_t JDR2; __IO uint32_t JDR3; __IO uint32_t JDR4; __IO uint32_t DR; } ADC_TypeDef; /** * @brief Backup Registers */ typedef struct { uint32_t RESERVED0; __IO uint16_t DR1; uint16_t RESERVED1; __IO uint16_t DR2; uint16_t RESERVED2; __IO uint16_t DR3; uint16_t RESERVED3; __IO uint16_t DR4; uint16_t RESERVED4; __IO uint16_t DR5; uint16_t RESERVED5; __IO uint16_t DR6; uint16_t RESERVED6; __IO uint16_t DR7; uint16_t RESERVED7; __IO uint16_t DR8; uint16_t RESERVED8; __IO uint16_t DR9; uint16_t RESERVED9; __IO uint16_t DR10; uint16_t RESERVED10; __IO uint16_t RTCCR; uint16_t RESERVED11; __IO uint16_t CR; uint16_t RESERVED12; __IO uint16_t CSR; uint16_t RESERVED13[5]; __IO uint16_t DR11; uint16_t RESERVED14; __IO uint16_t DR12; uint16_t RESERVED15; __IO uint16_t DR13; uint16_t RESERVED16; __IO uint16_t DR14; uint16_t RESERVED17; __IO uint16_t DR15; uint16_t RESERVED18; __IO uint16_t DR16; uint16_t RESERVED19; __IO uint16_t DR17; uint16_t RESERVED20; __IO uint16_t DR18; uint16_t RESERVED21; __IO uint16_t DR19; uint16_t RESERVED22; __IO uint16_t DR20; uint16_t RESERVED23; __IO uint16_t DR21; uint16_t RESERVED24; __IO uint16_t DR22; uint16_t RESERVED25; __IO uint16_t DR23; uint16_t RESERVED26; __IO uint16_t DR24; uint16_t RESERVED27; __IO uint16_t DR25; uint16_t RESERVED28; __IO uint16_t DR26; uint16_t RESERVED29; __IO uint16_t DR27; uint16_t RESERVED30; __IO uint16_t DR28; uint16_t RESERVED31; __IO uint16_t DR29; uint16_t RESERVED32; __IO uint16_t DR30; uint16_t RESERVED33; __IO uint16_t DR31; uint16_t RESERVED34; __IO uint16_t DR32; uint16_t RESERVED35; __IO uint16_t DR33; uint16_t RESERVED36; __IO uint16_t DR34; uint16_t RESERVED37; __IO uint16_t DR35; uint16_t RESERVED38; __IO uint16_t DR36; uint16_t RESERVED39; __IO uint16_t DR37; uint16_t RESERVED40; __IO uint16_t DR38; uint16_t RESERVED41; __IO uint16_t DR39; uint16_t RESERVED42; __IO uint16_t DR40; uint16_t RESERVED43; __IO uint16_t DR41; uint16_t RESERVED44; __IO uint16_t DR42; uint16_t RESERVED45; } BKP_TypeDef; /** * @brief Controller Area Network TxMailBox */ typedef struct { __IO uint32_t TIR; __IO uint32_t TDTR; __IO uint32_t TDLR; __IO uint32_t TDHR; } CAN_TxMailBox_TypeDef; /** * @brief Controller Area Network FIFOMailBox */ typedef struct { __IO uint32_t RIR; __IO uint32_t RDTR; __IO uint32_t RDLR; __IO uint32_t RDHR; } CAN_FIFOMailBox_TypeDef; /** * @brief Controller Area Network FilterRegister */ typedef struct { __IO uint32_t FR1; __IO uint32_t FR2; } CAN_FilterRegister_TypeDef; /** * @brief Controller Area Network */ typedef struct { __IO uint32_t MCR; __IO uint32_t MSR; __IO uint32_t TSR; __IO uint32_t RF0R; __IO uint32_t RF1R; __IO uint32_t IER; __IO uint32_t ESR; __IO uint32_t BTR; uint32_t RESERVED0[88]; CAN_TxMailBox_TypeDef sTxMailBox[3]; CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; uint32_t RESERVED1[12]; __IO uint32_t FMR; __IO uint32_t FM1R; uint32_t RESERVED2; __IO uint32_t FS1R; uint32_t RESERVED3; __IO uint32_t FFA1R; uint32_t RESERVED4; __IO uint32_t FA1R; uint32_t RESERVED5[8]; #ifndef STM32F10X_CL CAN_FilterRegister_TypeDef sFilterRegister[14]; #else CAN_FilterRegister_TypeDef sFilterRegister[28]; #endif } CAN_TypeDef; /** * @brief HDMI-CEC */ typedef struct { __IO uint32_t CFGR; __IO uint32_t OAR; __IO uint32_t PRES; __IO uint32_t ESR; __IO uint32_t CSR; __IO uint32_t TXD; __IO uint32_t RXD; } CEC_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; __IO uint8_t IDR; uint8_t RESERVED0; uint16_t RESERVED1; __IO uint32_t CR; } CRC_TypeDef; /** * @brief Digital to Analog Converter */ typedef struct { __IO uint32_t CR; __IO uint32_t SWTRIGR; __IO uint32_t DHR12R1; __IO uint32_t DHR12L1; __IO uint32_t DHR8R1; __IO uint32_t DHR12R2; __IO uint32_t DHR12L2; __IO uint32_t DHR8R2; __IO uint32_t DHR12RD; __IO uint32_t DHR12LD; __IO uint32_t DHR8RD; __IO uint32_t DOR1; __IO uint32_t DOR2; #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) __IO uint32_t SR; #endif } DAC_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; __IO uint32_t CR; } DBGMCU_TypeDef; /** * @brief DMA Channel */ typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; __IO uint32_t CPAR; __IO uint32_t CMAR; } DMA_Channel_TypeDef; /** * @brief Direct Memory Access Controller */ typedef struct { __IO uint32_t ISR; __IO uint32_t IFCR; } DMA_TypeDef; /** * @brief Ethernet MAC */ typedef struct { __IO uint32_t MACCR; __IO uint32_t MACFFR; __IO uint32_t MACHTHR; __IO uint32_t MACHTLR; __IO uint32_t MACMIIAR; __IO uint32_t MACMIIDR; __IO uint32_t MACFCR; __IO uint32_t MACVLANTR; uint32_t RESERVED0[2]; __IO uint32_t MACRWUFFR; __IO uint32_t MACPMTCSR; uint32_t RESERVED1[2]; __IO uint32_t MACSR; __IO uint32_t MACIMR; __IO uint32_t MACA0HR; __IO uint32_t MACA0LR; __IO uint32_t MACA1HR; __IO uint32_t MACA1LR; __IO uint32_t MACA2HR; __IO uint32_t MACA2LR; __IO uint32_t MACA3HR; __IO uint32_t MACA3LR; uint32_t RESERVED2[40]; __IO uint32_t MMCCR; __IO uint32_t MMCRIR; __IO uint32_t MMCTIR; __IO uint32_t MMCRIMR; __IO uint32_t MMCTIMR; uint32_t RESERVED3[14]; __IO uint32_t MMCTGFSCCR; __IO uint32_t MMCTGFMSCCR; uint32_t RESERVED4[5]; __IO uint32_t MMCTGFCR; uint32_t RESERVED5[10]; __IO uint32_t MMCRFCECR; __IO uint32_t MMCRFAECR; uint32_t RESERVED6[10]; __IO uint32_t MMCRGUFCR; uint32_t RESERVED7[334]; __IO uint32_t PTPTSCR; __IO uint32_t PTPSSIR; __IO uint32_t PTPTSHR; __IO uint32_t PTPTSLR; __IO uint32_t PTPTSHUR; __IO uint32_t PTPTSLUR; __IO uint32_t PTPTSAR; __IO uint32_t PTPTTHR; __IO uint32_t PTPTTLR; uint32_t RESERVED8[567]; __IO uint32_t DMABMR; __IO uint32_t DMATPDR; __IO uint32_t DMARPDR; __IO uint32_t DMARDLAR; __IO uint32_t DMATDLAR; __IO uint32_t DMASR; __IO uint32_t DMAOMR; __IO uint32_t DMAIER; __IO uint32_t DMAMFBOCR; uint32_t RESERVED9[9]; __IO uint32_t DMACHTDR; __IO uint32_t DMACHRDR; __IO uint32_t DMACHTBAR; __IO uint32_t DMACHRBAR; } ETH_TypeDef; /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t IMR; __IO uint32_t EMR; __IO uint32_t RTSR; __IO uint32_t FTSR; __IO uint32_t SWIER; __IO uint32_t PR; } EXTI_TypeDef; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t ACR; __IO uint32_t KEYR; __IO uint32_t OPTKEYR; __IO uint32_t SR; __IO uint32_t CR; __IO uint32_t AR; __IO uint32_t RESERVED; __IO uint32_t OBR; __IO uint32_t WRPR; #ifdef STM32F10X_XL uint32_t RESERVED1[8]; __IO uint32_t KEYR2; uint32_t RESERVED2; __IO uint32_t SR2; __IO uint32_t CR2; __IO uint32_t AR2; #endif } FLASH_TypeDef; /** * @brief Option Bytes Registers */ typedef struct { __IO uint16_t RDP; __IO uint16_t USER; __IO uint16_t Data0; __IO uint16_t Data1; __IO uint16_t WRP0; __IO uint16_t WRP1; __IO uint16_t WRP2; __IO uint16_t WRP3; } OB_TypeDef; /** * @brief Flexible Static Memory Controller */ typedef struct { __IO uint32_t BTCR[8]; } FSMC_Bank1_TypeDef; /** * @brief Flexible Static Memory Controller Bank1E */ typedef struct { __IO uint32_t BWTR[7]; } FSMC_Bank1E_TypeDef; /** * @brief Flexible Static Memory Controller Bank2 */ typedef struct { __IO uint32_t PCR2; __IO uint32_t SR2; __IO uint32_t PMEM2; __IO uint32_t PATT2; uint32_t RESERVED0; __IO uint32_t ECCR2; } FSMC_Bank2_TypeDef; /** * @brief Flexible Static Memory Controller Bank3 */ typedef struct { __IO uint32_t PCR3; __IO uint32_t SR3; __IO uint32_t PMEM3; __IO uint32_t PATT3; uint32_t RESERVED0; __IO uint32_t ECCR3; } FSMC_Bank3_TypeDef; /** * @brief Flexible Static Memory Controller Bank4 */ typedef struct { __IO uint32_t PCR4; __IO uint32_t SR4; __IO uint32_t PMEM4; __IO uint32_t PATT4; __IO uint32_t PIO4; } FSMC_Bank4_TypeDef; /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t CRL; __IO uint32_t CRH; __IO uint32_t IDR; __IO uint32_t ODR; __IO uint32_t BSRR; __IO uint32_t BRR; __IO uint32_t LCKR; } GPIO_TypeDef; /** * @brief Alternate Function I/O */ typedef struct { __IO uint32_t EVCR; __IO uint32_t MAPR; __IO uint32_t EXTICR[4]; uint32_t RESERVED0; __IO uint32_t MAPR2; } AFIO_TypeDef; /** * @brief Inter Integrated Circuit Interface */ typedef struct { __IO uint16_t CR1; uint16_t RESERVED0; __IO uint16_t CR2; uint16_t RESERVED1; __IO uint16_t OAR1; uint16_t RESERVED2; __IO uint16_t OAR2; uint16_t RESERVED3; __IO uint16_t DR; uint16_t RESERVED4; __IO uint16_t SR1; uint16_t RESERVED5; __IO uint16_t SR2; uint16_t RESERVED6; __IO uint16_t CCR; uint16_t RESERVED7; __IO uint16_t TRISE; uint16_t RESERVED8; } I2C_TypeDef; /** * @brief Independent WATCHDOG */ typedef struct { __IO uint32_t KR; __IO uint32_t PR; __IO uint32_t RLR; __IO uint32_t SR; } IWDG_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t CR; __IO uint32_t CSR; } PWR_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; __IO uint32_t CFGR; __IO uint32_t CIR; __IO uint32_t APB2RSTR; __IO uint32_t APB1RSTR; __IO uint32_t AHBENR; __IO uint32_t APB2ENR; __IO uint32_t APB1ENR; __IO uint32_t BDCR; __IO uint32_t CSR; #ifdef STM32F10X_CL __IO uint32_t AHBRSTR; __IO uint32_t CFGR2; #endif /* STM32F10X_CL */ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) uint32_t RESERVED0; __IO uint32_t CFGR2; #endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ } RCC_TypeDef; /** * @brief Real-Time Clock */ typedef struct { __IO uint16_t CRH; uint16_t RESERVED0; __IO uint16_t CRL; uint16_t RESERVED1; __IO uint16_t PRLH; uint16_t RESERVED2; __IO uint16_t PRLL; uint16_t RESERVED3; __IO uint16_t DIVH; uint16_t RESERVED4; __IO uint16_t DIVL; uint16_t RESERVED5; __IO uint16_t CNTH; uint16_t RESERVED6; __IO uint16_t CNTL; uint16_t RESERVED7; __IO uint16_t ALRH; uint16_t RESERVED8; __IO uint16_t ALRL; uint16_t RESERVED9; } RTC_TypeDef; /** * @brief SD host Interface */ typedef struct { __IO uint32_t POWER; __IO uint32_t CLKCR; __IO uint32_t ARG; __IO uint32_t CMD; __I uint32_t RESPCMD; __I uint32_t RESP1; __I uint32_t RESP2; __I uint32_t RESP3; __I uint32_t RESP4; __IO uint32_t DTIMER; __IO uint32_t DLEN; __IO uint32_t DCTRL; __I uint32_t DCOUNT; __I uint32_t STA; __IO uint32_t ICR; __IO uint32_t MASK; uint32_t RESERVED0[2]; __I uint32_t FIFOCNT; uint32_t RESERVED1[13]; __IO uint32_t FIFO; } SDIO_TypeDef; /** * @brief Serial Peripheral Interface */ typedef struct { __IO uint16_t CR1; uint16_t RESERVED0; __IO uint16_t CR2; uint16_t RESERVED1; __IO uint16_t SR; uint16_t RESERVED2; __IO uint16_t DR; uint16_t RESERVED3; __IO uint16_t CRCPR; uint16_t RESERVED4; __IO uint16_t RXCRCR; uint16_t RESERVED5; __IO uint16_t TXCRCR; uint16_t RESERVED6; __IO uint16_t I2SCFGR; uint16_t RESERVED7; __IO uint16_t I2SPR; uint16_t RESERVED8; } SPI_TypeDef; /** * @brief TIM */ typedef struct { __IO uint16_t CR1; uint16_t RESERVED0; __IO uint16_t CR2; uint16_t RESERVED1; __IO uint16_t SMCR; uint16_t RESERVED2; __IO uint16_t DIER; uint16_t RESERVED3; __IO uint16_t SR; uint16_t RESERVED4; __IO uint16_t EGR; uint16_t RESERVED5; __IO uint16_t CCMR1; uint16_t RESERVED6; __IO uint16_t CCMR2; uint16_t RESERVED7; __IO uint16_t CCER; uint16_t RESERVED8; __IO uint16_t CNT; uint16_t RESERVED9; __IO uint16_t PSC; uint16_t RESERVED10; __IO uint16_t ARR; uint16_t RESERVED11; __IO uint16_t RCR; uint16_t RESERVED12; __IO uint16_t CCR1; uint16_t RESERVED13; __IO uint16_t CCR2; uint16_t RESERVED14; __IO uint16_t CCR3; uint16_t RESERVED15; __IO uint16_t CCR4; uint16_t RESERVED16; __IO uint16_t BDTR; uint16_t RESERVED17; __IO uint16_t DCR; uint16_t RESERVED18; __IO uint16_t DMAR; uint16_t RESERVED19; } TIM_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint16_t SR; uint16_t RESERVED0; __IO uint16_t DR; uint16_t RESERVED1; __IO uint16_t BRR; uint16_t RESERVED2; __IO uint16_t CR1; uint16_t RESERVED3; __IO uint16_t CR2; uint16_t RESERVED4; __IO uint16_t CR3; uint16_t RESERVED5; __IO uint16_t GTPR; uint16_t RESERVED6; } USART_TypeDef; /** * @brief Window WATCHDOG */ typedef struct { __IO uint32_t CR; __IO uint32_t CFR; __IO uint32_t SR; } WWDG_TypeDef; #ifdef __cplusplus } #endif #endif