{
  "source": "E2EBotConversation",
  "sessionUuid": "331803a7-5015-4c16-886f-75f95a9f7cfd",
  "messages": [
    {
      "id": "64003589",
      "summary": "S32K144启动文件汇编错误分析",
      "role": "user",
      "status": "success",
      "content": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S(123): error: A1163E: Unknown opcode __flash_vector_table__ , expecting opcode or Macro",
      "payload": {
        "query": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S(123): error: A1163E: Unknown opcode __flash_vector_table__ , expecting opcode or Macro",
        "model": {
          "displayName": "Auto",
          "modelId": "auto",
          "requestType": "COMATE_DEFAULT_MODE",
          "mode": "NORMAL"
        },
        "metrics": {
          "model": "",
          "function": ""
        },
        "knowledgeList": [],
        "isCurrentFileSelected": false,
        "isSpec": false,
        "agent": {}
      },
      "context": {
        "taskId": 580394,
        "conversationId": 18637338,
        "userMessageId": 64003589,
        "sessionId": 25907996
      }
    },
    {
      "id": "c16001b7-4920-4ac1-8d06-1e326cdb4b55",
      "userMessageId": "64003589",
      "reportedId": null,
      "role": "assistant",
      "status": "completed",
      "content": {},
      "elements": [
        {
          "id": "d2846dfc-22c7-4210-99ed-e9a11e48458e",
          "type": "TEXT",
          "status": "success",
          "content": "我看到您遇到了编译错误，这是在汇编文件中出现的问题。错误显示在 `RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S` 文件的第123行，编译器无法识别 `__flash_vector_table__` 这个操作码。让我来查看这个文件，找出问题所在。\n\n首先我需要查看这个启动文件的内容，特别是错误发生的位置附近：\n\n",
          "composer": {
            "markdown": "",
            "tasks": []
          },
          "isErrorMessage": false,
          "parentMessageId": ""
        },
        {
          "id": "0745628a-37b8-4a59-9fc3-17e44cc3f486",
          "type": "TOOL_CALL",
          "status": "success",
          "toolName": "extract_content_blocks",
          "composer": {
            "markdown": "",
            "tasks": []
          },
          "workflowStatus": "success",
          "displayParams": {
            "firstFilePath": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S"
          },
          "displayResult": {
            "fileBlocks": [
              {
                "path": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S",
                "startLine": 1,
                "endLine": 1
              }
            ]
          },
          "workflowSnapshot": {
            "status": "success",
            "result": {
              "name": "extract_content_blocks",
              "type": "tool_use",
              "params": {
                "pathes": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S\n"
              },
              "success": true,
              "message": "",
              "code": 0,
              "result": [
                {
                  "path": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S",
                  "content": "",
                  "start_line": 1,
                  "end_line": 1,
                  "line_count": 1
                }
              ]
            }
          },
          "params": {
            "pathes": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S\n"
          },
          "parentMessageId": ""
        },
        {
          "id": "165ae812-4356-49c3-b979-b43898102ac5",
          "type": "TEXT",
          "status": "success",
          "content": "看起来这个文件内容不完整，我需要重新检查一下。让我先查看项目中的其他启动文件，因为错误提示的是 [`startup_S32K144.S`](RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S)，项目中可能有多个这样的文件：\n\n",
          "composer": {
            "markdown": "",
            "tasks": []
          },
          "isErrorMessage": false,
          "parentMessageId": ""
        },
        {
          "id": "a17d518c-e7e6-4ff0-a0f7-ff31cdf0e439",
          "type": "TOOL_CALL",
          "status": "failed",
          "toolName": "search_files",
          "composer": {
            "markdown": "",
            "tasks": []
          },
          "workflowStatus": "failed",
          "displayParams": {
            "path": "d:/Keil/ARM/Packs/Keil/S32_SDK_DFP/1.5.1/CMSIS/Flash/CVD_S32",
            "regex": "**/startup_S32K144.S"
          },
          "displayResult": {
            "searchFiles": []
          },
          "workflowSnapshot": {
            "searchFiles": [],
            "status": "failed",
            "result": {
              "name": "search_files",
              "type": "tool_use",
              "params": {
                "file_pattern": "**/startup_S32K144.S"
              },
              "success": false,
              "message": "ripgrep process error: error: Found argument '--glob !(node_modules|site_packages|bundle|dist|.git|.svn)' which wasn't expected, or isn't valid in this context\n\tDid you mean --glob?\n\nUSAGE:\n    \n    rg [OPTIONS] PATTERN [PATH ...]\n    rg [OPTIONS] -e PATTERN ... [PATH ...]\n    rg [OPTIONS] -f PATTERNFILE ... [PATH ...]\n    rg [OPTIONS] --files [PATH ...]\n    rg [OPTIONS] --type-list\n    command | rg [OPTIONS] PATTERN\n    rg [OPTIONS] --help\n    rg [OPTIONS] --version\n\nFor more information try --help\n\n",
              "code": 1,
              "result": null
            }
          },
          "params": {
            "file_pattern": "**/startup_S32K144.S"
          },
          "parentMessageId": ""
        },
        {
          "id": "18afd3e7-8122-48a2-b4e1-9567b8e792cd",
          "type": "TEXT",
          "status": "success",
          "content": "我看到搜索命令出现了问题。让我使用 `list_files` 工具来查看项目结构，特别是启动文件的位置：\n\n",
          "composer": {
            "markdown": "",
            "tasks": []
          },
          "isErrorMessage": false,
          "parentMessageId": ""
        },
        {
          "id": "0e74730e-d4b9-4bee-ab36-08d5b0727b6e",
          "type": "TOOL_CALL",
          "status": "success",
          "toolName": "list_files",
          "composer": {
            "markdown": "",
            "tasks": []
          },
          "workflowStatus": "success",
          "displayParams": {
            "path": "RTE/Device/S32K144HFxxxLLx"
          },
          "displayResult": {
            "fileCount": 5
          },
          "workflowSnapshot": {
            "status": "success",
            "result": {
              "name": "list_files",
              "type": "tool_use",
              "params": {
                "path": "RTE\\Device\\S32K144HFxxxLLx",
                "recursive": "true"
              },
              "success": true,
              "message": "",
              "code": 0,
              "result": [
                {
                  "path": "S32K144_64_flash.sct",
                  "type": "file"
                },
                {
                  "path": "S32K144_64_ram.sct",
                  "type": "file"
                },
                {
                  "path": "startup_S32K144.S",
                  "type": "file"
                },
                {
                  "path": "system_S32K144.c",
                  "type": "file"
                },
                {
                  "path": "system_S32K144.h",
                  "type": "file"
                }
              ]
            }
          },
          "params": {
            "path": "RTE\\Device\\S32K144HFxxxLLx",
            "recursive": "true"
          },
          "parentMessageId": ""
        },
        {
          "id": "1628f107-2c2a-4519-ace2-52679eb4830c",
          "type": "TEXT",
          "status": "success",
          "content": "很好，现在我找到了启动文件的位置。让我查看这个启动文件的内容，特别是错误发生的第123行附近：\n\n",
          "composer": {
            "markdown": "",
            "tasks": []
          },
          "isErrorMessage": false,
          "parentMessageId": ""
        },
        {
          "id": "e73d3fff-8a75-40fe-b362-4902fae24c90",
          "type": "TOOL_CALL",
          "status": "success",
          "toolName": "extract_content_blocks",
          "composer": {
            "markdown": "",
            "tasks": []
          },
          "workflowStatus": "success",
          "displayParams": {
            "firstFilePath": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S"
          },
          "displayResult": {
            "fileBlocks": [
              {
                "path": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S",
                "startLine": 1,
                "endLine": 781
              }
            ]
          },
          "workflowSnapshot": {
            "status": "success",
            "result": {
              "name": "extract_content_blocks",
              "type": "tool_use",
              "params": {
                "pathes": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S\n"
              },
              "success": true,
              "message": "",
              "code": 0,
              "result": [
                {
                  "path": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S",
                  "content": ";\n; modified by ARM\n;\n; ---------------------------------------------------------------------------------------\n;  @file:    startup_S32K144.S\n;  @purpose: ARM Compiler Collection Startup File\n;            S32K144\n;  @version: 2.2.0\n;  @date:    2017-1-10\n;  @build:   b170107\n; ---------------------------------------------------------------------------------------\n;\n; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc.\n; Copyright 2016-2017 NXP\n; All rights reserved.\n;\n; NXP Confidential. This software is owned or controlled by NXP and may only be\n; used strictly in accordance with the applicable license terms. By expressly\n; accepting such terms or by downloading, installing, activating and/or otherwise\n; using the software, you are agreeing that you have read, and that you agree to\n; comply with and are bound by, such license terms. If you do not agree to be\n; bound by the applicable license terms, then you may not retain, install,\n; activate or otherwise use the software. The production use license in\n; Section 2.3 is expressly granted for this software.\n;***************************************************************************\n; Version: ARMC Compiler Collection\n;***************************************************************************\n\n;// ------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n\n\n                PRESERVE8\n                THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n                AREA    |.text|, CODE, READONLY\n                EXPORT  __Vectors\n\n                EXPORT __RAM_VECTOR_TABLE_SIZE\n                EXPORT __VECTOR_RAM\n                EXPORT __VECTOR_ROM\n\n                EXPORT __BSS_START\n                EXPORT __BSS_END\n\n                EXPORT __CODE_ROM\n                EXPORT __CODE_END\n                EXPORT __CODE_RAM\n\n                EXPORT __DATA_ROM\n                EXPORT __DATA_END\n                EXPORT __DATA_RAM\n                EXPORT __VECTOR_ROM_START\n                EXPORT __VECTOR_ROM_END\n                EXPORT __DATA_RAM_START\n                EXPORT __DATA_RAM_END\n                EXPORT __CUSTOM_SECTION_START\n                EXPORT __CUSTOM_SECTION_END\n                EXPORT __CODE_RAM_START\n                EXPORT __CODE_RAM_END\n\n                EXPORT __RAM_START\n                EXPORT __RAM_END\n\n                IMPORT init_data_bss\n                IMPORT  main\n                IMPORT  __main\n                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|\n                IMPORT  |Image$$RW_m_data_2$$ZI$$Base|\n                IMPORT  |Image$$RW_m_data_2$$ZI$$Limit|\n\n                IMPORT  |Image$$ER_m_text_const$$Base|\n                IMPORT  |Image$$ER_m_text_const$$Limit|\n\n                IMPORT  |Image$$RW_m_data$$Base|\n\n                IMPORT  |Image$$ER_m_text_const$$Base|\n                IMPORT  |Image$$ER_m_text_const$$Limit|\n\n                IMPORT  |Image$$RW_m_data$$Length|\n                IMPORT |Image$$RW_m_code$$Base|\n                IMPORT |Image$$RW_m_code$$Length|\n                IMPORT |Image$$ER_m_text$$Limit|\n\n                IMPORT |Image$$VECTOR_RAM$$Length|\n                IMPORT |Image$$VECTOR_RAM$$Base|\n\n                IMPORT |Image$$VECTOR_ROM$$Length|\n                IMPORT |Image$$VECTOR_ROM$$Base|\n                IMPORT |Image$$RW_m_custom_section$$Base|\n                IMPORT |Image$$RW_m_custom_section$$Limit|\n\n                IMPORT |Image$$RW_m_data$$Limit|\n                IMPORT |Image$$RW_m_code$$Limit|\n                IMPORT |Image$$VECTOR_ROM$$Limit|\n\n                IMPORT |Image$$ARM_LIB_STACK$$Limit|\n__RAM_VECTOR_TABLE_SIZE DCD |Image$$VECTOR_ROM$$Length|\n__VECTOR_RAM DCD |Image$$VECTOR_RAM$$Base|\n__VECTOR_ROM DCD |Image$$VECTOR_ROM$$Base|\n__VECTOR_ROM_START DCD |Image$$VECTOR_ROM$$Base|\n__VECTOR_ROM_END DCD |Image$$VECTOR_ROM$$Limit|\n\n__CODE_ROM DCD  |Image$$RW_m_data$$Length|+ |Image$$ER_m_text$$Limit|\n__CODE_END DCD  |Image$$RW_m_data$$Length|+ |Image$$ER_m_text$$Limit| + |Image$$RW_m_code$$Length|\n__CODE_RAM DCD |Image$$RW_m_code$$Base|\n__CODE_RAM_START DCD |Image$$RW_m_code$$Base|\n__CODE_RAM_END DCD |Image$$RW_m_code$$Limit|\n\n__BSS_START DCD  |Image$$RW_m_data_2$$ZI$$Base|\n__BSS_END DCD  |Image$$RW_m_data_2$$ZI$$Limit|\n\n__DATA_RAM DCD  |Image$$RW_m_data$$Base|\n__DATA_RAM_START DCD  |Image$$RW_m_data$$Base|\n__DATA_RAM_END DCD  |Image$$RW_m_data$$Limit|\n__DATA_ROM DCD  |Image$$ER_m_text$$Limit|\n__DATA_END DCD  |Image$$RW_m_data$$Length|+ |Image$$ER_m_text$$Limit|\n__CUSTOM_SECTION_START DCD |Image$$RW_m_custom_section$$Base|\n__CUSTOM_SECTION_END DCD |Image$$RW_m_custom_section$$Limit|\n\n#ifndef __flash_vector_table__\n__RAM_START DCD |Image$$VECTOR_RAM$$Base|\n#else\n__RAM_START DCD |Image$$RW_m_data$$Base|\n#endif\n__RAM_END   DCD |Image$$ARM_LIB_STACK$$Limit|\n\n\t\tAREA    RESET, DATA, READONLY\n__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit|   ; Top of Stack\n                DCD     Reset_Handler                       ; Reset Handler\n                DCD     NMI_Handler                         ; NMI Handler\n                DCD     HardFault_Handler                   ; Hard Fault Handler\n                DCD     MemManage_Handler                   ; MPU Fault Handler\n                DCD     BusFault_Handler                    ; Bus Fault Handler\n                DCD     UsageFault_Handler                  ; Usage Fault Handler\n                DCD     0                                   ; Reserved\n                DCD     0                                   ; Reserved\n                DCD     0                                   ; Reserved\n                DCD     0                                   ; Reserved\n                DCD     SVC_Handler                         ; SVCall Handler\n                DCD     DebugMon_Handler                    ; Debug Monitor Handler\n                DCD     0                                   ; Reserved\n                DCD     PendSV_Handler                      ; PendSV Handler\n                DCD     SysTick_Handler                     ; SysTick Handler\n\n                                                            ; External Interrupts\n    DCD   DMA0_IRQHandler                                 ; DMA channel 0 transfer complete\n    DCD   DMA1_IRQHandler                                 ; DMA channel 1 transfer complete\n    DCD   DMA2_IRQHandler                                 ; DMA channel 2 transfer complete\n    DCD   DMA3_IRQHandler                                 ; DMA channel 3 transfer complete\n    DCD   DMA4_IRQHandler                                 ; DMA channel 4 transfer complete\n    DCD   DMA5_IRQHandler                                 ; DMA channel 5 transfer complete\n    DCD   DMA6_IRQHandler                                 ; DMA channel 6 transfer complete\n    DCD   DMA7_IRQHandler                                 ; DMA channel 7 transfer complete\n    DCD   DMA8_IRQHandler                                 ; DMA channel 8 transfer complete\n    DCD   DMA9_IRQHandler                                 ; DMA channel 9 transfer complete\n    DCD   DMA10_IRQHandler                                ; DMA channel 10 transfer complete\n    DCD   DMA11_IRQHandler                                ; DMA channel 11 transfer complete\n    DCD   DMA12_IRQHandler                                ; DMA channel 12 transfer complete\n    DCD   DMA13_IRQHandler                                ; DMA channel 13 transfer complete\n    DCD   DMA14_IRQHandler                                ; DMA channel 14 transfer complete\n    DCD   DMA15_IRQHandler                                ; DMA channel 15 transfer complete\n    DCD   DMA_Error_IRQHandler                            ; DMA error interrupt channels 0-15\n    DCD   MCM_IRQHandler                                  ; FPU sources\n    DCD   FTFC_IRQHandler                                 ; FTFC Command complete\n    DCD   Read_Collision_IRQHandler                       ; FTFC Read collision\n    DCD   LVD_LVW_IRQHandler                              ; PMC Low voltage detect interrupt\n    DCD   FTFC_Fault_IRQHandler                           ; FTFC Double bit fault detect\n    DCD   WDOG_EWM_IRQHandler                             ; Single interrupt vector for WDOG and EWM\n    DCD   RCM_IRQHandler                                  ; RCM Asynchronous Interrupt\n    DCD   LPI2C0_Master_IRQHandler                        ; LPI2C0 Master Interrupt\n    DCD   LPI2C0_Slave_IRQHandler                         ; LPI2C0 Slave Interrupt\n    DCD   LPSPI0_IRQHandler                               ; LPSPI0 Interrupt\n    DCD   LPSPI1_IRQHandler                               ; LPSPI1 Interrupt\n    DCD   LPSPI2_IRQHandler                               ; LPSPI2 Interrupt\n    DCD   Reserved45_IRQHandler                           ; Reserved Interrupt 45\n    DCD   Reserved46_IRQHandler                           ; Reserved Interrupt 46\n    DCD   LPUART0_RxTx_IRQHandler                         ; LPUART0 Transmit / Receive Interrupt\n    DCD   Reserved48_IRQHandler                           ; Reserved Interrupt 48\n    DCD   LPUART1_RxTx_IRQHandler                         ; LPUART1 Transmit / Receive  Interrupt\n    DCD   Reserved50_IRQHandler                           ; Reserved Interrupt 50\n    DCD   LPUART2_RxTx_IRQHandler                         ; LPUART2 Transmit / Receive  Interrupt\n    DCD   Reserved52_IRQHandler                           ; Reserved Interrupt 52\n    DCD   Reserved53_IRQHandler                           ; Reserved Interrupt 53\n    DCD   Reserved54_IRQHandler                           ; Reserved Interrupt 54\n    DCD   ADC0_IRQHandler                                 ; ADC0 interrupt request.\n    DCD   ADC1_IRQHandler                                 ; ADC1 interrupt request.\n    DCD   CMP0_IRQHandler                                 ; CMP0 interrupt request\n    DCD   Reserved58_IRQHandler                           ; Reserved Interrupt 58\n    DCD   Reserved59_IRQHandler                           ; Reserved Interrupt 59\n    DCD   ERM_single_fault_IRQHandler                     ; ERM single bit error correction\n    DCD   ERM_double_fault_IRQHandler                     ; ERM double bit error non-correctable\n    DCD   RTC_IRQHandler                                  ; RTC alarm interrupt\n    DCD   RTC_Seconds_IRQHandler                          ; RTC seconds interrupt\n    DCD   LPIT0_Ch0_IRQHandler                            ; LPIT0 channel 0 overflow interrupt\n    DCD   LPIT0_Ch1_IRQHandler                            ; LPIT0 channel 1 overflow interrupt\n    DCD   LPIT0_Ch2_IRQHandler                            ; LPIT0 channel 2 overflow interrupt\n    DCD   LPIT0_Ch3_IRQHandler                            ; LPIT0 channel 3 overflow interrupt\n    DCD   PDB0_IRQHandler                                 ; PDB0 interrupt\n    DCD   Reserved69_IRQHandler                           ; Reserved Interrupt 69\n    DCD   Reserved70_IRQHandler                           ; Reserved Interrupt 70\n    DCD   Reserved71_IRQHandler                           ; Reserved Interrupt 71\n    DCD   Reserved72_IRQHandler                           ; Reserved Interrupt 72\n    DCD   SCG_IRQHandler                                  ; SCG bus interrupt request\n    DCD   LPTMR0_IRQHandler                               ; LPTIMER interrupt request\n    DCD   PORTA_IRQHandler                                ; Port A pin detect interrupt\n    DCD   PORTB_IRQHandler                                ; Port B pin detect interrupt\n    DCD   PORTC_IRQHandler                                ; Port C pin detect interrupt\n    DCD   PORTD_IRQHandler                                ; Port D pin detect interrupt\n    DCD   PORTE_IRQHandler                                ; Port E pin detect interrupt\n    DCD   SWI_IRQHandler                                  ; Software interrupt\n    DCD   Reserved81_IRQHandler                           ; Reserved Interrupt 81\n    DCD   Reserved82_IRQHandler                           ; Reserved Interrupt 82\n    DCD   Reserved83_IRQHandler                           ; Reserved Interrupt 83\n    DCD   PDB1_IRQHandler                                 ; PDB1 interrupt\n    DCD   FLEXIO_IRQHandler                               ; FlexIO Interrupt\n    DCD   Reserved86_IRQHandler                           ; Reserved Interrupt 86\n    DCD   Reserved87_IRQHandler                           ; Reserved Interrupt 87\n    DCD   Reserved88_IRQHandler                           ; Reserved Interrupt 88\n    DCD   Reserved89_IRQHandler                           ; Reserved Interrupt 89\n    DCD   Reserved90_IRQHandler                           ; Reserved Interrupt 90\n    DCD   Reserved91_IRQHandler                           ; Reserved Interrupt 91\n    DCD   Reserved92_IRQHandler                           ; Reserved Interrupt 92\n    DCD   Reserved93_IRQHandler                           ; Reserved Interrupt 93\n    DCD   CAN0_ORed_IRQHandler                            ; CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\n    DCD   CAN0_Error_IRQHandler                           ; CAN0 Interrupt indicating that errors were detected on the CAN bus\n    DCD   CAN0_Wake_Up_IRQHandler                         ; CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode\n    DCD   CAN0_ORed_0_15_MB_IRQHandler                    ; CAN0 OR'ed Message buffer (0-15)\n    DCD   CAN0_ORed_16_31_MB_IRQHandler                   ; CAN0 OR'ed Message buffer (16-31)\n    DCD   Reserved99_IRQHandler                           ; Reserved Interrupt 99\n    DCD   Reserved100_IRQHandler                          ; Reserved Interrupt 100\n    DCD   CAN1_ORed_IRQHandler                            ; CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\n    DCD   CAN1_Error_IRQHandler                           ; CAN1 Interrupt indicating that errors were detected on the CAN bus\n    DCD   Reserved103_IRQHandler                          ; Reserved Interrupt 103\n    DCD   CAN1_ORed_0_15_MB_IRQHandler                    ; CAN1 OR'ed Interrupt for Message buffer (0-15)\n    DCD   Reserved105_IRQHandler                          ; Reserved Interrupt 105\n    DCD   Reserved106_IRQHandler                          ; Reserved Interrupt 106\n    DCD   Reserved107_IRQHandler                          ; Reserved Interrupt 107\n    DCD   CAN2_ORed_IRQHandler                            ; CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\n    DCD   CAN2_Error_IRQHandler                           ; CAN2 Interrupt indicating that errors were detected on the CAN bus\n    DCD   Reserved110_IRQHandler                          ; Reserved Interrupt 110\n    DCD   CAN2_ORed_0_15_MB_IRQHandler                    ; CAN2 OR'ed Message buffer (0-15)\n    DCD   Reserved112_IRQHandler                          ; Reserved Interrupt 112\n    DCD   Reserved113_IRQHandler                          ; Reserved Interrupt 113\n    DCD   Reserved114_IRQHandler                          ; Reserved Interrupt 114\n    DCD   FTM0_Ch0_Ch1_IRQHandler                         ; FTM0 Channel 0 and 1 interrupt\n    DCD   FTM0_Ch2_Ch3_IRQHandler                         ; FTM0 Channel 2 and 3 interrupt\n    DCD   FTM0_Ch4_Ch5_IRQHandler                         ; FTM0 Channel 4 and 5 interrupt\n    DCD   FTM0_Ch6_Ch7_IRQHandler                         ; FTM0 Channel 6 and 7 interrupt\n    DCD   FTM0_Fault_IRQHandler                           ; FTM0 Fault interrupt\n    DCD   FTM0_Ovf_Reload_IRQHandler                      ; FTM0 Counter overflow and Reload interrupt\n    DCD   FTM1_Ch0_Ch1_IRQHandler                         ; FTM1 Channel 0 and 1 interrupt\n    DCD   FTM1_Ch2_Ch3_IRQHandler                         ; FTM1 Channel 2 and 3 interrupt\n    DCD   FTM1_Ch4_Ch5_IRQHandler                         ; FTM1 Channel 4 and 5 interrupt\n    DCD   FTM1_Ch6_Ch7_IRQHandler                         ; FTM1 Channel 6 and 7 interrupt\n    DCD   FTM1_Fault_IRQHandler                           ; FTM1 Fault interrupt\n    DCD   FTM1_Ovf_Reload_IRQHandler                      ; FTM1 Counter overflow and Reload interrupt\n    DCD   FTM2_Ch0_Ch1_IRQHandler                         ; FTM2 Channel 0 and 1 interrupt\n    DCD   FTM2_Ch2_Ch3_IRQHandler                         ; FTM2 Channel 2 and 3 interrupt\n    DCD   FTM2_Ch4_Ch5_IRQHandler                         ; FTM2 Channel 4 and 5 interrupt\n    DCD   FTM2_Ch6_Ch7_IRQHandler                         ; FTM2 Channel 6 and 7 interrupt\n    DCD   FTM2_Fault_IRQHandler                           ; FTM2 Fault interrupt\n    DCD   FTM2_Ovf_Reload_IRQHandler                      ; FTM2 Counter overflow and Reload interrupt\n    DCD   FTM3_Ch0_Ch1_IRQHandler                         ; FTM3 Channel 0 and 1 interrupt\n    DCD   FTM3_Ch2_Ch3_IRQHandler                         ; FTM3 Channel 2 and 3 interrupt\n    DCD   FTM3_Ch4_Ch5_IRQHandler                         ; FTM3 Channel 4 and 5 interrupt\n    DCD   FTM3_Ch6_Ch7_IRQHandler                         ; FTM3 Channel 6 and 7 interrupt\n    DCD   FTM3_Fault_IRQHandler                           ; FTM3 Fault interrupt\n    DCD   FTM3_Ovf_Reload_IRQHandler                      ; FTM3 Counter overflow and Reload interrupt\n    DCD   DefaultISR                                      ; Default ISR\n__Vectors_End\n__Vectors_Size  EQU     __Vectors_End - __Vectors\n\n; <h> Flash Configuration\n;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)\n;   <i> and security information that allows the MCU to restrict access to the FTFL module.\n;   <h> Backdoor Comparison Key\n;     <o0>  Backdoor Comparison Key 0.  <0x0-0xFF:2>\n;     <o1>  Backdoor Comparison Key 1.  <0x0-0xFF:2>\n;     <o2>  Backdoor Comparison Key 2.  <0x0-0xFF:2>\n;     <o3>  Backdoor Comparison Key 3.  <0x0-0xFF:2>\n;     <o4>  Backdoor Comparison Key 4.  <0x0-0xFF:2>\n;     <o5>  Backdoor Comparison Key 5.  <0x0-0xFF:2>\n;     <o6>  Backdoor Comparison Key 6.  <0x0-0xFF:2>\n;     <o7>  Backdoor Comparison Key 7.  <0x0-0xFF:2>\nBackDoorK0      EQU     0xFF\nBackDoorK1      EQU     0xFF\nBackDoorK2      EQU     0xFF\nBackDoorK3      EQU     0xFF\nBackDoorK4      EQU     0xFF\nBackDoorK5      EQU     0xFF\nBackDoorK6      EQU     0xFF\nBackDoorK7      EQU     0xFF\n;   </h>\n;   <h> Program flash protection bytes (FPROT)\n;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.\n;     <i> Each bit protects a 1/32 region of the program flash memory.\n;     <h> FPROT0\n;       <i> Program Flash Region Protect Register 0\n;       <i> 1/32 - 8/32 region\n;       <o.0>   FPROT0.0\n;       <o.1>   FPROT0.1\n;       <o.2>   FPROT0.2\n;       <o.3>   FPROT0.3\n;       <o.4>   FPROT0.4\n;       <o.5>   FPROT0.5\n;       <o.6>   FPROT0.6\n;       <o.7>   FPROT0.7\nnFPROT0         EQU     0x00\nFPROT0          EQU     nFPROT0:EOR:0xFF\n;     </h>\n;     <h> FPROT1\n;       <i> Program Flash Region Protect Register 1\n;       <i> 9/32 - 16/32 region\n;       <o.0>   FPROT1.0\n;       <o.1>   FPROT1.1\n;       <o.2>   FPROT1.2\n;       <o.3>   FPROT1.3\n;       <o.4>   FPROT1.4\n;       <o.5>   FPROT1.5\n;       <o.6>   FPROT1.6\n;       <o.7>   FPROT1.7\nnFPROT1         EQU     0x00\nFPROT1          EQU     nFPROT1:EOR:0xFF\n;     </h>\n;     <h> FPROT2\n;       <i> Program Flash Region Protect Register 2\n;       <i> 17/32 - 24/32 region\n;       <o.0>   FPROT2.0\n;       <o.1>   FPROT2.1\n;       <o.2>   FPROT2.2\n;       <o.3>   FPROT2.3\n;       <o.4>   FPROT2.4\n;       <o.5>   FPROT2.5\n;       <o.6>   FPROT2.6\n;       <o.7>   FPROT2.7\nnFPROT2         EQU     0x00\nFPROT2          EQU     nFPROT2:EOR:0xFF\n;     </h>\n;     <h> FPROT3\n;       <i> Program Flash Region Protect Register 3\n;       <i> 25/32 - 32/32 region\n;       <o.0>   FPROT3.0\n;       <o.1>   FPROT3.1\n;       <o.2>   FPROT3.2\n;       <o.3>   FPROT3.3\n;       <o.4>   FPROT3.4\n;       <o.5>   FPROT3.5\n;       <o.6>   FPROT3.6\n;       <o.7>   FPROT3.7\nnFPROT3         EQU     0x00\nFPROT3          EQU     nFPROT3:EOR:0xFF\n;     </h>\n;   </h>\n;   <h> Data flash protection byte (FDPROT)\n;     <i> Each bit protects a 1/8 region of the data flash memory.\n;     <i> (Program flash only devices: Reserved)\n;       <o.0>   FDPROT.0\n;       <o.1>   FDPROT.1\n;       <o.2>   FDPROT.2\n;       <o.3>   FDPROT.3\n;       <o.4>   FDPROT.4\n;       <o.5>   FDPROT.5\n;       <o.6>   FDPROT.6\n;       <o.7>   FDPROT.7\nnFDPROT         EQU     0x00\nFDPROT          EQU     nFDPROT:EOR:0xFF\n;   </h>\n;   <h> EEPROM protection byte (FEPROT)\n;     <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.\n;     <i> (Program flash only devices: Reserved)\n;       <o.0>   FEPROT.0\n;       <o.1>   FEPROT.1\n;       <o.2>   FEPROT.2\n;       <o.3>   FEPROT.3\n;       <o.4>   FEPROT.4\n;       <o.5>   FEPROT.5\n;       <o.6>   FEPROT.6\n;       <o.7>   FEPROT.7\nnFEPROT         EQU     0x00\nFEPROT          EQU     nFEPROT:EOR:0xFF\n;   </h>\n;   <h> Flash nonvolatile option byte (FOPT)\n;     <i> Allows the user to customize the operation of the MCU at boot time.\n;     <o.0> LPBOOT\n;       <0=> Low-power boot\n;       <1=> Normal boot\n;     <o.1> EZPORT_DIS\n;       <0=> EzPort operation is disabled\n;       <1=> EzPort operation is enabled\nFOPT          EQU     0xFD\n;   </h>\n;   <h> Flash security byte (FSEC)\n;     <i> WARNING: If SEC field is configured as \"MCU security status is secure\" and MEEN field is configured as \"Mass erase is disabled\",\n;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!\n;     <o.0..1> SEC\n;       <2=> MCU security status is unsecure\n;       <3=> MCU security status is secure\n;         <i> Flash Security\n;     <o.2..3> FSLACC\n;       <2=> Freescale factory access denied\n;       <3=> Freescale factory access granted\n;         <i> Freescale Failure Analysis Access Code\n;     <o.4..5> MEEN\n;       <2=> Mass erase is disabled\n;       <3=> Mass erase is enabled\n;     <o.6..7> KEYEN\n;       <2=> Backdoor key access enabled\n;       <3=> Backdoor key access disabled\n;         <i> Backdoor Key Security Enable\nFSEC          EQU     0xFE\n;   </h>\n; </h>\n\n#ifndef RAM_TARGET\n                AREA    FlashConfig, DATA, READONLY\n__FlashConfig\n                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3\n                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7\n                DCB     FPROT0    , FPROT1    , FPROT2    , FPROT3\n                DCB     FSEC      , FOPT      , FEPROT    , FDPROT\n#endif\n\n\n                AREA    |.text|, CODE, READONLY\n\n\nReset_Handler   PROC\n                ALIGN   4\n                EXPORT  Reset_Handler             [WEAK]\n                IMPORT  SystemInit\n\n#ifndef RAM_TARGET\n                REQUIRE FlashConfig\n#endif\n\n\n                CPSID   I               ; Mask interrupts\n\n#ifdef START_FROM_FLASH\n                ; Init ECC RAM\n                LDR     R1, =__RAM_START\n                LDR     R1, [R1]\n                LDR     R2, =__RAM_END\n                LDR     R2, [R2]\n                SUBS    R2, R1\n                SUBS    R2, #1\n                BLE LC5\n\n                MOVS    R0, #0\n                MOVS    R3, #4\nLC4\n                STR     R0, [R1]\n                ADD     R1, R1, R3\n                SUBS    R2, #4\n                BGE LC4\nLC5\n                NOP\n#endif\n\n                LDR     R0, =0xE000ED08\n                LDR     R1, =__Vectors\n                STR     R1, [R0]\n                LDR     R2, [R1]\n                MSR     MSP, R2\n                LDR     R0, =SystemInit\n                BLX     R0\n                LDR     R0, =init_data_bss\n                BLX     R0\n                CPSIE   i               ; Unmask interrupts\n                LDR     R0, =__main\n                BLX     R0\n                ENDP\n\nNMI_Handler\\\n                PROC\n                EXPORT  NMI_Handler         [WEAK]\n                B       .\n                ENDP\nHardFault_Handler\\\n                PROC\n                EXPORT  HardFault_Handler         [WEAK]\n                B       .\n                ENDP\nMemManage_Handler\\\n                PROC\n                EXPORT  MemManage_Handler         [WEAK]\n                B       .\n                ENDP\nBusFault_Handler\\\n                PROC\n                EXPORT  BusFault_Handler         [WEAK]\n                B       .\n                ENDP\nUsageFault_Handler\\\n                PROC\n                EXPORT  UsageFault_Handler         [WEAK]\n                B       .\n                ENDP\nSVC_Handler\\\n                PROC\n                EXPORT  SVC_Handler         [WEAK]\n                B       .\n                ENDP\nDebugMon_Handler\\\n                PROC\n                EXPORT  DebugMon_Handler         [WEAK]\n                B       .\n                ENDP\nPendSV_Handler\\\n                PROC\n                EXPORT  PendSV_Handler         [WEAK]\n                B       .\n                ENDP\nSysTick_Handler\\\n                PROC\n                EXPORT  SysTick_Handler         [WEAK]\n                B       .\n                ENDP\nDefaultISR\\\n                PROC\n                EXPORT  DefaultISR         [WEAK]\n                B       .\n                ENDP\nDefault_Handler PROC\n                EXPORT  DMA0_IRQHandler                      [WEAK]\n                EXPORT  DMA1_IRQHandler                      [WEAK]\n                EXPORT  DMA2_IRQHandler                      [WEAK]\n                EXPORT  DMA3_IRQHandler                      [WEAK]\n                EXPORT  DMA4_IRQHandler                      [WEAK]\n                EXPORT  DMA5_IRQHandler                      [WEAK]\n                EXPORT  DMA6_IRQHandler                      [WEAK]\n                EXPORT  DMA7_IRQHandler                      [WEAK]\n                EXPORT  DMA8_IRQHandler                      [WEAK]\n                EXPORT  DMA9_IRQHandler                      [WEAK]\n                EXPORT  DMA10_IRQHandler                     [WEAK]\n                EXPORT  DMA11_IRQHandler                     [WEAK]\n                EXPORT  DMA12_IRQHandler                     [WEAK]\n                EXPORT  DMA13_IRQHandler                     [WEAK]\n                EXPORT  DMA14_IRQHandler                     [WEAK]\n                EXPORT  DMA15_IRQHandler                     [WEAK]\n                EXPORT  DMA_Error_IRQHandler                 [WEAK]\n                EXPORT  MCM_IRQHandler                       [WEAK]\n                EXPORT  FTFC_IRQHandler                      [WEAK]\n                EXPORT  Read_Collision_IRQHandler            [WEAK]\n                EXPORT  LVD_LVW_IRQHandler                   [WEAK]\n                EXPORT  FTFC_Fault_IRQHandler                [WEAK]\n                EXPORT  WDOG_EWM_IRQHandler                  [WEAK]\n                EXPORT  RCM_IRQHandler                       [WEAK]\n                EXPORT  LPI2C0_Master_IRQHandler             [WEAK]\n                EXPORT  LPI2C0_Slave_IRQHandler              [WEAK]\n                EXPORT  LPSPI0_IRQHandler                    [WEAK]\n                EXPORT  LPSPI1_IRQHandler                    [WEAK]\n                EXPORT  LPSPI2_IRQHandler                    [WEAK]\n                EXPORT  Reserved45_IRQHandler                [WEAK]\n                EXPORT  Reserved46_IRQHandler                [WEAK]\n                EXPORT  LPUART0_RxTx_IRQHandler              [WEAK]\n                EXPORT  Reserved48_IRQHandler                [WEAK]\n                EXPORT  LPUART1_RxTx_IRQHandler              [WEAK]\n                EXPORT  Reserved50_IRQHandler                [WEAK]\n                EXPORT  LPUART2_RxTx_IRQHandler              [WEAK]\n                EXPORT  Reserved52_IRQHandler                [WEAK]\n                EXPORT  Reserved53_IRQHandler                [WEAK]\n                EXPORT  Reserved54_IRQHandler                [WEAK]\n                EXPORT  ADC0_IRQHandler                      [WEAK]\n                EXPORT  ADC1_IRQHandler                      [WEAK]\n                EXPORT  CMP0_IRQHandler                      [WEAK]\n                EXPORT  Reserved58_IRQHandler                [WEAK]\n                EXPORT  Reserved59_IRQHandler                [WEAK]\n                EXPORT  ERM_single_fault_IRQHandler          [WEAK]\n                EXPORT  ERM_double_fault_IRQHandler          [WEAK]\n                EXPORT  RTC_IRQHandler                       [WEAK]\n                EXPORT  RTC_Seconds_IRQHandler               [WEAK]\n                EXPORT  LPIT0_Ch0_IRQHandler                 [WEAK]\n                EXPORT  LPIT0_Ch1_IRQHandler                 [WEAK]\n                EXPORT  LPIT0_Ch2_IRQHandler                 [WEAK]\n                EXPORT  LPIT0_Ch3_IRQHandler                 [WEAK]\n                EXPORT  PDB0_IRQHandler                      [WEAK]\n                EXPORT  Reserved69_IRQHandler                [WEAK]\n                EXPORT  Reserved70_IRQHandler                [WEAK]\n                EXPORT  Reserved71_IRQHandler                [WEAK]\n                EXPORT  Reserved72_IRQHandler                [WEAK]\n                EXPORT  SCG_IRQHandler                       [WEAK]\n                EXPORT  LPTMR0_IRQHandler                    [WEAK]\n                EXPORT  PORTA_IRQHandler                     [WEAK]\n                EXPORT  PORTB_IRQHandler                     [WEAK]\n                EXPORT  PORTC_IRQHandler                     [WEAK]\n                EXPORT  PORTD_IRQHandler                     [WEAK]\n                EXPORT  PORTE_IRQHandler                     [WEAK]\n                EXPORT  SWI_IRQHandler                       [WEAK]\n                EXPORT  Reserved81_IRQHandler                [WEAK]\n                EXPORT  Reserved82_IRQHandler                [WEAK]\n                EXPORT  Reserved83_IRQHandler                [WEAK]\n                EXPORT  PDB1_IRQHandler                      [WEAK]\n                EXPORT  FLEXIO_IRQHandler                    [WEAK]\n                EXPORT  Reserved86_IRQHandler                [WEAK]\n                EXPORT  Reserved87_IRQHandler                [WEAK]\n                EXPORT  Reserved88_IRQHandler                [WEAK]\n                EXPORT  Reserved89_IRQHandler                [WEAK]\n                EXPORT  Reserved90_IRQHandler                [WEAK]\n                EXPORT  Reserved91_IRQHandler                [WEAK]\n                EXPORT  Reserved92_IRQHandler                [WEAK]\n                EXPORT  Reserved93_IRQHandler                [WEAK]\n                EXPORT  CAN0_ORed_IRQHandler                 [WEAK]\n                EXPORT  CAN0_Error_IRQHandler                [WEAK]\n                EXPORT  CAN0_Wake_Up_IRQHandler              [WEAK]\n                EXPORT  CAN0_ORed_0_15_MB_IRQHandler         [WEAK]\n                EXPORT  CAN0_ORed_16_31_MB_IRQHandler        [WEAK]\n                EXPORT  Reserved99_IRQHandler                [WEAK]\n                EXPORT  Reserved100_IRQHandler               [WEAK]\n                EXPORT  CAN1_ORed_IRQHandler                 [WEAK]\n                EXPORT  CAN1_Error_IRQHandler                [WEAK]\n                EXPORT  Reserved103_IRQHandler               [WEAK]\n                EXPORT  CAN1_ORed_0_15_MB_IRQHandler         [WEAK]\n                EXPORT  Reserved105_IRQHandler               [WEAK]\n                EXPORT  Reserved106_IRQHandler               [WEAK]\n                EXPORT  Reserved107_IRQHandler               [WEAK]\n                EXPORT  CAN2_ORed_IRQHandler                 [WEAK]\n                EXPORT  CAN2_Error_IRQHandler                [WEAK]\n                EXPORT  Reserved110_IRQHandler               [WEAK]\n                EXPORT  CAN2_ORed_0_15_MB_IRQHandler         [WEAK]\n                EXPORT  Reserved112_IRQHandler               [WEAK]\n                EXPORT  Reserved113_IRQHandler               [WEAK]\n                EXPORT  Reserved114_IRQHandler               [WEAK]\n                EXPORT  FTM0_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM0_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM0_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM0_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM0_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM0_Ovf_Reload_IRQHandler           [WEAK]\n                EXPORT  FTM1_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM1_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM1_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM1_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM1_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM1_Ovf_Reload_IRQHandler           [WEAK]\n                EXPORT  FTM2_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM2_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM2_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM2_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM2_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM2_Ovf_Reload_IRQHandler           [WEAK]\n                EXPORT  FTM3_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM3_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM3_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM3_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM3_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM3_Ovf_Reload_IRQHandler           [WEAK]\nDMA0_IRQHandler                                  ; DMA channel 0 transfer complete\nDMA1_IRQHandler                                  ; DMA channel 1 transfer complete\nDMA2_IRQHandler                                  ; DMA channel 2 transfer complete\nDMA3_IRQHandler                                  ; DMA channel 3 transfer complete\nDMA4_IRQHandler                                  ; DMA channel 4 transfer complete\nDMA5_IRQHandler                                  ; DMA channel 5 transfer complete\nDMA6_IRQHandler                                  ; DMA channel 6 transfer complete\nDMA7_IRQHandler                                  ; DMA channel 7 transfer complete\nDMA8_IRQHandler                                  ; DMA channel 8 transfer complete\nDMA9_IRQHandler                                  ; DMA channel 9 transfer complete\nDMA10_IRQHandler                                 ; DMA channel 10 transfer complete\nDMA11_IRQHandler                                 ; DMA channel 11 transfer complete\nDMA12_IRQHandler                                 ; DMA channel 12 transfer complete\nDMA13_IRQHandler                                 ; DMA channel 13 transfer complete\nDMA14_IRQHandler                                 ; DMA channel 14 transfer complete\nDMA15_IRQHandler                                 ; DMA channel 15 transfer complete\nDMA_Error_IRQHandler                             ; DMA error interrupt channels 0-15\nMCM_IRQHandler                                   ; FPU sources\nFTFC_IRQHandler                                  ; FTFC Command complete\nRead_Collision_IRQHandler                        ; FTFC Read collision\nLVD_LVW_IRQHandler                               ; PMC Low voltage detect interrupt\nFTFC_Fault_IRQHandler                            ; FTFC Double bit fault detect\nWDOG_EWM_IRQHandler                              ; Single interrupt vector for WDOG and EWM\nRCM_IRQHandler                                   ; RCM Asynchronous Interrupt\nLPI2C0_Master_IRQHandler                         ; LPI2C0 Master Interrupt\nLPI2C0_Slave_IRQHandler                          ; LPI2C0 Slave Interrupt\nLPSPI0_IRQHandler                                ; LPSPI0 Interrupt\nLPSPI1_IRQHandler                                ; LPSPI1 Interrupt\nLPSPI2_IRQHandler                                ; LPSPI2 Interrupt\nReserved45_IRQHandler                            ; Reserved Interrupt 45\nReserved46_IRQHandler                            ; Reserved Interrupt 46\nLPUART0_RxTx_IRQHandler                          ; LPUART0 Transmit / Receive Interrupt\nReserved48_IRQHandler                            ; Reserved Interrupt 48\nLPUART1_RxTx_IRQHandler                          ; LPUART1 Transmit / Receive  Interrupt\nReserved50_IRQHandler                            ; Reserved Interrupt 50\nLPUART2_RxTx_IRQHandler                          ; LPUART2 Transmit / Receive  Interrupt\nReserved52_IRQHandler                            ; Reserved Interrupt 52\nReserved53_IRQHandler                            ; Reserved Interrupt 53\nReserved54_IRQHandler                            ; Reserved Interrupt 54\nADC0_IRQHandler                                  ; ADC0 interrupt request.\nADC1_IRQHandler                                  ; ADC1 interrupt request.\nCMP0_IRQHandler                                  ; CMP0 interrupt request\nReserved58_IRQHandler                            ; Reserved Interrupt 58\nReserved59_IRQHandler                            ; Reserved Interrupt 59\nERM_single_fault_IRQHandler                      ; ERM single bit error correction\nERM_double_fault_IRQHandler                      ; ERM double bit error non-correctable\nRTC_IRQHandler                                   ; RTC alarm interrupt\nRTC_Seconds_IRQHandler                           ; RTC seconds interrupt\nLPIT0_Ch0_IRQHandler                             ; LPIT0 channel 0 overflow interrupt\nLPIT0_Ch1_IRQHandler                             ; LPIT0 channel 1 overflow interrupt\nLPIT0_Ch2_IRQHandler                             ; LPIT0 channel 2 overflow interrupt\nLPIT0_Ch3_IRQHandler                             ; LPIT0 channel 3 overflow interrupt\nPDB0_IRQHandler                                  ; PDB0 interrupt\nReserved69_IRQHandler                            ; Reserved Interrupt 69\nReserved70_IRQHandler                            ; Reserved Interrupt 70\nReserved71_IRQHandler                            ; Reserved Interrupt 71\nReserved72_IRQHandler                            ; Reserved Interrupt 72\nSCG_IRQHandler                                   ; SCG bus interrupt request\nLPTMR0_IRQHandler                                ; LPTIMER interrupt request\nPORTA_IRQHandler                                 ; Port A pin detect interrupt\nPORTB_IRQHandler                                 ; Port B pin detect interrupt\nPORTC_IRQHandler                                 ; Port C pin detect interrupt\nPORTD_IRQHandler                                 ; Port D pin detect interrupt\nPORTE_IRQHandler                                 ; Port E pin detect interrupt\nSWI_IRQHandler                                   ; Software interrupt\nReserved81_IRQHandler                            ; Reserved Interrupt 81\nReserved82_IRQHandler                            ; Reserved Interrupt 82\nReserved83_IRQHandler                            ; Reserved Interrupt 83\nPDB1_IRQHandler                                  ; PDB1 interrupt\nFLEXIO_IRQHandler                                ; FlexIO Interrupt\nReserved86_IRQHandler                            ; Reserved Interrupt 86\nReserved87_IRQHandler                            ; Reserved Interrupt 87\nReserved88_IRQHandler                            ; Reserved Interrupt 88\nReserved89_IRQHandler                            ; Reserved Interrupt 89\nReserved90_IRQHandler                            ; Reserved Interrupt 90\nReserved91_IRQHandler                            ; Reserved Interrupt 91\nReserved92_IRQHandler                            ; Reserved Interrupt 92\nReserved93_IRQHandler                            ; Reserved Interrupt 93\nCAN0_ORed_IRQHandler                             ; CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\nCAN0_Error_IRQHandler                            ; CAN0 Interrupt indicating that errors were detected on the CAN bus\nCAN0_Wake_Up_IRQHandler                          ; CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode\nCAN0_ORed_0_15_MB_IRQHandler                     ; CAN0 OR'ed Message buffer (0-15)\nCAN0_ORed_16_31_MB_IRQHandler                    ; CAN0 OR'ed Message buffer (16-31)\nReserved99_IRQHandler                            ; Reserved Interrupt 99\nReserved100_IRQHandler                           ; Reserved Interrupt 100\nCAN1_ORed_IRQHandler                             ; CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\nCAN1_Error_IRQHandler                            ; CAN1 Interrupt indicating that errors were detected on the CAN bus\nReserved103_IRQHandler                           ; Reserved Interrupt 103\nCAN1_ORed_0_15_MB_IRQHandler                     ; CAN1 OR'ed Interrupt for Message buffer (0-15)\nReserved105_IRQHandler                           ; Reserved Interrupt 105\nReserved106_IRQHandler                           ; Reserved Interrupt 106\nReserved107_IRQHandler                           ; Reserved Interrupt 107\nCAN2_ORed_IRQHandler                             ; CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\nCAN2_Error_IRQHandler                            ; CAN2 Interrupt indicating that errors were detected on the CAN bus\nReserved110_IRQHandler                           ; Reserved Interrupt 110\nCAN2_ORed_0_15_MB_IRQHandler                     ; CAN2 OR'ed Message buffer (0-15)\nReserved112_IRQHandler                           ; Reserved Interrupt 112\nReserved113_IRQHandler                           ; Reserved Interrupt 113\nReserved114_IRQHandler                           ; Reserved Interrupt 114\nFTM0_Ch0_Ch1_IRQHandler                          ; FTM0 Channel 0 and 1 interrupt\nFTM0_Ch2_Ch3_IRQHandler                          ; FTM0 Channel 2 and 3 interrupt\nFTM0_Ch4_Ch5_IRQHandler                          ; FTM0 Channel 4 and 5 interrupt\nFTM0_Ch6_Ch7_IRQHandler                          ; FTM0 Channel 6 and 7 interrupt\nFTM0_Fault_IRQHandler                            ; FTM0 Fault interrupt\nFTM0_Ovf_Reload_IRQHandler                       ; FTM0 Counter overflow and Reload interrupt\nFTM1_Ch0_Ch1_IRQHandler                          ; FTM1 Channel 0 and 1 interrupt\nFTM1_Ch2_Ch3_IRQHandler                          ; FTM1 Channel 2 and 3 interrupt\nFTM1_Ch4_Ch5_IRQHandler                          ; FTM1 Channel 4 and 5 interrupt\nFTM1_Ch6_Ch7_IRQHandler                          ; FTM1 Channel 6 and 7 interrupt\nFTM1_Fault_IRQHandler                            ; FTM1 Fault interrupt\nFTM1_Ovf_Reload_IRQHandler                       ; FTM1 Counter overflow and Reload interrupt\nFTM2_Ch0_Ch1_IRQHandler                          ; FTM2 Channel 0 and 1 interrupt\nFTM2_Ch2_Ch3_IRQHandler                          ; FTM2 Channel 2 and 3 interrupt\nFTM2_Ch4_Ch5_IRQHandler                          ; FTM2 Channel 4 and 5 interrupt\nFTM2_Ch6_Ch7_IRQHandler                          ; FTM2 Channel 6 and 7 interrupt\nFTM2_Fault_IRQHandler                            ; FTM2 Fault interrupt\nFTM2_Ovf_Reload_IRQHandler                       ; FTM2 Counter overflow and Reload interrupt\nFTM3_Ch0_Ch1_IRQHandler                          ; FTM3 Channel 0 and 1 interrupt\nFTM3_Ch2_Ch3_IRQHandler                          ; FTM3 Channel 2 and 3 interrupt\nFTM3_Ch4_Ch5_IRQHandler                          ; FTM3 Channel 4 and 5 interrupt\nFTM3_Ch6_Ch7_IRQHandler                          ; FTM3 Channel 6 and 7 interrupt\nFTM3_Fault_IRQHandler                            ; FTM3 Fault interrupt\nFTM3_Ovf_Reload_IRQHandler                       ; FTM3 Counter overflow and Reload interrupt\n\n                B       .\n\n                ENDP\n\n                ALIGN\n                END\n",
                  "start_line": 1,
                  "end_line": 781,
                  "line_count": 781
                }
              ]
            }
          },
          "params": {
            "pathes": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S\n"
          },
          "parentMessageId": ""
        },
        {
          "id": "d424d1da-dec9-4bf6-b305-eecf8ba25a2d",
          "type": "TEXT",
          "status": "success",
          "content": "我已经检查了错误信息和启动文件内容。问题出在 [`startup_S32K144.S`](RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S) 文件的第123行附近，编译器无法识别 `__flash_vector_table__` 这个操作码。\n\n在查看文件内容后，我发现问题可能与条件编译有关。在文件中的第122-126行附近有一个条件指令：\n\n```\n#ifndef __flash_vector_table__\n__RAM_START DCD |Image$$VECTOR_RAM$$Base|\n#else\n__RAM_START DCD |Image$$RW_m_data$$Base|\n#endif\n```\n\n错误出现在这里，因为编译器不认识 `__flash_vector_table__` 这个宏定义。这个宏应该是用来决定向量表放在RAM还是Flash中的条件标志。\n\n让我查看一下项目中其他可能定义这个宏的文件：\n\n",
          "composer": {
            "markdown": "",
            "tasks": []
          },
          "isErrorMessage": false,
          "parentMessageId": ""
        },
        {
          "id": "5646a5b1-d919-4413-b07d-c8d0a4f5c3b5",
          "type": "TOOL_CALL",
          "status": "success",
          "toolName": "search_files",
          "composer": {
            "markdown": "",
            "tasks": []
          },
          "workflowStatus": "success",
          "displayParams": {
            "path": "d:/Keil/ARM/Packs/Keil/S32_SDK_DFP/1.5.1/CMSIS/Flash/CVD_S32",
            "regex": "__flash_vector_table__"
          },
          "displayResult": {
            "searchFiles": []
          },
          "workflowSnapshot": {
            "searchFiles": [],
            "status": "success",
            "result": {
              "name": "search_files",
              "type": "tool_use",
              "params": {
                "regex": "__flash_vector_table__",
                "file_pattern": "**/*.h"
              },
              "success": true,
              "message": "",
              "code": 0,
              "result": []
            }
          },
          "params": {
            "regex": "__flash_vector_table__",
            "file_pattern": "**/*.h"
          },
          "parentMessageId": ""
        },
        {
          "id": "808cfcdc-2a8d-4656-bd87-cee34ab9a6ac",
          "type": "TEXT",
          "status": "success",
          "content": "我看到在头文件中没有找到 `__flash_vector_table__` 这个宏定义。让我们查看一下项目中的其他文件，特别是可能包含编译配置的文件：\n\n",
          "composer": {
            "markdown": "",
            "tasks": []
          },
          "isErrorMessage": false,
          "parentMessageId": ""
        },
        {
          "id": "6bee33eb-f9f0-406d-89c8-212e37da35f0",
          "type": "TOOL_CALL",
          "status": "success",
          "toolName": "search_files",
          "composer": {
            "markdown": "",
            "tasks": []
          },
          "workflowStatus": "success",
          "displayParams": {
            "path": "d:/Keil/ARM/Packs/Keil/S32_SDK_DFP/1.5.1/CMSIS/Flash/CVD_S32",
            "regex": "flash_vector_table|FLASH_VECTOR_TABLE"
          },
          "displayResult": {
            "searchFiles": [
              {
                "path": "S32K.uvprojx",
                "startLine": 755,
                "endLine": 757
              },
              {
                "path": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S",
                "startLine": 122,
                "endLine": 124
              },
              {
                "path": "RTE\\Device\\S32K144HFxxxLLx\\S32K144_64_flash.sct",
                "startLine": 4,
                "endLine": 7
              },
              {
                "path": "RTE\\Device\\S32K144HFxxxLLx\\S32K144_64_flash.sct",
                "startLine": 34,
                "endLine": 36
              },
              {
                "path": "RTE\\Device\\S32K144HFxxxLLx\\S32K144_64_flash.sct",
                "startLine": 76,
                "endLine": 78
              },
              {
                "path": "platform\\devices\\common\\startup_S32K144.S",
                "startLine": 122,
                "endLine": 124
              },
              {
                "path": "Output\\S32K144_P512_4KB_SEC.build_log.htm",
                "startLine": 30,
                "endLine": 32
              },
              {
                "path": "Output\\S32K_S32K144_P512_4KB_SEC.dep",
                "startLine": 2,
                "endLine": 4
              },
              {
                "path": "Output\\S32K_S32K144_P512_4KB_SEC.dep",
                "startLine": 17,
                "endLine": 19
              },
              {
                "path": "Output\\S32K_S32K144_P512_4KB_SEC.dep",
                "startLine": 31,
                "endLine": 33
              }
            ]
          },
          "workflowSnapshot": {
            "searchFiles": [
              {
                "match": "              <MiscControls>--c99</MiscControls>\n              <Define>S32K144 __flash_vector_table__</Define>\n              <Undefine></Undefine>\n",
                "start_line": 755,
                "end_line": 757,
                "path": "S32K.uvprojx"
              },
              {
                "match": "\n#ifndef __flash_vector_table__\n__RAM_START DCD |Image$$VECTOR_RAM$$Base|\n",
                "start_line": 122,
                "end_line": 124,
                "path": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S"
              },
              {
                "match": " *\n * If __flash_vector_table__ is defined then interrupt vector table is not copied to RAM.\n * If __flash_vector_table__ is defined at link time then it must also be defined for \n * assembling startup_14*.s\n",
                "start_line": 4,
                "end_line": 7,
                "path": "RTE\\Device\\S32K144HFxxxLLx\\S32K144_64_flash.sct"
              },
              {
                "match": "\n#if (defined(__flash_vector_table__))\n  #define __ram_vector_table_size__    0x00000000\n",
                "start_line": 34,
                "end_line": 36,
                "path": "RTE\\Device\\S32K144HFxxxLLx\\S32K144_64_flash.sct"
              },
              {
                "match": "\n#if (defined(__flash_vector_table__))\n  VECTOR_RAM m_interrupts_start EMPTY 0 {\n",
                "start_line": 76,
                "end_line": 78,
                "path": "RTE\\Device\\S32K144HFxxxLLx\\S32K144_64_flash.sct"
              },
              {
                "match": "\n#ifndef __flash_vector_table__\n__RAM_START DCD |Image$$VECTOR_RAM$$Base|\n",
                "start_line": 122,
                "end_line": 124,
                "path": "platform\\devices\\common\\startup_S32K144.S"
              },
              {
                "match": "assembling startup_S32K144.S...\r\nRTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S(123): error: A1163E: Unknown opcode __flash_vector_table__ , expecting opcode or Macro\r\nRTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S(125): error: A1167E: Invalid line start \r\n",
                "start_line": 30,
                "end_line": 32,
                "path": "Output\\S32K144_P512_4KB_SEC.build_log.htm"
              },
              {
                "match": "CompilerVersion: 6190000::V6.19::ARMCLANG\r\nF (.\\FlashPrg.c)(0x65D4247A)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c\r\r-fno-rtti -funsigned-char -fshort-enums -fshort-wchar\r\r-gdwarf-4 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ./ -I ./platform/devices -I ./platform/devices/common -I ./platform/drivers/inc -I ../../../../../../../ARM_Compiler_5.06u7/include --c99\r\r-ID:/Keil/ARM/Packs/Keil/S32_SDK_DFP/1.5.1/platform/devices\r\r-Id:/Keil/ARM/CMSIS/Include\r\r-D__UVISION_VERSION=\"538\" -DCPU_S32K144HFT0VLLT -DS32K144 -D__flash_vector_table__\r\r-o ./output/flashprg.o -MD)\r\nI (d:\\Program)(0x00000000)\r\n",
                "start_line": 2,
                "end_line": 4,
                "path": "Output\\S32K_S32K144_P512_4KB_SEC.dep"
              },
              {
                "match": "I (.\\platform\\devices\\common\\s32_core_cm4.h)(0x65D4247A)\r\nF (.\\platform\\drivers\\src\\flash\\flash_driver.c)(0x65D4247A)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c\r\r-fno-rtti -funsigned-char -fshort-enums -fshort-wchar\r\r-gdwarf-4 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ./ -I ./platform/devices -I ./platform/devices/common -I ./platform/drivers/inc -I ../../../../../../../ARM_Compiler_5.06u7/include --c99\r\r-ID:/Keil/ARM/Packs/Keil/S32_SDK_DFP/1.5.1/platform/devices\r\r-Id:/Keil/ARM/CMSIS/Include\r\r-D__UVISION_VERSION=\"538\" -DCPU_S32K144HFT0VLLT -DS32K144 -D__flash_vector_table__\r\r-o ./output/flash_driver.o -MD)\r\nI (.\\platform\\drivers\\inc\\flash_driver.h)(0x693D72E7)\r\n",
                "start_line": 17,
                "end_line": 19,
                "path": "Output\\S32K_S32K144_P512_4KB_SEC.dep"
              },
              {
                "match": "I (.\\platform\\devices\\common\\s32_core_cm4.h)(0x65D4247A)\r\nF (.\\RTE\\Device\\S32K144HFxxxLLx\\system_S32K144.c)(0x6934DFB7)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c\r\r-fno-rtti -funsigned-char -fshort-enums -fshort-wchar\r\r-gdwarf-4 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ./ -I ./platform/devices -I ./platform/devices/common -I ./platform/drivers/inc -I ../../../../../../../ARM_Compiler_5.06u7/include --c99\r\r-ID:/Keil/ARM/Packs/Keil/S32_SDK_DFP/1.5.1/platform/devices\r\r-Id:/Keil/ARM/CMSIS/Include\r\r-D__UVISION_VERSION=\"538\" -DCPU_S32K144HFT0VLLT -DS32K144 -D__flash_vector_table__\r\r-o ./output/system_s32k144.o -MD)\r\nI (.\\platform\\devices\\device_registers.h)(0x65D4247A)\r\n",
                "start_line": 31,
                "end_line": 33,
                "path": "Output\\S32K_S32K144_P512_4KB_SEC.dep"
              }
            ],
            "status": "success",
            "result": {
              "name": "search_files",
              "type": "tool_use",
              "params": {
                "regex": "flash_vector_table|FLASH_VECTOR_TABLE",
                "file_pattern": "**/*.*"
              },
              "success": true,
              "message": "",
              "code": 0,
              "result": [
                {
                  "match": "              <MiscControls>--c99</MiscControls>\n              <Define>S32K144 __flash_vector_table__</Define>\n              <Undefine></Undefine>\n",
                  "start_line": 755,
                  "end_line": 757,
                  "path": "S32K.uvprojx"
                },
                {
                  "match": "\n#ifndef __flash_vector_table__\n__RAM_START DCD |Image$$VECTOR_RAM$$Base|\n",
                  "start_line": 122,
                  "end_line": 124,
                  "path": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S"
                },
                {
                  "match": " *\n * If __flash_vector_table__ is defined then interrupt vector table is not copied to RAM.\n * If __flash_vector_table__ is defined at link time then it must also be defined for \n * assembling startup_14*.s\n",
                  "start_line": 4,
                  "end_line": 7,
                  "path": "RTE\\Device\\S32K144HFxxxLLx\\S32K144_64_flash.sct"
                },
                {
                  "match": "\n#if (defined(__flash_vector_table__))\n  #define __ram_vector_table_size__    0x00000000\n",
                  "start_line": 34,
                  "end_line": 36,
                  "path": "RTE\\Device\\S32K144HFxxxLLx\\S32K144_64_flash.sct"
                },
                {
                  "match": "\n#if (defined(__flash_vector_table__))\n  VECTOR_RAM m_interrupts_start EMPTY 0 {\n",
                  "start_line": 76,
                  "end_line": 78,
                  "path": "RTE\\Device\\S32K144HFxxxLLx\\S32K144_64_flash.sct"
                },
                {
                  "match": "\n#ifndef __flash_vector_table__\n__RAM_START DCD |Image$$VECTOR_RAM$$Base|\n",
                  "start_line": 122,
                  "end_line": 124,
                  "path": "platform\\devices\\common\\startup_S32K144.S"
                },
                {
                  "match": "assembling startup_S32K144.S...\r\nRTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S(123): error: A1163E: Unknown opcode __flash_vector_table__ , expecting opcode or Macro\r\nRTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S(125): error: A1167E: Invalid line start \r\n",
                  "start_line": 30,
                  "end_line": 32,
                  "path": "Output\\S32K144_P512_4KB_SEC.build_log.htm"
                },
                {
                  "match": "CompilerVersion: 6190000::V6.19::ARMCLANG\r\nF (.\\FlashPrg.c)(0x65D4247A)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c\r\r-fno-rtti -funsigned-char -fshort-enums -fshort-wchar\r\r-gdwarf-4 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ./ -I ./platform/devices -I ./platform/devices/common -I ./platform/drivers/inc -I ../../../../../../../ARM_Compiler_5.06u7/include --c99\r\r-ID:/Keil/ARM/Packs/Keil/S32_SDK_DFP/1.5.1/platform/devices\r\r-Id:/Keil/ARM/CMSIS/Include\r\r-D__UVISION_VERSION=\"538\" -DCPU_S32K144HFT0VLLT -DS32K144 -D__flash_vector_table__\r\r-o ./output/flashprg.o -MD)\r\nI (d:\\Program)(0x00000000)\r\n",
                  "start_line": 2,
                  "end_line": 4,
                  "path": "Output\\S32K_S32K144_P512_4KB_SEC.dep"
                },
                {
                  "match": "I (.\\platform\\devices\\common\\s32_core_cm4.h)(0x65D4247A)\r\nF (.\\platform\\drivers\\src\\flash\\flash_driver.c)(0x65D4247A)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c\r\r-fno-rtti -funsigned-char -fshort-enums -fshort-wchar\r\r-gdwarf-4 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ./ -I ./platform/devices -I ./platform/devices/common -I ./platform/drivers/inc -I ../../../../../../../ARM_Compiler_5.06u7/include --c99\r\r-ID:/Keil/ARM/Packs/Keil/S32_SDK_DFP/1.5.1/platform/devices\r\r-Id:/Keil/ARM/CMSIS/Include\r\r-D__UVISION_VERSION=\"538\" -DCPU_S32K144HFT0VLLT -DS32K144 -D__flash_vector_table__\r\r-o ./output/flash_driver.o -MD)\r\nI (.\\platform\\drivers\\inc\\flash_driver.h)(0x693D72E7)\r\n",
                  "start_line": 17,
                  "end_line": 19,
                  "path": "Output\\S32K_S32K144_P512_4KB_SEC.dep"
                },
                {
                  "match": "I (.\\platform\\devices\\common\\s32_core_cm4.h)(0x65D4247A)\r\nF (.\\RTE\\Device\\S32K144HFxxxLLx\\system_S32K144.c)(0x6934DFB7)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c\r\r-fno-rtti -funsigned-char -fshort-enums -fshort-wchar\r\r-gdwarf-4 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ./ -I ./platform/devices -I ./platform/devices/common -I ./platform/drivers/inc -I ../../../../../../../ARM_Compiler_5.06u7/include --c99\r\r-ID:/Keil/ARM/Packs/Keil/S32_SDK_DFP/1.5.1/platform/devices\r\r-Id:/Keil/ARM/CMSIS/Include\r\r-D__UVISION_VERSION=\"538\" -DCPU_S32K144HFT0VLLT -DS32K144 -D__flash_vector_table__\r\r-o ./output/system_s32k144.o -MD)\r\nI (.\\platform\\devices\\device_registers.h)(0x65D4247A)\r\n",
                  "start_line": 31,
                  "end_line": 33,
                  "path": "Output\\S32K_S32K144_P512_4KB_SEC.dep"
                }
              ]
            }
          },
          "params": {
            "regex": "flash_vector_table|FLASH_VECTOR_TABLE",
            "file_pattern": "**/*.*"
          },
          "parentMessageId": ""
        },
        {
          "id": "2b021618-b9ba-405b-b794-644f4e00da2d",
          "type": "TEXT",
          "status": "success",
          "content": "现在我已经找到了问题所在。通过搜索结果，我发现 `__flash_vector_table__` 这个宏确实被定义在项目中，但是在汇编文件中使用时出现了问题。\n\n我注意到几个重要线索：\n\n1. 在项目文件 [`S32K.uvprojx`](S32K.uvprojx) 中，`__flash_vector_table__` 被定义为编译选项\n2. 在多个 C 文件的编译命令中，也包含了 `-D__flash_vector_table__` 参数\n3. 错误出现在汇编文件 `startup_S32K144.S` 中，编译器无法识别这个宏\n\n问题的原因是：在 ARM 汇编中，条件编译的宏定义方式与 C 语言不同。汇编文件中需要使用不同的方式定义或传递宏。\n\n我们可以通过以下方法解决这个问题：\n\n",
          "composer": {
            "markdown": "",
            "tasks": []
          },
          "isErrorMessage": false,
          "parentMessageId": ""
        },
        {
          "id": "a5160725-a6fd-4c1b-89bf-38022b778807",
          "type": "TOOL_CALL",
          "status": "success",
          "toolName": "patch_file",
          "composer": {
            "markdown": "",
            "tasks": [
              {
                "action": "edit",
                "accepted": 1,
                "status": "success",
                "filePath": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S",
                "absolutePath": "d:\\Keil\\ARM\\Packs\\Keil\\S32_SDK_DFP\\1.5.1\\CMSIS\\Flash\\CVD_S32\\RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S",
                "basename": "startup_S32K144.S",
                "originalContent": ";\n; modified by ARM\n;\n; ---------------------------------------------------------------------------------------\n;  @file:    startup_S32K144.S\n;  @purpose: ARM Compiler Collection Startup File\n;            S32K144\n;  @version: 2.2.0\n;  @date:    2017-1-10\n;  @build:   b170107\n; ---------------------------------------------------------------------------------------\n;\n; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc.\n; Copyright 2016-2017 NXP\n; All rights reserved.\n;\n; NXP Confidential. This software is owned or controlled by NXP and may only be\n; used strictly in accordance with the applicable license terms. By expressly\n; accepting such terms or by downloading, installing, activating and/or otherwise\n; using the software, you are agreeing that you have read, and that you agree to\n; comply with and are bound by, such license terms. If you do not agree to be\n; bound by the applicable license terms, then you may not retain, install,\n; activate or otherwise use the software. The production use license in\n; Section 2.3 is expressly granted for this software.\n;***************************************************************************\n; Version: ARMC Compiler Collection\n;***************************************************************************\n\n;// ------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n\n\n                PRESERVE8\n                THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n                AREA    |.text|, CODE, READONLY\n                EXPORT  __Vectors\n\n                EXPORT __RAM_VECTOR_TABLE_SIZE\n                EXPORT __VECTOR_RAM\n                EXPORT __VECTOR_ROM\n\n                EXPORT __BSS_START\n                EXPORT __BSS_END\n\n                EXPORT __CODE_ROM\n                EXPORT __CODE_END\n                EXPORT __CODE_RAM\n\n                EXPORT __DATA_ROM\n                EXPORT __DATA_END\n                EXPORT __DATA_RAM\n                EXPORT __VECTOR_ROM_START\n                EXPORT __VECTOR_ROM_END\n                EXPORT __DATA_RAM_START\n                EXPORT __DATA_RAM_END\n                EXPORT __CUSTOM_SECTION_START\n                EXPORT __CUSTOM_SECTION_END\n                EXPORT __CODE_RAM_START\n                EXPORT __CODE_RAM_END\n\n                EXPORT __RAM_START\n                EXPORT __RAM_END\n\n                IMPORT init_data_bss\n                IMPORT  main\n                IMPORT  __main\n                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|\n                IMPORT  |Image$$RW_m_data_2$$ZI$$Base|\n                IMPORT  |Image$$RW_m_data_2$$ZI$$Limit|\n\n                IMPORT  |Image$$ER_m_text_const$$Base|\n                IMPORT  |Image$$ER_m_text_const$$Limit|\n\n                IMPORT  |Image$$RW_m_data$$Base|\n\n                IMPORT  |Image$$ER_m_text_const$$Base|\n                IMPORT  |Image$$ER_m_text_const$$Limit|\n\n                IMPORT  |Image$$RW_m_data$$Length|\n                IMPORT |Image$$RW_m_code$$Base|\n                IMPORT |Image$$RW_m_code$$Length|\n                IMPORT |Image$$ER_m_text$$Limit|\n\n                IMPORT |Image$$VECTOR_RAM$$Length|\n                IMPORT |Image$$VECTOR_RAM$$Base|\n\n                IMPORT |Image$$VECTOR_ROM$$Length|\n                IMPORT |Image$$VECTOR_ROM$$Base|\n                IMPORT |Image$$RW_m_custom_section$$Base|\n                IMPORT |Image$$RW_m_custom_section$$Limit|\n\n                IMPORT |Image$$RW_m_data$$Limit|\n                IMPORT |Image$$RW_m_code$$Limit|\n                IMPORT |Image$$VECTOR_ROM$$Limit|\n\n                IMPORT |Image$$ARM_LIB_STACK$$Limit|\n__RAM_VECTOR_TABLE_SIZE DCD |Image$$VECTOR_ROM$$Length|\n__VECTOR_RAM DCD |Image$$VECTOR_RAM$$Base|\n__VECTOR_ROM DCD |Image$$VECTOR_ROM$$Base|\n__VECTOR_ROM_START DCD |Image$$VECTOR_ROM$$Base|\n__VECTOR_ROM_END DCD |Image$$VECTOR_ROM$$Limit|\n\n__CODE_ROM DCD  |Image$$RW_m_data$$Length|+ |Image$$ER_m_text$$Limit|\n__CODE_END DCD  |Image$$RW_m_data$$Length|+ |Image$$ER_m_text$$Limit| + |Image$$RW_m_code$$Length|\n__CODE_RAM DCD |Image$$RW_m_code$$Base|\n__CODE_RAM_START DCD |Image$$RW_m_code$$Base|\n__CODE_RAM_END DCD |Image$$RW_m_code$$Limit|\n\n__BSS_START DCD  |Image$$RW_m_data_2$$ZI$$Base|\n__BSS_END DCD  |Image$$RW_m_data_2$$ZI$$Limit|\n\n__DATA_RAM DCD  |Image$$RW_m_data$$Base|\n__DATA_RAM_START DCD  |Image$$RW_m_data$$Base|\n__DATA_RAM_END DCD  |Image$$RW_m_data$$Limit|\n__DATA_ROM DCD  |Image$$ER_m_text$$Limit|\n__DATA_END DCD  |Image$$RW_m_data$$Length|+ |Image$$ER_m_text$$Limit|\n__CUSTOM_SECTION_START DCD |Image$$RW_m_custom_section$$Base|\n__CUSTOM_SECTION_END DCD |Image$$RW_m_custom_section$$Limit|\n\n#ifndef __flash_vector_table__\n__RAM_START DCD |Image$$VECTOR_RAM$$Base|\n#else\n__RAM_START DCD |Image$$RW_m_data$$Base|\n#endif\n__RAM_END   DCD |Image$$ARM_LIB_STACK$$Limit|\n\n\t\tAREA    RESET, DATA, READONLY\n__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit|   ; Top of Stack\n                DCD     Reset_Handler                       ; Reset Handler\n                DCD     NMI_Handler                         ; NMI Handler\n                DCD     HardFault_Handler                   ; Hard Fault Handler\n                DCD     MemManage_Handler                   ; MPU Fault Handler\n                DCD     BusFault_Handler                    ; Bus Fault Handler\n                DCD     UsageFault_Handler                  ; Usage Fault Handler\n                DCD     0                                   ; Reserved\n                DCD     0                                   ; Reserved\n                DCD     0                                   ; Reserved\n                DCD     0                                   ; Reserved\n                DCD     SVC_Handler                         ; SVCall Handler\n                DCD     DebugMon_Handler                    ; Debug Monitor Handler\n                DCD     0                                   ; Reserved\n                DCD     PendSV_Handler                      ; PendSV Handler\n                DCD     SysTick_Handler                     ; SysTick Handler\n\n                                                            ; External Interrupts\n    DCD   DMA0_IRQHandler                                 ; DMA channel 0 transfer complete\n    DCD   DMA1_IRQHandler                                 ; DMA channel 1 transfer complete\n    DCD   DMA2_IRQHandler                                 ; DMA channel 2 transfer complete\n    DCD   DMA3_IRQHandler                                 ; DMA channel 3 transfer complete\n    DCD   DMA4_IRQHandler                                 ; DMA channel 4 transfer complete\n    DCD   DMA5_IRQHandler                                 ; DMA channel 5 transfer complete\n    DCD   DMA6_IRQHandler                                 ; DMA channel 6 transfer complete\n    DCD   DMA7_IRQHandler                                 ; DMA channel 7 transfer complete\n    DCD   DMA8_IRQHandler                                 ; DMA channel 8 transfer complete\n    DCD   DMA9_IRQHandler                                 ; DMA channel 9 transfer complete\n    DCD   DMA10_IRQHandler                                ; DMA channel 10 transfer complete\n    DCD   DMA11_IRQHandler                                ; DMA channel 11 transfer complete\n    DCD   DMA12_IRQHandler                                ; DMA channel 12 transfer complete\n    DCD   DMA13_IRQHandler                                ; DMA channel 13 transfer complete\n    DCD   DMA14_IRQHandler                                ; DMA channel 14 transfer complete\n    DCD   DMA15_IRQHandler                                ; DMA channel 15 transfer complete\n    DCD   DMA_Error_IRQHandler                            ; DMA error interrupt channels 0-15\n    DCD   MCM_IRQHandler                                  ; FPU sources\n    DCD   FTFC_IRQHandler                                 ; FTFC Command complete\n    DCD   Read_Collision_IRQHandler                       ; FTFC Read collision\n    DCD   LVD_LVW_IRQHandler                              ; PMC Low voltage detect interrupt\n    DCD   FTFC_Fault_IRQHandler                           ; FTFC Double bit fault detect\n    DCD   WDOG_EWM_IRQHandler                             ; Single interrupt vector for WDOG and EWM\n    DCD   RCM_IRQHandler                                  ; RCM Asynchronous Interrupt\n    DCD   LPI2C0_Master_IRQHandler                        ; LPI2C0 Master Interrupt\n    DCD   LPI2C0_Slave_IRQHandler                         ; LPI2C0 Slave Interrupt\n    DCD   LPSPI0_IRQHandler                               ; LPSPI0 Interrupt\n    DCD   LPSPI1_IRQHandler                               ; LPSPI1 Interrupt\n    DCD   LPSPI2_IRQHandler                               ; LPSPI2 Interrupt\n    DCD   Reserved45_IRQHandler                           ; Reserved Interrupt 45\n    DCD   Reserved46_IRQHandler                           ; Reserved Interrupt 46\n    DCD   LPUART0_RxTx_IRQHandler                         ; LPUART0 Transmit / Receive Interrupt\n    DCD   Reserved48_IRQHandler                           ; Reserved Interrupt 48\n    DCD   LPUART1_RxTx_IRQHandler                         ; LPUART1 Transmit / Receive  Interrupt\n    DCD   Reserved50_IRQHandler                           ; Reserved Interrupt 50\n    DCD   LPUART2_RxTx_IRQHandler                         ; LPUART2 Transmit / Receive  Interrupt\n    DCD   Reserved52_IRQHandler                           ; Reserved Interrupt 52\n    DCD   Reserved53_IRQHandler                           ; Reserved Interrupt 53\n    DCD   Reserved54_IRQHandler                           ; Reserved Interrupt 54\n    DCD   ADC0_IRQHandler                                 ; ADC0 interrupt request.\n    DCD   ADC1_IRQHandler                                 ; ADC1 interrupt request.\n    DCD   CMP0_IRQHandler                                 ; CMP0 interrupt request\n    DCD   Reserved58_IRQHandler                           ; Reserved Interrupt 58\n    DCD   Reserved59_IRQHandler                           ; Reserved Interrupt 59\n    DCD   ERM_single_fault_IRQHandler                     ; ERM single bit error correction\n    DCD   ERM_double_fault_IRQHandler                     ; ERM double bit error non-correctable\n    DCD   RTC_IRQHandler                                  ; RTC alarm interrupt\n    DCD   RTC_Seconds_IRQHandler                          ; RTC seconds interrupt\n    DCD   LPIT0_Ch0_IRQHandler                            ; LPIT0 channel 0 overflow interrupt\n    DCD   LPIT0_Ch1_IRQHandler                            ; LPIT0 channel 1 overflow interrupt\n    DCD   LPIT0_Ch2_IRQHandler                            ; LPIT0 channel 2 overflow interrupt\n    DCD   LPIT0_Ch3_IRQHandler                            ; LPIT0 channel 3 overflow interrupt\n    DCD   PDB0_IRQHandler                                 ; PDB0 interrupt\n    DCD   Reserved69_IRQHandler                           ; Reserved Interrupt 69\n    DCD   Reserved70_IRQHandler                           ; Reserved Interrupt 70\n    DCD   Reserved71_IRQHandler                           ; Reserved Interrupt 71\n    DCD   Reserved72_IRQHandler                           ; Reserved Interrupt 72\n    DCD   SCG_IRQHandler                                  ; SCG bus interrupt request\n    DCD   LPTMR0_IRQHandler                               ; LPTIMER interrupt request\n    DCD   PORTA_IRQHandler                                ; Port A pin detect interrupt\n    DCD   PORTB_IRQHandler                                ; Port B pin detect interrupt\n    DCD   PORTC_IRQHandler                                ; Port C pin detect interrupt\n    DCD   PORTD_IRQHandler                                ; Port D pin detect interrupt\n    DCD   PORTE_IRQHandler                                ; Port E pin detect interrupt\n    DCD   SWI_IRQHandler                                  ; Software interrupt\n    DCD   Reserved81_IRQHandler                           ; Reserved Interrupt 81\n    DCD   Reserved82_IRQHandler                           ; Reserved Interrupt 82\n    DCD   Reserved83_IRQHandler                           ; Reserved Interrupt 83\n    DCD   PDB1_IRQHandler                                 ; PDB1 interrupt\n    DCD   FLEXIO_IRQHandler                               ; FlexIO Interrupt\n    DCD   Reserved86_IRQHandler                           ; Reserved Interrupt 86\n    DCD   Reserved87_IRQHandler                           ; Reserved Interrupt 87\n    DCD   Reserved88_IRQHandler                           ; Reserved Interrupt 88\n    DCD   Reserved89_IRQHandler                           ; Reserved Interrupt 89\n    DCD   Reserved90_IRQHandler                           ; Reserved Interrupt 90\n    DCD   Reserved91_IRQHandler                           ; Reserved Interrupt 91\n    DCD   Reserved92_IRQHandler                           ; Reserved Interrupt 92\n    DCD   Reserved93_IRQHandler                           ; Reserved Interrupt 93\n    DCD   CAN0_ORed_IRQHandler                            ; CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\n    DCD   CAN0_Error_IRQHandler                           ; CAN0 Interrupt indicating that errors were detected on the CAN bus\n    DCD   CAN0_Wake_Up_IRQHandler                         ; CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode\n    DCD   CAN0_ORed_0_15_MB_IRQHandler                    ; CAN0 OR'ed Message buffer (0-15)\n    DCD   CAN0_ORed_16_31_MB_IRQHandler                   ; CAN0 OR'ed Message buffer (16-31)\n    DCD   Reserved99_IRQHandler                           ; Reserved Interrupt 99\n    DCD   Reserved100_IRQHandler                          ; Reserved Interrupt 100\n    DCD   CAN1_ORed_IRQHandler                            ; CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\n    DCD   CAN1_Error_IRQHandler                           ; CAN1 Interrupt indicating that errors were detected on the CAN bus\n    DCD   Reserved103_IRQHandler                          ; Reserved Interrupt 103\n    DCD   CAN1_ORed_0_15_MB_IRQHandler                    ; CAN1 OR'ed Interrupt for Message buffer (0-15)\n    DCD   Reserved105_IRQHandler                          ; Reserved Interrupt 105\n    DCD   Reserved106_IRQHandler                          ; Reserved Interrupt 106\n    DCD   Reserved107_IRQHandler                          ; Reserved Interrupt 107\n    DCD   CAN2_ORed_IRQHandler                            ; CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\n    DCD   CAN2_Error_IRQHandler                           ; CAN2 Interrupt indicating that errors were detected on the CAN bus\n    DCD   Reserved110_IRQHandler                          ; Reserved Interrupt 110\n    DCD   CAN2_ORed_0_15_MB_IRQHandler                    ; CAN2 OR'ed Message buffer (0-15)\n    DCD   Reserved112_IRQHandler                          ; Reserved Interrupt 112\n    DCD   Reserved113_IRQHandler                          ; Reserved Interrupt 113\n    DCD   Reserved114_IRQHandler                          ; Reserved Interrupt 114\n    DCD   FTM0_Ch0_Ch1_IRQHandler                         ; FTM0 Channel 0 and 1 interrupt\n    DCD   FTM0_Ch2_Ch3_IRQHandler                         ; FTM0 Channel 2 and 3 interrupt\n    DCD   FTM0_Ch4_Ch5_IRQHandler                         ; FTM0 Channel 4 and 5 interrupt\n    DCD   FTM0_Ch6_Ch7_IRQHandler                         ; FTM0 Channel 6 and 7 interrupt\n    DCD   FTM0_Fault_IRQHandler                           ; FTM0 Fault interrupt\n    DCD   FTM0_Ovf_Reload_IRQHandler                      ; FTM0 Counter overflow and Reload interrupt\n    DCD   FTM1_Ch0_Ch1_IRQHandler                         ; FTM1 Channel 0 and 1 interrupt\n    DCD   FTM1_Ch2_Ch3_IRQHandler                         ; FTM1 Channel 2 and 3 interrupt\n    DCD   FTM1_Ch4_Ch5_IRQHandler                         ; FTM1 Channel 4 and 5 interrupt\n    DCD   FTM1_Ch6_Ch7_IRQHandler                         ; FTM1 Channel 6 and 7 interrupt\n    DCD   FTM1_Fault_IRQHandler                           ; FTM1 Fault interrupt\n    DCD   FTM1_Ovf_Reload_IRQHandler                      ; FTM1 Counter overflow and Reload interrupt\n    DCD   FTM2_Ch0_Ch1_IRQHandler                         ; FTM2 Channel 0 and 1 interrupt\n    DCD   FTM2_Ch2_Ch3_IRQHandler                         ; FTM2 Channel 2 and 3 interrupt\n    DCD   FTM2_Ch4_Ch5_IRQHandler                         ; FTM2 Channel 4 and 5 interrupt\n    DCD   FTM2_Ch6_Ch7_IRQHandler                         ; FTM2 Channel 6 and 7 interrupt\n    DCD   FTM2_Fault_IRQHandler                           ; FTM2 Fault interrupt\n    DCD   FTM2_Ovf_Reload_IRQHandler                      ; FTM2 Counter overflow and Reload interrupt\n    DCD   FTM3_Ch0_Ch1_IRQHandler                         ; FTM3 Channel 0 and 1 interrupt\n    DCD   FTM3_Ch2_Ch3_IRQHandler                         ; FTM3 Channel 2 and 3 interrupt\n    DCD   FTM3_Ch4_Ch5_IRQHandler                         ; FTM3 Channel 4 and 5 interrupt\n    DCD   FTM3_Ch6_Ch7_IRQHandler                         ; FTM3 Channel 6 and 7 interrupt\n    DCD   FTM3_Fault_IRQHandler                           ; FTM3 Fault interrupt\n    DCD   FTM3_Ovf_Reload_IRQHandler                      ; FTM3 Counter overflow and Reload interrupt\n    DCD   DefaultISR                                      ; Default ISR\n__Vectors_End\n__Vectors_Size  EQU     __Vectors_End - __Vectors\n\n; <h> Flash Configuration\n;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)\n;   <i> and security information that allows the MCU to restrict access to the FTFL module.\n;   <h> Backdoor Comparison Key\n;     <o0>  Backdoor Comparison Key 0.  <0x0-0xFF:2>\n;     <o1>  Backdoor Comparison Key 1.  <0x0-0xFF:2>\n;     <o2>  Backdoor Comparison Key 2.  <0x0-0xFF:2>\n;     <o3>  Backdoor Comparison Key 3.  <0x0-0xFF:2>\n;     <o4>  Backdoor Comparison Key 4.  <0x0-0xFF:2>\n;     <o5>  Backdoor Comparison Key 5.  <0x0-0xFF:2>\n;     <o6>  Backdoor Comparison Key 6.  <0x0-0xFF:2>\n;     <o7>  Backdoor Comparison Key 7.  <0x0-0xFF:2>\nBackDoorK0      EQU     0xFF\nBackDoorK1      EQU     0xFF\nBackDoorK2      EQU     0xFF\nBackDoorK3      EQU     0xFF\nBackDoorK4      EQU     0xFF\nBackDoorK5      EQU     0xFF\nBackDoorK6      EQU     0xFF\nBackDoorK7      EQU     0xFF\n;   </h>\n;   <h> Program flash protection bytes (FPROT)\n;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.\n;     <i> Each bit protects a 1/32 region of the program flash memory.\n;     <h> FPROT0\n;       <i> Program Flash Region Protect Register 0\n;       <i> 1/32 - 8/32 region\n;       <o.0>   FPROT0.0\n;       <o.1>   FPROT0.1\n;       <o.2>   FPROT0.2\n;       <o.3>   FPROT0.3\n;       <o.4>   FPROT0.4\n;       <o.5>   FPROT0.5\n;       <o.6>   FPROT0.6\n;       <o.7>   FPROT0.7\nnFPROT0         EQU     0x00\nFPROT0          EQU     nFPROT0:EOR:0xFF\n;     </h>\n;     <h> FPROT1\n;       <i> Program Flash Region Protect Register 1\n;       <i> 9/32 - 16/32 region\n;       <o.0>   FPROT1.0\n;       <o.1>   FPROT1.1\n;       <o.2>   FPROT1.2\n;       <o.3>   FPROT1.3\n;       <o.4>   FPROT1.4\n;       <o.5>   FPROT1.5\n;       <o.6>   FPROT1.6\n;       <o.7>   FPROT1.7\nnFPROT1         EQU     0x00\nFPROT1          EQU     nFPROT1:EOR:0xFF\n;     </h>\n;     <h> FPROT2\n;       <i> Program Flash Region Protect Register 2\n;       <i> 17/32 - 24/32 region\n;       <o.0>   FPROT2.0\n;       <o.1>   FPROT2.1\n;       <o.2>   FPROT2.2\n;       <o.3>   FPROT2.3\n;       <o.4>   FPROT2.4\n;       <o.5>   FPROT2.5\n;       <o.6>   FPROT2.6\n;       <o.7>   FPROT2.7\nnFPROT2         EQU     0x00\nFPROT2          EQU     nFPROT2:EOR:0xFF\n;     </h>\n;     <h> FPROT3\n;       <i> Program Flash Region Protect Register 3\n;       <i> 25/32 - 32/32 region\n;       <o.0>   FPROT3.0\n;       <o.1>   FPROT3.1\n;       <o.2>   FPROT3.2\n;       <o.3>   FPROT3.3\n;       <o.4>   FPROT3.4\n;       <o.5>   FPROT3.5\n;       <o.6>   FPROT3.6\n;       <o.7>   FPROT3.7\nnFPROT3         EQU     0x00\nFPROT3          EQU     nFPROT3:EOR:0xFF\n;     </h>\n;   </h>\n;   <h> Data flash protection byte (FDPROT)\n;     <i> Each bit protects a 1/8 region of the data flash memory.\n;     <i> (Program flash only devices: Reserved)\n;       <o.0>   FDPROT.0\n;       <o.1>   FDPROT.1\n;       <o.2>   FDPROT.2\n;       <o.3>   FDPROT.3\n;       <o.4>   FDPROT.4\n;       <o.5>   FDPROT.5\n;       <o.6>   FDPROT.6\n;       <o.7>   FDPROT.7\nnFDPROT         EQU     0x00\nFDPROT          EQU     nFDPROT:EOR:0xFF\n;   </h>\n;   <h> EEPROM protection byte (FEPROT)\n;     <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.\n;     <i> (Program flash only devices: Reserved)\n;       <o.0>   FEPROT.0\n;       <o.1>   FEPROT.1\n;       <o.2>   FEPROT.2\n;       <o.3>   FEPROT.3\n;       <o.4>   FEPROT.4\n;       <o.5>   FEPROT.5\n;       <o.6>   FEPROT.6\n;       <o.7>   FEPROT.7\nnFEPROT         EQU     0x00\nFEPROT          EQU     nFEPROT:EOR:0xFF\n;   </h>\n;   <h> Flash nonvolatile option byte (FOPT)\n;     <i> Allows the user to customize the operation of the MCU at boot time.\n;     <o.0> LPBOOT\n;       <0=> Low-power boot\n;       <1=> Normal boot\n;     <o.1> EZPORT_DIS\n;       <0=> EzPort operation is disabled\n;       <1=> EzPort operation is enabled\nFOPT          EQU     0xFD\n;   </h>\n;   <h> Flash security byte (FSEC)\n;     <i> WARNING: If SEC field is configured as \"MCU security status is secure\" and MEEN field is configured as \"Mass erase is disabled\",\n;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!\n;     <o.0..1> SEC\n;       <2=> MCU security status is unsecure\n;       <3=> MCU security status is secure\n;         <i> Flash Security\n;     <o.2..3> FSLACC\n;       <2=> Freescale factory access denied\n;       <3=> Freescale factory access granted\n;         <i> Freescale Failure Analysis Access Code\n;     <o.4..5> MEEN\n;       <2=> Mass erase is disabled\n;       <3=> Mass erase is enabled\n;     <o.6..7> KEYEN\n;       <2=> Backdoor key access enabled\n;       <3=> Backdoor key access disabled\n;         <i> Backdoor Key Security Enable\nFSEC          EQU     0xFE\n;   </h>\n; </h>\n\n#ifndef RAM_TARGET\n                AREA    FlashConfig, DATA, READONLY\n__FlashConfig\n                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3\n                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7\n                DCB     FPROT0    , FPROT1    , FPROT2    , FPROT3\n                DCB     FSEC      , FOPT      , FEPROT    , FDPROT\n#endif\n\n\n                AREA    |.text|, CODE, READONLY\n\n\nReset_Handler   PROC\n                ALIGN   4\n                EXPORT  Reset_Handler             [WEAK]\n                IMPORT  SystemInit\n\n#ifndef RAM_TARGET\n                REQUIRE FlashConfig\n#endif\n\n\n                CPSID   I               ; Mask interrupts\n\n#ifdef START_FROM_FLASH\n                ; Init ECC RAM\n                LDR     R1, =__RAM_START\n                LDR     R1, [R1]\n                LDR     R2, =__RAM_END\n                LDR     R2, [R2]\n                SUBS    R2, R1\n                SUBS    R2, #1\n                BLE LC5\n\n                MOVS    R0, #0\n                MOVS    R3, #4\nLC4\n                STR     R0, [R1]\n                ADD     R1, R1, R3\n                SUBS    R2, #4\n                BGE LC4\nLC5\n                NOP\n#endif\n\n                LDR     R0, =0xE000ED08\n                LDR     R1, =__Vectors\n                STR     R1, [R0]\n                LDR     R2, [R1]\n                MSR     MSP, R2\n                LDR     R0, =SystemInit\n                BLX     R0\n                LDR     R0, =init_data_bss\n                BLX     R0\n                CPSIE   i               ; Unmask interrupts\n                LDR     R0, =__main\n                BLX     R0\n                ENDP\n\nNMI_Handler\\\n                PROC\n                EXPORT  NMI_Handler         [WEAK]\n                B       .\n                ENDP\nHardFault_Handler\\\n                PROC\n                EXPORT  HardFault_Handler         [WEAK]\n                B       .\n                ENDP\nMemManage_Handler\\\n                PROC\n                EXPORT  MemManage_Handler         [WEAK]\n                B       .\n                ENDP\nBusFault_Handler\\\n                PROC\n                EXPORT  BusFault_Handler         [WEAK]\n                B       .\n                ENDP\nUsageFault_Handler\\\n                PROC\n                EXPORT  UsageFault_Handler         [WEAK]\n                B       .\n                ENDP\nSVC_Handler\\\n                PROC\n                EXPORT  SVC_Handler         [WEAK]\n                B       .\n                ENDP\nDebugMon_Handler\\\n                PROC\n                EXPORT  DebugMon_Handler         [WEAK]\n                B       .\n                ENDP\nPendSV_Handler\\\n                PROC\n                EXPORT  PendSV_Handler         [WEAK]\n                B       .\n                ENDP\nSysTick_Handler\\\n                PROC\n                EXPORT  SysTick_Handler         [WEAK]\n                B       .\n                ENDP\nDefaultISR\\\n                PROC\n                EXPORT  DefaultISR         [WEAK]\n                B       .\n                ENDP\nDefault_Handler PROC\n                EXPORT  DMA0_IRQHandler                      [WEAK]\n                EXPORT  DMA1_IRQHandler                      [WEAK]\n                EXPORT  DMA2_IRQHandler                      [WEAK]\n                EXPORT  DMA3_IRQHandler                      [WEAK]\n                EXPORT  DMA4_IRQHandler                      [WEAK]\n                EXPORT  DMA5_IRQHandler                      [WEAK]\n                EXPORT  DMA6_IRQHandler                      [WEAK]\n                EXPORT  DMA7_IRQHandler                      [WEAK]\n                EXPORT  DMA8_IRQHandler                      [WEAK]\n                EXPORT  DMA9_IRQHandler                      [WEAK]\n                EXPORT  DMA10_IRQHandler                     [WEAK]\n                EXPORT  DMA11_IRQHandler                     [WEAK]\n                EXPORT  DMA12_IRQHandler                     [WEAK]\n                EXPORT  DMA13_IRQHandler                     [WEAK]\n                EXPORT  DMA14_IRQHandler                     [WEAK]\n                EXPORT  DMA15_IRQHandler                     [WEAK]\n                EXPORT  DMA_Error_IRQHandler                 [WEAK]\n                EXPORT  MCM_IRQHandler                       [WEAK]\n                EXPORT  FTFC_IRQHandler                      [WEAK]\n                EXPORT  Read_Collision_IRQHandler            [WEAK]\n                EXPORT  LVD_LVW_IRQHandler                   [WEAK]\n                EXPORT  FTFC_Fault_IRQHandler                [WEAK]\n                EXPORT  WDOG_EWM_IRQHandler                  [WEAK]\n                EXPORT  RCM_IRQHandler                       [WEAK]\n                EXPORT  LPI2C0_Master_IRQHandler             [WEAK]\n                EXPORT  LPI2C0_Slave_IRQHandler              [WEAK]\n                EXPORT  LPSPI0_IRQHandler                    [WEAK]\n                EXPORT  LPSPI1_IRQHandler                    [WEAK]\n                EXPORT  LPSPI2_IRQHandler                    [WEAK]\n                EXPORT  Reserved45_IRQHandler                [WEAK]\n                EXPORT  Reserved46_IRQHandler                [WEAK]\n                EXPORT  LPUART0_RxTx_IRQHandler              [WEAK]\n                EXPORT  Reserved48_IRQHandler                [WEAK]\n                EXPORT  LPUART1_RxTx_IRQHandler              [WEAK]\n                EXPORT  Reserved50_IRQHandler                [WEAK]\n                EXPORT  LPUART2_RxTx_IRQHandler              [WEAK]\n                EXPORT  Reserved52_IRQHandler                [WEAK]\n                EXPORT  Reserved53_IRQHandler                [WEAK]\n                EXPORT  Reserved54_IRQHandler                [WEAK]\n                EXPORT  ADC0_IRQHandler                      [WEAK]\n                EXPORT  ADC1_IRQHandler                      [WEAK]\n                EXPORT  CMP0_IRQHandler                      [WEAK]\n                EXPORT  Reserved58_IRQHandler                [WEAK]\n                EXPORT  Reserved59_IRQHandler                [WEAK]\n                EXPORT  ERM_single_fault_IRQHandler          [WEAK]\n                EXPORT  ERM_double_fault_IRQHandler          [WEAK]\n                EXPORT  RTC_IRQHandler                       [WEAK]\n                EXPORT  RTC_Seconds_IRQHandler               [WEAK]\n                EXPORT  LPIT0_Ch0_IRQHandler                 [WEAK]\n                EXPORT  LPIT0_Ch1_IRQHandler                 [WEAK]\n                EXPORT  LPIT0_Ch2_IRQHandler                 [WEAK]\n                EXPORT  LPIT0_Ch3_IRQHandler                 [WEAK]\n                EXPORT  PDB0_IRQHandler                      [WEAK]\n                EXPORT  Reserved69_IRQHandler                [WEAK]\n                EXPORT  Reserved70_IRQHandler                [WEAK]\n                EXPORT  Reserved71_IRQHandler                [WEAK]\n                EXPORT  Reserved72_IRQHandler                [WEAK]\n                EXPORT  SCG_IRQHandler                       [WEAK]\n                EXPORT  LPTMR0_IRQHandler                    [WEAK]\n                EXPORT  PORTA_IRQHandler                     [WEAK]\n                EXPORT  PORTB_IRQHandler                     [WEAK]\n                EXPORT  PORTC_IRQHandler                     [WEAK]\n                EXPORT  PORTD_IRQHandler                     [WEAK]\n                EXPORT  PORTE_IRQHandler                     [WEAK]\n                EXPORT  SWI_IRQHandler                       [WEAK]\n                EXPORT  Reserved81_IRQHandler                [WEAK]\n                EXPORT  Reserved82_IRQHandler                [WEAK]\n                EXPORT  Reserved83_IRQHandler                [WEAK]\n                EXPORT  PDB1_IRQHandler                      [WEAK]\n                EXPORT  FLEXIO_IRQHandler                    [WEAK]\n                EXPORT  Reserved86_IRQHandler                [WEAK]\n                EXPORT  Reserved87_IRQHandler                [WEAK]\n                EXPORT  Reserved88_IRQHandler                [WEAK]\n                EXPORT  Reserved89_IRQHandler                [WEAK]\n                EXPORT  Reserved90_IRQHandler                [WEAK]\n                EXPORT  Reserved91_IRQHandler                [WEAK]\n                EXPORT  Reserved92_IRQHandler                [WEAK]\n                EXPORT  Reserved93_IRQHandler                [WEAK]\n                EXPORT  CAN0_ORed_IRQHandler                 [WEAK]\n                EXPORT  CAN0_Error_IRQHandler                [WEAK]\n                EXPORT  CAN0_Wake_Up_IRQHandler              [WEAK]\n                EXPORT  CAN0_ORed_0_15_MB_IRQHandler         [WEAK]\n                EXPORT  CAN0_ORed_16_31_MB_IRQHandler        [WEAK]\n                EXPORT  Reserved99_IRQHandler                [WEAK]\n                EXPORT  Reserved100_IRQHandler               [WEAK]\n                EXPORT  CAN1_ORed_IRQHandler                 [WEAK]\n                EXPORT  CAN1_Error_IRQHandler                [WEAK]\n                EXPORT  Reserved103_IRQHandler               [WEAK]\n                EXPORT  CAN1_ORed_0_15_MB_IRQHandler         [WEAK]\n                EXPORT  Reserved105_IRQHandler               [WEAK]\n                EXPORT  Reserved106_IRQHandler               [WEAK]\n                EXPORT  Reserved107_IRQHandler               [WEAK]\n                EXPORT  CAN2_ORed_IRQHandler                 [WEAK]\n                EXPORT  CAN2_Error_IRQHandler                [WEAK]\n                EXPORT  Reserved110_IRQHandler               [WEAK]\n                EXPORT  CAN2_ORed_0_15_MB_IRQHandler         [WEAK]\n                EXPORT  Reserved112_IRQHandler               [WEAK]\n                EXPORT  Reserved113_IRQHandler               [WEAK]\n                EXPORT  Reserved114_IRQHandler               [WEAK]\n                EXPORT  FTM0_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM0_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM0_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM0_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM0_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM0_Ovf_Reload_IRQHandler           [WEAK]\n                EXPORT  FTM1_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM1_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM1_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM1_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM1_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM1_Ovf_Reload_IRQHandler           [WEAK]\n                EXPORT  FTM2_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM2_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM2_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM2_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM2_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM2_Ovf_Reload_IRQHandler           [WEAK]\n                EXPORT  FTM3_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM3_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM3_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM3_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM3_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM3_Ovf_Reload_IRQHandler           [WEAK]\nDMA0_IRQHandler                                  ; DMA channel 0 transfer complete\nDMA1_IRQHandler                                  ; DMA channel 1 transfer complete\nDMA2_IRQHandler                                  ; DMA channel 2 transfer complete\nDMA3_IRQHandler                                  ; DMA channel 3 transfer complete\nDMA4_IRQHandler                                  ; DMA channel 4 transfer complete\nDMA5_IRQHandler                                  ; DMA channel 5 transfer complete\nDMA6_IRQHandler                                  ; DMA channel 6 transfer complete\nDMA7_IRQHandler                                  ; DMA channel 7 transfer complete\nDMA8_IRQHandler                                  ; DMA channel 8 transfer complete\nDMA9_IRQHandler                                  ; DMA channel 9 transfer complete\nDMA10_IRQHandler                                 ; DMA channel 10 transfer complete\nDMA11_IRQHandler                                 ; DMA channel 11 transfer complete\nDMA12_IRQHandler                                 ; DMA channel 12 transfer complete\nDMA13_IRQHandler                                 ; DMA channel 13 transfer complete\nDMA14_IRQHandler                                 ; DMA channel 14 transfer complete\nDMA15_IRQHandler                                 ; DMA channel 15 transfer complete\nDMA_Error_IRQHandler                             ; DMA error interrupt channels 0-15\nMCM_IRQHandler                                   ; FPU sources\nFTFC_IRQHandler                                  ; FTFC Command complete\nRead_Collision_IRQHandler                        ; FTFC Read collision\nLVD_LVW_IRQHandler                               ; PMC Low voltage detect interrupt\nFTFC_Fault_IRQHandler                            ; FTFC Double bit fault detect\nWDOG_EWM_IRQHandler                              ; Single interrupt vector for WDOG and EWM\nRCM_IRQHandler                                   ; RCM Asynchronous Interrupt\nLPI2C0_Master_IRQHandler                         ; LPI2C0 Master Interrupt\nLPI2C0_Slave_IRQHandler                          ; LPI2C0 Slave Interrupt\nLPSPI0_IRQHandler                                ; LPSPI0 Interrupt\nLPSPI1_IRQHandler                                ; LPSPI1 Interrupt\nLPSPI2_IRQHandler                                ; LPSPI2 Interrupt\nReserved45_IRQHandler                            ; Reserved Interrupt 45\nReserved46_IRQHandler                            ; Reserved Interrupt 46\nLPUART0_RxTx_IRQHandler                          ; LPUART0 Transmit / Receive Interrupt\nReserved48_IRQHandler                            ; Reserved Interrupt 48\nLPUART1_RxTx_IRQHandler                          ; LPUART1 Transmit / Receive  Interrupt\nReserved50_IRQHandler                            ; Reserved Interrupt 50\nLPUART2_RxTx_IRQHandler                          ; LPUART2 Transmit / Receive  Interrupt\nReserved52_IRQHandler                            ; Reserved Interrupt 52\nReserved53_IRQHandler                            ; Reserved Interrupt 53\nReserved54_IRQHandler                            ; Reserved Interrupt 54\nADC0_IRQHandler                                  ; ADC0 interrupt request.\nADC1_IRQHandler                                  ; ADC1 interrupt request.\nCMP0_IRQHandler                                  ; CMP0 interrupt request\nReserved58_IRQHandler                            ; Reserved Interrupt 58\nReserved59_IRQHandler                            ; Reserved Interrupt 59\nERM_single_fault_IRQHandler                      ; ERM single bit error correction\nERM_double_fault_IRQHandler                      ; ERM double bit error non-correctable\nRTC_IRQHandler                                   ; RTC alarm interrupt\nRTC_Seconds_IRQHandler                           ; RTC seconds interrupt\nLPIT0_Ch0_IRQHandler                             ; LPIT0 channel 0 overflow interrupt\nLPIT0_Ch1_IRQHandler                             ; LPIT0 channel 1 overflow interrupt\nLPIT0_Ch2_IRQHandler                             ; LPIT0 channel 2 overflow interrupt\nLPIT0_Ch3_IRQHandler                             ; LPIT0 channel 3 overflow interrupt\nPDB0_IRQHandler                                  ; PDB0 interrupt\nReserved69_IRQHandler                            ; Reserved Interrupt 69\nReserved70_IRQHandler                            ; Reserved Interrupt 70\nReserved71_IRQHandler                            ; Reserved Interrupt 71\nReserved72_IRQHandler                            ; Reserved Interrupt 72\nSCG_IRQHandler                                   ; SCG bus interrupt request\nLPTMR0_IRQHandler                                ; LPTIMER interrupt request\nPORTA_IRQHandler                                 ; Port A pin detect interrupt\nPORTB_IRQHandler                                 ; Port B pin detect interrupt\nPORTC_IRQHandler                                 ; Port C pin detect interrupt\nPORTD_IRQHandler                                 ; Port D pin detect interrupt\nPORTE_IRQHandler                                 ; Port E pin detect interrupt\nSWI_IRQHandler                                   ; Software interrupt\nReserved81_IRQHandler                            ; Reserved Interrupt 81\nReserved82_IRQHandler                            ; Reserved Interrupt 82\nReserved83_IRQHandler                            ; Reserved Interrupt 83\nPDB1_IRQHandler                                  ; PDB1 interrupt\nFLEXIO_IRQHandler                                ; FlexIO Interrupt\nReserved86_IRQHandler                            ; Reserved Interrupt 86\nReserved87_IRQHandler                            ; Reserved Interrupt 87\nReserved88_IRQHandler                            ; Reserved Interrupt 88\nReserved89_IRQHandler                            ; Reserved Interrupt 89\nReserved90_IRQHandler                            ; Reserved Interrupt 90\nReserved91_IRQHandler                            ; Reserved Interrupt 91\nReserved92_IRQHandler                            ; Reserved Interrupt 92\nReserved93_IRQHandler                            ; Reserved Interrupt 93\nCAN0_ORed_IRQHandler                             ; CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\nCAN0_Error_IRQHandler                            ; CAN0 Interrupt indicating that errors were detected on the CAN bus\nCAN0_Wake_Up_IRQHandler                          ; CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode\nCAN0_ORed_0_15_MB_IRQHandler                     ; CAN0 OR'ed Message buffer (0-15)\nCAN0_ORed_16_31_MB_IRQHandler                    ; CAN0 OR'ed Message buffer (16-31)\nReserved99_IRQHandler                            ; Reserved Interrupt 99\nReserved100_IRQHandler                           ; Reserved Interrupt 100\nCAN1_ORed_IRQHandler                             ; CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\nCAN1_Error_IRQHandler                            ; CAN1 Interrupt indicating that errors were detected on the CAN bus\nReserved103_IRQHandler                           ; Reserved Interrupt 103\nCAN1_ORed_0_15_MB_IRQHandler                     ; CAN1 OR'ed Interrupt for Message buffer (0-15)\nReserved105_IRQHandler                           ; Reserved Interrupt 105\nReserved106_IRQHandler                           ; Reserved Interrupt 106\nReserved107_IRQHandler                           ; Reserved Interrupt 107\nCAN2_ORed_IRQHandler                             ; CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\nCAN2_Error_IRQHandler                            ; CAN2 Interrupt indicating that errors were detected on the CAN bus\nReserved110_IRQHandler                           ; Reserved Interrupt 110\nCAN2_ORed_0_15_MB_IRQHandler                     ; CAN2 OR'ed Message buffer (0-15)\nReserved112_IRQHandler                           ; Reserved Interrupt 112\nReserved113_IRQHandler                           ; Reserved Interrupt 113\nReserved114_IRQHandler                           ; Reserved Interrupt 114\nFTM0_Ch0_Ch1_IRQHandler                          ; FTM0 Channel 0 and 1 interrupt\nFTM0_Ch2_Ch3_IRQHandler                          ; FTM0 Channel 2 and 3 interrupt\nFTM0_Ch4_Ch5_IRQHandler                          ; FTM0 Channel 4 and 5 interrupt\nFTM0_Ch6_Ch7_IRQHandler                          ; FTM0 Channel 6 and 7 interrupt\nFTM0_Fault_IRQHandler                            ; FTM0 Fault interrupt\nFTM0_Ovf_Reload_IRQHandler                       ; FTM0 Counter overflow and Reload interrupt\nFTM1_Ch0_Ch1_IRQHandler                          ; FTM1 Channel 0 and 1 interrupt\nFTM1_Ch2_Ch3_IRQHandler                          ; FTM1 Channel 2 and 3 interrupt\nFTM1_Ch4_Ch5_IRQHandler                          ; FTM1 Channel 4 and 5 interrupt\nFTM1_Ch6_Ch7_IRQHandler                          ; FTM1 Channel 6 and 7 interrupt\nFTM1_Fault_IRQHandler                            ; FTM1 Fault interrupt\nFTM1_Ovf_Reload_IRQHandler                       ; FTM1 Counter overflow and Reload interrupt\nFTM2_Ch0_Ch1_IRQHandler                          ; FTM2 Channel 0 and 1 interrupt\nFTM2_Ch2_Ch3_IRQHandler                          ; FTM2 Channel 2 and 3 interrupt\nFTM2_Ch4_Ch5_IRQHandler                          ; FTM2 Channel 4 and 5 interrupt\nFTM2_Ch6_Ch7_IRQHandler                          ; FTM2 Channel 6 and 7 interrupt\nFTM2_Fault_IRQHandler                            ; FTM2 Fault interrupt\nFTM2_Ovf_Reload_IRQHandler                       ; FTM2 Counter overflow and Reload interrupt\nFTM3_Ch0_Ch1_IRQHandler                          ; FTM3 Channel 0 and 1 interrupt\nFTM3_Ch2_Ch3_IRQHandler                          ; FTM3 Channel 2 and 3 interrupt\nFTM3_Ch4_Ch5_IRQHandler                          ; FTM3 Channel 4 and 5 interrupt\nFTM3_Ch6_Ch7_IRQHandler                          ; FTM3 Channel 6 and 7 interrupt\nFTM3_Fault_IRQHandler                            ; FTM3 Fault interrupt\nFTM3_Ovf_Reload_IRQHandler                       ; FTM3 Counter overflow and Reload interrupt\n\n                B       .\n\n                ENDP\n\n                ALIGN\n                END\n",
                "content": ";\n; modified by ARM\n;\n; ---------------------------------------------------------------------------------------\n;  @file:    startup_S32K144.S\n;  @purpose: ARM Compiler Collection Startup File\n;            S32K144\n;  @version: 2.2.0\n;  @date:    2017-1-10\n;  @build:   b170107\n; ---------------------------------------------------------------------------------------\n;\n; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc.\n; Copyright 2016-2017 NXP\n; All rights reserved.\n;\n; NXP Confidential. This software is owned or controlled by NXP and may only be\n; used strictly in accordance with the applicable license terms. By expressly\n; accepting such terms or by downloading, installing, activating and/or otherwise\n; using the software, you are agreeing that you have read, and that you agree to\n; comply with and are bound by, such license terms. If you do not agree to be\n; bound by the applicable license terms, then you may not retain, install,\n; activate or otherwise use the software. The production use license in\n; Section 2.3 is expressly granted for this software.\n;***************************************************************************\n; Version: ARMC Compiler Collection\n;***************************************************************************\n\n;// ------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n\n\n                PRESERVE8\n                THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n                AREA    |.text|, CODE, READONLY\n                EXPORT  __Vectors\n\n                EXPORT __RAM_VECTOR_TABLE_SIZE\n                EXPORT __VECTOR_RAM\n                EXPORT __VECTOR_ROM\n\n                EXPORT __BSS_START\n                EXPORT __BSS_END\n\n                EXPORT __CODE_ROM\n                EXPORT __CODE_END\n                EXPORT __CODE_RAM\n\n                EXPORT __DATA_ROM\n                EXPORT __DATA_END\n                EXPORT __DATA_RAM\n                EXPORT __VECTOR_ROM_START\n                EXPORT __VECTOR_ROM_END\n                EXPORT __DATA_RAM_START\n                EXPORT __DATA_RAM_END\n                EXPORT __CUSTOM_SECTION_START\n                EXPORT __CUSTOM_SECTION_END\n                EXPORT __CODE_RAM_START\n                EXPORT __CODE_RAM_END\n\n                EXPORT __RAM_START\n                EXPORT __RAM_END\n\n                IMPORT init_data_bss\n                IMPORT  main\n                IMPORT  __main\n                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|\n                IMPORT  |Image$$RW_m_data_2$$ZI$$Base|\n                IMPORT  |Image$$RW_m_data_2$$ZI$$Limit|\n\n                IMPORT  |Image$$ER_m_text_const$$Base|\n                IMPORT  |Image$$ER_m_text_const$$Limit|\n\n                IMPORT  |Image$$RW_m_data$$Base|\n\n                IMPORT  |Image$$ER_m_text_const$$Base|\n                IMPORT  |Image$$ER_m_text_const$$Limit|\n\n                IMPORT  |Image$$RW_m_data$$Length|\n                IMPORT |Image$$RW_m_code$$Base|\n                IMPORT |Image$$RW_m_code$$Length|\n                IMPORT |Image$$ER_m_text$$Limit|\n\n                IMPORT |Image$$VECTOR_RAM$$Length|\n                IMPORT |Image$$VECTOR_RAM$$Base|\n\n                IMPORT |Image$$VECTOR_ROM$$Length|\n                IMPORT |Image$$VECTOR_ROM$$Base|\n                IMPORT |Image$$RW_m_custom_section$$Base|\n                IMPORT |Image$$RW_m_custom_section$$Limit|\n\n                IMPORT |Image$$RW_m_data$$Limit|\n                IMPORT |Image$$RW_m_code$$Limit|\n                IMPORT |Image$$VECTOR_ROM$$Limit|\n\n                IMPORT |Image$$ARM_LIB_STACK$$Limit|\n__RAM_VECTOR_TABLE_SIZE DCD |Image$$VECTOR_ROM$$Length|\n__VECTOR_RAM DCD |Image$$VECTOR_RAM$$Base|\n__VECTOR_ROM DCD |Image$$VECTOR_ROM$$Base|\n__VECTOR_ROM_START DCD |Image$$VECTOR_ROM$$Base|\n__VECTOR_ROM_END DCD |Image$$VECTOR_ROM$$Limit|\n\n__CODE_ROM DCD  |Image$$RW_m_data$$Length|+ |Image$$ER_m_text$$Limit|\n__CODE_END DCD  |Image$$RW_m_data$$Length|+ |Image$$ER_m_text$$Limit| + |Image$$RW_m_code$$Length|\n__CODE_RAM DCD |Image$$RW_m_code$$Base|\n__CODE_RAM_START DCD |Image$$RW_m_code$$Base|\n__CODE_RAM_END DCD |Image$$RW_m_code$$Limit|\n\n__BSS_START DCD  |Image$$RW_m_data_2$$ZI$$Base|\n__BSS_END DCD  |Image$$RW_m_data_2$$ZI$$Limit|\n\n__DATA_RAM DCD  |Image$$RW_m_data$$Base|\n__DATA_RAM_START DCD  |Image$$RW_m_data$$Base|\n__DATA_RAM_END DCD  |Image$$RW_m_data$$Limit|\n__DATA_ROM DCD  |Image$$ER_m_text$$Limit|\n__DATA_END DCD  |Image$$RW_m_data$$Length|+ |Image$$ER_m_text$$Limit|\n__CUSTOM_SECTION_START DCD |Image$$RW_m_custom_section$$Base|\n__CUSTOM_SECTION_END DCD |Image$$RW_m_custom_section$$Limit|\n\n    IF :DEF:__flash_vector_table__\n__RAM_START DCD |Image$$RW_m_data$$Base|\n    ELSE\n__RAM_START DCD |Image$$VECTOR_RAM$$Base|\n    ENDIF\n__RAM_END   DCD |Image$$ARM_LIB_STACK$$Limit|\n\n\t\tAREA    RESET, DATA, READONLY\n__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit|   ; Top of Stack\n                DCD     Reset_Handler                       ; Reset Handler\n                DCD     NMI_Handler                         ; NMI Handler\n                DCD     HardFault_Handler                   ; Hard Fault Handler\n                DCD     MemManage_Handler                   ; MPU Fault Handler\n                DCD     BusFault_Handler                    ; Bus Fault Handler\n                DCD     UsageFault_Handler                  ; Usage Fault Handler\n                DCD     0                                   ; Reserved\n                DCD     0                                   ; Reserved\n                DCD     0                                   ; Reserved\n                DCD     0                                   ; Reserved\n                DCD     SVC_Handler                         ; SVCall Handler\n                DCD     DebugMon_Handler                    ; Debug Monitor Handler\n                DCD     0                                   ; Reserved\n                DCD     PendSV_Handler                      ; PendSV Handler\n                DCD     SysTick_Handler                     ; SysTick Handler\n\n                                                            ; External Interrupts\n    DCD   DMA0_IRQHandler                                 ; DMA channel 0 transfer complete\n    DCD   DMA1_IRQHandler                                 ; DMA channel 1 transfer complete\n    DCD   DMA2_IRQHandler                                 ; DMA channel 2 transfer complete\n    DCD   DMA3_IRQHandler                                 ; DMA channel 3 transfer complete\n    DCD   DMA4_IRQHandler                                 ; DMA channel 4 transfer complete\n    DCD   DMA5_IRQHandler                                 ; DMA channel 5 transfer complete\n    DCD   DMA6_IRQHandler                                 ; DMA channel 6 transfer complete\n    DCD   DMA7_IRQHandler                                 ; DMA channel 7 transfer complete\n    DCD   DMA8_IRQHandler                                 ; DMA channel 8 transfer complete\n    DCD   DMA9_IRQHandler                                 ; DMA channel 9 transfer complete\n    DCD   DMA10_IRQHandler                                ; DMA channel 10 transfer complete\n    DCD   DMA11_IRQHandler                                ; DMA channel 11 transfer complete\n    DCD   DMA12_IRQHandler                                ; DMA channel 12 transfer complete\n    DCD   DMA13_IRQHandler                                ; DMA channel 13 transfer complete\n    DCD   DMA14_IRQHandler                                ; DMA channel 14 transfer complete\n    DCD   DMA15_IRQHandler                                ; DMA channel 15 transfer complete\n    DCD   DMA_Error_IRQHandler                            ; DMA error interrupt channels 0-15\n    DCD   MCM_IRQHandler                                  ; FPU sources\n    DCD   FTFC_IRQHandler                                 ; FTFC Command complete\n    DCD   Read_Collision_IRQHandler                       ; FTFC Read collision\n    DCD   LVD_LVW_IRQHandler                              ; PMC Low voltage detect interrupt\n    DCD   FTFC_Fault_IRQHandler                           ; FTFC Double bit fault detect\n    DCD   WDOG_EWM_IRQHandler                             ; Single interrupt vector for WDOG and EWM\n    DCD   RCM_IRQHandler                                  ; RCM Asynchronous Interrupt\n    DCD   LPI2C0_Master_IRQHandler                        ; LPI2C0 Master Interrupt\n    DCD   LPI2C0_Slave_IRQHandler                         ; LPI2C0 Slave Interrupt\n    DCD   LPSPI0_IRQHandler                               ; LPSPI0 Interrupt\n    DCD   LPSPI1_IRQHandler                               ; LPSPI1 Interrupt\n    DCD   LPSPI2_IRQHandler                               ; LPSPI2 Interrupt\n    DCD   Reserved45_IRQHandler                           ; Reserved Interrupt 45\n    DCD   Reserved46_IRQHandler                           ; Reserved Interrupt 46\n    DCD   LPUART0_RxTx_IRQHandler                         ; LPUART0 Transmit / Receive Interrupt\n    DCD   Reserved48_IRQHandler                           ; Reserved Interrupt 48\n    DCD   LPUART1_RxTx_IRQHandler                         ; LPUART1 Transmit / Receive  Interrupt\n    DCD   Reserved50_IRQHandler                           ; Reserved Interrupt 50\n    DCD   LPUART2_RxTx_IRQHandler                         ; LPUART2 Transmit / Receive  Interrupt\n    DCD   Reserved52_IRQHandler                           ; Reserved Interrupt 52\n    DCD   Reserved53_IRQHandler                           ; Reserved Interrupt 53\n    DCD   Reserved54_IRQHandler                           ; Reserved Interrupt 54\n    DCD   ADC0_IRQHandler                                 ; ADC0 interrupt request.\n    DCD   ADC1_IRQHandler                                 ; ADC1 interrupt request.\n    DCD   CMP0_IRQHandler                                 ; CMP0 interrupt request\n    DCD   Reserved58_IRQHandler                           ; Reserved Interrupt 58\n    DCD   Reserved59_IRQHandler                           ; Reserved Interrupt 59\n    DCD   ERM_single_fault_IRQHandler                     ; ERM single bit error correction\n    DCD   ERM_double_fault_IRQHandler                     ; ERM double bit error non-correctable\n    DCD   RTC_IRQHandler                                  ; RTC alarm interrupt\n    DCD   RTC_Seconds_IRQHandler                          ; RTC seconds interrupt\n    DCD   LPIT0_Ch0_IRQHandler                            ; LPIT0 channel 0 overflow interrupt\n    DCD   LPIT0_Ch1_IRQHandler                            ; LPIT0 channel 1 overflow interrupt\n    DCD   LPIT0_Ch2_IRQHandler                            ; LPIT0 channel 2 overflow interrupt\n    DCD   LPIT0_Ch3_IRQHandler                            ; LPIT0 channel 3 overflow interrupt\n    DCD   PDB0_IRQHandler                                 ; PDB0 interrupt\n    DCD   Reserved69_IRQHandler                           ; Reserved Interrupt 69\n    DCD   Reserved70_IRQHandler                           ; Reserved Interrupt 70\n    DCD   Reserved71_IRQHandler                           ; Reserved Interrupt 71\n    DCD   Reserved72_IRQHandler                           ; Reserved Interrupt 72\n    DCD   SCG_IRQHandler                                  ; SCG bus interrupt request\n    DCD   LPTMR0_IRQHandler                               ; LPTIMER interrupt request\n    DCD   PORTA_IRQHandler                                ; Port A pin detect interrupt\n    DCD   PORTB_IRQHandler                                ; Port B pin detect interrupt\n    DCD   PORTC_IRQHandler                                ; Port C pin detect interrupt\n    DCD   PORTD_IRQHandler                                ; Port D pin detect interrupt\n    DCD   PORTE_IRQHandler                                ; Port E pin detect interrupt\n    DCD   SWI_IRQHandler                                  ; Software interrupt\n    DCD   Reserved81_IRQHandler                           ; Reserved Interrupt 81\n    DCD   Reserved82_IRQHandler                           ; Reserved Interrupt 82\n    DCD   Reserved83_IRQHandler                           ; Reserved Interrupt 83\n    DCD   PDB1_IRQHandler                                 ; PDB1 interrupt\n    DCD   FLEXIO_IRQHandler                               ; FlexIO Interrupt\n    DCD   Reserved86_IRQHandler                           ; Reserved Interrupt 86\n    DCD   Reserved87_IRQHandler                           ; Reserved Interrupt 87\n    DCD   Reserved88_IRQHandler                           ; Reserved Interrupt 88\n    DCD   Reserved89_IRQHandler                           ; Reserved Interrupt 89\n    DCD   Reserved90_IRQHandler                           ; Reserved Interrupt 90\n    DCD   Reserved91_IRQHandler                           ; Reserved Interrupt 91\n    DCD   Reserved92_IRQHandler                           ; Reserved Interrupt 92\n    DCD   Reserved93_IRQHandler                           ; Reserved Interrupt 93\n    DCD   CAN0_ORed_IRQHandler                            ; CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\n    DCD   CAN0_Error_IRQHandler                           ; CAN0 Interrupt indicating that errors were detected on the CAN bus\n    DCD   CAN0_Wake_Up_IRQHandler                         ; CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode\n    DCD   CAN0_ORed_0_15_MB_IRQHandler                    ; CAN0 OR'ed Message buffer (0-15)\n    DCD   CAN0_ORed_16_31_MB_IRQHandler                   ; CAN0 OR'ed Message buffer (16-31)\n    DCD   Reserved99_IRQHandler                           ; Reserved Interrupt 99\n    DCD   Reserved100_IRQHandler                          ; Reserved Interrupt 100\n    DCD   CAN1_ORed_IRQHandler                            ; CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\n    DCD   CAN1_Error_IRQHandler                           ; CAN1 Interrupt indicating that errors were detected on the CAN bus\n    DCD   Reserved103_IRQHandler                          ; Reserved Interrupt 103\n    DCD   CAN1_ORed_0_15_MB_IRQHandler                    ; CAN1 OR'ed Interrupt for Message buffer (0-15)\n    DCD   Reserved105_IRQHandler                          ; Reserved Interrupt 105\n    DCD   Reserved106_IRQHandler                          ; Reserved Interrupt 106\n    DCD   Reserved107_IRQHandler                          ; Reserved Interrupt 107\n    DCD   CAN2_ORed_IRQHandler                            ; CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\n    DCD   CAN2_Error_IRQHandler                           ; CAN2 Interrupt indicating that errors were detected on the CAN bus\n    DCD   Reserved110_IRQHandler                          ; Reserved Interrupt 110\n    DCD   CAN2_ORed_0_15_MB_IRQHandler                    ; CAN2 OR'ed Message buffer (0-15)\n    DCD   Reserved112_IRQHandler                          ; Reserved Interrupt 112\n    DCD   Reserved113_IRQHandler                          ; Reserved Interrupt 113\n    DCD   Reserved114_IRQHandler                          ; Reserved Interrupt 114\n    DCD   FTM0_Ch0_Ch1_IRQHandler                         ; FTM0 Channel 0 and 1 interrupt\n    DCD   FTM0_Ch2_Ch3_IRQHandler                         ; FTM0 Channel 2 and 3 interrupt\n    DCD   FTM0_Ch4_Ch5_IRQHandler                         ; FTM0 Channel 4 and 5 interrupt\n    DCD   FTM0_Ch6_Ch7_IRQHandler                         ; FTM0 Channel 6 and 7 interrupt\n    DCD   FTM0_Fault_IRQHandler                           ; FTM0 Fault interrupt\n    DCD   FTM0_Ovf_Reload_IRQHandler                      ; FTM0 Counter overflow and Reload interrupt\n    DCD   FTM1_Ch0_Ch1_IRQHandler                         ; FTM1 Channel 0 and 1 interrupt\n    DCD   FTM1_Ch2_Ch3_IRQHandler                         ; FTM1 Channel 2 and 3 interrupt\n    DCD   FTM1_Ch4_Ch5_IRQHandler                         ; FTM1 Channel 4 and 5 interrupt\n    DCD   FTM1_Ch6_Ch7_IRQHandler                         ; FTM1 Channel 6 and 7 interrupt\n    DCD   FTM1_Fault_IRQHandler                           ; FTM1 Fault interrupt\n    DCD   FTM1_Ovf_Reload_IRQHandler                      ; FTM1 Counter overflow and Reload interrupt\n    DCD   FTM2_Ch0_Ch1_IRQHandler                         ; FTM2 Channel 0 and 1 interrupt\n    DCD   FTM2_Ch2_Ch3_IRQHandler                         ; FTM2 Channel 2 and 3 interrupt\n    DCD   FTM2_Ch4_Ch5_IRQHandler                         ; FTM2 Channel 4 and 5 interrupt\n    DCD   FTM2_Ch6_Ch7_IRQHandler                         ; FTM2 Channel 6 and 7 interrupt\n    DCD   FTM2_Fault_IRQHandler                           ; FTM2 Fault interrupt\n    DCD   FTM2_Ovf_Reload_IRQHandler                      ; FTM2 Counter overflow and Reload interrupt\n    DCD   FTM3_Ch0_Ch1_IRQHandler                         ; FTM3 Channel 0 and 1 interrupt\n    DCD   FTM3_Ch2_Ch3_IRQHandler                         ; FTM3 Channel 2 and 3 interrupt\n    DCD   FTM3_Ch4_Ch5_IRQHandler                         ; FTM3 Channel 4 and 5 interrupt\n    DCD   FTM3_Ch6_Ch7_IRQHandler                         ; FTM3 Channel 6 and 7 interrupt\n    DCD   FTM3_Fault_IRQHandler                           ; FTM3 Fault interrupt\n    DCD   FTM3_Ovf_Reload_IRQHandler                      ; FTM3 Counter overflow and Reload interrupt\n    DCD   DefaultISR                                      ; Default ISR\n__Vectors_End\n__Vectors_Size  EQU     __Vectors_End - __Vectors\n\n; <h> Flash Configuration\n;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)\n;   <i> and security information that allows the MCU to restrict access to the FTFL module.\n;   <h> Backdoor Comparison Key\n;     <o0>  Backdoor Comparison Key 0.  <0x0-0xFF:2>\n;     <o1>  Backdoor Comparison Key 1.  <0x0-0xFF:2>\n;     <o2>  Backdoor Comparison Key 2.  <0x0-0xFF:2>\n;     <o3>  Backdoor Comparison Key 3.  <0x0-0xFF:2>\n;     <o4>  Backdoor Comparison Key 4.  <0x0-0xFF:2>\n;     <o5>  Backdoor Comparison Key 5.  <0x0-0xFF:2>\n;     <o6>  Backdoor Comparison Key 6.  <0x0-0xFF:2>\n;     <o7>  Backdoor Comparison Key 7.  <0x0-0xFF:2>\nBackDoorK0      EQU     0xFF\nBackDoorK1      EQU     0xFF\nBackDoorK2      EQU     0xFF\nBackDoorK3      EQU     0xFF\nBackDoorK4      EQU     0xFF\nBackDoorK5      EQU     0xFF\nBackDoorK6      EQU     0xFF\nBackDoorK7      EQU     0xFF\n;   </h>\n;   <h> Program flash protection bytes (FPROT)\n;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.\n;     <i> Each bit protects a 1/32 region of the program flash memory.\n;     <h> FPROT0\n;       <i> Program Flash Region Protect Register 0\n;       <i> 1/32 - 8/32 region\n;       <o.0>   FPROT0.0\n;       <o.1>   FPROT0.1\n;       <o.2>   FPROT0.2\n;       <o.3>   FPROT0.3\n;       <o.4>   FPROT0.4\n;       <o.5>   FPROT0.5\n;       <o.6>   FPROT0.6\n;       <o.7>   FPROT0.7\nnFPROT0         EQU     0x00\nFPROT0          EQU     nFPROT0:EOR:0xFF\n;     </h>\n;     <h> FPROT1\n;       <i> Program Flash Region Protect Register 1\n;       <i> 9/32 - 16/32 region\n;       <o.0>   FPROT1.0\n;       <o.1>   FPROT1.1\n;       <o.2>   FPROT1.2\n;       <o.3>   FPROT1.3\n;       <o.4>   FPROT1.4\n;       <o.5>   FPROT1.5\n;       <o.6>   FPROT1.6\n;       <o.7>   FPROT1.7\nnFPROT1         EQU     0x00\nFPROT1          EQU     nFPROT1:EOR:0xFF\n;     </h>\n;     <h> FPROT2\n;       <i> Program Flash Region Protect Register 2\n;       <i> 17/32 - 24/32 region\n;       <o.0>   FPROT2.0\n;       <o.1>   FPROT2.1\n;       <o.2>   FPROT2.2\n;       <o.3>   FPROT2.3\n;       <o.4>   FPROT2.4\n;       <o.5>   FPROT2.5\n;       <o.6>   FPROT2.6\n;       <o.7>   FPROT2.7\nnFPROT2         EQU     0x00\nFPROT2          EQU     nFPROT2:EOR:0xFF\n;     </h>\n;     <h> FPROT3\n;       <i> Program Flash Region Protect Register 3\n;       <i> 25/32 - 32/32 region\n;       <o.0>   FPROT3.0\n;       <o.1>   FPROT3.1\n;       <o.2>   FPROT3.2\n;       <o.3>   FPROT3.3\n;       <o.4>   FPROT3.4\n;       <o.5>   FPROT3.5\n;       <o.6>   FPROT3.6\n;       <o.7>   FPROT3.7\nnFPROT3         EQU     0x00\nFPROT3          EQU     nFPROT3:EOR:0xFF\n;     </h>\n;   </h>\n;   <h> Data flash protection byte (FDPROT)\n;     <i> Each bit protects a 1/8 region of the data flash memory.\n;     <i> (Program flash only devices: Reserved)\n;       <o.0>   FDPROT.0\n;       <o.1>   FDPROT.1\n;       <o.2>   FDPROT.2\n;       <o.3>   FDPROT.3\n;       <o.4>   FDPROT.4\n;       <o.5>   FDPROT.5\n;       <o.6>   FDPROT.6\n;       <o.7>   FDPROT.7\nnFDPROT         EQU     0x00\nFDPROT          EQU     nFDPROT:EOR:0xFF\n;   </h>\n;   <h> EEPROM protection byte (FEPROT)\n;     <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.\n;     <i> (Program flash only devices: Reserved)\n;       <o.0>   FEPROT.0\n;       <o.1>   FEPROT.1\n;       <o.2>   FEPROT.2\n;       <o.3>   FEPROT.3\n;       <o.4>   FEPROT.4\n;       <o.5>   FEPROT.5\n;       <o.6>   FEPROT.6\n;       <o.7>   FEPROT.7\nnFEPROT         EQU     0x00\nFEPROT          EQU     nFEPROT:EOR:0xFF\n;   </h>\n;   <h> Flash nonvolatile option byte (FOPT)\n;     <i> Allows the user to customize the operation of the MCU at boot time.\n;     <o.0> LPBOOT\n;       <0=> Low-power boot\n;       <1=> Normal boot\n;     <o.1> EZPORT_DIS\n;       <0=> EzPort operation is disabled\n;       <1=> EzPort operation is enabled\nFOPT          EQU     0xFD\n;   </h>\n;   <h> Flash security byte (FSEC)\n;     <i> WARNING: If SEC field is configured as \"MCU security status is secure\" and MEEN field is configured as \"Mass erase is disabled\",\n;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!\n;     <o.0..1> SEC\n;       <2=> MCU security status is unsecure\n;       <3=> MCU security status is secure\n;         <i> Flash Security\n;     <o.2..3> FSLACC\n;       <2=> Freescale factory access denied\n;       <3=> Freescale factory access granted\n;         <i> Freescale Failure Analysis Access Code\n;     <o.4..5> MEEN\n;       <2=> Mass erase is disabled\n;       <3=> Mass erase is enabled\n;     <o.6..7> KEYEN\n;       <2=> Backdoor key access enabled\n;       <3=> Backdoor key access disabled\n;         <i> Backdoor Key Security Enable\nFSEC          EQU     0xFE\n;   </h>\n; </h>\n\n#ifndef RAM_TARGET\n                AREA    FlashConfig, DATA, READONLY\n__FlashConfig\n                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3\n                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7\n                DCB     FPROT0    , FPROT1    , FPROT2    , FPROT3\n                DCB     FSEC      , FOPT      , FEPROT    , FDPROT\n#endif\n\n\n                AREA    |.text|, CODE, READONLY\n\n\nReset_Handler   PROC\n                ALIGN   4\n                EXPORT  Reset_Handler             [WEAK]\n                IMPORT  SystemInit\n\n#ifndef RAM_TARGET\n                REQUIRE FlashConfig\n#endif\n\n\n                CPSID   I               ; Mask interrupts\n\n#ifdef START_FROM_FLASH\n                ; Init ECC RAM\n                LDR     R1, =__RAM_START\n                LDR     R1, [R1]\n                LDR     R2, =__RAM_END\n                LDR     R2, [R2]\n                SUBS    R2, R1\n                SUBS    R2, #1\n                BLE LC5\n\n                MOVS    R0, #0\n                MOVS    R3, #4\nLC4\n                STR     R0, [R1]\n                ADD     R1, R1, R3\n                SUBS    R2, #4\n                BGE LC4\nLC5\n                NOP\n#endif\n\n                LDR     R0, =0xE000ED08\n                LDR     R1, =__Vectors\n                STR     R1, [R0]\n                LDR     R2, [R1]\n                MSR     MSP, R2\n                LDR     R0, =SystemInit\n                BLX     R0\n                LDR     R0, =init_data_bss\n                BLX     R0\n                CPSIE   i               ; Unmask interrupts\n                LDR     R0, =__main\n                BLX     R0\n                ENDP\n\nNMI_Handler\\\n                PROC\n                EXPORT  NMI_Handler         [WEAK]\n                B       .\n                ENDP\nHardFault_Handler\\\n                PROC\n                EXPORT  HardFault_Handler         [WEAK]\n                B       .\n                ENDP\nMemManage_Handler\\\n                PROC\n                EXPORT  MemManage_Handler         [WEAK]\n                B       .\n                ENDP\nBusFault_Handler\\\n                PROC\n                EXPORT  BusFault_Handler         [WEAK]\n                B       .\n                ENDP\nUsageFault_Handler\\\n                PROC\n                EXPORT  UsageFault_Handler         [WEAK]\n                B       .\n                ENDP\nSVC_Handler\\\n                PROC\n                EXPORT  SVC_Handler         [WEAK]\n                B       .\n                ENDP\nDebugMon_Handler\\\n                PROC\n                EXPORT  DebugMon_Handler         [WEAK]\n                B       .\n                ENDP\nPendSV_Handler\\\n                PROC\n                EXPORT  PendSV_Handler         [WEAK]\n                B       .\n                ENDP\nSysTick_Handler\\\n                PROC\n                EXPORT  SysTick_Handler         [WEAK]\n                B       .\n                ENDP\nDefaultISR\\\n                PROC\n                EXPORT  DefaultISR         [WEAK]\n                B       .\n                ENDP\nDefault_Handler PROC\n                EXPORT  DMA0_IRQHandler                      [WEAK]\n                EXPORT  DMA1_IRQHandler                      [WEAK]\n                EXPORT  DMA2_IRQHandler                      [WEAK]\n                EXPORT  DMA3_IRQHandler                      [WEAK]\n                EXPORT  DMA4_IRQHandler                      [WEAK]\n                EXPORT  DMA5_IRQHandler                      [WEAK]\n                EXPORT  DMA6_IRQHandler                      [WEAK]\n                EXPORT  DMA7_IRQHandler                      [WEAK]\n                EXPORT  DMA8_IRQHandler                      [WEAK]\n                EXPORT  DMA9_IRQHandler                      [WEAK]\n                EXPORT  DMA10_IRQHandler                     [WEAK]\n                EXPORT  DMA11_IRQHandler                     [WEAK]\n                EXPORT  DMA12_IRQHandler                     [WEAK]\n                EXPORT  DMA13_IRQHandler                     [WEAK]\n                EXPORT  DMA14_IRQHandler                     [WEAK]\n                EXPORT  DMA15_IRQHandler                     [WEAK]\n                EXPORT  DMA_Error_IRQHandler                 [WEAK]\n                EXPORT  MCM_IRQHandler                       [WEAK]\n                EXPORT  FTFC_IRQHandler                      [WEAK]\n                EXPORT  Read_Collision_IRQHandler            [WEAK]\n                EXPORT  LVD_LVW_IRQHandler                   [WEAK]\n                EXPORT  FTFC_Fault_IRQHandler                [WEAK]\n                EXPORT  WDOG_EWM_IRQHandler                  [WEAK]\n                EXPORT  RCM_IRQHandler                       [WEAK]\n                EXPORT  LPI2C0_Master_IRQHandler             [WEAK]\n                EXPORT  LPI2C0_Slave_IRQHandler              [WEAK]\n                EXPORT  LPSPI0_IRQHandler                    [WEAK]\n                EXPORT  LPSPI1_IRQHandler                    [WEAK]\n                EXPORT  LPSPI2_IRQHandler                    [WEAK]\n                EXPORT  Reserved45_IRQHandler                [WEAK]\n                EXPORT  Reserved46_IRQHandler                [WEAK]\n                EXPORT  LPUART0_RxTx_IRQHandler              [WEAK]\n                EXPORT  Reserved48_IRQHandler                [WEAK]\n                EXPORT  LPUART1_RxTx_IRQHandler              [WEAK]\n                EXPORT  Reserved50_IRQHandler                [WEAK]\n                EXPORT  LPUART2_RxTx_IRQHandler              [WEAK]\n                EXPORT  Reserved52_IRQHandler                [WEAK]\n                EXPORT  Reserved53_IRQHandler                [WEAK]\n                EXPORT  Reserved54_IRQHandler                [WEAK]\n                EXPORT  ADC0_IRQHandler                      [WEAK]\n                EXPORT  ADC1_IRQHandler                      [WEAK]\n                EXPORT  CMP0_IRQHandler                      [WEAK]\n                EXPORT  Reserved58_IRQHandler                [WEAK]\n                EXPORT  Reserved59_IRQHandler                [WEAK]\n                EXPORT  ERM_single_fault_IRQHandler          [WEAK]\n                EXPORT  ERM_double_fault_IRQHandler          [WEAK]\n                EXPORT  RTC_IRQHandler                       [WEAK]\n                EXPORT  RTC_Seconds_IRQHandler               [WEAK]\n                EXPORT  LPIT0_Ch0_IRQHandler                 [WEAK]\n                EXPORT  LPIT0_Ch1_IRQHandler                 [WEAK]\n                EXPORT  LPIT0_Ch2_IRQHandler                 [WEAK]\n                EXPORT  LPIT0_Ch3_IRQHandler                 [WEAK]\n                EXPORT  PDB0_IRQHandler                      [WEAK]\n                EXPORT  Reserved69_IRQHandler                [WEAK]\n                EXPORT  Reserved70_IRQHandler                [WEAK]\n                EXPORT  Reserved71_IRQHandler                [WEAK]\n                EXPORT  Reserved72_IRQHandler                [WEAK]\n                EXPORT  SCG_IRQHandler                       [WEAK]\n                EXPORT  LPTMR0_IRQHandler                    [WEAK]\n                EXPORT  PORTA_IRQHandler                     [WEAK]\n                EXPORT  PORTB_IRQHandler                     [WEAK]\n                EXPORT  PORTC_IRQHandler                     [WEAK]\n                EXPORT  PORTD_IRQHandler                     [WEAK]\n                EXPORT  PORTE_IRQHandler                     [WEAK]\n                EXPORT  SWI_IRQHandler                       [WEAK]\n                EXPORT  Reserved81_IRQHandler                [WEAK]\n                EXPORT  Reserved82_IRQHandler                [WEAK]\n                EXPORT  Reserved83_IRQHandler                [WEAK]\n                EXPORT  PDB1_IRQHandler                      [WEAK]\n                EXPORT  FLEXIO_IRQHandler                    [WEAK]\n                EXPORT  Reserved86_IRQHandler                [WEAK]\n                EXPORT  Reserved87_IRQHandler                [WEAK]\n                EXPORT  Reserved88_IRQHandler                [WEAK]\n                EXPORT  Reserved89_IRQHandler                [WEAK]\n                EXPORT  Reserved90_IRQHandler                [WEAK]\n                EXPORT  Reserved91_IRQHandler                [WEAK]\n                EXPORT  Reserved92_IRQHandler                [WEAK]\n                EXPORT  Reserved93_IRQHandler                [WEAK]\n                EXPORT  CAN0_ORed_IRQHandler                 [WEAK]\n                EXPORT  CAN0_Error_IRQHandler                [WEAK]\n                EXPORT  CAN0_Wake_Up_IRQHandler              [WEAK]\n                EXPORT  CAN0_ORed_0_15_MB_IRQHandler         [WEAK]\n                EXPORT  CAN0_ORed_16_31_MB_IRQHandler        [WEAK]\n                EXPORT  Reserved99_IRQHandler                [WEAK]\n                EXPORT  Reserved100_IRQHandler               [WEAK]\n                EXPORT  CAN1_ORed_IRQHandler                 [WEAK]\n                EXPORT  CAN1_Error_IRQHandler                [WEAK]\n                EXPORT  Reserved103_IRQHandler               [WEAK]\n                EXPORT  CAN1_ORed_0_15_MB_IRQHandler         [WEAK]\n                EXPORT  Reserved105_IRQHandler               [WEAK]\n                EXPORT  Reserved106_IRQHandler               [WEAK]\n                EXPORT  Reserved107_IRQHandler               [WEAK]\n                EXPORT  CAN2_ORed_IRQHandler                 [WEAK]\n                EXPORT  CAN2_Error_IRQHandler                [WEAK]\n                EXPORT  Reserved110_IRQHandler               [WEAK]\n                EXPORT  CAN2_ORed_0_15_MB_IRQHandler         [WEAK]\n                EXPORT  Reserved112_IRQHandler               [WEAK]\n                EXPORT  Reserved113_IRQHandler               [WEAK]\n                EXPORT  Reserved114_IRQHandler               [WEAK]\n                EXPORT  FTM0_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM0_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM0_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM0_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM0_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM0_Ovf_Reload_IRQHandler           [WEAK]\n                EXPORT  FTM1_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM1_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM1_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM1_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM1_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM1_Ovf_Reload_IRQHandler           [WEAK]\n                EXPORT  FTM2_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM2_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM2_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM2_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM2_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM2_Ovf_Reload_IRQHandler           [WEAK]\n                EXPORT  FTM3_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM3_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM3_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM3_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM3_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM3_Ovf_Reload_IRQHandler           [WEAK]\nDMA0_IRQHandler                                  ; DMA channel 0 transfer complete\nDMA1_IRQHandler                                  ; DMA channel 1 transfer complete\nDMA2_IRQHandler                                  ; DMA channel 2 transfer complete\nDMA3_IRQHandler                                  ; DMA channel 3 transfer complete\nDMA4_IRQHandler                                  ; DMA channel 4 transfer complete\nDMA5_IRQHandler                                  ; DMA channel 5 transfer complete\nDMA6_IRQHandler                                  ; DMA channel 6 transfer complete\nDMA7_IRQHandler                                  ; DMA channel 7 transfer complete\nDMA8_IRQHandler                                  ; DMA channel 8 transfer complete\nDMA9_IRQHandler                                  ; DMA channel 9 transfer complete\nDMA10_IRQHandler                                 ; DMA channel 10 transfer complete\nDMA11_IRQHandler                                 ; DMA channel 11 transfer complete\nDMA12_IRQHandler                                 ; DMA channel 12 transfer complete\nDMA13_IRQHandler                                 ; DMA channel 13 transfer complete\nDMA14_IRQHandler                                 ; DMA channel 14 transfer complete\nDMA15_IRQHandler                                 ; DMA channel 15 transfer complete\nDMA_Error_IRQHandler                             ; DMA error interrupt channels 0-15\nMCM_IRQHandler                                   ; FPU sources\nFTFC_IRQHandler                                  ; FTFC Command complete\nRead_Collision_IRQHandler                        ; FTFC Read collision\nLVD_LVW_IRQHandler                               ; PMC Low voltage detect interrupt\nFTFC_Fault_IRQHandler                            ; FTFC Double bit fault detect\nWDOG_EWM_IRQHandler                              ; Single interrupt vector for WDOG and EWM\nRCM_IRQHandler                                   ; RCM Asynchronous Interrupt\nLPI2C0_Master_IRQHandler                         ; LPI2C0 Master Interrupt\nLPI2C0_Slave_IRQHandler                          ; LPI2C0 Slave Interrupt\nLPSPI0_IRQHandler                                ; LPSPI0 Interrupt\nLPSPI1_IRQHandler                                ; LPSPI1 Interrupt\nLPSPI2_IRQHandler                                ; LPSPI2 Interrupt\nReserved45_IRQHandler                            ; Reserved Interrupt 45\nReserved46_IRQHandler                            ; Reserved Interrupt 46\nLPUART0_RxTx_IRQHandler                          ; LPUART0 Transmit / Receive Interrupt\nReserved48_IRQHandler                            ; Reserved Interrupt 48\nLPUART1_RxTx_IRQHandler                          ; LPUART1 Transmit / Receive  Interrupt\nReserved50_IRQHandler                            ; Reserved Interrupt 50\nLPUART2_RxTx_IRQHandler                          ; LPUART2 Transmit / Receive  Interrupt\nReserved52_IRQHandler                            ; Reserved Interrupt 52\nReserved53_IRQHandler                            ; Reserved Interrupt 53\nReserved54_IRQHandler                            ; Reserved Interrupt 54\nADC0_IRQHandler                                  ; ADC0 interrupt request.\nADC1_IRQHandler                                  ; ADC1 interrupt request.\nCMP0_IRQHandler                                  ; CMP0 interrupt request\nReserved58_IRQHandler                            ; Reserved Interrupt 58\nReserved59_IRQHandler                            ; Reserved Interrupt 59\nERM_single_fault_IRQHandler                      ; ERM single bit error correction\nERM_double_fault_IRQHandler                      ; ERM double bit error non-correctable\nRTC_IRQHandler                                   ; RTC alarm interrupt\nRTC_Seconds_IRQHandler                           ; RTC seconds interrupt\nLPIT0_Ch0_IRQHandler                             ; LPIT0 channel 0 overflow interrupt\nLPIT0_Ch1_IRQHandler                             ; LPIT0 channel 1 overflow interrupt\nLPIT0_Ch2_IRQHandler                             ; LPIT0 channel 2 overflow interrupt\nLPIT0_Ch3_IRQHandler                             ; LPIT0 channel 3 overflow interrupt\nPDB0_IRQHandler                                  ; PDB0 interrupt\nReserved69_IRQHandler                            ; Reserved Interrupt 69\nReserved70_IRQHandler                            ; Reserved Interrupt 70\nReserved71_IRQHandler                            ; Reserved Interrupt 71\nReserved72_IRQHandler                            ; Reserved Interrupt 72\nSCG_IRQHandler                                   ; SCG bus interrupt request\nLPTMR0_IRQHandler                                ; LPTIMER interrupt request\nPORTA_IRQHandler                                 ; Port A pin detect interrupt\nPORTB_IRQHandler                                 ; Port B pin detect interrupt\nPORTC_IRQHandler                                 ; Port C pin detect interrupt\nPORTD_IRQHandler                                 ; Port D pin detect interrupt\nPORTE_IRQHandler                                 ; Port E pin detect interrupt\nSWI_IRQHandler                                   ; Software interrupt\nReserved81_IRQHandler                            ; Reserved Interrupt 81\nReserved82_IRQHandler                            ; Reserved Interrupt 82\nReserved83_IRQHandler                            ; Reserved Interrupt 83\nPDB1_IRQHandler                                  ; PDB1 interrupt\nFLEXIO_IRQHandler                                ; FlexIO Interrupt\nReserved86_IRQHandler                            ; Reserved Interrupt 86\nReserved87_IRQHandler                            ; Reserved Interrupt 87\nReserved88_IRQHandler                            ; Reserved Interrupt 88\nReserved89_IRQHandler                            ; Reserved Interrupt 89\nReserved90_IRQHandler                            ; Reserved Interrupt 90\nReserved91_IRQHandler                            ; Reserved Interrupt 91\nReserved92_IRQHandler                            ; Reserved Interrupt 92\nReserved93_IRQHandler                            ; Reserved Interrupt 93\nCAN0_ORed_IRQHandler                             ; CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\nCAN0_Error_IRQHandler                            ; CAN0 Interrupt indicating that errors were detected on the CAN bus\nCAN0_Wake_Up_IRQHandler                          ; CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode\nCAN0_ORed_0_15_MB_IRQHandler                     ; CAN0 OR'ed Message buffer (0-15)\nCAN0_ORed_16_31_MB_IRQHandler                    ; CAN0 OR'ed Message buffer (16-31)\nReserved99_IRQHandler                            ; Reserved Interrupt 99\nReserved100_IRQHandler                           ; Reserved Interrupt 100\nCAN1_ORed_IRQHandler                             ; CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\nCAN1_Error_IRQHandler                            ; CAN1 Interrupt indicating that errors were detected on the CAN bus\nReserved103_IRQHandler                           ; Reserved Interrupt 103\nCAN1_ORed_0_15_MB_IRQHandler                     ; CAN1 OR'ed Interrupt for Message buffer (0-15)\nReserved105_IRQHandler                           ; Reserved Interrupt 105\nReserved106_IRQHandler                           ; Reserved Interrupt 106\nReserved107_IRQHandler                           ; Reserved Interrupt 107\nCAN2_ORed_IRQHandler                             ; CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\nCAN2_Error_IRQHandler                            ; CAN2 Interrupt indicating that errors were detected on the CAN bus\nReserved110_IRQHandler                           ; Reserved Interrupt 110\nCAN2_ORed_0_15_MB_IRQHandler                     ; CAN2 OR'ed Message buffer (0-15)\nReserved112_IRQHandler                           ; Reserved Interrupt 112\nReserved113_IRQHandler                           ; Reserved Interrupt 113\nReserved114_IRQHandler                           ; Reserved Interrupt 114\nFTM0_Ch0_Ch1_IRQHandler                          ; FTM0 Channel 0 and 1 interrupt\nFTM0_Ch2_Ch3_IRQHandler                          ; FTM0 Channel 2 and 3 interrupt\nFTM0_Ch4_Ch5_IRQHandler                          ; FTM0 Channel 4 and 5 interrupt\nFTM0_Ch6_Ch7_IRQHandler                          ; FTM0 Channel 6 and 7 interrupt\nFTM0_Fault_IRQHandler                            ; FTM0 Fault interrupt\nFTM0_Ovf_Reload_IRQHandler                       ; FTM0 Counter overflow and Reload interrupt\nFTM1_Ch0_Ch1_IRQHandler                          ; FTM1 Channel 0 and 1 interrupt\nFTM1_Ch2_Ch3_IRQHandler                          ; FTM1 Channel 2 and 3 interrupt\nFTM1_Ch4_Ch5_IRQHandler                          ; FTM1 Channel 4 and 5 interrupt\nFTM1_Ch6_Ch7_IRQHandler                          ; FTM1 Channel 6 and 7 interrupt\nFTM1_Fault_IRQHandler                            ; FTM1 Fault interrupt\nFTM1_Ovf_Reload_IRQHandler                       ; FTM1 Counter overflow and Reload interrupt\nFTM2_Ch0_Ch1_IRQHandler                          ; FTM2 Channel 0 and 1 interrupt\nFTM2_Ch2_Ch3_IRQHandler                          ; FTM2 Channel 2 and 3 interrupt\nFTM2_Ch4_Ch5_IRQHandler                          ; FTM2 Channel 4 and 5 interrupt\nFTM2_Ch6_Ch7_IRQHandler                          ; FTM2 Channel 6 and 7 interrupt\nFTM2_Fault_IRQHandler                            ; FTM2 Fault interrupt\nFTM2_Ovf_Reload_IRQHandler                       ; FTM2 Counter overflow and Reload interrupt\nFTM3_Ch0_Ch1_IRQHandler                          ; FTM3 Channel 0 and 1 interrupt\nFTM3_Ch2_Ch3_IRQHandler                          ; FTM3 Channel 2 and 3 interrupt\nFTM3_Ch4_Ch5_IRQHandler                          ; FTM3 Channel 4 and 5 interrupt\nFTM3_Ch6_Ch7_IRQHandler                          ; FTM3 Channel 6 and 7 interrupt\nFTM3_Fault_IRQHandler                            ; FTM3 Fault interrupt\nFTM3_Ovf_Reload_IRQHandler                       ; FTM3 Counter overflow and Reload interrupt\n\n                B       .\n\n                ENDP\n\n                ALIGN\n                END\n",
                "addLineCount": 4,
                "removeLineCount": 4
              }
            ]
          },
          "workflowStatus": "success",
          "displayParams": {
            "path": "RTE/Device/S32K144HFxxxLLx/startup_S32K144.S",
            "askApproval": false
          },
          "displayResult": {},
          "workflowSnapshot": {
            "status": "success",
            "result": {
              "name": "patch_file",
              "type": "tool_use",
              "params": {
                "path": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S",
                "content": "<<< SEARCH <<<\n#ifndef __flash_vector_table__\n__RAM_START DCD |Image$$VECTOR_RAM$$Base|\n#else\n__RAM_START DCD |Image$$RW_m_data$$Base|\n#endif\n==== REPLACED_BY ====\n    IF :DEF:__flash_vector_table__\n__RAM_START DCD |Image$$RW_m_data$$Base|\n    ELSE\n__RAM_START DCD |Image$$VECTOR_RAM$$Base|\n    ENDIF\n>>> END >>>"
              },
              "success": true,
              "message": "",
              "code": 0,
              "result": {
                "failedPatchIndex": -1,
                "fileName": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S",
                "beforeChangeFileContent": ";\n; modified by ARM\n;\n; ---------------------------------------------------------------------------------------\n;  @file:    startup_S32K144.S\n;  @purpose: ARM Compiler Collection Startup File\n;            S32K144\n;  @version: 2.2.0\n;  @date:    2017-1-10\n;  @build:   b170107\n; ---------------------------------------------------------------------------------------\n;\n; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc.\n; Copyright 2016-2017 NXP\n; All rights reserved.\n;\n; NXP Confidential. This software is owned or controlled by NXP and may only be\n; used strictly in accordance with the applicable license terms. By expressly\n; accepting such terms or by downloading, installing, activating and/or otherwise\n; using the software, you are agreeing that you have read, and that you agree to\n; comply with and are bound by, such license terms. If you do not agree to be\n; bound by the applicable license terms, then you may not retain, install,\n; activate or otherwise use the software. The production use license in\n; Section 2.3 is expressly granted for this software.\n;***************************************************************************\n; Version: ARMC Compiler Collection\n;***************************************************************************\n\n;// ------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n\n\n                PRESERVE8\n                THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n                AREA    |.text|, CODE, READONLY\n                EXPORT  __Vectors\n\n                EXPORT __RAM_VECTOR_TABLE_SIZE\n                EXPORT __VECTOR_RAM\n                EXPORT __VECTOR_ROM\n\n                EXPORT __BSS_START\n                EXPORT __BSS_END\n\n                EXPORT __CODE_ROM\n                EXPORT __CODE_END\n                EXPORT __CODE_RAM\n\n                EXPORT __DATA_ROM\n                EXPORT __DATA_END\n                EXPORT __DATA_RAM\n                EXPORT __VECTOR_ROM_START\n                EXPORT __VECTOR_ROM_END\n                EXPORT __DATA_RAM_START\n                EXPORT __DATA_RAM_END\n                EXPORT __CUSTOM_SECTION_START\n                EXPORT __CUSTOM_SECTION_END\n                EXPORT __CODE_RAM_START\n                EXPORT __CODE_RAM_END\n\n                EXPORT __RAM_START\n                EXPORT __RAM_END\n\n                IMPORT init_data_bss\n                IMPORT  main\n                IMPORT  __main\n                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|\n                IMPORT  |Image$$RW_m_data_2$$ZI$$Base|\n                IMPORT  |Image$$RW_m_data_2$$ZI$$Limit|\n\n                IMPORT  |Image$$ER_m_text_const$$Base|\n                IMPORT  |Image$$ER_m_text_const$$Limit|\n\n                IMPORT  |Image$$RW_m_data$$Base|\n\n                IMPORT  |Image$$ER_m_text_const$$Base|\n                IMPORT  |Image$$ER_m_text_const$$Limit|\n\n                IMPORT  |Image$$RW_m_data$$Length|\n                IMPORT |Image$$RW_m_code$$Base|\n                IMPORT |Image$$RW_m_code$$Length|\n                IMPORT |Image$$ER_m_text$$Limit|\n\n                IMPORT |Image$$VECTOR_RAM$$Length|\n                IMPORT |Image$$VECTOR_RAM$$Base|\n\n                IMPORT |Image$$VECTOR_ROM$$Length|\n                IMPORT |Image$$VECTOR_ROM$$Base|\n                IMPORT |Image$$RW_m_custom_section$$Base|\n                IMPORT |Image$$RW_m_custom_section$$Limit|\n\n                IMPORT |Image$$RW_m_data$$Limit|\n                IMPORT |Image$$RW_m_code$$Limit|\n                IMPORT |Image$$VECTOR_ROM$$Limit|\n\n                IMPORT |Image$$ARM_LIB_STACK$$Limit|\n__RAM_VECTOR_TABLE_SIZE DCD |Image$$VECTOR_ROM$$Length|\n__VECTOR_RAM DCD |Image$$VECTOR_RAM$$Base|\n__VECTOR_ROM DCD |Image$$VECTOR_ROM$$Base|\n__VECTOR_ROM_START DCD |Image$$VECTOR_ROM$$Base|\n__VECTOR_ROM_END DCD |Image$$VECTOR_ROM$$Limit|\n\n__CODE_ROM DCD  |Image$$RW_m_data$$Length|+ |Image$$ER_m_text$$Limit|\n__CODE_END DCD  |Image$$RW_m_data$$Length|+ |Image$$ER_m_text$$Limit| + |Image$$RW_m_code$$Length|\n__CODE_RAM DCD |Image$$RW_m_code$$Base|\n__CODE_RAM_START DCD |Image$$RW_m_code$$Base|\n__CODE_RAM_END DCD |Image$$RW_m_code$$Limit|\n\n__BSS_START DCD  |Image$$RW_m_data_2$$ZI$$Base|\n__BSS_END DCD  |Image$$RW_m_data_2$$ZI$$Limit|\n\n__DATA_RAM DCD  |Image$$RW_m_data$$Base|\n__DATA_RAM_START DCD  |Image$$RW_m_data$$Base|\n__DATA_RAM_END DCD  |Image$$RW_m_data$$Limit|\n__DATA_ROM DCD  |Image$$ER_m_text$$Limit|\n__DATA_END DCD  |Image$$RW_m_data$$Length|+ |Image$$ER_m_text$$Limit|\n__CUSTOM_SECTION_START DCD |Image$$RW_m_custom_section$$Base|\n__CUSTOM_SECTION_END DCD |Image$$RW_m_custom_section$$Limit|\n\n#ifndef __flash_vector_table__\n__RAM_START DCD |Image$$VECTOR_RAM$$Base|\n#else\n__RAM_START DCD |Image$$RW_m_data$$Base|\n#endif\n__RAM_END   DCD |Image$$ARM_LIB_STACK$$Limit|\n\n\t\tAREA    RESET, DATA, READONLY\n__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit|   ; Top of Stack\n                DCD     Reset_Handler                       ; Reset Handler\n                DCD     NMI_Handler                         ; NMI Handler\n                DCD     HardFault_Handler                   ; Hard Fault Handler\n                DCD     MemManage_Handler                   ; MPU Fault Handler\n                DCD     BusFault_Handler                    ; Bus Fault Handler\n                DCD     UsageFault_Handler                  ; Usage Fault Handler\n                DCD     0                                   ; Reserved\n                DCD     0                                   ; Reserved\n                DCD     0                                   ; Reserved\n                DCD     0                                   ; Reserved\n                DCD     SVC_Handler                         ; SVCall Handler\n                DCD     DebugMon_Handler                    ; Debug Monitor Handler\n                DCD     0                                   ; Reserved\n                DCD     PendSV_Handler                      ; PendSV Handler\n                DCD     SysTick_Handler                     ; SysTick Handler\n\n                                                            ; External Interrupts\n    DCD   DMA0_IRQHandler                                 ; DMA channel 0 transfer complete\n    DCD   DMA1_IRQHandler                                 ; DMA channel 1 transfer complete\n    DCD   DMA2_IRQHandler                                 ; DMA channel 2 transfer complete\n    DCD   DMA3_IRQHandler                                 ; DMA channel 3 transfer complete\n    DCD   DMA4_IRQHandler                                 ; DMA channel 4 transfer complete\n    DCD   DMA5_IRQHandler                                 ; DMA channel 5 transfer complete\n    DCD   DMA6_IRQHandler                                 ; DMA channel 6 transfer complete\n    DCD   DMA7_IRQHandler                                 ; DMA channel 7 transfer complete\n    DCD   DMA8_IRQHandler                                 ; DMA channel 8 transfer complete\n    DCD   DMA9_IRQHandler                                 ; DMA channel 9 transfer complete\n    DCD   DMA10_IRQHandler                                ; DMA channel 10 transfer complete\n    DCD   DMA11_IRQHandler                                ; DMA channel 11 transfer complete\n    DCD   DMA12_IRQHandler                                ; DMA channel 12 transfer complete\n    DCD   DMA13_IRQHandler                                ; DMA channel 13 transfer complete\n    DCD   DMA14_IRQHandler                                ; DMA channel 14 transfer complete\n    DCD   DMA15_IRQHandler                                ; DMA channel 15 transfer complete\n    DCD   DMA_Error_IRQHandler                            ; DMA error interrupt channels 0-15\n    DCD   MCM_IRQHandler                                  ; FPU sources\n    DCD   FTFC_IRQHandler                                 ; FTFC Command complete\n    DCD   Read_Collision_IRQHandler                       ; FTFC Read collision\n    DCD   LVD_LVW_IRQHandler                              ; PMC Low voltage detect interrupt\n    DCD   FTFC_Fault_IRQHandler                           ; FTFC Double bit fault detect\n    DCD   WDOG_EWM_IRQHandler                             ; Single interrupt vector for WDOG and EWM\n    DCD   RCM_IRQHandler                                  ; RCM Asynchronous Interrupt\n    DCD   LPI2C0_Master_IRQHandler                        ; LPI2C0 Master Interrupt\n    DCD   LPI2C0_Slave_IRQHandler                         ; LPI2C0 Slave Interrupt\n    DCD   LPSPI0_IRQHandler                               ; LPSPI0 Interrupt\n    DCD   LPSPI1_IRQHandler                               ; LPSPI1 Interrupt\n    DCD   LPSPI2_IRQHandler                               ; LPSPI2 Interrupt\n    DCD   Reserved45_IRQHandler                           ; Reserved Interrupt 45\n    DCD   Reserved46_IRQHandler                           ; Reserved Interrupt 46\n    DCD   LPUART0_RxTx_IRQHandler                         ; LPUART0 Transmit / Receive Interrupt\n    DCD   Reserved48_IRQHandler                           ; Reserved Interrupt 48\n    DCD   LPUART1_RxTx_IRQHandler                         ; LPUART1 Transmit / Receive  Interrupt\n    DCD   Reserved50_IRQHandler                           ; Reserved Interrupt 50\n    DCD   LPUART2_RxTx_IRQHandler                         ; LPUART2 Transmit / Receive  Interrupt\n    DCD   Reserved52_IRQHandler                           ; Reserved Interrupt 52\n    DCD   Reserved53_IRQHandler                           ; Reserved Interrupt 53\n    DCD   Reserved54_IRQHandler                           ; Reserved Interrupt 54\n    DCD   ADC0_IRQHandler                                 ; ADC0 interrupt request.\n    DCD   ADC1_IRQHandler                                 ; ADC1 interrupt request.\n    DCD   CMP0_IRQHandler                                 ; CMP0 interrupt request\n    DCD   Reserved58_IRQHandler                           ; Reserved Interrupt 58\n    DCD   Reserved59_IRQHandler                           ; Reserved Interrupt 59\n    DCD   ERM_single_fault_IRQHandler                     ; ERM single bit error correction\n    DCD   ERM_double_fault_IRQHandler                     ; ERM double bit error non-correctable\n    DCD   RTC_IRQHandler                                  ; RTC alarm interrupt\n    DCD   RTC_Seconds_IRQHandler                          ; RTC seconds interrupt\n    DCD   LPIT0_Ch0_IRQHandler                            ; LPIT0 channel 0 overflow interrupt\n    DCD   LPIT0_Ch1_IRQHandler                            ; LPIT0 channel 1 overflow interrupt\n    DCD   LPIT0_Ch2_IRQHandler                            ; LPIT0 channel 2 overflow interrupt\n    DCD   LPIT0_Ch3_IRQHandler                            ; LPIT0 channel 3 overflow interrupt\n    DCD   PDB0_IRQHandler                                 ; PDB0 interrupt\n    DCD   Reserved69_IRQHandler                           ; Reserved Interrupt 69\n    DCD   Reserved70_IRQHandler                           ; Reserved Interrupt 70\n    DCD   Reserved71_IRQHandler                           ; Reserved Interrupt 71\n    DCD   Reserved72_IRQHandler                           ; Reserved Interrupt 72\n    DCD   SCG_IRQHandler                                  ; SCG bus interrupt request\n    DCD   LPTMR0_IRQHandler                               ; LPTIMER interrupt request\n    DCD   PORTA_IRQHandler                                ; Port A pin detect interrupt\n    DCD   PORTB_IRQHandler                                ; Port B pin detect interrupt\n    DCD   PORTC_IRQHandler                                ; Port C pin detect interrupt\n    DCD   PORTD_IRQHandler                                ; Port D pin detect interrupt\n    DCD   PORTE_IRQHandler                                ; Port E pin detect interrupt\n    DCD   SWI_IRQHandler                                  ; Software interrupt\n    DCD   Reserved81_IRQHandler                           ; Reserved Interrupt 81\n    DCD   Reserved82_IRQHandler                           ; Reserved Interrupt 82\n    DCD   Reserved83_IRQHandler                           ; Reserved Interrupt 83\n    DCD   PDB1_IRQHandler                                 ; PDB1 interrupt\n    DCD   FLEXIO_IRQHandler                               ; FlexIO Interrupt\n    DCD   Reserved86_IRQHandler                           ; Reserved Interrupt 86\n    DCD   Reserved87_IRQHandler                           ; Reserved Interrupt 87\n    DCD   Reserved88_IRQHandler                           ; Reserved Interrupt 88\n    DCD   Reserved89_IRQHandler                           ; Reserved Interrupt 89\n    DCD   Reserved90_IRQHandler                           ; Reserved Interrupt 90\n    DCD   Reserved91_IRQHandler                           ; Reserved Interrupt 91\n    DCD   Reserved92_IRQHandler                           ; Reserved Interrupt 92\n    DCD   Reserved93_IRQHandler                           ; Reserved Interrupt 93\n    DCD   CAN0_ORed_IRQHandler                            ; CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\n    DCD   CAN0_Error_IRQHandler                           ; CAN0 Interrupt indicating that errors were detected on the CAN bus\n    DCD   CAN0_Wake_Up_IRQHandler                         ; CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode\n    DCD   CAN0_ORed_0_15_MB_IRQHandler                    ; CAN0 OR'ed Message buffer (0-15)\n    DCD   CAN0_ORed_16_31_MB_IRQHandler                   ; CAN0 OR'ed Message buffer (16-31)\n    DCD   Reserved99_IRQHandler                           ; Reserved Interrupt 99\n    DCD   Reserved100_IRQHandler                          ; Reserved Interrupt 100\n    DCD   CAN1_ORed_IRQHandler                            ; CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\n    DCD   CAN1_Error_IRQHandler                           ; CAN1 Interrupt indicating that errors were detected on the CAN bus\n    DCD   Reserved103_IRQHandler                          ; Reserved Interrupt 103\n    DCD   CAN1_ORed_0_15_MB_IRQHandler                    ; CAN1 OR'ed Interrupt for Message buffer (0-15)\n    DCD   Reserved105_IRQHandler                          ; Reserved Interrupt 105\n    DCD   Reserved106_IRQHandler                          ; Reserved Interrupt 106\n    DCD   Reserved107_IRQHandler                          ; Reserved Interrupt 107\n    DCD   CAN2_ORed_IRQHandler                            ; CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\n    DCD   CAN2_Error_IRQHandler                           ; CAN2 Interrupt indicating that errors were detected on the CAN bus\n    DCD   Reserved110_IRQHandler                          ; Reserved Interrupt 110\n    DCD   CAN2_ORed_0_15_MB_IRQHandler                    ; CAN2 OR'ed Message buffer (0-15)\n    DCD   Reserved112_IRQHandler                          ; Reserved Interrupt 112\n    DCD   Reserved113_IRQHandler                          ; Reserved Interrupt 113\n    DCD   Reserved114_IRQHandler                          ; Reserved Interrupt 114\n    DCD   FTM0_Ch0_Ch1_IRQHandler                         ; FTM0 Channel 0 and 1 interrupt\n    DCD   FTM0_Ch2_Ch3_IRQHandler                         ; FTM0 Channel 2 and 3 interrupt\n    DCD   FTM0_Ch4_Ch5_IRQHandler                         ; FTM0 Channel 4 and 5 interrupt\n    DCD   FTM0_Ch6_Ch7_IRQHandler                         ; FTM0 Channel 6 and 7 interrupt\n    DCD   FTM0_Fault_IRQHandler                           ; FTM0 Fault interrupt\n    DCD   FTM0_Ovf_Reload_IRQHandler                      ; FTM0 Counter overflow and Reload interrupt\n    DCD   FTM1_Ch0_Ch1_IRQHandler                         ; FTM1 Channel 0 and 1 interrupt\n    DCD   FTM1_Ch2_Ch3_IRQHandler                         ; FTM1 Channel 2 and 3 interrupt\n    DCD   FTM1_Ch4_Ch5_IRQHandler                         ; FTM1 Channel 4 and 5 interrupt\n    DCD   FTM1_Ch6_Ch7_IRQHandler                         ; FTM1 Channel 6 and 7 interrupt\n    DCD   FTM1_Fault_IRQHandler                           ; FTM1 Fault interrupt\n    DCD   FTM1_Ovf_Reload_IRQHandler                      ; FTM1 Counter overflow and Reload interrupt\n    DCD   FTM2_Ch0_Ch1_IRQHandler                         ; FTM2 Channel 0 and 1 interrupt\n    DCD   FTM2_Ch2_Ch3_IRQHandler                         ; FTM2 Channel 2 and 3 interrupt\n    DCD   FTM2_Ch4_Ch5_IRQHandler                         ; FTM2 Channel 4 and 5 interrupt\n    DCD   FTM2_Ch6_Ch7_IRQHandler                         ; FTM2 Channel 6 and 7 interrupt\n    DCD   FTM2_Fault_IRQHandler                           ; FTM2 Fault interrupt\n    DCD   FTM2_Ovf_Reload_IRQHandler                      ; FTM2 Counter overflow and Reload interrupt\n    DCD   FTM3_Ch0_Ch1_IRQHandler                         ; FTM3 Channel 0 and 1 interrupt\n    DCD   FTM3_Ch2_Ch3_IRQHandler                         ; FTM3 Channel 2 and 3 interrupt\n    DCD   FTM3_Ch4_Ch5_IRQHandler                         ; FTM3 Channel 4 and 5 interrupt\n    DCD   FTM3_Ch6_Ch7_IRQHandler                         ; FTM3 Channel 6 and 7 interrupt\n    DCD   FTM3_Fault_IRQHandler                           ; FTM3 Fault interrupt\n    DCD   FTM3_Ovf_Reload_IRQHandler                      ; FTM3 Counter overflow and Reload interrupt\n    DCD   DefaultISR                                      ; Default ISR\n__Vectors_End\n__Vectors_Size  EQU     __Vectors_End - __Vectors\n\n; <h> Flash Configuration\n;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)\n;   <i> and security information that allows the MCU to restrict access to the FTFL module.\n;   <h> Backdoor Comparison Key\n;     <o0>  Backdoor Comparison Key 0.  <0x0-0xFF:2>\n;     <o1>  Backdoor Comparison Key 1.  <0x0-0xFF:2>\n;     <o2>  Backdoor Comparison Key 2.  <0x0-0xFF:2>\n;     <o3>  Backdoor Comparison Key 3.  <0x0-0xFF:2>\n;     <o4>  Backdoor Comparison Key 4.  <0x0-0xFF:2>\n;     <o5>  Backdoor Comparison Key 5.  <0x0-0xFF:2>\n;     <o6>  Backdoor Comparison Key 6.  <0x0-0xFF:2>\n;     <o7>  Backdoor Comparison Key 7.  <0x0-0xFF:2>\nBackDoorK0      EQU     0xFF\nBackDoorK1      EQU     0xFF\nBackDoorK2      EQU     0xFF\nBackDoorK3      EQU     0xFF\nBackDoorK4      EQU     0xFF\nBackDoorK5      EQU     0xFF\nBackDoorK6      EQU     0xFF\nBackDoorK7      EQU     0xFF\n;   </h>\n;   <h> Program flash protection bytes (FPROT)\n;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.\n;     <i> Each bit protects a 1/32 region of the program flash memory.\n;     <h> FPROT0\n;       <i> Program Flash Region Protect Register 0\n;       <i> 1/32 - 8/32 region\n;       <o.0>   FPROT0.0\n;       <o.1>   FPROT0.1\n;       <o.2>   FPROT0.2\n;       <o.3>   FPROT0.3\n;       <o.4>   FPROT0.4\n;       <o.5>   FPROT0.5\n;       <o.6>   FPROT0.6\n;       <o.7>   FPROT0.7\nnFPROT0         EQU     0x00\nFPROT0          EQU     nFPROT0:EOR:0xFF\n;     </h>\n;     <h> FPROT1\n;       <i> Program Flash Region Protect Register 1\n;       <i> 9/32 - 16/32 region\n;       <o.0>   FPROT1.0\n;       <o.1>   FPROT1.1\n;       <o.2>   FPROT1.2\n;       <o.3>   FPROT1.3\n;       <o.4>   FPROT1.4\n;       <o.5>   FPROT1.5\n;       <o.6>   FPROT1.6\n;       <o.7>   FPROT1.7\nnFPROT1         EQU     0x00\nFPROT1          EQU     nFPROT1:EOR:0xFF\n;     </h>\n;     <h> FPROT2\n;       <i> Program Flash Region Protect Register 2\n;       <i> 17/32 - 24/32 region\n;       <o.0>   FPROT2.0\n;       <o.1>   FPROT2.1\n;       <o.2>   FPROT2.2\n;       <o.3>   FPROT2.3\n;       <o.4>   FPROT2.4\n;       <o.5>   FPROT2.5\n;       <o.6>   FPROT2.6\n;       <o.7>   FPROT2.7\nnFPROT2         EQU     0x00\nFPROT2          EQU     nFPROT2:EOR:0xFF\n;     </h>\n;     <h> FPROT3\n;       <i> Program Flash Region Protect Register 3\n;       <i> 25/32 - 32/32 region\n;       <o.0>   FPROT3.0\n;       <o.1>   FPROT3.1\n;       <o.2>   FPROT3.2\n;       <o.3>   FPROT3.3\n;       <o.4>   FPROT3.4\n;       <o.5>   FPROT3.5\n;       <o.6>   FPROT3.6\n;       <o.7>   FPROT3.7\nnFPROT3         EQU     0x00\nFPROT3          EQU     nFPROT3:EOR:0xFF\n;     </h>\n;   </h>\n;   <h> Data flash protection byte (FDPROT)\n;     <i> Each bit protects a 1/8 region of the data flash memory.\n;     <i> (Program flash only devices: Reserved)\n;       <o.0>   FDPROT.0\n;       <o.1>   FDPROT.1\n;       <o.2>   FDPROT.2\n;       <o.3>   FDPROT.3\n;       <o.4>   FDPROT.4\n;       <o.5>   FDPROT.5\n;       <o.6>   FDPROT.6\n;       <o.7>   FDPROT.7\nnFDPROT         EQU     0x00\nFDPROT          EQU     nFDPROT:EOR:0xFF\n;   </h>\n;   <h> EEPROM protection byte (FEPROT)\n;     <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.\n;     <i> (Program flash only devices: Reserved)\n;       <o.0>   FEPROT.0\n;       <o.1>   FEPROT.1\n;       <o.2>   FEPROT.2\n;       <o.3>   FEPROT.3\n;       <o.4>   FEPROT.4\n;       <o.5>   FEPROT.5\n;       <o.6>   FEPROT.6\n;       <o.7>   FEPROT.7\nnFEPROT         EQU     0x00\nFEPROT          EQU     nFEPROT:EOR:0xFF\n;   </h>\n;   <h> Flash nonvolatile option byte (FOPT)\n;     <i> Allows the user to customize the operation of the MCU at boot time.\n;     <o.0> LPBOOT\n;       <0=> Low-power boot\n;       <1=> Normal boot\n;     <o.1> EZPORT_DIS\n;       <0=> EzPort operation is disabled\n;       <1=> EzPort operation is enabled\nFOPT          EQU     0xFD\n;   </h>\n;   <h> Flash security byte (FSEC)\n;     <i> WARNING: If SEC field is configured as \"MCU security status is secure\" and MEEN field is configured as \"Mass erase is disabled\",\n;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!\n;     <o.0..1> SEC\n;       <2=> MCU security status is unsecure\n;       <3=> MCU security status is secure\n;         <i> Flash Security\n;     <o.2..3> FSLACC\n;       <2=> Freescale factory access denied\n;       <3=> Freescale factory access granted\n;         <i> Freescale Failure Analysis Access Code\n;     <o.4..5> MEEN\n;       <2=> Mass erase is disabled\n;       <3=> Mass erase is enabled\n;     <o.6..7> KEYEN\n;       <2=> Backdoor key access enabled\n;       <3=> Backdoor key access disabled\n;         <i> Backdoor Key Security Enable\nFSEC          EQU     0xFE\n;   </h>\n; </h>\n\n#ifndef RAM_TARGET\n                AREA    FlashConfig, DATA, READONLY\n__FlashConfig\n                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3\n                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7\n                DCB     FPROT0    , FPROT1    , FPROT2    , FPROT3\n                DCB     FSEC      , FOPT      , FEPROT    , FDPROT\n#endif\n\n\n                AREA    |.text|, CODE, READONLY\n\n\nReset_Handler   PROC\n                ALIGN   4\n                EXPORT  Reset_Handler             [WEAK]\n                IMPORT  SystemInit\n\n#ifndef RAM_TARGET\n                REQUIRE FlashConfig\n#endif\n\n\n                CPSID   I               ; Mask interrupts\n\n#ifdef START_FROM_FLASH\n                ; Init ECC RAM\n                LDR     R1, =__RAM_START\n                LDR     R1, [R1]\n                LDR     R2, =__RAM_END\n                LDR     R2, [R2]\n                SUBS    R2, R1\n                SUBS    R2, #1\n                BLE LC5\n\n                MOVS    R0, #0\n                MOVS    R3, #4\nLC4\n                STR     R0, [R1]\n                ADD     R1, R1, R3\n                SUBS    R2, #4\n                BGE LC4\nLC5\n                NOP\n#endif\n\n                LDR     R0, =0xE000ED08\n                LDR     R1, =__Vectors\n                STR     R1, [R0]\n                LDR     R2, [R1]\n                MSR     MSP, R2\n                LDR     R0, =SystemInit\n                BLX     R0\n                LDR     R0, =init_data_bss\n                BLX     R0\n                CPSIE   i               ; Unmask interrupts\n                LDR     R0, =__main\n                BLX     R0\n                ENDP\n\nNMI_Handler\\\n                PROC\n                EXPORT  NMI_Handler         [WEAK]\n                B       .\n                ENDP\nHardFault_Handler\\\n                PROC\n                EXPORT  HardFault_Handler         [WEAK]\n                B       .\n                ENDP\nMemManage_Handler\\\n                PROC\n                EXPORT  MemManage_Handler         [WEAK]\n                B       .\n                ENDP\nBusFault_Handler\\\n                PROC\n                EXPORT  BusFault_Handler         [WEAK]\n                B       .\n                ENDP\nUsageFault_Handler\\\n                PROC\n                EXPORT  UsageFault_Handler         [WEAK]\n                B       .\n                ENDP\nSVC_Handler\\\n                PROC\n                EXPORT  SVC_Handler         [WEAK]\n                B       .\n                ENDP\nDebugMon_Handler\\\n                PROC\n                EXPORT  DebugMon_Handler         [WEAK]\n                B       .\n                ENDP\nPendSV_Handler\\\n                PROC\n                EXPORT  PendSV_Handler         [WEAK]\n                B       .\n                ENDP\nSysTick_Handler\\\n                PROC\n                EXPORT  SysTick_Handler         [WEAK]\n                B       .\n                ENDP\nDefaultISR\\\n                PROC\n                EXPORT  DefaultISR         [WEAK]\n                B       .\n                ENDP\nDefault_Handler PROC\n                EXPORT  DMA0_IRQHandler                      [WEAK]\n                EXPORT  DMA1_IRQHandler                      [WEAK]\n                EXPORT  DMA2_IRQHandler                      [WEAK]\n                EXPORT  DMA3_IRQHandler                      [WEAK]\n                EXPORT  DMA4_IRQHandler                      [WEAK]\n                EXPORT  DMA5_IRQHandler                      [WEAK]\n                EXPORT  DMA6_IRQHandler                      [WEAK]\n                EXPORT  DMA7_IRQHandler                      [WEAK]\n                EXPORT  DMA8_IRQHandler                      [WEAK]\n                EXPORT  DMA9_IRQHandler                      [WEAK]\n                EXPORT  DMA10_IRQHandler                     [WEAK]\n                EXPORT  DMA11_IRQHandler                     [WEAK]\n                EXPORT  DMA12_IRQHandler                     [WEAK]\n                EXPORT  DMA13_IRQHandler                     [WEAK]\n                EXPORT  DMA14_IRQHandler                     [WEAK]\n                EXPORT  DMA15_IRQHandler                     [WEAK]\n                EXPORT  DMA_Error_IRQHandler                 [WEAK]\n                EXPORT  MCM_IRQHandler                       [WEAK]\n                EXPORT  FTFC_IRQHandler                      [WEAK]\n                EXPORT  Read_Collision_IRQHandler            [WEAK]\n                EXPORT  LVD_LVW_IRQHandler                   [WEAK]\n                EXPORT  FTFC_Fault_IRQHandler                [WEAK]\n                EXPORT  WDOG_EWM_IRQHandler                  [WEAK]\n                EXPORT  RCM_IRQHandler                       [WEAK]\n                EXPORT  LPI2C0_Master_IRQHandler             [WEAK]\n                EXPORT  LPI2C0_Slave_IRQHandler              [WEAK]\n                EXPORT  LPSPI0_IRQHandler                    [WEAK]\n                EXPORT  LPSPI1_IRQHandler                    [WEAK]\n                EXPORT  LPSPI2_IRQHandler                    [WEAK]\n                EXPORT  Reserved45_IRQHandler                [WEAK]\n                EXPORT  Reserved46_IRQHandler                [WEAK]\n                EXPORT  LPUART0_RxTx_IRQHandler              [WEAK]\n                EXPORT  Reserved48_IRQHandler                [WEAK]\n                EXPORT  LPUART1_RxTx_IRQHandler              [WEAK]\n                EXPORT  Reserved50_IRQHandler                [WEAK]\n                EXPORT  LPUART2_RxTx_IRQHandler              [WEAK]\n                EXPORT  Reserved52_IRQHandler                [WEAK]\n                EXPORT  Reserved53_IRQHandler                [WEAK]\n                EXPORT  Reserved54_IRQHandler                [WEAK]\n                EXPORT  ADC0_IRQHandler                      [WEAK]\n                EXPORT  ADC1_IRQHandler                      [WEAK]\n                EXPORT  CMP0_IRQHandler                      [WEAK]\n                EXPORT  Reserved58_IRQHandler                [WEAK]\n                EXPORT  Reserved59_IRQHandler                [WEAK]\n                EXPORT  ERM_single_fault_IRQHandler          [WEAK]\n                EXPORT  ERM_double_fault_IRQHandler          [WEAK]\n                EXPORT  RTC_IRQHandler                       [WEAK]\n                EXPORT  RTC_Seconds_IRQHandler               [WEAK]\n                EXPORT  LPIT0_Ch0_IRQHandler                 [WEAK]\n                EXPORT  LPIT0_Ch1_IRQHandler                 [WEAK]\n                EXPORT  LPIT0_Ch2_IRQHandler                 [WEAK]\n                EXPORT  LPIT0_Ch3_IRQHandler                 [WEAK]\n                EXPORT  PDB0_IRQHandler                      [WEAK]\n                EXPORT  Reserved69_IRQHandler                [WEAK]\n                EXPORT  Reserved70_IRQHandler                [WEAK]\n                EXPORT  Reserved71_IRQHandler                [WEAK]\n                EXPORT  Reserved72_IRQHandler                [WEAK]\n                EXPORT  SCG_IRQHandler                       [WEAK]\n                EXPORT  LPTMR0_IRQHandler                    [WEAK]\n                EXPORT  PORTA_IRQHandler                     [WEAK]\n                EXPORT  PORTB_IRQHandler                     [WEAK]\n                EXPORT  PORTC_IRQHandler                     [WEAK]\n                EXPORT  PORTD_IRQHandler                     [WEAK]\n                EXPORT  PORTE_IRQHandler                     [WEAK]\n                EXPORT  SWI_IRQHandler                       [WEAK]\n                EXPORT  Reserved81_IRQHandler                [WEAK]\n                EXPORT  Reserved82_IRQHandler                [WEAK]\n                EXPORT  Reserved83_IRQHandler                [WEAK]\n                EXPORT  PDB1_IRQHandler                      [WEAK]\n                EXPORT  FLEXIO_IRQHandler                    [WEAK]\n                EXPORT  Reserved86_IRQHandler                [WEAK]\n                EXPORT  Reserved87_IRQHandler                [WEAK]\n                EXPORT  Reserved88_IRQHandler                [WEAK]\n                EXPORT  Reserved89_IRQHandler                [WEAK]\n                EXPORT  Reserved90_IRQHandler                [WEAK]\n                EXPORT  Reserved91_IRQHandler                [WEAK]\n                EXPORT  Reserved92_IRQHandler                [WEAK]\n                EXPORT  Reserved93_IRQHandler                [WEAK]\n                EXPORT  CAN0_ORed_IRQHandler                 [WEAK]\n                EXPORT  CAN0_Error_IRQHandler                [WEAK]\n                EXPORT  CAN0_Wake_Up_IRQHandler              [WEAK]\n                EXPORT  CAN0_ORed_0_15_MB_IRQHandler         [WEAK]\n                EXPORT  CAN0_ORed_16_31_MB_IRQHandler        [WEAK]\n                EXPORT  Reserved99_IRQHandler                [WEAK]\n                EXPORT  Reserved100_IRQHandler               [WEAK]\n                EXPORT  CAN1_ORed_IRQHandler                 [WEAK]\n                EXPORT  CAN1_Error_IRQHandler                [WEAK]\n                EXPORT  Reserved103_IRQHandler               [WEAK]\n                EXPORT  CAN1_ORed_0_15_MB_IRQHandler         [WEAK]\n                EXPORT  Reserved105_IRQHandler               [WEAK]\n                EXPORT  Reserved106_IRQHandler               [WEAK]\n                EXPORT  Reserved107_IRQHandler               [WEAK]\n                EXPORT  CAN2_ORed_IRQHandler                 [WEAK]\n                EXPORT  CAN2_Error_IRQHandler                [WEAK]\n                EXPORT  Reserved110_IRQHandler               [WEAK]\n                EXPORT  CAN2_ORed_0_15_MB_IRQHandler         [WEAK]\n                EXPORT  Reserved112_IRQHandler               [WEAK]\n                EXPORT  Reserved113_IRQHandler               [WEAK]\n                EXPORT  Reserved114_IRQHandler               [WEAK]\n                EXPORT  FTM0_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM0_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM0_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM0_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM0_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM0_Ovf_Reload_IRQHandler           [WEAK]\n                EXPORT  FTM1_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM1_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM1_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM1_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM1_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM1_Ovf_Reload_IRQHandler           [WEAK]\n                EXPORT  FTM2_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM2_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM2_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM2_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM2_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM2_Ovf_Reload_IRQHandler           [WEAK]\n                EXPORT  FTM3_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM3_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM3_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM3_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM3_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM3_Ovf_Reload_IRQHandler           [WEAK]\nDMA0_IRQHandler                                  ; DMA channel 0 transfer complete\nDMA1_IRQHandler                                  ; DMA channel 1 transfer complete\nDMA2_IRQHandler                                  ; DMA channel 2 transfer complete\nDMA3_IRQHandler                                  ; DMA channel 3 transfer complete\nDMA4_IRQHandler                                  ; DMA channel 4 transfer complete\nDMA5_IRQHandler                                  ; DMA channel 5 transfer complete\nDMA6_IRQHandler                                  ; DMA channel 6 transfer complete\nDMA7_IRQHandler                                  ; DMA channel 7 transfer complete\nDMA8_IRQHandler                                  ; DMA channel 8 transfer complete\nDMA9_IRQHandler                                  ; DMA channel 9 transfer complete\nDMA10_IRQHandler                                 ; DMA channel 10 transfer complete\nDMA11_IRQHandler                                 ; DMA channel 11 transfer complete\nDMA12_IRQHandler                                 ; DMA channel 12 transfer complete\nDMA13_IRQHandler                                 ; DMA channel 13 transfer complete\nDMA14_IRQHandler                                 ; DMA channel 14 transfer complete\nDMA15_IRQHandler                                 ; DMA channel 15 transfer complete\nDMA_Error_IRQHandler                             ; DMA error interrupt channels 0-15\nMCM_IRQHandler                                   ; FPU sources\nFTFC_IRQHandler                                  ; FTFC Command complete\nRead_Collision_IRQHandler                        ; FTFC Read collision\nLVD_LVW_IRQHandler                               ; PMC Low voltage detect interrupt\nFTFC_Fault_IRQHandler                            ; FTFC Double bit fault detect\nWDOG_EWM_IRQHandler                              ; Single interrupt vector for WDOG and EWM\nRCM_IRQHandler                                   ; RCM Asynchronous Interrupt\nLPI2C0_Master_IRQHandler                         ; LPI2C0 Master Interrupt\nLPI2C0_Slave_IRQHandler                          ; LPI2C0 Slave Interrupt\nLPSPI0_IRQHandler                                ; LPSPI0 Interrupt\nLPSPI1_IRQHandler                                ; LPSPI1 Interrupt\nLPSPI2_IRQHandler                                ; LPSPI2 Interrupt\nReserved45_IRQHandler                            ; Reserved Interrupt 45\nReserved46_IRQHandler                            ; Reserved Interrupt 46\nLPUART0_RxTx_IRQHandler                          ; LPUART0 Transmit / Receive Interrupt\nReserved48_IRQHandler                            ; Reserved Interrupt 48\nLPUART1_RxTx_IRQHandler                          ; LPUART1 Transmit / Receive  Interrupt\nReserved50_IRQHandler                            ; Reserved Interrupt 50\nLPUART2_RxTx_IRQHandler                          ; LPUART2 Transmit / Receive  Interrupt\nReserved52_IRQHandler                            ; Reserved Interrupt 52\nReserved53_IRQHandler                            ; Reserved Interrupt 53\nReserved54_IRQHandler                            ; Reserved Interrupt 54\nADC0_IRQHandler                                  ; ADC0 interrupt request.\nADC1_IRQHandler                                  ; ADC1 interrupt request.\nCMP0_IRQHandler                                  ; CMP0 interrupt request\nReserved58_IRQHandler                            ; Reserved Interrupt 58\nReserved59_IRQHandler                            ; Reserved Interrupt 59\nERM_single_fault_IRQHandler                      ; ERM single bit error correction\nERM_double_fault_IRQHandler                      ; ERM double bit error non-correctable\nRTC_IRQHandler                                   ; RTC alarm interrupt\nRTC_Seconds_IRQHandler                           ; RTC seconds interrupt\nLPIT0_Ch0_IRQHandler                             ; LPIT0 channel 0 overflow interrupt\nLPIT0_Ch1_IRQHandler                             ; LPIT0 channel 1 overflow interrupt\nLPIT0_Ch2_IRQHandler                             ; LPIT0 channel 2 overflow interrupt\nLPIT0_Ch3_IRQHandler                             ; LPIT0 channel 3 overflow interrupt\nPDB0_IRQHandler                                  ; PDB0 interrupt\nReserved69_IRQHandler                            ; Reserved Interrupt 69\nReserved70_IRQHandler                            ; Reserved Interrupt 70\nReserved71_IRQHandler                            ; Reserved Interrupt 71\nReserved72_IRQHandler                            ; Reserved Interrupt 72\nSCG_IRQHandler                                   ; SCG bus interrupt request\nLPTMR0_IRQHandler                                ; LPTIMER interrupt request\nPORTA_IRQHandler                                 ; Port A pin detect interrupt\nPORTB_IRQHandler                                 ; Port B pin detect interrupt\nPORTC_IRQHandler                                 ; Port C pin detect interrupt\nPORTD_IRQHandler                                 ; Port D pin detect interrupt\nPORTE_IRQHandler                                 ; Port E pin detect interrupt\nSWI_IRQHandler                                   ; Software interrupt\nReserved81_IRQHandler                            ; Reserved Interrupt 81\nReserved82_IRQHandler                            ; Reserved Interrupt 82\nReserved83_IRQHandler                            ; Reserved Interrupt 83\nPDB1_IRQHandler                                  ; PDB1 interrupt\nFLEXIO_IRQHandler                                ; FlexIO Interrupt\nReserved86_IRQHandler                            ; Reserved Interrupt 86\nReserved87_IRQHandler                            ; Reserved Interrupt 87\nReserved88_IRQHandler                            ; Reserved Interrupt 88\nReserved89_IRQHandler                            ; Reserved Interrupt 89\nReserved90_IRQHandler                            ; Reserved Interrupt 90\nReserved91_IRQHandler                            ; Reserved Interrupt 91\nReserved92_IRQHandler                            ; Reserved Interrupt 92\nReserved93_IRQHandler                            ; Reserved Interrupt 93\nCAN0_ORed_IRQHandler                             ; CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\nCAN0_Error_IRQHandler                            ; CAN0 Interrupt indicating that errors were detected on the CAN bus\nCAN0_Wake_Up_IRQHandler                          ; CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode\nCAN0_ORed_0_15_MB_IRQHandler                     ; CAN0 OR'ed Message buffer (0-15)\nCAN0_ORed_16_31_MB_IRQHandler                    ; CAN0 OR'ed Message buffer (16-31)\nReserved99_IRQHandler                            ; Reserved Interrupt 99\nReserved100_IRQHandler                           ; Reserved Interrupt 100\nCAN1_ORed_IRQHandler                             ; CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\nCAN1_Error_IRQHandler                            ; CAN1 Interrupt indicating that errors were detected on the CAN bus\nReserved103_IRQHandler                           ; Reserved Interrupt 103\nCAN1_ORed_0_15_MB_IRQHandler                     ; CAN1 OR'ed Interrupt for Message buffer (0-15)\nReserved105_IRQHandler                           ; Reserved Interrupt 105\nReserved106_IRQHandler                           ; Reserved Interrupt 106\nReserved107_IRQHandler                           ; Reserved Interrupt 107\nCAN2_ORed_IRQHandler                             ; CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\nCAN2_Error_IRQHandler                            ; CAN2 Interrupt indicating that errors were detected on the CAN bus\nReserved110_IRQHandler                           ; Reserved Interrupt 110\nCAN2_ORed_0_15_MB_IRQHandler                     ; CAN2 OR'ed Message buffer (0-15)\nReserved112_IRQHandler                           ; Reserved Interrupt 112\nReserved113_IRQHandler                           ; Reserved Interrupt 113\nReserved114_IRQHandler                           ; Reserved Interrupt 114\nFTM0_Ch0_Ch1_IRQHandler                          ; FTM0 Channel 0 and 1 interrupt\nFTM0_Ch2_Ch3_IRQHandler                          ; FTM0 Channel 2 and 3 interrupt\nFTM0_Ch4_Ch5_IRQHandler                          ; FTM0 Channel 4 and 5 interrupt\nFTM0_Ch6_Ch7_IRQHandler                          ; FTM0 Channel 6 and 7 interrupt\nFTM0_Fault_IRQHandler                            ; FTM0 Fault interrupt\nFTM0_Ovf_Reload_IRQHandler                       ; FTM0 Counter overflow and Reload interrupt\nFTM1_Ch0_Ch1_IRQHandler                          ; FTM1 Channel 0 and 1 interrupt\nFTM1_Ch2_Ch3_IRQHandler                          ; FTM1 Channel 2 and 3 interrupt\nFTM1_Ch4_Ch5_IRQHandler                          ; FTM1 Channel 4 and 5 interrupt\nFTM1_Ch6_Ch7_IRQHandler                          ; FTM1 Channel 6 and 7 interrupt\nFTM1_Fault_IRQHandler                            ; FTM1 Fault interrupt\nFTM1_Ovf_Reload_IRQHandler                       ; FTM1 Counter overflow and Reload interrupt\nFTM2_Ch0_Ch1_IRQHandler                          ; FTM2 Channel 0 and 1 interrupt\nFTM2_Ch2_Ch3_IRQHandler                          ; FTM2 Channel 2 and 3 interrupt\nFTM2_Ch4_Ch5_IRQHandler                          ; FTM2 Channel 4 and 5 interrupt\nFTM2_Ch6_Ch7_IRQHandler                          ; FTM2 Channel 6 and 7 interrupt\nFTM2_Fault_IRQHandler                            ; FTM2 Fault interrupt\nFTM2_Ovf_Reload_IRQHandler                       ; FTM2 Counter overflow and Reload interrupt\nFTM3_Ch0_Ch1_IRQHandler                          ; FTM3 Channel 0 and 1 interrupt\nFTM3_Ch2_Ch3_IRQHandler                          ; FTM3 Channel 2 and 3 interrupt\nFTM3_Ch4_Ch5_IRQHandler                          ; FTM3 Channel 4 and 5 interrupt\nFTM3_Ch6_Ch7_IRQHandler                          ; FTM3 Channel 6 and 7 interrupt\nFTM3_Fault_IRQHandler                            ; FTM3 Fault interrupt\nFTM3_Ovf_Reload_IRQHandler                       ; FTM3 Counter overflow and Reload interrupt\n\n                B       .\n\n                ENDP\n\n                ALIGN\n                END\n",
                "afterChangeFileContent": ";\n; modified by ARM\n;\n; ---------------------------------------------------------------------------------------\n;  @file:    startup_S32K144.S\n;  @purpose: ARM Compiler Collection Startup File\n;            S32K144\n;  @version: 2.2.0\n;  @date:    2017-1-10\n;  @build:   b170107\n; ---------------------------------------------------------------------------------------\n;\n; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc.\n; Copyright 2016-2017 NXP\n; All rights reserved.\n;\n; NXP Confidential. This software is owned or controlled by NXP and may only be\n; used strictly in accordance with the applicable license terms. By expressly\n; accepting such terms or by downloading, installing, activating and/or otherwise\n; using the software, you are agreeing that you have read, and that you agree to\n; comply with and are bound by, such license terms. If you do not agree to be\n; bound by the applicable license terms, then you may not retain, install,\n; activate or otherwise use the software. The production use license in\n; Section 2.3 is expressly granted for this software.\n;***************************************************************************\n; Version: ARMC Compiler Collection\n;***************************************************************************\n\n;// ------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n\n\n                PRESERVE8\n                THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n                AREA    |.text|, CODE, READONLY\n                EXPORT  __Vectors\n\n                EXPORT __RAM_VECTOR_TABLE_SIZE\n                EXPORT __VECTOR_RAM\n                EXPORT __VECTOR_ROM\n\n                EXPORT __BSS_START\n                EXPORT __BSS_END\n\n                EXPORT __CODE_ROM\n                EXPORT __CODE_END\n                EXPORT __CODE_RAM\n\n                EXPORT __DATA_ROM\n                EXPORT __DATA_END\n                EXPORT __DATA_RAM\n                EXPORT __VECTOR_ROM_START\n                EXPORT __VECTOR_ROM_END\n                EXPORT __DATA_RAM_START\n                EXPORT __DATA_RAM_END\n                EXPORT __CUSTOM_SECTION_START\n                EXPORT __CUSTOM_SECTION_END\n                EXPORT __CODE_RAM_START\n                EXPORT __CODE_RAM_END\n\n                EXPORT __RAM_START\n                EXPORT __RAM_END\n\n                IMPORT init_data_bss\n                IMPORT  main\n                IMPORT  __main\n                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|\n                IMPORT  |Image$$RW_m_data_2$$ZI$$Base|\n                IMPORT  |Image$$RW_m_data_2$$ZI$$Limit|\n\n                IMPORT  |Image$$ER_m_text_const$$Base|\n                IMPORT  |Image$$ER_m_text_const$$Limit|\n\n                IMPORT  |Image$$RW_m_data$$Base|\n\n                IMPORT  |Image$$ER_m_text_const$$Base|\n                IMPORT  |Image$$ER_m_text_const$$Limit|\n\n                IMPORT  |Image$$RW_m_data$$Length|\n                IMPORT |Image$$RW_m_code$$Base|\n                IMPORT |Image$$RW_m_code$$Length|\n                IMPORT |Image$$ER_m_text$$Limit|\n\n                IMPORT |Image$$VECTOR_RAM$$Length|\n                IMPORT |Image$$VECTOR_RAM$$Base|\n\n                IMPORT |Image$$VECTOR_ROM$$Length|\n                IMPORT |Image$$VECTOR_ROM$$Base|\n                IMPORT |Image$$RW_m_custom_section$$Base|\n                IMPORT |Image$$RW_m_custom_section$$Limit|\n\n                IMPORT |Image$$RW_m_data$$Limit|\n                IMPORT |Image$$RW_m_code$$Limit|\n                IMPORT |Image$$VECTOR_ROM$$Limit|\n\n                IMPORT |Image$$ARM_LIB_STACK$$Limit|\n__RAM_VECTOR_TABLE_SIZE DCD |Image$$VECTOR_ROM$$Length|\n__VECTOR_RAM DCD |Image$$VECTOR_RAM$$Base|\n__VECTOR_ROM DCD |Image$$VECTOR_ROM$$Base|\n__VECTOR_ROM_START DCD |Image$$VECTOR_ROM$$Base|\n__VECTOR_ROM_END DCD |Image$$VECTOR_ROM$$Limit|\n\n__CODE_ROM DCD  |Image$$RW_m_data$$Length|+ |Image$$ER_m_text$$Limit|\n__CODE_END DCD  |Image$$RW_m_data$$Length|+ |Image$$ER_m_text$$Limit| + |Image$$RW_m_code$$Length|\n__CODE_RAM DCD |Image$$RW_m_code$$Base|\n__CODE_RAM_START DCD |Image$$RW_m_code$$Base|\n__CODE_RAM_END DCD |Image$$RW_m_code$$Limit|\n\n__BSS_START DCD  |Image$$RW_m_data_2$$ZI$$Base|\n__BSS_END DCD  |Image$$RW_m_data_2$$ZI$$Limit|\n\n__DATA_RAM DCD  |Image$$RW_m_data$$Base|\n__DATA_RAM_START DCD  |Image$$RW_m_data$$Base|\n__DATA_RAM_END DCD  |Image$$RW_m_data$$Limit|\n__DATA_ROM DCD  |Image$$ER_m_text$$Limit|\n__DATA_END DCD  |Image$$RW_m_data$$Length|+ |Image$$ER_m_text$$Limit|\n__CUSTOM_SECTION_START DCD |Image$$RW_m_custom_section$$Base|\n__CUSTOM_SECTION_END DCD |Image$$RW_m_custom_section$$Limit|\n\n    IF :DEF:__flash_vector_table__\n__RAM_START DCD |Image$$RW_m_data$$Base|\n    ELSE\n__RAM_START DCD |Image$$VECTOR_RAM$$Base|\n    ENDIF\n__RAM_END   DCD |Image$$ARM_LIB_STACK$$Limit|\n\n\t\tAREA    RESET, DATA, READONLY\n__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit|   ; Top of Stack\n                DCD     Reset_Handler                       ; Reset Handler\n                DCD     NMI_Handler                         ; NMI Handler\n                DCD     HardFault_Handler                   ; Hard Fault Handler\n                DCD     MemManage_Handler                   ; MPU Fault Handler\n                DCD     BusFault_Handler                    ; Bus Fault Handler\n                DCD     UsageFault_Handler                  ; Usage Fault Handler\n                DCD     0                                   ; Reserved\n                DCD     0                                   ; Reserved\n                DCD     0                                   ; Reserved\n                DCD     0                                   ; Reserved\n                DCD     SVC_Handler                         ; SVCall Handler\n                DCD     DebugMon_Handler                    ; Debug Monitor Handler\n                DCD     0                                   ; Reserved\n                DCD     PendSV_Handler                      ; PendSV Handler\n                DCD     SysTick_Handler                     ; SysTick Handler\n\n                                                            ; External Interrupts\n    DCD   DMA0_IRQHandler                                 ; DMA channel 0 transfer complete\n    DCD   DMA1_IRQHandler                                 ; DMA channel 1 transfer complete\n    DCD   DMA2_IRQHandler                                 ; DMA channel 2 transfer complete\n    DCD   DMA3_IRQHandler                                 ; DMA channel 3 transfer complete\n    DCD   DMA4_IRQHandler                                 ; DMA channel 4 transfer complete\n    DCD   DMA5_IRQHandler                                 ; DMA channel 5 transfer complete\n    DCD   DMA6_IRQHandler                                 ; DMA channel 6 transfer complete\n    DCD   DMA7_IRQHandler                                 ; DMA channel 7 transfer complete\n    DCD   DMA8_IRQHandler                                 ; DMA channel 8 transfer complete\n    DCD   DMA9_IRQHandler                                 ; DMA channel 9 transfer complete\n    DCD   DMA10_IRQHandler                                ; DMA channel 10 transfer complete\n    DCD   DMA11_IRQHandler                                ; DMA channel 11 transfer complete\n    DCD   DMA12_IRQHandler                                ; DMA channel 12 transfer complete\n    DCD   DMA13_IRQHandler                                ; DMA channel 13 transfer complete\n    DCD   DMA14_IRQHandler                                ; DMA channel 14 transfer complete\n    DCD   DMA15_IRQHandler                                ; DMA channel 15 transfer complete\n    DCD   DMA_Error_IRQHandler                            ; DMA error interrupt channels 0-15\n    DCD   MCM_IRQHandler                                  ; FPU sources\n    DCD   FTFC_IRQHandler                                 ; FTFC Command complete\n    DCD   Read_Collision_IRQHandler                       ; FTFC Read collision\n    DCD   LVD_LVW_IRQHandler                              ; PMC Low voltage detect interrupt\n    DCD   FTFC_Fault_IRQHandler                           ; FTFC Double bit fault detect\n    DCD   WDOG_EWM_IRQHandler                             ; Single interrupt vector for WDOG and EWM\n    DCD   RCM_IRQHandler                                  ; RCM Asynchronous Interrupt\n    DCD   LPI2C0_Master_IRQHandler                        ; LPI2C0 Master Interrupt\n    DCD   LPI2C0_Slave_IRQHandler                         ; LPI2C0 Slave Interrupt\n    DCD   LPSPI0_IRQHandler                               ; LPSPI0 Interrupt\n    DCD   LPSPI1_IRQHandler                               ; LPSPI1 Interrupt\n    DCD   LPSPI2_IRQHandler                               ; LPSPI2 Interrupt\n    DCD   Reserved45_IRQHandler                           ; Reserved Interrupt 45\n    DCD   Reserved46_IRQHandler                           ; Reserved Interrupt 46\n    DCD   LPUART0_RxTx_IRQHandler                         ; LPUART0 Transmit / Receive Interrupt\n    DCD   Reserved48_IRQHandler                           ; Reserved Interrupt 48\n    DCD   LPUART1_RxTx_IRQHandler                         ; LPUART1 Transmit / Receive  Interrupt\n    DCD   Reserved50_IRQHandler                           ; Reserved Interrupt 50\n    DCD   LPUART2_RxTx_IRQHandler                         ; LPUART2 Transmit / Receive  Interrupt\n    DCD   Reserved52_IRQHandler                           ; Reserved Interrupt 52\n    DCD   Reserved53_IRQHandler                           ; Reserved Interrupt 53\n    DCD   Reserved54_IRQHandler                           ; Reserved Interrupt 54\n    DCD   ADC0_IRQHandler                                 ; ADC0 interrupt request.\n    DCD   ADC1_IRQHandler                                 ; ADC1 interrupt request.\n    DCD   CMP0_IRQHandler                                 ; CMP0 interrupt request\n    DCD   Reserved58_IRQHandler                           ; Reserved Interrupt 58\n    DCD   Reserved59_IRQHandler                           ; Reserved Interrupt 59\n    DCD   ERM_single_fault_IRQHandler                     ; ERM single bit error correction\n    DCD   ERM_double_fault_IRQHandler                     ; ERM double bit error non-correctable\n    DCD   RTC_IRQHandler                                  ; RTC alarm interrupt\n    DCD   RTC_Seconds_IRQHandler                          ; RTC seconds interrupt\n    DCD   LPIT0_Ch0_IRQHandler                            ; LPIT0 channel 0 overflow interrupt\n    DCD   LPIT0_Ch1_IRQHandler                            ; LPIT0 channel 1 overflow interrupt\n    DCD   LPIT0_Ch2_IRQHandler                            ; LPIT0 channel 2 overflow interrupt\n    DCD   LPIT0_Ch3_IRQHandler                            ; LPIT0 channel 3 overflow interrupt\n    DCD   PDB0_IRQHandler                                 ; PDB0 interrupt\n    DCD   Reserved69_IRQHandler                           ; Reserved Interrupt 69\n    DCD   Reserved70_IRQHandler                           ; Reserved Interrupt 70\n    DCD   Reserved71_IRQHandler                           ; Reserved Interrupt 71\n    DCD   Reserved72_IRQHandler                           ; Reserved Interrupt 72\n    DCD   SCG_IRQHandler                                  ; SCG bus interrupt request\n    DCD   LPTMR0_IRQHandler                               ; LPTIMER interrupt request\n    DCD   PORTA_IRQHandler                                ; Port A pin detect interrupt\n    DCD   PORTB_IRQHandler                                ; Port B pin detect interrupt\n    DCD   PORTC_IRQHandler                                ; Port C pin detect interrupt\n    DCD   PORTD_IRQHandler                                ; Port D pin detect interrupt\n    DCD   PORTE_IRQHandler                                ; Port E pin detect interrupt\n    DCD   SWI_IRQHandler                                  ; Software interrupt\n    DCD   Reserved81_IRQHandler                           ; Reserved Interrupt 81\n    DCD   Reserved82_IRQHandler                           ; Reserved Interrupt 82\n    DCD   Reserved83_IRQHandler                           ; Reserved Interrupt 83\n    DCD   PDB1_IRQHandler                                 ; PDB1 interrupt\n    DCD   FLEXIO_IRQHandler                               ; FlexIO Interrupt\n    DCD   Reserved86_IRQHandler                           ; Reserved Interrupt 86\n    DCD   Reserved87_IRQHandler                           ; Reserved Interrupt 87\n    DCD   Reserved88_IRQHandler                           ; Reserved Interrupt 88\n    DCD   Reserved89_IRQHandler                           ; Reserved Interrupt 89\n    DCD   Reserved90_IRQHandler                           ; Reserved Interrupt 90\n    DCD   Reserved91_IRQHandler                           ; Reserved Interrupt 91\n    DCD   Reserved92_IRQHandler                           ; Reserved Interrupt 92\n    DCD   Reserved93_IRQHandler                           ; Reserved Interrupt 93\n    DCD   CAN0_ORed_IRQHandler                            ; CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\n    DCD   CAN0_Error_IRQHandler                           ; CAN0 Interrupt indicating that errors were detected on the CAN bus\n    DCD   CAN0_Wake_Up_IRQHandler                         ; CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode\n    DCD   CAN0_ORed_0_15_MB_IRQHandler                    ; CAN0 OR'ed Message buffer (0-15)\n    DCD   CAN0_ORed_16_31_MB_IRQHandler                   ; CAN0 OR'ed Message buffer (16-31)\n    DCD   Reserved99_IRQHandler                           ; Reserved Interrupt 99\n    DCD   Reserved100_IRQHandler                          ; Reserved Interrupt 100\n    DCD   CAN1_ORed_IRQHandler                            ; CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\n    DCD   CAN1_Error_IRQHandler                           ; CAN1 Interrupt indicating that errors were detected on the CAN bus\n    DCD   Reserved103_IRQHandler                          ; Reserved Interrupt 103\n    DCD   CAN1_ORed_0_15_MB_IRQHandler                    ; CAN1 OR'ed Interrupt for Message buffer (0-15)\n    DCD   Reserved105_IRQHandler                          ; Reserved Interrupt 105\n    DCD   Reserved106_IRQHandler                          ; Reserved Interrupt 106\n    DCD   Reserved107_IRQHandler                          ; Reserved Interrupt 107\n    DCD   CAN2_ORed_IRQHandler                            ; CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\n    DCD   CAN2_Error_IRQHandler                           ; CAN2 Interrupt indicating that errors were detected on the CAN bus\n    DCD   Reserved110_IRQHandler                          ; Reserved Interrupt 110\n    DCD   CAN2_ORed_0_15_MB_IRQHandler                    ; CAN2 OR'ed Message buffer (0-15)\n    DCD   Reserved112_IRQHandler                          ; Reserved Interrupt 112\n    DCD   Reserved113_IRQHandler                          ; Reserved Interrupt 113\n    DCD   Reserved114_IRQHandler                          ; Reserved Interrupt 114\n    DCD   FTM0_Ch0_Ch1_IRQHandler                         ; FTM0 Channel 0 and 1 interrupt\n    DCD   FTM0_Ch2_Ch3_IRQHandler                         ; FTM0 Channel 2 and 3 interrupt\n    DCD   FTM0_Ch4_Ch5_IRQHandler                         ; FTM0 Channel 4 and 5 interrupt\n    DCD   FTM0_Ch6_Ch7_IRQHandler                         ; FTM0 Channel 6 and 7 interrupt\n    DCD   FTM0_Fault_IRQHandler                           ; FTM0 Fault interrupt\n    DCD   FTM0_Ovf_Reload_IRQHandler                      ; FTM0 Counter overflow and Reload interrupt\n    DCD   FTM1_Ch0_Ch1_IRQHandler                         ; FTM1 Channel 0 and 1 interrupt\n    DCD   FTM1_Ch2_Ch3_IRQHandler                         ; FTM1 Channel 2 and 3 interrupt\n    DCD   FTM1_Ch4_Ch5_IRQHandler                         ; FTM1 Channel 4 and 5 interrupt\n    DCD   FTM1_Ch6_Ch7_IRQHandler                         ; FTM1 Channel 6 and 7 interrupt\n    DCD   FTM1_Fault_IRQHandler                           ; FTM1 Fault interrupt\n    DCD   FTM1_Ovf_Reload_IRQHandler                      ; FTM1 Counter overflow and Reload interrupt\n    DCD   FTM2_Ch0_Ch1_IRQHandler                         ; FTM2 Channel 0 and 1 interrupt\n    DCD   FTM2_Ch2_Ch3_IRQHandler                         ; FTM2 Channel 2 and 3 interrupt\n    DCD   FTM2_Ch4_Ch5_IRQHandler                         ; FTM2 Channel 4 and 5 interrupt\n    DCD   FTM2_Ch6_Ch7_IRQHandler                         ; FTM2 Channel 6 and 7 interrupt\n    DCD   FTM2_Fault_IRQHandler                           ; FTM2 Fault interrupt\n    DCD   FTM2_Ovf_Reload_IRQHandler                      ; FTM2 Counter overflow and Reload interrupt\n    DCD   FTM3_Ch0_Ch1_IRQHandler                         ; FTM3 Channel 0 and 1 interrupt\n    DCD   FTM3_Ch2_Ch3_IRQHandler                         ; FTM3 Channel 2 and 3 interrupt\n    DCD   FTM3_Ch4_Ch5_IRQHandler                         ; FTM3 Channel 4 and 5 interrupt\n    DCD   FTM3_Ch6_Ch7_IRQHandler                         ; FTM3 Channel 6 and 7 interrupt\n    DCD   FTM3_Fault_IRQHandler                           ; FTM3 Fault interrupt\n    DCD   FTM3_Ovf_Reload_IRQHandler                      ; FTM3 Counter overflow and Reload interrupt\n    DCD   DefaultISR                                      ; Default ISR\n__Vectors_End\n__Vectors_Size  EQU     __Vectors_End - __Vectors\n\n; <h> Flash Configuration\n;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)\n;   <i> and security information that allows the MCU to restrict access to the FTFL module.\n;   <h> Backdoor Comparison Key\n;     <o0>  Backdoor Comparison Key 0.  <0x0-0xFF:2>\n;     <o1>  Backdoor Comparison Key 1.  <0x0-0xFF:2>\n;     <o2>  Backdoor Comparison Key 2.  <0x0-0xFF:2>\n;     <o3>  Backdoor Comparison Key 3.  <0x0-0xFF:2>\n;     <o4>  Backdoor Comparison Key 4.  <0x0-0xFF:2>\n;     <o5>  Backdoor Comparison Key 5.  <0x0-0xFF:2>\n;     <o6>  Backdoor Comparison Key 6.  <0x0-0xFF:2>\n;     <o7>  Backdoor Comparison Key 7.  <0x0-0xFF:2>\nBackDoorK0      EQU     0xFF\nBackDoorK1      EQU     0xFF\nBackDoorK2      EQU     0xFF\nBackDoorK3      EQU     0xFF\nBackDoorK4      EQU     0xFF\nBackDoorK5      EQU     0xFF\nBackDoorK6      EQU     0xFF\nBackDoorK7      EQU     0xFF\n;   </h>\n;   <h> Program flash protection bytes (FPROT)\n;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.\n;     <i> Each bit protects a 1/32 region of the program flash memory.\n;     <h> FPROT0\n;       <i> Program Flash Region Protect Register 0\n;       <i> 1/32 - 8/32 region\n;       <o.0>   FPROT0.0\n;       <o.1>   FPROT0.1\n;       <o.2>   FPROT0.2\n;       <o.3>   FPROT0.3\n;       <o.4>   FPROT0.4\n;       <o.5>   FPROT0.5\n;       <o.6>   FPROT0.6\n;       <o.7>   FPROT0.7\nnFPROT0         EQU     0x00\nFPROT0          EQU     nFPROT0:EOR:0xFF\n;     </h>\n;     <h> FPROT1\n;       <i> Program Flash Region Protect Register 1\n;       <i> 9/32 - 16/32 region\n;       <o.0>   FPROT1.0\n;       <o.1>   FPROT1.1\n;       <o.2>   FPROT1.2\n;       <o.3>   FPROT1.3\n;       <o.4>   FPROT1.4\n;       <o.5>   FPROT1.5\n;       <o.6>   FPROT1.6\n;       <o.7>   FPROT1.7\nnFPROT1         EQU     0x00\nFPROT1          EQU     nFPROT1:EOR:0xFF\n;     </h>\n;     <h> FPROT2\n;       <i> Program Flash Region Protect Register 2\n;       <i> 17/32 - 24/32 region\n;       <o.0>   FPROT2.0\n;       <o.1>   FPROT2.1\n;       <o.2>   FPROT2.2\n;       <o.3>   FPROT2.3\n;       <o.4>   FPROT2.4\n;       <o.5>   FPROT2.5\n;       <o.6>   FPROT2.6\n;       <o.7>   FPROT2.7\nnFPROT2         EQU     0x00\nFPROT2          EQU     nFPROT2:EOR:0xFF\n;     </h>\n;     <h> FPROT3\n;       <i> Program Flash Region Protect Register 3\n;       <i> 25/32 - 32/32 region\n;       <o.0>   FPROT3.0\n;       <o.1>   FPROT3.1\n;       <o.2>   FPROT3.2\n;       <o.3>   FPROT3.3\n;       <o.4>   FPROT3.4\n;       <o.5>   FPROT3.5\n;       <o.6>   FPROT3.6\n;       <o.7>   FPROT3.7\nnFPROT3         EQU     0x00\nFPROT3          EQU     nFPROT3:EOR:0xFF\n;     </h>\n;   </h>\n;   <h> Data flash protection byte (FDPROT)\n;     <i> Each bit protects a 1/8 region of the data flash memory.\n;     <i> (Program flash only devices: Reserved)\n;       <o.0>   FDPROT.0\n;       <o.1>   FDPROT.1\n;       <o.2>   FDPROT.2\n;       <o.3>   FDPROT.3\n;       <o.4>   FDPROT.4\n;       <o.5>   FDPROT.5\n;       <o.6>   FDPROT.6\n;       <o.7>   FDPROT.7\nnFDPROT         EQU     0x00\nFDPROT          EQU     nFDPROT:EOR:0xFF\n;   </h>\n;   <h> EEPROM protection byte (FEPROT)\n;     <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.\n;     <i> (Program flash only devices: Reserved)\n;       <o.0>   FEPROT.0\n;       <o.1>   FEPROT.1\n;       <o.2>   FEPROT.2\n;       <o.3>   FEPROT.3\n;       <o.4>   FEPROT.4\n;       <o.5>   FEPROT.5\n;       <o.6>   FEPROT.6\n;       <o.7>   FEPROT.7\nnFEPROT         EQU     0x00\nFEPROT          EQU     nFEPROT:EOR:0xFF\n;   </h>\n;   <h> Flash nonvolatile option byte (FOPT)\n;     <i> Allows the user to customize the operation of the MCU at boot time.\n;     <o.0> LPBOOT\n;       <0=> Low-power boot\n;       <1=> Normal boot\n;     <o.1> EZPORT_DIS\n;       <0=> EzPort operation is disabled\n;       <1=> EzPort operation is enabled\nFOPT          EQU     0xFD\n;   </h>\n;   <h> Flash security byte (FSEC)\n;     <i> WARNING: If SEC field is configured as \"MCU security status is secure\" and MEEN field is configured as \"Mass erase is disabled\",\n;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!\n;     <o.0..1> SEC\n;       <2=> MCU security status is unsecure\n;       <3=> MCU security status is secure\n;         <i> Flash Security\n;     <o.2..3> FSLACC\n;       <2=> Freescale factory access denied\n;       <3=> Freescale factory access granted\n;         <i> Freescale Failure Analysis Access Code\n;     <o.4..5> MEEN\n;       <2=> Mass erase is disabled\n;       <3=> Mass erase is enabled\n;     <o.6..7> KEYEN\n;       <2=> Backdoor key access enabled\n;       <3=> Backdoor key access disabled\n;         <i> Backdoor Key Security Enable\nFSEC          EQU     0xFE\n;   </h>\n; </h>\n\n#ifndef RAM_TARGET\n                AREA    FlashConfig, DATA, READONLY\n__FlashConfig\n                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3\n                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7\n                DCB     FPROT0    , FPROT1    , FPROT2    , FPROT3\n                DCB     FSEC      , FOPT      , FEPROT    , FDPROT\n#endif\n\n\n                AREA    |.text|, CODE, READONLY\n\n\nReset_Handler   PROC\n                ALIGN   4\n                EXPORT  Reset_Handler             [WEAK]\n                IMPORT  SystemInit\n\n#ifndef RAM_TARGET\n                REQUIRE FlashConfig\n#endif\n\n\n                CPSID   I               ; Mask interrupts\n\n#ifdef START_FROM_FLASH\n                ; Init ECC RAM\n                LDR     R1, =__RAM_START\n                LDR     R1, [R1]\n                LDR     R2, =__RAM_END\n                LDR     R2, [R2]\n                SUBS    R2, R1\n                SUBS    R2, #1\n                BLE LC5\n\n                MOVS    R0, #0\n                MOVS    R3, #4\nLC4\n                STR     R0, [R1]\n                ADD     R1, R1, R3\n                SUBS    R2, #4\n                BGE LC4\nLC5\n                NOP\n#endif\n\n                LDR     R0, =0xE000ED08\n                LDR     R1, =__Vectors\n                STR     R1, [R0]\n                LDR     R2, [R1]\n                MSR     MSP, R2\n                LDR     R0, =SystemInit\n                BLX     R0\n                LDR     R0, =init_data_bss\n                BLX     R0\n                CPSIE   i               ; Unmask interrupts\n                LDR     R0, =__main\n                BLX     R0\n                ENDP\n\nNMI_Handler\\\n                PROC\n                EXPORT  NMI_Handler         [WEAK]\n                B       .\n                ENDP\nHardFault_Handler\\\n                PROC\n                EXPORT  HardFault_Handler         [WEAK]\n                B       .\n                ENDP\nMemManage_Handler\\\n                PROC\n                EXPORT  MemManage_Handler         [WEAK]\n                B       .\n                ENDP\nBusFault_Handler\\\n                PROC\n                EXPORT  BusFault_Handler         [WEAK]\n                B       .\n                ENDP\nUsageFault_Handler\\\n                PROC\n                EXPORT  UsageFault_Handler         [WEAK]\n                B       .\n                ENDP\nSVC_Handler\\\n                PROC\n                EXPORT  SVC_Handler         [WEAK]\n                B       .\n                ENDP\nDebugMon_Handler\\\n                PROC\n                EXPORT  DebugMon_Handler         [WEAK]\n                B       .\n                ENDP\nPendSV_Handler\\\n                PROC\n                EXPORT  PendSV_Handler         [WEAK]\n                B       .\n                ENDP\nSysTick_Handler\\\n                PROC\n                EXPORT  SysTick_Handler         [WEAK]\n                B       .\n                ENDP\nDefaultISR\\\n                PROC\n                EXPORT  DefaultISR         [WEAK]\n                B       .\n                ENDP\nDefault_Handler PROC\n                EXPORT  DMA0_IRQHandler                      [WEAK]\n                EXPORT  DMA1_IRQHandler                      [WEAK]\n                EXPORT  DMA2_IRQHandler                      [WEAK]\n                EXPORT  DMA3_IRQHandler                      [WEAK]\n                EXPORT  DMA4_IRQHandler                      [WEAK]\n                EXPORT  DMA5_IRQHandler                      [WEAK]\n                EXPORT  DMA6_IRQHandler                      [WEAK]\n                EXPORT  DMA7_IRQHandler                      [WEAK]\n                EXPORT  DMA8_IRQHandler                      [WEAK]\n                EXPORT  DMA9_IRQHandler                      [WEAK]\n                EXPORT  DMA10_IRQHandler                     [WEAK]\n                EXPORT  DMA11_IRQHandler                     [WEAK]\n                EXPORT  DMA12_IRQHandler                     [WEAK]\n                EXPORT  DMA13_IRQHandler                     [WEAK]\n                EXPORT  DMA14_IRQHandler                     [WEAK]\n                EXPORT  DMA15_IRQHandler                     [WEAK]\n                EXPORT  DMA_Error_IRQHandler                 [WEAK]\n                EXPORT  MCM_IRQHandler                       [WEAK]\n                EXPORT  FTFC_IRQHandler                      [WEAK]\n                EXPORT  Read_Collision_IRQHandler            [WEAK]\n                EXPORT  LVD_LVW_IRQHandler                   [WEAK]\n                EXPORT  FTFC_Fault_IRQHandler                [WEAK]\n                EXPORT  WDOG_EWM_IRQHandler                  [WEAK]\n                EXPORT  RCM_IRQHandler                       [WEAK]\n                EXPORT  LPI2C0_Master_IRQHandler             [WEAK]\n                EXPORT  LPI2C0_Slave_IRQHandler              [WEAK]\n                EXPORT  LPSPI0_IRQHandler                    [WEAK]\n                EXPORT  LPSPI1_IRQHandler                    [WEAK]\n                EXPORT  LPSPI2_IRQHandler                    [WEAK]\n                EXPORT  Reserved45_IRQHandler                [WEAK]\n                EXPORT  Reserved46_IRQHandler                [WEAK]\n                EXPORT  LPUART0_RxTx_IRQHandler              [WEAK]\n                EXPORT  Reserved48_IRQHandler                [WEAK]\n                EXPORT  LPUART1_RxTx_IRQHandler              [WEAK]\n                EXPORT  Reserved50_IRQHandler                [WEAK]\n                EXPORT  LPUART2_RxTx_IRQHandler              [WEAK]\n                EXPORT  Reserved52_IRQHandler                [WEAK]\n                EXPORT  Reserved53_IRQHandler                [WEAK]\n                EXPORT  Reserved54_IRQHandler                [WEAK]\n                EXPORT  ADC0_IRQHandler                      [WEAK]\n                EXPORT  ADC1_IRQHandler                      [WEAK]\n                EXPORT  CMP0_IRQHandler                      [WEAK]\n                EXPORT  Reserved58_IRQHandler                [WEAK]\n                EXPORT  Reserved59_IRQHandler                [WEAK]\n                EXPORT  ERM_single_fault_IRQHandler          [WEAK]\n                EXPORT  ERM_double_fault_IRQHandler          [WEAK]\n                EXPORT  RTC_IRQHandler                       [WEAK]\n                EXPORT  RTC_Seconds_IRQHandler               [WEAK]\n                EXPORT  LPIT0_Ch0_IRQHandler                 [WEAK]\n                EXPORT  LPIT0_Ch1_IRQHandler                 [WEAK]\n                EXPORT  LPIT0_Ch2_IRQHandler                 [WEAK]\n                EXPORT  LPIT0_Ch3_IRQHandler                 [WEAK]\n                EXPORT  PDB0_IRQHandler                      [WEAK]\n                EXPORT  Reserved69_IRQHandler                [WEAK]\n                EXPORT  Reserved70_IRQHandler                [WEAK]\n                EXPORT  Reserved71_IRQHandler                [WEAK]\n                EXPORT  Reserved72_IRQHandler                [WEAK]\n                EXPORT  SCG_IRQHandler                       [WEAK]\n                EXPORT  LPTMR0_IRQHandler                    [WEAK]\n                EXPORT  PORTA_IRQHandler                     [WEAK]\n                EXPORT  PORTB_IRQHandler                     [WEAK]\n                EXPORT  PORTC_IRQHandler                     [WEAK]\n                EXPORT  PORTD_IRQHandler                     [WEAK]\n                EXPORT  PORTE_IRQHandler                     [WEAK]\n                EXPORT  SWI_IRQHandler                       [WEAK]\n                EXPORT  Reserved81_IRQHandler                [WEAK]\n                EXPORT  Reserved82_IRQHandler                [WEAK]\n                EXPORT  Reserved83_IRQHandler                [WEAK]\n                EXPORT  PDB1_IRQHandler                      [WEAK]\n                EXPORT  FLEXIO_IRQHandler                    [WEAK]\n                EXPORT  Reserved86_IRQHandler                [WEAK]\n                EXPORT  Reserved87_IRQHandler                [WEAK]\n                EXPORT  Reserved88_IRQHandler                [WEAK]\n                EXPORT  Reserved89_IRQHandler                [WEAK]\n                EXPORT  Reserved90_IRQHandler                [WEAK]\n                EXPORT  Reserved91_IRQHandler                [WEAK]\n                EXPORT  Reserved92_IRQHandler                [WEAK]\n                EXPORT  Reserved93_IRQHandler                [WEAK]\n                EXPORT  CAN0_ORed_IRQHandler                 [WEAK]\n                EXPORT  CAN0_Error_IRQHandler                [WEAK]\n                EXPORT  CAN0_Wake_Up_IRQHandler              [WEAK]\n                EXPORT  CAN0_ORed_0_15_MB_IRQHandler         [WEAK]\n                EXPORT  CAN0_ORed_16_31_MB_IRQHandler        [WEAK]\n                EXPORT  Reserved99_IRQHandler                [WEAK]\n                EXPORT  Reserved100_IRQHandler               [WEAK]\n                EXPORT  CAN1_ORed_IRQHandler                 [WEAK]\n                EXPORT  CAN1_Error_IRQHandler                [WEAK]\n                EXPORT  Reserved103_IRQHandler               [WEAK]\n                EXPORT  CAN1_ORed_0_15_MB_IRQHandler         [WEAK]\n                EXPORT  Reserved105_IRQHandler               [WEAK]\n                EXPORT  Reserved106_IRQHandler               [WEAK]\n                EXPORT  Reserved107_IRQHandler               [WEAK]\n                EXPORT  CAN2_ORed_IRQHandler                 [WEAK]\n                EXPORT  CAN2_Error_IRQHandler                [WEAK]\n                EXPORT  Reserved110_IRQHandler               [WEAK]\n                EXPORT  CAN2_ORed_0_15_MB_IRQHandler         [WEAK]\n                EXPORT  Reserved112_IRQHandler               [WEAK]\n                EXPORT  Reserved113_IRQHandler               [WEAK]\n                EXPORT  Reserved114_IRQHandler               [WEAK]\n                EXPORT  FTM0_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM0_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM0_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM0_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM0_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM0_Ovf_Reload_IRQHandler           [WEAK]\n                EXPORT  FTM1_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM1_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM1_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM1_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM1_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM1_Ovf_Reload_IRQHandler           [WEAK]\n                EXPORT  FTM2_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM2_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM2_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM2_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM2_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM2_Ovf_Reload_IRQHandler           [WEAK]\n                EXPORT  FTM3_Ch0_Ch1_IRQHandler              [WEAK]\n                EXPORT  FTM3_Ch2_Ch3_IRQHandler              [WEAK]\n                EXPORT  FTM3_Ch4_Ch5_IRQHandler              [WEAK]\n                EXPORT  FTM3_Ch6_Ch7_IRQHandler              [WEAK]\n                EXPORT  FTM3_Fault_IRQHandler                [WEAK]\n                EXPORT  FTM3_Ovf_Reload_IRQHandler           [WEAK]\nDMA0_IRQHandler                                  ; DMA channel 0 transfer complete\nDMA1_IRQHandler                                  ; DMA channel 1 transfer complete\nDMA2_IRQHandler                                  ; DMA channel 2 transfer complete\nDMA3_IRQHandler                                  ; DMA channel 3 transfer complete\nDMA4_IRQHandler                                  ; DMA channel 4 transfer complete\nDMA5_IRQHandler                                  ; DMA channel 5 transfer complete\nDMA6_IRQHandler                                  ; DMA channel 6 transfer complete\nDMA7_IRQHandler                                  ; DMA channel 7 transfer complete\nDMA8_IRQHandler                                  ; DMA channel 8 transfer complete\nDMA9_IRQHandler                                  ; DMA channel 9 transfer complete\nDMA10_IRQHandler                                 ; DMA channel 10 transfer complete\nDMA11_IRQHandler                                 ; DMA channel 11 transfer complete\nDMA12_IRQHandler                                 ; DMA channel 12 transfer complete\nDMA13_IRQHandler                                 ; DMA channel 13 transfer complete\nDMA14_IRQHandler                                 ; DMA channel 14 transfer complete\nDMA15_IRQHandler                                 ; DMA channel 15 transfer complete\nDMA_Error_IRQHandler                             ; DMA error interrupt channels 0-15\nMCM_IRQHandler                                   ; FPU sources\nFTFC_IRQHandler                                  ; FTFC Command complete\nRead_Collision_IRQHandler                        ; FTFC Read collision\nLVD_LVW_IRQHandler                               ; PMC Low voltage detect interrupt\nFTFC_Fault_IRQHandler                            ; FTFC Double bit fault detect\nWDOG_EWM_IRQHandler                              ; Single interrupt vector for WDOG and EWM\nRCM_IRQHandler                                   ; RCM Asynchronous Interrupt\nLPI2C0_Master_IRQHandler                         ; LPI2C0 Master Interrupt\nLPI2C0_Slave_IRQHandler                          ; LPI2C0 Slave Interrupt\nLPSPI0_IRQHandler                                ; LPSPI0 Interrupt\nLPSPI1_IRQHandler                                ; LPSPI1 Interrupt\nLPSPI2_IRQHandler                                ; LPSPI2 Interrupt\nReserved45_IRQHandler                            ; Reserved Interrupt 45\nReserved46_IRQHandler                            ; Reserved Interrupt 46\nLPUART0_RxTx_IRQHandler                          ; LPUART0 Transmit / Receive Interrupt\nReserved48_IRQHandler                            ; Reserved Interrupt 48\nLPUART1_RxTx_IRQHandler                          ; LPUART1 Transmit / Receive  Interrupt\nReserved50_IRQHandler                            ; Reserved Interrupt 50\nLPUART2_RxTx_IRQHandler                          ; LPUART2 Transmit / Receive  Interrupt\nReserved52_IRQHandler                            ; Reserved Interrupt 52\nReserved53_IRQHandler                            ; Reserved Interrupt 53\nReserved54_IRQHandler                            ; Reserved Interrupt 54\nADC0_IRQHandler                                  ; ADC0 interrupt request.\nADC1_IRQHandler                                  ; ADC1 interrupt request.\nCMP0_IRQHandler                                  ; CMP0 interrupt request\nReserved58_IRQHandler                            ; Reserved Interrupt 58\nReserved59_IRQHandler                            ; Reserved Interrupt 59\nERM_single_fault_IRQHandler                      ; ERM single bit error correction\nERM_double_fault_IRQHandler                      ; ERM double bit error non-correctable\nRTC_IRQHandler                                   ; RTC alarm interrupt\nRTC_Seconds_IRQHandler                           ; RTC seconds interrupt\nLPIT0_Ch0_IRQHandler                             ; LPIT0 channel 0 overflow interrupt\nLPIT0_Ch1_IRQHandler                             ; LPIT0 channel 1 overflow interrupt\nLPIT0_Ch2_IRQHandler                             ; LPIT0 channel 2 overflow interrupt\nLPIT0_Ch3_IRQHandler                             ; LPIT0 channel 3 overflow interrupt\nPDB0_IRQHandler                                  ; PDB0 interrupt\nReserved69_IRQHandler                            ; Reserved Interrupt 69\nReserved70_IRQHandler                            ; Reserved Interrupt 70\nReserved71_IRQHandler                            ; Reserved Interrupt 71\nReserved72_IRQHandler                            ; Reserved Interrupt 72\nSCG_IRQHandler                                   ; SCG bus interrupt request\nLPTMR0_IRQHandler                                ; LPTIMER interrupt request\nPORTA_IRQHandler                                 ; Port A pin detect interrupt\nPORTB_IRQHandler                                 ; Port B pin detect interrupt\nPORTC_IRQHandler                                 ; Port C pin detect interrupt\nPORTD_IRQHandler                                 ; Port D pin detect interrupt\nPORTE_IRQHandler                                 ; Port E pin detect interrupt\nSWI_IRQHandler                                   ; Software interrupt\nReserved81_IRQHandler                            ; Reserved Interrupt 81\nReserved82_IRQHandler                            ; Reserved Interrupt 82\nReserved83_IRQHandler                            ; Reserved Interrupt 83\nPDB1_IRQHandler                                  ; PDB1 interrupt\nFLEXIO_IRQHandler                                ; FlexIO Interrupt\nReserved86_IRQHandler                            ; Reserved Interrupt 86\nReserved87_IRQHandler                            ; Reserved Interrupt 87\nReserved88_IRQHandler                            ; Reserved Interrupt 88\nReserved89_IRQHandler                            ; Reserved Interrupt 89\nReserved90_IRQHandler                            ; Reserved Interrupt 90\nReserved91_IRQHandler                            ; Reserved Interrupt 91\nReserved92_IRQHandler                            ; Reserved Interrupt 92\nReserved93_IRQHandler                            ; Reserved Interrupt 93\nCAN0_ORed_IRQHandler                             ; CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\nCAN0_Error_IRQHandler                            ; CAN0 Interrupt indicating that errors were detected on the CAN bus\nCAN0_Wake_Up_IRQHandler                          ; CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode\nCAN0_ORed_0_15_MB_IRQHandler                     ; CAN0 OR'ed Message buffer (0-15)\nCAN0_ORed_16_31_MB_IRQHandler                    ; CAN0 OR'ed Message buffer (16-31)\nReserved99_IRQHandler                            ; Reserved Interrupt 99\nReserved100_IRQHandler                           ; Reserved Interrupt 100\nCAN1_ORed_IRQHandler                             ; CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\nCAN1_Error_IRQHandler                            ; CAN1 Interrupt indicating that errors were detected on the CAN bus\nReserved103_IRQHandler                           ; Reserved Interrupt 103\nCAN1_ORed_0_15_MB_IRQHandler                     ; CAN1 OR'ed Interrupt for Message buffer (0-15)\nReserved105_IRQHandler                           ; Reserved Interrupt 105\nReserved106_IRQHandler                           ; Reserved Interrupt 106\nReserved107_IRQHandler                           ; Reserved Interrupt 107\nCAN2_ORed_IRQHandler                             ; CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]\nCAN2_Error_IRQHandler                            ; CAN2 Interrupt indicating that errors were detected on the CAN bus\nReserved110_IRQHandler                           ; Reserved Interrupt 110\nCAN2_ORed_0_15_MB_IRQHandler                     ; CAN2 OR'ed Message buffer (0-15)\nReserved112_IRQHandler                           ; Reserved Interrupt 112\nReserved113_IRQHandler                           ; Reserved Interrupt 113\nReserved114_IRQHandler                           ; Reserved Interrupt 114\nFTM0_Ch0_Ch1_IRQHandler                          ; FTM0 Channel 0 and 1 interrupt\nFTM0_Ch2_Ch3_IRQHandler                          ; FTM0 Channel 2 and 3 interrupt\nFTM0_Ch4_Ch5_IRQHandler                          ; FTM0 Channel 4 and 5 interrupt\nFTM0_Ch6_Ch7_IRQHandler                          ; FTM0 Channel 6 and 7 interrupt\nFTM0_Fault_IRQHandler                            ; FTM0 Fault interrupt\nFTM0_Ovf_Reload_IRQHandler                       ; FTM0 Counter overflow and Reload interrupt\nFTM1_Ch0_Ch1_IRQHandler                          ; FTM1 Channel 0 and 1 interrupt\nFTM1_Ch2_Ch3_IRQHandler                          ; FTM1 Channel 2 and 3 interrupt\nFTM1_Ch4_Ch5_IRQHandler                          ; FTM1 Channel 4 and 5 interrupt\nFTM1_Ch6_Ch7_IRQHandler                          ; FTM1 Channel 6 and 7 interrupt\nFTM1_Fault_IRQHandler                            ; FTM1 Fault interrupt\nFTM1_Ovf_Reload_IRQHandler                       ; FTM1 Counter overflow and Reload interrupt\nFTM2_Ch0_Ch1_IRQHandler                          ; FTM2 Channel 0 and 1 interrupt\nFTM2_Ch2_Ch3_IRQHandler                          ; FTM2 Channel 2 and 3 interrupt\nFTM2_Ch4_Ch5_IRQHandler                          ; FTM2 Channel 4 and 5 interrupt\nFTM2_Ch6_Ch7_IRQHandler                          ; FTM2 Channel 6 and 7 interrupt\nFTM2_Fault_IRQHandler                            ; FTM2 Fault interrupt\nFTM2_Ovf_Reload_IRQHandler                       ; FTM2 Counter overflow and Reload interrupt\nFTM3_Ch0_Ch1_IRQHandler                          ; FTM3 Channel 0 and 1 interrupt\nFTM3_Ch2_Ch3_IRQHandler                          ; FTM3 Channel 2 and 3 interrupt\nFTM3_Ch4_Ch5_IRQHandler                          ; FTM3 Channel 4 and 5 interrupt\nFTM3_Ch6_Ch7_IRQHandler                          ; FTM3 Channel 6 and 7 interrupt\nFTM3_Fault_IRQHandler                            ; FTM3 Fault interrupt\nFTM3_Ovf_Reload_IRQHandler                       ; FTM3 Counter overflow and Reload interrupt\n\n                B       .\n\n                ENDP\n\n                ALIGN\n                END\n"
              }
            }
          },
          "params": {
            "path": "RTE\\Device\\S32K144HFxxxLLx\\startup_S32K144.S",
            "content": "<<< SEARCH <<<\n#ifndef __flash_vector_table__\n__RAM_START DCD |Image$$VECTOR_RAM$$Base|\n#else\n__RAM_START DCD |Image$$RW_m_data$$Base|\n#endif\n==== REPLACED_BY ====\n    IF :DEF:__flash_vector_table__\n__RAM_START DCD |Image$$RW_m_data$$Base|\n    ELSE\n__RAM_START DCD |Image$$VECTOR_RAM$$Base|\n    ENDIF\n>>> END >>>"
          },
          "parentMessageId": ""
        },
        {
          "id": "692a4f55-93e1-4898-b9df-b82a706971f2",
          "type": "TEXT",
          "status": "success",
          "content": "我已经成功修复了启动文件中的错误。问题出在汇编文件中的条件编译语法上。\n\n在 ARM 汇编中，C 风格的 `#ifndef` 和 `#else` 预处理指令不被支持，而应该使用 ARM 汇编特有的条件汇编指令 `IF :DEF:` 和 `ELSE`。\n\n我将原来的代码：\n```\n#ifndef __flash_vector_table__\n__RAM_START DCD |Image$$VECTOR_RAM$$Base|\n#else\n__RAM_START DCD |Image$$RW_m_data$$Base|\n#endif\n```\n\n修改为：\n```\nIF :DEF:__flash_vector_table__\n__RAM_START DCD |Image$$RW_m_data$$Base|\nELSE\n__RAM_START DCD |Image$$VECTOR_RAM$$Base|\nENDIF\n```\n\n这样修改后，汇编器就能正确理解这个条件判断了。从项目配置中可以看出，`__flash_vector_table__` 确实已经在编译选项中定义，但是在汇编文件中需要使用 ARM 汇编特有的条件指令语法才能正确识别这个宏。\n\n现在您应该能够成功编译项目了。如果还有其他问题，请随时告诉我。",
          "composer": {
            "markdown": "",
            "tasks": []
          },
          "isErrorMessage": false,
          "parentMessageId": ""
        }
      ]
    }
  ],
  "title": "S32K144启动文件汇编错误分析",
  "ctime": 1765637952180,
  "utime": 1765638034676,
  "workspaceDirectory": "d:\\Keil\\ARM\\Packs\\Keil\\S32_SDK_DFP\\1.5.1\\CMSIS\\Flash\\CVD_S32",
  "summary": "S32K144启动文件汇编错误分析"
}