#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-mx.dtsi"
#include "stm32mp15-u-boot.dtsi"
#include "stm32mp15-ddr.dtsi"

/* USER CODE BEGIN includes */
/* USER CODE END includes */

/{

	/* USER CODE BEGIN root */

	aliases{
		i2c3 = &i2c4;
		mmc0 = &sdmmc1;
		usb0 = &usbotg_hs;
	};

	config{
		u-boot,boot-led = "heartbeat";
		u-boot,error-led = "error";
		u-boot,mmc-env-partition = "ssbl";
		st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
		st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
		st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
	};

	led{

		red{
			label = "error";
			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
			default-state = "off";
			status = "okay";
		};
	};

	firmware{

		optee{
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};

	reserved-memory{

		optee@de000000{
			reg = <0xde000000 0x02000000>;
			no-map;
		};
	};
	/* USER CODE END root */

	clocks{

#ifndef CONFIG_STM32MP1_TRUSTED

		clk_lsi:clk-lsi{
		};

		clk_hsi:clk-hsi{
		};

		clk_csi:clk-csi{
			status = "disabled";
		};

		clk_lse:clk-lse{
			st,drive = < LSEDRV_MEDIUM_HIGH >;
		};

		clk_hse:clk-hse{
			st,digbypass;
		};
#endif
	};
};

#ifndef CONFIG_STM32MP1_TRUSTED

&rcc{
	u-boot,dm-pre-reloc;
	st,clksrc = <
		CLK_MPU_PLL1P
		CLK_AXI_PLL2P
		CLK_MCU_PLL3P
		CLK_PLL12_HSE
		CLK_PLL3_HSE
		CLK_PLL4_HSE
		CLK_RTC_LSE
		CLK_MCO1_DISABLED
		CLK_MCO2_DISABLED
	>;
	st,clkdiv = <
		1 		
		0 		
		0 		
		1 		
		1 		
		1 		
		1 		
		2 		
		23 		
		0 		
		0 		
	>;
	st,pkcs = <
		CLK_CKPER_HSE
		CLK_ETH_PLL4P
		CLK_SDMMC12_PLL4P
		CLK_DSI_DSIPLL
		CLK_STGEN_HSE
		CLK_USBPHY_HSE
		CLK_SPI2S1_DISABLED
		CLK_SPI2S23_PLL3Q
		CLK_SPI45_DISABLED
		CLK_SPI6_DISABLED
		CLK_I2C46_HSI
		CLK_SDMMC3_DISABLED
		CLK_USBO_USBPHY
		CLK_ADC_CKPER
		CLK_CEC_LSE
		CLK_I2C12_HSI
		CLK_I2C35_DISABLED
		CLK_UART1_DISABLED
		CLK_UART24_HSI
		CLK_UART35_DISABLED
		CLK_UART6_DISABLED
		CLK_UART78_DISABLED
		CLK_SPDIF_DISABLED
		CLK_SAI1_DISABLED
		CLK_SAI2_PLL3Q
		CLK_SAI3_DISABLED
		CLK_SAI4_DISABLED
		CLK_RNG1_LSI
		CLK_LPTIM1_DISABLED
		CLK_LPTIM23_DISABLED
		CLK_LPTIM45_DISABLED
	>;

	pll2:st,pll@1{
		compatible = "st,stm32mp1-pll";
		reg = <1>;
		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
		frac = < 0x1400 >;
		u-boot,dm-pre-reloc;
	};

	pll3:st,pll@2{
		compatible = "st,stm32mp1-pll";
		reg = <2>;
		cfg = < 1 33 1 16 36 PQR(1,1,0) >;
		frac = < 0x1a04 >;
		u-boot,dm-pre-reloc;
	};

	pll4:st,pll@3{
		compatible = "st,stm32mp1-pll";
		reg = <3>;
		cfg = < 3 98 5 7 7 PQR(1,1,0) >;
		u-boot,dm-pre-reloc;
	};
};

&i2c4{
	u-boot,dm-pre-reloc;
};

&sdmmc1{
	u-boot,dm-pre-reloc;
};
#endif

&cryp1{
	u-boot,dm-pre-reloc;
};

&hash1{
	u-boot,dm-pre-reloc;
};

&uart4{
	u-boot,dm-pre-reloc;
};

&usbotg_hs{
	u-boot,dm-pre-reloc;

	/* USER CODE BEGIN usbotg_hs */
	u-boot,force-b-session-valid;
	hnp-srp-disable;
	dr_mode = "peripheral";
	/* USER CODE END usbotg_hs */
};

&usbphyc{
	u-boot,dm-pre-reloc;
};

&usbphyc_port0{
	u-boot,dm-pre-reloc;
};

&usbphyc_port1{
	u-boot,dm-pre-reloc;
};

/* USER CODE BEGIN addons */

&adc{
	status = "okay";
};
/* USER CODE END addons */