FSMC_BANK1_NORSRAM1 FSMC_NORSRAM_BANK1 FSMC_BANK1_NORSRAM2 FSMC_NORSRAM_BANK2 FSMC_BANK1_NORSRAM3 FSMC_NORSRAM_BANK3 FSMC_BANK1_NORSRAM4 FSMC_NORSRAM_BANK4 AES_FLAG_RDERR CRYP_FLAG_RDERR AES_FLAG_WRERR CRYP_FLAG_WRERR AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR ADC_RESOLUTION12b ADC_RESOLUTION_12B ADC_RESOLUTION10b ADC_RESOLUTION_10B ADC_RESOLUTION8b ADC_RESOLUTION_8B ADC_RESOLUTION6b ADC_RESOLUTION_6B OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV EOC_SEQ_CONV ADC_EOC_SEQ_CONV EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV REGULAR_GROUP ADC_REGULAR_GROUP INJECTED_GROUP ADC_INJECTED_GROUP REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP AWD_EVENT ADC_AWD_EVENT AWD1_EVENT ADC_AWD1_EVENT AWD2_EVENT ADC_AWD2_EVENT AWD3_EVENT ADC_AWD3_EVENT OVR_EVENT ADC_OVR_EVENT JQOVF_EVENT ADC_JQOVF_EVENT ALL_CHANNELS ADC_ALL_CHANNELS REGULAR_CHANNELS ADC_REGULAR_CHANNELS INJECTED_CHANNELS ADC_INJECTED_CHANNELS SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE DAC1_CHANNEL_1 DAC_CHANNEL_1 DAC1_CHANNEL_2 DAC_CHANNEL_2 DAC2_CHANNEL_1 DAC_CHANNEL_1 DAC_WAVE_NONE ((uint32_t)0x00000000U) DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) DAC_WAVEGENERATION_NONE DAC_WAVE_NONE DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 IS_HAL_REMAPDMA IS_DMA_REMAP __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS TYPEERASE_PAGES FLASH_TYPEERASE_PAGES TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE WRPSTATE_DISABLE OB_WRPSTATE_DISABLE WRPSTATE_ENABLE OB_WRPSTATE_ENABLE HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE OBEX_PCROP OPTIONBYTE_PCROP OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD PAGESIZE FLASH_PAGE_SIZE TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE FLASH_ERROR_RD HAL_FLASH_ERROR_RD FLASH_ERROR_PG HAL_FLASH_ERROR_PROG FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS OB_WDG_SW OB_IWDG_SW OB_WDG_HW OB_IWDG_HW OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR OB_RDP_LEVEL0 OB_RDP_LEVEL_0 OB_RDP_LEVEL1 OB_RDP_LEVEL_1 OB_RDP_LEVEL2 OB_RDP_LEVEL_2 HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef GET_GPIO_SOURCE GPIO_GET_INDEX GET_GPIO_INDEX GPIO_GET_INDEX GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE KR_KEY_RELOAD IWDG_KEY_RELOAD KR_KEY_ENABLE IWDG_KEY_ENABLE KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS HAL_NAND_Read_Page HAL_NAND_Read_Page_8b HAL_NAND_Write_Page HAL_NAND_Write_Page_8b HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b NAND_AddressTypedef NAND_AddressTypeDef __ARRAY_ADDRESS ARRAY_ADDRESS __ADDR_1st_CYCLE ADDR_1ST_CYCLE __ADDR_2nd_CYCLE ADDR_2ND_CYCLE __ADDR_3rd_CYCLE ADDR_3RD_CYCLE __ADDR_4th_CYCLE ADDR_4TH_CYCLE NOR_StatusTypedef HAL_NOR_StatusTypeDef NOR_SUCCESS HAL_NOR_STATUS_SUCCESS NOR_ONGOING HAL_NOR_STATUS_ONGOING NOR_ERROR HAL_NOR_STATUS_ERROR NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT __NOR_WRITE NOR_WRITE __NOR_ADDR_SHIFT NOR_ADDR_SHIFT OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS CF_DATA ATA_DATA CF_SECTOR_COUNT ATA_SECTOR_COUNT CF_SECTOR_NUMBER ATA_SECTOR_NUMBER CF_CYLINDER_LOW ATA_CYLINDER_LOW CF_CYLINDER_HIGH ATA_CYLINDER_HIGH CF_CARD_HEAD ATA_CARD_HEAD CF_STATUS_CMD ATA_STATUS_CMD CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD CF_IDENTIFY_CMD ATA_IDENTIFY_CMD PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING PCCARD_ERROR HAL_PCCARD_STATUS_ERROR PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT FORMAT_BIN RTC_FORMAT_BIN FORMAT_BCD RTC_FORMAT_BCD RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE CCER_CCxE_MASK TIM_CCER_CCxE_MASK CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK TIM_DMABase_CR1 TIM_DMABASE_CR1 TIM_DMABase_CR2 TIM_DMABASE_CR2 TIM_DMABase_SMCR TIM_DMABASE_SMCR TIM_DMABase_DIER TIM_DMABASE_DIER TIM_DMABase_SR TIM_DMABASE_SR TIM_DMABase_EGR TIM_DMABASE_EGR TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 TIM_DMABase_CCER TIM_DMABASE_CCER TIM_DMABase_CNT TIM_DMABASE_CNT TIM_DMABase_PSC TIM_DMABASE_PSC TIM_DMABase_ARR TIM_DMABASE_ARR TIM_DMABase_RCR TIM_DMABASE_RCR TIM_DMABase_CCR1 TIM_DMABASE_CCR1 TIM_DMABase_CCR2 TIM_DMABASE_CCR2 TIM_DMABase_CCR3 TIM_DMABASE_CCR3 TIM_DMABase_CCR4 TIM_DMABASE_CCR4 TIM_DMABase_BDTR TIM_DMABASE_BDTR TIM_DMABase_DCR TIM_DMABASE_DCR TIM_DMABase_DMAR TIM_DMABASE_DMAR TIM_DMABase_OR1 TIM_DMABASE_OR1 TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 TIM_DMABase_CCR5 TIM_DMABASE_CCR5 TIM_DMABase_CCR6 TIM_DMABASE_CCR6 TIM_DMABase_OR2 TIM_DMABASE_OR2 TIM_DMABase_OR3 TIM_DMABASE_OR3 TIM_DMABase_OR TIM_DMABASE_OR TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 TIM_EventSource_COM TIM_EVENTSOURCE_COM TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER TIM_EventSource_Break TIM_EVENTSOURCE_BREAK TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE __DIV_SAMPLING16 UART_DIV_SAMPLING16 __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 __DIV_SAMPLING8 UART_DIV_SAMPLING8 __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK USART_CLOCK_DISABLED USART_CLOCK_DISABLE USART_CLOCK_ENABLED USART_CLOCK_ENABLE USARTNACK_ENABLED USART_NACK_ENABLE USARTNACK_DISABLED USART_NACK_DISABLE CFR_BASE WWDG_CFR_BASE CAN_FilterFIFO0 CAN_FILTER_FIFO0 CAN_FilterFIFO1 CAN_FILTER_FIFO1 CAN_IT_RQCP0 CAN_IT_TME CAN_IT_RQCP1 CAN_IT_TME CAN_IT_RQCP2 CAN_IT_TME INAK_TIMEOUT CAN_TIMEOUT_VALUE SLAK_TIMEOUT CAN_TIMEOUT_VALUE CAN_TXSTATUS_FAILED ((uint8_t)0x00U) CAN_TXSTATUS_OK ((uint8_t)0x01U) CAN_TXSTATUS_PENDING ((uint8_t)0x02U) VLAN_TAG ETH_VLAN_TAG MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK ETH_MMCCR ((uint32_t)0x00000100U) ETH_MMCRIR ((uint32_t)0x00000104U) ETH_MMCTIR ((uint32_t)0x00000108U) ETH_MMCRIMR ((uint32_t)0x0000010CU) ETH_MMCTIMR ((uint32_t)0x00000110U) ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) ETH_MMCTGFCR ((uint32_t)0x00000168U) ETH_MMCRFCECR ((uint32_t)0x00000194U) ETH_MMCRFAECR ((uint32_t)0x00000198U) ETH_MMCRGUFCR ((uint32_t)0x000001C4U) HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR DCMI_IT_OVF DCMI_IT_OVR DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 HASH_AlgoMode_HASH HASH_ALGOMODE_HASH HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter HAL_PWR_PVDConfig HAL_PWR_ConfigPVD HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING CR_OFFSET_BB PWR_CR_OFFSET_BB CSR_OFFSET_BB PWR_CSR_OFFSET_BB DBP_BitNumber DBP_BIT_NUMBER PVDE_BitNumber PVDE_BIT_NUMBER PMODE_BitNumber PMODE_BIT_NUMBER EWUP_BitNumber EWUP_BIT_NUMBER FPDS_BitNumber FPDS_BIT_NUMBER ODEN_BitNumber ODEN_BIT_NUMBER ODSWEN_BitNumber ODSWEN_BIT_NUMBER MRLVDS_BitNumber MRLVDS_BIT_NUMBER LPLVDS_BitNumber LPLVDS_BIT_NUMBER BRE_BitNumber BRE_BIT_NUMBER PWR_MODE_EVT PWR_PVD_MODE_NORMAL HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt HAL_TIM_DMAError TIM_DMAError HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback AES_IT_CC CRYP_IT_CC AES_IT_ERR CRYP_IT_ERR AES_FLAG_CCF CRYP_FLAG_CCF __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER CMP_PD_BitNumber CMP_PD_BIT_NUMBER __ADC_ENABLE __HAL_ADC_ENABLE __ADC_DISABLE __HAL_ADC_DISABLE __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS __HAL_ADC_IS_ENABLED ADC_IS_ENABLE __ADC_IS_ENABLED ADC_IS_ENABLE __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION __HAL_ADC_JSQR_RK ADC_JSQR_RK __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER __HAL_ADC_SQR1 ADC_SQR1 __HAL_ADC_SMPR1 ADC_SMPR1 __HAL_ADC_SMPR2 ADC_SMPR2 __HAL_ADC_SQR3_RK ADC_SQR3_RK __HAL_ADC_SQR2_RK ADC_SQR2_RK __HAL_ADC_SQR1_RK ADC_SQR1_RK __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq __HAL_ADC_JSQR ADC_JSQR __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT IS_DAC_GENERATE_WAVE IS_DAC_WAVE __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE IS_WRPAREA IS_OB_WRPAREA IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM IS_TYPEERASE IS_FLASH_TYPEERASE IS_NBSECTORS IS_FLASH_NBSECTORS IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE __HAL_I2C_RESET_CR2 I2C_RESET_CR2 __HAL_I2C_GENERATE_START I2C_GENERATE_START __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE __HAL_I2C_RISE_TIME I2C_RISE_TIME __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD __HAL_I2C_SPEED_FAST I2C_SPEED_FAST __HAL_I2C_SPEED I2C_SPEED __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB __HAL_I2C_FREQRANGE I2C_FREQRANGE IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT __IRDA_DISABLE __HAL_IRDA_DISABLE __IRDA_ENABLE __HAL_IRDA_ENABLE __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI HAL_RCC_CCSCallback HAL_RCC_CSSCallback __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE IS_RCC_SYSCLK_DIV IS_RCC_HCLK IS_RCC_HCLK_DIV IS_RCC_PCLK IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK RCC_IT_HSI14 RCC_IT_HSI14RDY IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG RCC_MCO_NODIV RCC_MCODIV_1 RCC_MCO_DIV1 RCC_MCODIV_1 RCC_MCO_DIV2 RCC_MCODIV_2 RCC_MCO_DIV4 RCC_MCODIV_4 RCC_MCO_DIV8 RCC_MCODIV_8 RCC_MCO_DIV16 RCC_MCODIV_16 RCC_MCO_DIV32 RCC_MCODIV_32 RCC_MCO_DIV64 RCC_MCODIV_64 RCC_MCO_DIV128 RCC_MCODIV_128 RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 HSION_BitNumber RCC_HSION_BIT_NUMBER HSION_BITNUMBER RCC_HSION_BIT_NUMBER HSEON_BitNumber RCC_HSEON_BIT_NUMBER HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER MSION_BITNUMBER RCC_MSION_BIT_NUMBER CSSON_BitNumber RCC_CSSON_BIT_NUMBER CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER PLLON_BitNumber RCC_PLLON_BIT_NUMBER PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER BDRST_BitNumber RCC_BDRST_BIT_NUMBER BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER LSION_BitNumber RCC_LSION_BIT_NUMBER LSION_BITNUMBER RCC_LSION_BIT_NUMBER LSEON_BitNumber RCC_LSEON_BIT_NUMBER LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER RMVF_BitNumber RCC_RMVF_BIT_NUMBER RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE CR_HSION_BB RCC_CR_HSION_BB CR_CSSON_BB RCC_CR_CSSON_BB CR_PLLON_BB RCC_CR_PLLON_BB CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB CR_MSION_BB RCC_CR_MSION_BB CSR_LSION_BB RCC_CSR_LSION_BB CSR_LSEON_BB RCC_CSR_LSEON_BB CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB CSR_RTCEN_BB RCC_CSR_RTCEN_BB CSR_RTCRST_BB RCC_CSR_RTCRST_BB CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB BDCR_BDRST_BB RCC_BDCR_BDRST_BB CR_HSEON_BB RCC_CR_HSEON_BB CSR_RMVF_BB RCC_CSR_RMVF_BB CR_PLLSAION_BB RCC_CR_PLLSAION_BB DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN RCC_CRS_TRIMOV RCC_CRS_TRIMOVF RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED DfsdmClockSelection Dfsdm1ClockSelection RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT IS_ALARM IS_RTC_ALARM IS_ALARM_MASK IS_RTC_ALARM_MASK IS_TAMPER IS_RTC_TAMPER IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH __HAL_SMBUS_GET_DIR SMBUS_GET_DIR __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED __HAL_SPI_1LINE_TX SPI_1LINE_TX __HAL_SPI_1LINE_RX SPI_1LINE_RX __HAL_SPI_RESET_CRC SPI_RESET_CRC __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE __UART_MASK_COMPUTATION UART_MASK_COMPUTATION IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE __USART_ENABLE_IT __HAL_USART_ENABLE_IT __USART_DISABLE_IT __HAL_USART_DISABLE_IT __USART_ENABLE __HAL_USART_ENABLE __USART_DISABLE __HAL_USART_DISABLE __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE __HAL_LTDC_LAYER LTDC_LAYER SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE SAI_STREOMODE SAI_STEREOMODE SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 #if defined(STM32F373xC) || defined(STM32F378xx) COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #if defined(STM32L4) || defined(STM32F7) FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #if defined(STM32L4) || defined(STM32F7) FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 #if defined(STM32L4) || defined(STM32F7) FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 #if defined(STM32L4) || defined(STM32F7) FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE !(#if defined(STM32L4) || defined(STM32F7)) FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE !(#if defined(STM32L4) || defined(STM32F7)) FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 !(#if defined(STM32L4) || defined(STM32F7)) FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 !(#if defined(STM32L4) || defined(STM32F7)) GPIO_AF12_SDMMC GPIO_AF12_SDIO #if defined(STM32F4) GPIO_AF12_SDMMC1 GPIO_AF12_SDIO #if defined(STM32F4) GPIO_AF12_SDIO GPIO_AF12_SDMMC1 #if defined(STM32F7) GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 #if defined(STM32F7) GPIO_AF12_SDIO GPIO_AF12_SDMMC1 #if defined(STM32L4) GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 #if defined(STM32L4) GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)|| defined(STM32F1)|| defined(STM32F3)|| defined(STM32F0) GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)|| defined(STM32F1)|| defined(STM32F3)|| defined(STM32F0) GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM #if defined(STM32L1) GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH #if defined(STM32L1) GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW #if defined(STM32L1) GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32L1) GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) COMP_START __HAL_COMP_ENABLE #if defined(STM32F3) COMP_STOP __HAL_COMP_DISABLE #if defined(STM32F3) COMP_LOCK __HAL_COMP_LOCK #if defined(STM32F3) __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() #if defined (STM32F4) __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() #if defined (STM32F4) __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() #if defined (STM32F4) __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() #if defined (STM32F4) __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() #if defined (STM32F4) __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG !(#if defined (STM32F4)) __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT !(#if defined (STM32F4)) __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT !(#if defined (STM32F4)) __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT !(#if defined (STM32F4)) __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG !(#if defined (STM32F4)) __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #if defined(STM32F4) __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #if defined(STM32F4) __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #if defined(STM32F4) __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE #if defined(STM32F4) __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE #if defined(STM32F4) __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE #if defined(STM32F4) __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED #if defined(STM32F4) __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED #if defined(STM32F4) Sdmmc1ClockSelection SdioClockSelection #if defined(STM32F4) RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO #if defined(STM32F4) RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 #if defined(STM32F4) RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK #if defined(STM32F4) __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG #if defined(STM32F4) __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE #if defined(STM32F4) __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET #if defined(STM32F7) || defined(STM32L4) __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET #if defined(STM32F7) || defined(STM32L4) __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE #if defined(STM32F7) || defined(STM32L4) __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE #if defined(STM32F7) || defined(STM32L4) __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE #if defined(STM32F7) || defined(STM32L4) __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE #if defined(STM32F7) || defined(STM32L4) __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED #if defined(STM32F7) || defined(STM32L4) __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED #if defined(STM32F7) || defined(STM32L4) SdioClockSelection Sdmmc1ClockSelection #if defined(STM32F7) || defined(STM32L4) RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 #if defined(STM32F7) || defined(STM32L4) __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG #if defined(STM32F7) || defined(STM32L4) __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE #if defined(STM32F7) || defined(STM32L4) RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48 #if defined(STM32F7) RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK #if defined(STM32F7) RCC_IT_LSECSS RCC_IT_CSSLSE #if defined(STM32L0) RCC_IT_CSS RCC_IT_CSSHSE #if defined(STM32L0) __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() #if defined (STM32F1) __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() #if defined (STM32F1) __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() #if defined (STM32F1) __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() #if defined (STM32F1) __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() #if defined (STM32F1) SD_SDMMC_DISABLED SD_SDIO_DISABLED #if defined(STM32F4) SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY #if defined(STM32F4) SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED #if defined(STM32F4) SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION #if defined(STM32F4) SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND #if defined(STM32F4) SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT #if defined(STM32F4) SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED #if defined(STM32F4) __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE #if defined(STM32F4) __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE #if defined(STM32F4) __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE #if defined(STM32F4) __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL #if defined(STM32F4) __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT #if defined(STM32F4) __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT #if defined(STM32F4) __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG #if defined(STM32F4) __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG #if defined(STM32F4) __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT #if defined(STM32F4) __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT #if defined(STM32F4) SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS #if defined(STM32F4) SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT #if defined(STM32F4) SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND #if defined(STM32F4) SDMMC1_IRQn SDIO_IRQn #if defined(STM32F4) SDMMC1_IRQHandler SDIO_IRQHandler #if defined(STM32F4) SD_SDIO_DISABLED SD_SDMMC_DISABLED #if defined(STM32F7) || defined(STM32L4) SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY #if defined(STM32F7) || defined(STM32L4) SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED #if defined(STM32F7) || defined(STM32L4) SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION #if defined(STM32F7) || defined(STM32L4) SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND #if defined(STM32F7) || defined(STM32L4) SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT #if defined(STM32F7) || defined(STM32L4) SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED #if defined(STM32F7) || defined(STM32L4) __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE #if defined(STM32F7) || defined(STM32L4) __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE #if defined(STM32F7) || defined(STM32L4) __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE #if defined(STM32F7) || defined(STM32L4) __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE #if defined(STM32F7) || defined(STM32L4) __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT #if defined(STM32F7) || defined(STM32L4) __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT #if defined(STM32F7) || defined(STM32L4) __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG #if defined(STM32F7) || defined(STM32L4) __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG #if defined(STM32F7) || defined(STM32L4) __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT #if defined(STM32F7) || defined(STM32L4) __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT #if defined(STM32F7) || defined(STM32L4) SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS #if defined(STM32F7) || defined(STM32L4) SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT #if defined(STM32F7) || defined(STM32L4) SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND #if defined(STM32F7) || defined(STM32L4) SDIO_IRQn SDMMC1_IRQn #if defined(STM32F7) || defined(STM32L4) SDIO_IRQHandler SDMMC1_IRQHandler #if defined(STM32F7) || defined(STM32L4) COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON #if defined(STM32L0) || defined(STM32L4) COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 #if defined(STM32L0) || defined(STM32L4) COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 #if defined(STM32L0) || defined(STM32L4) COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 #if defined(STM32L0) || defined(STM32L4) COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 #if defined(STM32L0) || defined(STM32L4) COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 #if defined(STM32L0) || defined(STM32L4) COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 #if defined(STM32L0) || defined(STM32L4) COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT #if defined(STM32L0) || defined(STM32L4) COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT #if defined(STM32L0) || defined(STM32L4) COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT #if defined(STM32L0) || defined(STM32L4) COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT #if defined(STM32L0) || defined(STM32L4) COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 #if defined(STM32L0) || defined(STM32L4) COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 #if defined(STM32L0) || defined(STM32L4) COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 #if defined(STM32L0) || defined(STM32L4) COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 #if defined(STM32L0) || defined(STM32L4) COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 #if defined(STM32L0) || defined(STM32L4) COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 #if defined(STM32L0) COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 #if defined(STM32L0) COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 #if defined(STM32L4) COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 #if defined(STM32L4) COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 #if defined(STM32L0) || defined(STM32L4) COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 #if defined(STM32L0) || defined(STM32L4) COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW #if defined(STM32L0) || defined(STM32L4) COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH #if defined(STM32L0) || defined(STM32L4) COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 #if defined(STM32L4) COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 #if defined(STM32L4) COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 #if defined(STM32L4) COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 #if defined(STM32L4) COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 #if defined(STM32L4) COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 #if defined(STM32L4) COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE #if defined(STM32L4) COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED #if defined(STM32L0) COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER #if defined(STM32L0) COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED #if defined(STM32L4) COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED #if defined(STM32L4) COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER #if defined(STM32L4) COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER #if defined(STM32L4) DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) DMA2D_RGB888 DMA2D_OUTPUT_RGB888 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) DMA2D_RGB565 DMA2D_OUTPUT_RGB565 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) CM_ARGB8888 DMA2D_INPUT_ARGB8888 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) CM_RGB888 DMA2D_INPUT_RGB888 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) CM_RGB565 DMA2D_INPUT_RGB565 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) CM_ARGB1555 DMA2D_INPUT_ARGB1555 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) CM_ARGB4444 DMA2D_INPUT_ARGB4444 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) CM_L8 DMA2D_INPUT_L8 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) CM_AL44 DMA2D_INPUT_AL44 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) CM_AL88 DMA2D_INPUT_AL88 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) CM_L4 DMA2D_INPUT_L4 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) CM_A8 DMA2D_INPUT_A8 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) CM_A4 DMA2D_INPUT_A4 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)