WWDG: Window WatchDog The resulting value of the clock is equal to (PCLK/4096)/prescaler for example (PCLK/4096)/8. Specifies the WWDG window value to be compared to the downcounter. If the software reloads the counter while the counter is greater than the value stored in the window register, then a reset is generated. Specifies the WWDG counter value.<br>It is decremented every (4096 x 2**WDGTB) PCLK cycles.<br>A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared). When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset. WWDG_Init WWDG_Init