TIM: Timer $IpInstance ConfigOCrefClear1 ConfigOCrefClear2 ConfigOCrefClear3 ConfigOCrefClear4 Base_Init TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH1 TIM_CHANNEL_1 TIM_ICSELECTION_DIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH1 TIM_CHANNEL_1 TIM_ICSELECTION_DIRECTTI RemapConfig_TIM14_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH1 TIM_CHANNEL_1 TIM_ICSELECTION_INDIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init SlaveConfigSynchronization IC_ConfigChannel_TRC1 TIM_CHANNEL_1 TIM_ICSELECTION_TRC TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH2 TIM_CHANNEL_2 TIM_ICSELECTION_DIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH2 TIM_CHANNEL_2 TIM_ICSELECTION_INDIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime SlaveConfigSynchronization IC_Init IC_ConfigChannel_TRC2 TIM_CHANNEL_2 TIM_ICSELECTION_TRC TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH3 TIM_CHANNEL_3 TIM_ICSELECTION_DIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH3 TIM_CHANNEL_3 TIM_ICSELECTION_INDIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init SlaveConfigSynchronization IC_ConfigChannel_TRC3 TIM_CHANNEL_3 TIM_ICSELECTION_TRC TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH4 TIM_CHANNEL_4 TIM_ICSELECTION_DIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH4 TIM_CHANNEL_4 TIM_ICSELECTION_INDIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime SlaveConfigSynchronization IC_Init IC_ConfigChannel_TRC4 TIM_CHANNEL_4 TIM_ICSELECTION_TRC TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_1 setOC1Preload_OC TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_2 setOC2Preload_OC TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_3 setOC3Preload_OC TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_4 setOC4Preload_OC TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_1 setOC1Preload_OC TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_2 setOC2Preload_OC TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_3 setOC3Preload_OC TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_4 setOC4Preload_OC TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_1 setOC1Preload_OC TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_2 setOC2Preload_OC TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_3 setOC3Preload_OC TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_1 setOC1Preload_OC TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_2 setOC2Preload_OC TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_3 setOC3Preload_OC TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_1 setOC1Preload_OC TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_2 setOC2Preload_OC TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_3 setOC3Preload_OC TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_4 setOC4Preload_OC TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_1 setOC1Preload_OC TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_2 setOC2Preload_OC TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_3 setOC3Preload_OC TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_1 setOC1Preload_OC TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_2 setOC2Preload_OC TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_3 setOC3Preload_OC TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_1 setOC1Preload_PWM TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_2 setOC2Preload_PWM TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_3 setOC3Preload_PWM TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_4 setOC4Preload_PWM TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_1 setOC1Preload_PWM TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_2 setOC2Preload_PWM TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_3 setOC3Preload_PWM TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_4 setOC4Preload_PWM TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_1 setOC1Preload_PWM TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_2 setOC2Preload_PWM TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_3 setOC3Preload_PWM TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_1 setOC1Preload_PWM TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_2 setOC2Preload_PWM TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_3 setOC3Preload_PWM TIM_CHANNEL_3 OnePulse_Init TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OPM_ConfigChannel_1 TIM_CHANNEL_1 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OPM_ConfigChannel_2 TIM_CHANNEL_2 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OPM_ConfigChannel_1 TIM_CHANNEL_1 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OPM_ConfigChannel_2 TIM_CHANNEL_2 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OPM_ConfigChannel_1 TIM_CHANNEL_1 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OPM_ConfigChannel_2 TIM_CHANNEL_2 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime HallSensor_Init TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime Encoder_Init TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Input_mode_CH1 TIM_TS_TI1FP1 TIM_SLAVEMODE_RESET TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Input_mode_CH2 TIM_TS_TI2FP2 TIM_SLAVEMODE_RESET ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_CLOCKPOLARITY_INVERTED TIM_CLOCKPOLARITY_NONINVERTED TIM_CLOCKPRESCALER_DIV1 TIM_CLOCKPRESCALER_DIV2 TIM_CLOCKPRESCALER_DIV4 TIM_CLOCKPRESCALER_DIV8 ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_CLOCKPOLARITY_BOTHEDGE ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_CLOCKPOLARITY_RISING TIM_CLOCKPOLARITY_FALLING TIM_CLOCKPOLARITY_BOTHEDGE ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_CLOCKPOLARITY_RISING TIM_CLOCKPOLARITY_FALLING TIM_CLOCKPOLARITY_BOTHEDGE ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigTI1Input Semaphore_ClockSourceInternal$IpInstance Semaphore_Activated$IpInstance Semaphore_ControllerMode$IpInstance Semaphore_ETH_ControllerMode$IpInstance Semaphore_SMC_Clock$IpInstance Semaphore_SMC_Reset$IpInstance Semaphore_SMC_Gated$IpInstance Semaphore_SMC_Trigger$IpInstance Semaphore_TriggerSource$IpInstance Semaphore_Trigger_DMA_Enable$IpInstance Semaphore_TriggerSourceITR0$IpInstance Semaphore_SourceTRC$IpInstance Semaphore_TriggerSourceITR1$IpInstance Semaphore_ETH_TriggerSourceITR1$IpInstance Semaphore_SourceTRC$IpInstance Semaphore_TriggerSourceITR2$IpInstance Semaphore_SourceTRC$IpInstance Semaphore_TriggerSourceITR3$IpInstance Semaphore_SourceTRC$IpInstance Semaphore_TriggerSourceETR$IpInstance Semaphore_ETRpinUsed$IpInstance Semaphore_TriggerSourceTI1ED$IpInstance Semaphore_ClockTriggerSourceOnTI1$IpInstance Semaphore_SourceTRC$IpInstance Semaphore_CH1pinUsed$IpInstance Semaphore_CH1_Input_IO_$IpInstance Semaphore_TriggerSourceTI1FP1$IpInstance Semaphore_ClockTriggerSourceOnTI1$IpInstance Semaphore_CH1pinUsed$IpInstance Semaphore_CH1_Input_IO_$IpInstance Semaphore_TriggerSourceTI2FP2$IpInstance Semaphore_ClockTriggerSourceOnTI2$IpInstance Semaphore_CH2_Input_IO_$IpInstance Semaphore_ClockSource$IpInstance Semaphore_ClockSourceInternal$IpInstance Semaphore_ClockSourceETRMode2$IpInstance Semaphore_ETRpinUsed$IpInstance Semaphore_Channel1$IpInstance Semaphore_CaptureCompare_1_DMA_Enable$IpInstance Semaphore_input_Channel1$IpInstance Semaphore_input_Channel1_direct$IpInstance Semaphore_CH1pinUsed$IpInstance Semaphore_CH1_Input_IO_$IpInstance Semaphore_input_Channel1$IpInstance Semaphore_input_Channel1_direct$IpInstance Semaphore_CH1pinUsed$IpInstance Semaphore_input_Channel1$IpInstance Semaphore_input_Channel1_direct$IpInstance Semaphore_CH1pinUsed$IpInstance Semaphore_input_Channel1$IpInstance Semaphore_input_Channel1_direct$IpInstance Semaphore_CH1pinUsed$IpInstance Semaphore_input_Channel1$IpInstance Semaphore_input_Channel1_indirect$IpInstance Semaphore_CH2_Input_IO_$IpInstance Semaphore_input_Channel1$IpInstance Semaphore_input_Channel_TRC$IpInstance Semaphore_input_Channel_TRC_TI1$IpInstance Semaphore_output_Channel$IpInstance Semaphore_output_Channel1$IpInstance Semaphore_OC_No_output_Channel1$IpInstance Semaphore_clearable$IpInstance Semaphore_Channel1x$IpInstance Semaphore_OSSR_TIM_1_8_$IpInstance Semaphore_OSSR_TIM_15_16_17_$IpInstance Semaphore_output_Channel$IpInstance Semaphore_output_Channel1$IpInstance Semaphore_clearable$IpInstance Semaphore_Channel1x$IpInstance Semaphore_CH1pinUsed$IpInstance Semaphore_OSSR_TIM_1_8_$IpInstance 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