TIM: Timer $IpInstance ConfigOCrefClear1 ConfigOCrefClear2 ConfigOCrefClear3 ConfigOCrefClear4 ConfigOCrefClear5 ConfigOCrefClear6 Base_Init TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH1 TIM_CHANNEL_1 TIM_ICSELECTION_DIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH1 TIM_CHANNEL_1 TIM_ICSELECTION_DIRECTTI TISelection_TIM1_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH1 TIM_CHANNEL_1 TIM_ICSELECTION_DIRECTTI TISelection_TIM2_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH1 TIM_CHANNEL_1 TIM_ICSELECTION_DIRECTTI TISelection_TIM3_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH1 TIM_CHANNEL_1 TIM_ICSELECTION_DIRECTTI TISelection_TIM4_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH1 TIM_CHANNEL_1 TIM_ICSELECTION_DIRECTTI TISelection_TIM5_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH1 TIM_CHANNEL_1 TIM_ICSELECTION_DIRECTTI TISelection_TIM8_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH1 TIM_CHANNEL_1 TIM_ICSELECTION_DIRECTTI TISelection_TIM15_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH1 TIM_CHANNEL_1 TIM_ICSELECTION_DIRECTTI TISelection_TIM16_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH1 TIM_CHANNEL_1 TIM_ICSELECTION_DIRECTTI TISelection_TIM17_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH1 TIM_CHANNEL_1 TIM_ICSELECTION_DIRECTTI TISelection_TIM20_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH1 TIM_CHANNEL_1 TIM_ICSELECTION_INDIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init SlaveConfigSynchronization IC_ConfigChannel_TRC1 TIM_CHANNEL_1 TIM_ICSELECTION_TRC TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH2 TIM_CHANNEL_2 TIM_ICSELECTION_DIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH2 TIM_CHANNEL_2 TIM_ICSELECTION_DIRECTTI TISelection_TIM2_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH2 TIM_CHANNEL_2 TIM_ICSELECTION_DIRECTTI TISelection_TIM3_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH2 TIM_CHANNEL_2 TIM_ICSELECTION_DIRECTTI TISelection_TIM4_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH2 TIM_CHANNEL_2 TIM_ICSELECTION_DIRECTTI TISelection_TIM5_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH2 TIM_CHANNEL_2 TIM_ICSELECTION_DIRECTTI TISelection_TIM15_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH2 TIM_CHANNEL_2 TIM_ICSELECTION_INDIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput SlaveConfigSynchronization IC_Init IC_ConfigChannel_TRC2 TIM_CHANNEL_2 TIM_ICSELECTION_TRC TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH3 TIM_CHANNEL_3 TIM_ICSELECTION_DIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH3 TIM_CHANNEL_3 TIM_ICSELECTION_DIRECTTI TISelection_TIM2_TI3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH3 TIM_CHANNEL_3 TIM_ICSELECTION_DIRECTTI TISelection_TIM3_TI3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH3 TIM_CHANNEL_3 TIM_ICSELECTION_DIRECTTI TISelection_TIM4_TI3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH3 TIM_CHANNEL_3 TIM_ICSELECTION_INDIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init SlaveConfigSynchronization IC_ConfigChannel_TRC3 TIM_CHANNEL_3 TIM_ICSELECTION_TRC TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH4 TIM_CHANNEL_4 TIM_ICSELECTION_DIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH4 TIM_CHANNEL_4 TIM_ICSELECTION_DIRECTTI TISelection_TIM2_TI4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH4 TIM_CHANNEL_4 TIM_ICSELECTION_DIRECTTI TISelection_TIM4_TI4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput IC_Init IC_ConfigChannel_CH4 TIM_CHANNEL_4 TIM_ICSELECTION_INDIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput SlaveConfigSynchronization IC_Init IC_ConfigChannel_TRC4 TIM_CHANNEL_4 TIM_ICSELECTION_TRC TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_1 setOC1Preload_OC TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_2 setOC2Preload_OC TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_3 setOC3Preload_OC TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_4 setOC4Preload_OC TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_5 setOC5Preload_OC TIM_CHANNEL_5 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_6 setOC6Preload_OC TIM_CHANNEL_6 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_1 setOC1Preload_OC TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_2 setOC2Preload_OC TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_3 setOC3Preload_OC TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_4 setOC4Preload_OC TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_1 setOC1Preload_OC TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_2 setOC2Preload_OC TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_3 setOC3Preload_OC TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_4 setOC4Preload_OC TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_1 setOC1Preload_OC TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_2 setOC2Preload_OC TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_3 setOC3Preload_OC TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_4 setOC4Preload_OC TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_forced_1 setOC1Preload_OC TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_forced_2 setOC2Preload_OC TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_forced_3 setOC3Preload_OC TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_forced_4 setOC4Preload_OC TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_forced_5 setOC5Preload_OC TIM_CHANNEL_5 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_forced_6 setOC6Preload_OC TIM_CHANNEL_6 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_forced_1 setOC1Preload_OC TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_forced_2 setOC2Preload_OC TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_forced_3 setOC3Preload_OC TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_forced_4 setOC4Preload_OC TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_forced_1 setOC1Preload_OC TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_forced_2 setOC2Preload_OC TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_forced_3 setOC3Preload_OC TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OC_Init OC_ConfigChannel_forced_4 setOC4Preload_OC TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Init PWM_ConfigChannel_1 setOC1Preload_PWM TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Init PWM_ConfigChannel_2 setOC2Preload_PWM TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Init PWM_ConfigChannel_3 setOC3Preload_PWM TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Init PWM_ConfigChannel_4 setOC4Preload_PWM TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Init PWM_ConfigChannel_1 setOC1Preload_PWM TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Init PWM_ConfigChannel_2 setOC2Preload_PWM TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Init PWM_ConfigChannel_3 setOC3Preload_PWM TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Init PWM_ConfigChannel_4 setOC4Preload_PWM TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Init PWM_ConfigChannel_5 setOC5Preload_PWM TIM_CHANNEL_5 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Init PWM_ConfigChannel_6 setOC6Preload_PWM TIM_CHANNEL_6 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Init PWM_ConfigChannel_1 setOC1Preload_PWM TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Init PWM_ConfigChannel_2 setOC2Preload_PWM TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Init PWM_ConfigChannel_3 setOC3Preload_PWM TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Init PWM_ConfigChannel_4 setOC4Preload_PWM TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Init PWM_ConfigChannel_1 setOC1Preload_PWM TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Init PWM_ConfigChannel_2 setOC2Preload_PWM TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Init PWM_ConfigChannel_3 setOC3Preload_PWM TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Init PWM_ConfigChannel_4 setOC4Preload_PWM TIM_CHANNEL_4 OnePulse_Init TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OPM_ConfigChannel_1 TIM_CHANNEL_1 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OPM_ConfigChannel_2 TIM_CHANNEL_2 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OPM_ConfigChannel_1 TIM_CHANNEL_1 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OPM_ConfigChannel_2 TIM_CHANNEL_2 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OPM_ConfigChannel_1 TIM_CHANNEL_1 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput OPM_ConfigChannel_2 TIM_CHANNEL_2 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput HallSensor_Init TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init TISelection_TIM1_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init TISelection_TIM2_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init TISelection_TIM2_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init TISelection_TIM2_TI1 TISelection_TIM2_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init TISelection_TIM3_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init TISelection_TIM3_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init TISelection_TIM3_TI1 TISelection_TIM3_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init TISelection_TIM4_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init TISelection_TIM4_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init TISelection_TIM4_TI1 TISelection_TIM4_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init TISelection_TIM5_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init TISelection_TIM5_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init TISelection_TIM5_TI1 TISelection_TIM5_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init TISelection_TIM8_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init TISelection_TIM20_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM1_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index RemapConfig_TIM1_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM1_TI1 RemapConfig_TIM1_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM2_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM2_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM2_TI1 TISelection_TIM2_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index RemapConfig_TIM2_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM2_TI2 RemapConfig_TIM2_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM2_TI1 RemapConfig_TIM2_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM2_TI1 TISelection_TIM2_TI2 RemapConfig_TIM2_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM3_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM3_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM3_TI1 TISelection_TIM3_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index RemapConfig_TIM3_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM3_TI2 RemapConfig_TIM3_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM3_TI1 RemapConfig_TIM3_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM3_TI1 TISelection_TIM3_TI2 RemapConfig_TIM3_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM4_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM4_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM4_TI1 TISelection_TIM4_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index RemapConfig_TIM4_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM4_TI2 RemapConfig_TIM4_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM4_TI1 RemapConfig_TIM4_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM4_TI1 TISelection_TIM4_TI2 RemapConfig_TIM4_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM5_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM5_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM5_TI1 TISelection_TIM5_TI2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index RemapConfig_TIM5_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM5_TI2 RemapConfig_TIM5_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM5_TI1 RemapConfig_TIM5_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM5_TI1 TISelection_TIM5_TI2 RemapConfig_TIM5_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM8_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index RemapConfig_TIM8_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM8_TI1 RemapConfig_TIM8_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM20_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index RemapConfig_TIM20_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput Encoder_Init Config_Encoder_Index TISelection_TIM20_TI1 RemapConfig_TIM20_ETR TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Input_mode_CH1 TIM_TS_TI1FP1 TIM_SLAVEMODE_RESET TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput PWM_Input_mode_CH2 TIM_TS_TI2FP2 TIM_SLAVEMODE_RESET ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput TIM_CLOCKPOLARITY_INVERTED TIM_CLOCKPOLARITY_NONINVERTED TIM_CLOCKPRESCALER_DIV1 TIM_CLOCKPRESCALER_DIV2 TIM_CLOCKPRESCALER_DIV4 TIM_CLOCKPRESCALER_DIV8 ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput TIM_CLOCKPOLARITY_INVERTED TIM_CLOCKPOLARITY_NONINVERTED TIM_CLOCKPRESCALER_DIV1 TIM_CLOCKPRESCALER_DIV2 TIM_CLOCKPRESCALER_DIV4 TIM_CLOCKPRESCALER_DIV8 ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput RemapConfig_TIM1_ETR TIM_CLOCKPOLARITY_INVERTED TIM_CLOCKPOLARITY_NONINVERTED TIM_CLOCKPRESCALER_DIV1 TIM_CLOCKPRESCALER_DIV2 TIM_CLOCKPRESCALER_DIV4 TIM_CLOCKPRESCALER_DIV8 ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput RemapConfig_TIM2_ETR TIM_CLOCKPOLARITY_INVERTED TIM_CLOCKPOLARITY_NONINVERTED TIM_CLOCKPRESCALER_DIV1 TIM_CLOCKPRESCALER_DIV2 TIM_CLOCKPRESCALER_DIV4 TIM_CLOCKPRESCALER_DIV8 ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput RemapConfig_TIM3_ETR TIM_CLOCKPOLARITY_INVERTED TIM_CLOCKPOLARITY_NONINVERTED TIM_CLOCKPRESCALER_DIV1 TIM_CLOCKPRESCALER_DIV2 TIM_CLOCKPRESCALER_DIV4 TIM_CLOCKPRESCALER_DIV8 ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput RemapConfig_TIM4_ETR TIM_CLOCKPOLARITY_INVERTED TIM_CLOCKPOLARITY_NONINVERTED TIM_CLOCKPRESCALER_DIV1 TIM_CLOCKPRESCALER_DIV2 TIM_CLOCKPRESCALER_DIV4 TIM_CLOCKPRESCALER_DIV8 ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput RemapConfig_TIM5_ETR TIM_CLOCKPOLARITY_INVERTED TIM_CLOCKPOLARITY_NONINVERTED TIM_CLOCKPRESCALER_DIV1 TIM_CLOCKPRESCALER_DIV2 TIM_CLOCKPRESCALER_DIV4 TIM_CLOCKPRESCALER_DIV8 ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput RemapConfig_TIM8_ETR TIM_CLOCKPOLARITY_INVERTED TIM_CLOCKPOLARITY_NONINVERTED TIM_CLOCKPRESCALER_DIV1 TIM_CLOCKPRESCALER_DIV2 TIM_CLOCKPRESCALER_DIV4 TIM_CLOCKPRESCALER_DIV8 ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput RemapConfig_TIM20_ETR ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput TIM_CLOCKPOLARITY_BOTHEDGE ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput TIM_CLOCKPOLARITY_RISING TIM_CLOCKPOLARITY_FALLING TIM_CLOCKPOLARITY_BOTHEDGE ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput TIM_CLOCKPOLARITY_RISING TIM_CLOCKPOLARITY_FALLING TIM_CLOCKPOLARITY_BOTHEDGE ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput RemapConfig_TIM1_ETR ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput RemapConfig_TIM2_ETR ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput RemapConfig_TIM3_ETR ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput RemapConfig_TIM4_ETR ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput RemapConfig_TIM5_ETR ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput RemapConfig_TIM8_ETR ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput RemapConfig_TIM20_ETR ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_ConfigBreakInput RemapConfig_TIM1_ETR RemapConfig_TIM2_ETR RemapConfig_TIM3_ETR RemapConfig_TIM4_ETR RemapConfig_TIM5_ETR RemapConfig_TIM8_ETR RemapConfig_TIM20_ETR ConfigTI1Input Semaphore_ClockSourceInternal$IpInstance Semaphore_Activated$IpInstance Semaphore_Activated$IpInstance_for_IRTIM$noContext Semaphore_ControllerMode$IpInstance Semaphore_ETH_ControllerMode$IpInstance Semaphore_SMC_Clock$IpInstance Semaphore_SMC_Reset$IpInstance Semaphore_SMC_Gated$IpInstance Semaphore_SMC_Trigger$IpInstance Semaphore_SMC_CombinedResetTrigger$IpInstance Semaphore_SMC_CombinedGatedReset$IpInstance Semaphore_TriggerSource$IpInstance Semaphore_Trigger_DMA_Enable$IpInstance Semaphore_TriggerSourceITR0$IpInstance Semaphore_TriggerSourceITRx$IpInstance Semaphore_SourceTRC$IpInstance Semaphore_TriggerSourceITR1$IpInstance Semaphore_TriggerSourceITRx$IpInstance Semaphore_ETH_TriggerSourceITR1$IpInstance Semaphore_SourceTRC$IpInstance Semaphore_TriggerSourceITR2$IpInstance Semaphore_TriggerSourceITRx$IpInstance Semaphore_SourceTRC$IpInstance Semaphore_TriggerSourceITR3$IpInstance Semaphore_TriggerSourceITRx$IpInstance Semaphore_SourceTRC$IpInstance Semaphore_TriggerSourceITR4$IpInstance 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