SPI: Serial Peripheral Interface Calculated Baudrate value based on SPI Clock source and Prescaler 1 Edge means the first clock transition is the first data capture edge (value 0) AND 2 Edge means the second clock transition is the first data capture edge (value 1) Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted additionally between active edge of SS and first data transaction start in master mode. Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between two consecutive data frames in master mode This parameter can be a value of SPI Master Inter-Data Ideleness Control continuous SPI transfer in master receiver mode and automatic management in order to avoid overrun condition. Control of Alternate function GPIOs state This parameter can be a value of Keep IO State Invert MISO/MOSI alternate functions. VM_NSSHARD VM_NSSHARD Spi_Init VM_MASTER SPI_MODE_MASTER SPI_DIRECTION_2LINES Spi_Init VM_SLAVE SPI_MODE_SLAVE SPI_DIRECTION_2LINES Spi_Init VM_MASTER SPI_MODE_MASTER SPI_DIRECTION_1LINE Spi_Init VM_SLAVE SPI_MODE_SLAVE SPI_DIRECTION_1LINE Spi_Init VM_MASTER SPI_MODE_MASTER SPI_DIRECTION_2LINES_RXONLY Spi_Init VM_SLAVE SPI_MODE_SLAVE SPI_DIRECTION_2LINES_RXONLY Spi_Init VM_MASTER SPI_MODE_MASTER SPI_DIRECTION_2LINES_TXONLY Spi_Init VM_SLAVE SPI_MODE_SLAVE SPI_DIRECTION_2LINES_TXONLY $IpInstance_DmaTransmit $IpInstance_DmaReceive $IpInstance_Master $IpInstance_DmaTransmit $IpInstance_DmaReceive $IpInstance_Slave $IpInstance_DmaTransmit $IpInstance_DmaReceive $IpInstance_Master $IpInstance_DmaTransmit $IpInstance_DmaReceive $IpInstance_Slave $IpInstance_DmaReceive $IpInstance_Master $IpInstance_DmaReceive $IpInstance_Slave $IpInstance_DmaTransmit $IpInstance_Master $IpInstance_DmaTransmit $IpInstance_Slave $IpInstance_Transmit $IpInstance$noContext $IpInstance_NSSHARD_Input $IpInstance_NSSHARD_Output $IpInstanceUsed_ForRCC