FMC: Flexible Memory Controller There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. Enables or disables the write FIFO used by the FMC controller. For Cellular RAM 1.5, specifies the memory page size from which a burst access is split. FMC_NORSRAM_DEVICE HAL_NOR1_Init HAL_SRAM1_Init NorPsramChipSelect1_1 NE1NorPsramChipSelect NorPsramChipSelect2_1 NorPsramChipSelect3_1 NorPsramChipSelect4_1 NorPsramChipSelect1 Lcd1 MuxedNorFlash1 MuxedPsram1 A25LcdUsed_1 OneBitAddress1 _8_bit_data1 _16_bit_data1 Data1 _8b_da1 _9b_da1 _10b_da1 _11b_da1 _12b_da1 _13b_da1 _14b_da1 _15b_da1 _16b_da1 _17b_da1 _18b_da1 _19b_da1 _20b_da1 _21b_da1 _22b_da1 _23b_da1 _24b_da1 _25b_da1 _26b_da1 NorPsramDataAddress1 BurstReadMode1 BurstWriteMode1 BurstReadMode1 BurstWriteMode1 NorPsramClock1 AddressValid1 AsynchronousWaitMode1 SynchronousWaitMode1 AsynchronousWaitMode1 SynchronousWaitMode1 NorPsramWait1