FMC: Flexible Memory Controller There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. Enables or disables the write FIFO used by the FMC controller. For Cellular RAM 1.5, specifies the memory page size from which a burst access is split. There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. Enables or disables the write FIFO used by the FMC controller. For Cellular RAM 1.5, specifies the memory page size from which a burst access is split. There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. Enables or disables the write FIFO used by the FMC controller. For Cellular RAM 1.5, specifies the memory page size from which a burst access is split. There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. There is only one continuous clock enable bit located in sub-bank Bank 1 - NOR/PSRAM 1. Enables or disables the write FIFO used by the FMC controller. For Cellular RAM 1.5, specifies the memory page size from which a burst access is split. NAND memory page size (without spare area) measured in bytes for 8-bit addressing or words for 16-bit addressing. NAND memory spare area size measured in bytes for 8-bit addressing or words for 16-bit addressing. NAND memory block size expressed in number of pages. NAND memory number of blocks. NAND memory number of planes. NAND memory plane size measured in number of blocks. NAND extra command needed for page reading mode. This parameter is mandatory for some NAND memories. Please check the read mode sequence in the NAND device datasheet. Specifies the SDRAM Column Access Strobe (CAS) latency in number of memory clock cycles. Specifies the SDRAM clock period for both SDRAM banks and allows disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized.<br>The corresponding bits in the FMC_SDCR2 register are read only. Enables burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO.<br>The corresponding bit in the FMC_SDCR2 register is don't care. Specifies the delay, in HCLK clock cycles, for reading data after CAS latency.<br>The corresponding bits in the FMC_SDCR2 register are read only. Specifies the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles.<br>If two SDRAM devices are connected, all the accesses performed simultaneously to both devices by the Command Mode register (Load Mode Register command) are issued using the timing parameters configured for Bank 1 (TMRD (Load mode register to active delay) and TRAS (Self-refresh time) timings) in the FMC_SDTR1 register.<br>The TRP (Row precharge delay) and TRC (Row cycle delay) timings are only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP and TRC timings must be programmed with the timings of the slowest device. Specifies the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles.<br>If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 registers must be programmed with the same Exit Self-refresh Delay corresponding to the slowest SDRAM device. Specifies the minimum Self-refresh period in number of memory clock cycles. Specifies the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands.<br>It is expressed in number of memory clock cycles.<br>The Row Cycle Delay is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the Row Cycle Delay must be programmed with the timings of the slowest device. Specifies the delay between a Write and a Precharge command in number of memory clock cycles.<br>WriteRecoveryTime must satisfy the following constraints:<br>1: WriteRecoveryTime >= SelfRefreshTime - RowToColumnDelay,<br>2: WriteRecoveryTime >= RowCycleDelay - RowToColumnDelay - RowPrechargeDelay.<br>If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 registers must be programmed with the same Write Recovery Time corresponding to the slowest SDRAM device. Specifies the delay between a Precharge command and another command in number of memory clock cycles.<br>The Row Precharge Delay is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the Row Precharge Delay must be programmed with the timing of the slowest device. Specifies the delay between the Activate command and a Read/Write command in number of memory clock cycles. Specifies the SDRAM Column Access Strobe (CAS) latency in number of memory clock cycles. Specifies the SDRAM clock period for both SDRAM banks and allows disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized.<br>The corresponding bits in the FMC_SDCR2 register are read only. Enables burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO.<br>The corresponding bit in the FMC_SDCR2 register is don't care. Specifies the delay, in HCLK clock cycles, for reading data after CAS latency.<br>The corresponding bits in the FMC_SDCR2 register are read only. Specifies the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles.<br>If two SDRAM devices are connected, all the accesses performed simultaneously to both devices by the Command Mode register (Load Mode Register command) are issued using the timing parameters configured for Bank 1 (TMRD (Load mode register to active delay) and TRAS (Self-refresh time) timings) in the FMC_SDTR1 register.<br>The TRP (Row precharge delay) and TRC (Row cycle delay) timings are only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP and TRC timings must be programmed with the timings of the slowest device. Specifies the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles.<br>If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 registers must be programmed with the same Exit Self-refresh Delay corresponding to the slowest SDRAM device. Specifies the minimum Self-refresh period in number of memory clock cycles. Specifies the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands.<br>It is expressed in number of memory clock cycles.<br>The Row Cycle Delay is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the Row Cycle Delay must be programmed with the timings of the slowest device. Specifies the delay between a Write and a Precharge command in number of memory clock cycles.<br>WriteRecoveryTime must satisfy the following constraints:<br>1: WriteRecoveryTime >= SelfRefreshTime - RowToColumnDelay,<br>2: WriteRecoveryTime >= RowCycleDelay - RowToColumnDelay - RowPrechargeDelay.<br>If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 registers must be programmed with the same Write Recovery Time corresponding to the slowest SDRAM device. Specifies the delay between a Precharge command and another command in number of memory clock cycles.<br>The Row Precharge Delay is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the Row Precharge Delay must be programmed with the timing of the slowest device. Specifies the delay between the Activate command and a Read/Write command in number of memory clock cycles. FMC_NORSRAM_DEVICE HAL_NOR1_Init HAL_SRAM1_Init FMC_NORSRAM_DEVICE HAL_NOR2_Init HAL_SRAM2_Init FMC_NORSRAM_DEVICE HAL_NOR3_Init HAL_SRAM3_Init FMC_NORSRAM_DEVICE HAL_NOR4_Init HAL_SRAM4_Init HAL_NAND1_Init FMC_NAND_DEVICE FMC_NAND_BANK2 FMC_NAND_BANK3 HAL_SDRAM1_Init FMC_SDRAM_DEVICE FMC_SDRAM_BANK1 FMC_SDRAM_BANK2 HAL_SDRAM2_Init FMC_SDRAM_DEVICE FMC_SDRAM_BANK1 FMC_SDRAM_BANK2 NorPsramChipSelect1_1 NE1NorPsramChipSelect NorPsramChipSelect2_1 NorPsramChipSelect3_1 NorPsramChipSelect4_1 NorPsramChipSelect1 NorFlash1 Psram1 Sram1 Rom1 Lcd1 MuxedNorFlash1 MuxedPsram1 Address1 A25LcdUsed_1 OneBitAddress1 _8_bit_data1 _16_bit_data1 _32_bit_data1 Data1 _8b_da1 _9b_da1 _10b_da1 _11b_da1 _12b_da1 _13b_da1 _14b_da1 _15b_da1 _16b_da1 _17b_da1 _18b_da1 _19b_da1 _20b_da1 _21b_da1 _22b_da1 _23b_da1 _24b_da1 _25b_da1 _26b_da1 NorPsramDataAddress1 BurstReadMode1 BurstWriteMode1 BurstReadMode1 BurstWriteMode1 NorPsramClock1 AddressValid1 AsynchronousWaitMode1 SynchronousWaitMode1 AsynchronousWaitMode1 SynchronousWaitMode1 NorPsramWait1 NorPsramChipSelect1_2 NE1NorPsramChipSelect NorPsramChipSelect2_2 NorPsramChipSelect3_2 NorPsramChipSelect4_2 NorPsramChipSelect2 NorFlash2 Psram2 Sram2 Rom2 Lcd2 MuxedNorFlash2 MuxedPsram2 Address2 A25LcdUsed_2 OneBitAddress2 _8_bit_data2 _16_bit_data2 _32_bit_data2 Data2 _8b_da2 _9b_da2 _10b_da2 _11b_da2 _12b_da2 _13b_da2 _14b_da2 _15b_da2 _16b_da2 _17b_da2 _18b_da2 _19b_da2 _20b_da2 _21b_da2 _22b_da2 _23b_da2 _24b_da2 _25b_da2 _26b_da2 NorPsramDataAddress2 BurstReadMode2 BurstWriteMode2 BurstReadMode2 BurstWriteMode2 NorPsramClock2 AddressValid2 AsynchronousWaitMode2 SynchronousWaitMode2 AsynchronousWaitMode2 SynchronousWaitMode2 NorPsramWait2 NorPsramChipSelect1_3 NE1NorPsramChipSelect NorPsramChipSelect2_3 NorPsramChipSelect3_3 NorPsramChipSelect4_3 NorPsramChipSelect3 NorFlash3 Psram3 Sram3 Rom3 Lcd3 MuxedNorFlash3 MuxedPsram3 Address3 A25LcdUsed_3 OneBitAddress3 _8_bit_data3 _16_bit_data3 _32_bit_data3 Data3 _8b_da3 _9b_da3 _10b_da3 _11b_da3 _12b_da3 _13b_da3 _14b_da3 _15b_da3 _16b_da3 _17b_da3 _18b_da3 _19b_da3 _20b_da3 _21b_da3 _22b_da3 _23b_da3 _24b_da3 _25b_da3 _26b_da3 NorPsramDataAddress3 BurstReadMode3 BurstWriteMode3 BurstReadMode3 BurstWriteMode3 NorPsramClock3 AddressValid3 AsynchronousWaitMode3 SynchronousWaitMode3 AsynchronousWaitMode3 SynchronousWaitMode3 NorPsramWait3 NorPsramChipSelect1_4 NE1NorPsramChipSelect NorPsramChipSelect2_4 NorPsramChipSelect3_4 NorPsramChipSelect4_4 NorPsramChipSelect4 NorFlash4 Psram4 Sram4 Rom4 Lcd4 MuxedNorFlash4 MuxedPsram4 Address4 A25LcdUsed_4 OneBitAddress4 _8_bit_data4 _16_bit_data4 _32_bit_data4 Data4 _8b_da4 _9b_da4 _10b_da4 _11b_da4 _12b_da4 _13b_da4 _14b_da4 _15b_da4 _16b_da4 _17b_da4 _18b_da4 _19b_da4 _20b_da4 _21b_da4 _22b_da4 _23b_da4 _24b_da4 _25b_da4 _26b_da4 NorPsramDataAddress4 BurstReadMode4 BurstWriteMode4 BurstReadMode4 BurstWriteMode4 NorPsramClock4 AddressValid4 AsynchronousWaitMode4 SynchronousWaitMode4 AsynchronousWaitMode4 SynchronousWaitMode4 NorPsramWait4 NandChipSelect2_1 NandChipSelect3_1 NandFlash1 _8b_dmux1 _16b_dmux1 NandDataAddressMux1 NandPccWait1 SdramChipSelect1_1 SdramChipSelect2_1 SdramChipSelect1 TwoSdramBanks1 FourSdramBanks1 SdramBanks1 _11_bit_addr1 _12_bit_addr1 _13_bit_addr1 SdAddr1 sd_8_bit_data1 sd_16_bit_data1 sd_32_bit_data1 SdData1 MW_FMC_MW SDRAM1 SdramChipSelect1_2 SdramChipSelect2_2 SdramChipSelect2 TwoSdramBanks2 FourSdramBanks2 SdramBanks2 _11_bit_addr2 _12_bit_addr2 _13_bit_addr2 SdAddr2 sd_8_bit_data2 sd_16_bit_data2 sd_32_bit_data2 SdData2 MW_FMC_MW SDRAM2 FMCUsed_ForRCC