FDCAN: Flexible Data-Rate Controller Area Network Specifies the FDCAN frame format. Specifies the FDCAN operating mode. Enable or disable the automatic retransmission mode. Specifies the FDCAN kernel clock divider when the clock calibration is bypassed. Enable or disable the transmitter delay compensation. Specifies the value by which the oscillator frequency is divided for generating the nominal bit time quanta. Specifies the maximum number of time quanta the FDCAN hardware is allowed to lengthen or shorten a bit to perform resynchronization. Specifies the number of time quanta in Bit Segment 1. Specifies the number of time quanta in Bit Segment 2. Specifies the value by which the oscillator frequency is divided for generating the data bit time quanta. Specifies the maximum number of time quanta the FDCAN hardware is allowed to lengthen or shorten a data bit to perform resynchronization. Specifies the number of time quanta in Data Bit Segment 1. Specifies the number of time quanta in Data Bit Segment 2. Specifies the number of standard Message ID filter. Specifies the number of extended Message ID filters. Specifies the number of Rx FIFO0 Elements. Specifies the Data Field Size in an Rx FIFO0 element. Specifies the number of Rx FIFO 1 Elements. Specifies the Rx FIFO 1 Data Field Size. Specifies the number of Dedicated Rx Buffer elements. Specifies the Rx Buffer Data Field Size. Specifies the number of Tx Event FIFO elements. Specifies the number of Dedicated Tx Buffers. Specifies the number of Tx Buffers used for Tx FIFO/Queue. Tx FIFO/Queue Mode selection. Specifies the Tx Element Data Field Size. Specifies the Filter List Standard Start Address. Specifies the Filter List Extended Start Address. Specifies the Rx FIFO 0 Start Address. Specifies the Rx FIFO 1 Start Address. Specifies the Rx Buffer Start Address. Specifies the Event FIFO Start Address. Specifies the Tx Buffers Start Address. Specifies the Tx FIFO/Queue Start Address. FDCAN Error code Specifies the identifier type. 0 and 63, if IdType is FDCAN_EXTENDED_ID Specifies the filter type. Specifies the filter configuration. 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID This parameter is ignored if FilterConfig is set to FDCAN_FILTER_TO_RXBUFFER Contains the index of the Rx buffer in which the matching message will be stored. 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID Specifies the identifier type for the message that will be transmitted. Specifies the frame type of the message that will be transmitted. Specifies the length of the frame that will be transmitted. Specifies the error state indicator. Specifies whether the Tx frame will be transmitted with or without bit rate switching. Specifies whether the Tx frame will be transmitted in classic or FD format. Specifies the event FIFO control. Specifies the message marker to be copied into Tx Event FIFO element for identification of Tx message status. Contains the location of the element to be transmitted. 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID Specifies the identifier type of the received message. Specifies the the received message frame type. Specifies the received frame length. Specifies the error state indicator. Specifies whether the Rx frame is received with or without bit rate switching. Specifies whether the Rx frame is received in classic or FD format. Specifies the timestamp counter value captured on start of frame reception. 0 and 64, if IdType is FDCAN_EXTENDED_ID Specifies whether the accepted frame did not match any Rx filter. Specifies the message RAM start address. Specifies the FDCAN Operation Mode. Specifies whether the instance is a slave or a potential master. Specifies the Synchronization Deviation Limit SDL of the TUR numerator : TUR = (Numerator ± SDL) / Denominator. Specifies the Initial Reference Trigger Offset. Enable or disable External Clock Synchronization. Specifies the Application Watchdog Limit : maximum time after which the application has to serve the application watchdog. Enable or disable Global Time Filtering. Enable or disable Automatic Clock Calibration. Specifies the Event Trigger Polarity. Specifies the length of Tx enable window in NTUs. Specifies the number of expected Tx_Triggers in the system matrix. Specifies the TUR (Time Unit Ratio) numerator. Specifies the TUR (Time Unit Ratio) denominator. Specifies the number of trigger memory elements. Specifies the input to be used as stop watch trigger. Specifies the input to be used as event trigger. Specifies the Trigger Memory Start Address. Enable or disable the clock calibration. Configures the minimum number of periods in two CAN bit times. Specifies the calibration field length. Configures the number of time quanta per bit time. Start value of the Calibration Watchdog Counter. 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID Specifies the identifier type for the message that will be transmitted. Specifies the frame type of the message that will be transmitted. Specifies the length of the frame that will be transmitted. Specifies the error state indicator. Specifies whether the Tx frame will be transmitted with or without bit rate switching. Specifies whether the Tx frame will be transmitted in classic or FD format. Specifies the timestamp counter value captured on start of frame transmission. Specifies the message marker to be copied into Tx Event FIFO element for identification of Tx message status. Specifies the event type. Specifies the trigger which will be configured. Specifies the cycle time for which the trigger becomes active. Specifies the trigger repeat factor. Specifies the index of the first cycle in which the trigger becomes active. Enable or disable the internal time mark event. Enable or disable the external time mark event. Specifies the trigger type. Specifies the filter identifier type. Specifies the index of the Tx buffer for which the trigger is valid. 0 and 63, if FilterType is FDCAN_EXTENDED_ID This parameter is taken in consideration only if the trigger is configured for reception. Enable or disable the Transmit Pause feature. Enable or disable the Protocol Exception Handling. Specifies the End Address of the allocated RAM. Enable or disable the ClockCalibration. Specifies the FDCAN TT Operation. Specifies the nubmer of basic cycles in the system matrix. Enable or disable synchronization pulse output at pin fdcan1_soc. Can_Init USB_OR_CAN $IpInstanceUsed_ForRCC