ETH: Ethernet MAC interface The Fisrt Tx Description address must be only in the D2 SRAM and AXI SRAM.These areas must not be cacheable. The First Rx Descriptor address must be only in the D2 SRAM and AXI SRAM. These areas must not be cacheable. The Fisrt Tx Description address must be only in the D2 SRAM and AXI SRAM. To ensure the zero copy capabilities, a received frame can't be divided into more than one buffer greater than the Rx Buffers Length. That is why we recommend to set this parameter to Ethernet Maximum Transfert Unit(MTU). Init HAL_ETH_MII_MODE Init HAL_ETH_RMII_MODE MII MW_ETH_MW MII MW_ETH_MW MW_ETH_MW MW_ETH_MW MW_ETH_MW ETHUsed_ForRCC