DSIHOST: Display Serial Interface Host This parameter enables the request for an acknowledge response at the end of each frame TX Escape clock division The values 0 and 1 stop the TX_ESC clock generation LP2HS = TLPX_CLK + TCLK_PREPARE + TCLK_ZERO HS2LP = TCLK_POST + TCLK_TRAIL + TCLK_EXIT TCLK_TRAIL=60ns TCLK_EXIT=100ns HS2LP = THS_TRAIL + THS_EXIT LP2HS = TLPX_DATA + THS_PREPARE + THS_ZERO The MRD_TIME field is used in LP mode to determine if there is time to complete a read command in a BLLP period. MRD_TIME = Time to transmit the read command in LP mode + Time to enter and leave LPmode + Time to return the read data packet from the peripheral device. MRD_TIME = (tHS2LP + tLP2HS + tLPDT + tlprd + tread + 2xtBTA) / lanebyteclkperiod. Timings are expressed in ns. tHS2LP = time to enter the LP mode. tLP2HS = time to leave the LP mode. tLPDT = D-PHY timing related to Escape mode entry, LPDT command, and Escape mode exit (according to the D-PHY specification, this value is always 11 bits in LP. tlprd = Read command time in LP mode (64 * TX esc clock). tread = Time to return the read data packet from the peripheral. tBTA = time to perform a bus turnaround (D-PHY dependent). The MRD_TIME field is used in HS to determine if there is time to complete a read command in a BLLP period. MRD_TIME = Time to enter and leave LPmode + Time to return the read data packet from the peripheral device. MRD_TIME = (tHS2LP + tLP2HS + tread + 2 x tBTA) / lanebyteclkperiod. Timings are expressed in ns. tHS2LP = time to enter the LP mode. tLP2HS = time to leave the LP mode. tread = Time to return the read data packet from the peripheral. tBTA = time to perform a bus turnaround (D-PHY dependent). The Burst mode increases the probability of the link spending more time in low-power mode: the DSI output bandwidth should be higher than the LTDC input bandwidth in a relation that enables the link to go to low-power once per line. The condition to use BURST mode is that the display device should support receiving a full pixel line in a single packet burst; if not use the Non Burst Mode The video packet size is limited by the size of the Pixel FIFO inside the display device. For 18-bit not loosely packed data types, this number must be a multiple of 4 The entire active pixel line is transmitted in a single packet.The display device should support receiving a full pixel line in a single packet burst The video packet size is limited by the size of the Pixel FIFO inside the display device. The pixel line is divided into several chunks of Video Packet Size pixels . If set to 0 or 1, the video line is transmitted in a single packet. If set to 1, the packet is part of a chunk, so a null packet follows it if Null Packet SIZE > 0. You must set the value to have Video Packet Size * Number of Chuncks = Number of Pixels per Line The pixel line is divided into several chunks of Video Packet Size pixels . If set to 0 or 1, the video line is transmitted in a single packet. If set to 1, the packet is part of a chunk, so a null packet follows it if Null Packet SIZE > 0. You must set the value to have Video Packet Size * Number of Chuncks = Number of Pixels per Line Each chunk is composed of Video Packet Size pixels followed by Null Packet Size in a way that LTDC interface input pixel ratio matches with the DSI output pixel ratio. If Null Packet are allowed, the following equation has to be verified : lanebyteclkperiod * Number_of_Chuncks (VideoPacketSize * bytes_per_pixel + 12 + NullPacketSize) / number_of_lanes = pixels_per_line * LTDC_Clock_period If Null Packet are not allowed, the following equation has to be verified : lanebyteclkperiod * Number_of_Chuncks (VideoPacketSize * bytes_per_pixel + 6) / number_of_lanes = pixels_per_line * LTDC_Clock_period If the commands are sent in high-speed in Video mode, the DSI Host automatically determines the area where each command can be sent and no programming or calculation is required. The LPSIZE field is compared directly with the size of the command to be transmitted to determine if there is time to transmit the command. LPSIZE = (tL - (tH1 + tHS2LP + tLP2HS + tLPDT + 2 tESCCLK)) / (2.8.tESCCLK). Timings are expressed in ns. tL = line time. tH1 = time of the HSA pulse for sync pulses mode or time to send the HSS packet, including EoTp. tHS2LP = time to enter the LP mode. tLP2HS = time to leave the LP mode. tLPDT = D-PHY timing related with Escape mode Entry, LPDT Command, and Escape Exit. According to the D-PHY specification, this value is always 11 bits in LP. tESCCLK = escape clock period the term 2 tESCCLK is a delay imposed by the DSI Host implementation. The division by (2.8.tESCCLK) allows to expressed LPSIZE in number of Bytes transfered using the Escape Clock where 1 byte is transmitted every 2 cycles The VLPSIZE field is compared directly with the size of the command to be transmitted to determine if there is time to transmit the command. VLPSIZE = (tL - (tHSA + tHBP + tHACT + tHS2LP + tLP2HS + tLPDT + 2 tESCCLK))/(2 . 8 . tESCCLK). Timings are expressed in ns. tL = line time. tHSA = time of the HSA pulse. tHBP = time of Horizontal back porch. tHACT = time of Video active. For Burst mode, the Video active is time compressed and is calculated as tHACT = (VPSIZE.Bytes_per_Pixel/Number_Lanes).tlanebyteclock tlanebyteclock = lane byte clock period tESCCLK = escape clock period tHS2LP = time to enter the LP mode. tLP2HS = time to leave the LP mode. tLPDT = D-PHY timing related with Escape mode Entry, LPDT Command, and Escape Exit. According to the D-PHY specification, this value is always 11 bits in LP. The division by (2.8.tESCCLK) allows to expressed LPSIZE in number of Bytes transfered using the Escape Clock where 1 byte is transmitted every 2 cycles The VLPSIZE field is compared directly with the size of the command to be transmitted to determine if there is time to transmit the command. VLPSIZE = (tL - (tHSA + tHBP + tHACT + tHS2LP + tLP2HS + tLPDT + 2 tESCCLK))/(2 . 8 . tESCCLK). Timings are expressed in ns. tL = line time. tHSA = time of the HSA pulse. tHBP = time of Horizontal back porch. tHACT = time of Video active. tESCCLK = escape clock period tHS2LP = time to enter the LP mode. tLP2HS = time to leave the LP mode. tLPDT = D-PHY timing related with Escape mode Entry, LPDT Command, and Escape Exit. According to the D-PHY specification, this value is always 11 bits in LP. The division by (2.8.tESCCLK) allows to expressed LPSIZE in number of Bytes transfered using the Escape Clock where 1 byte is transmitted every 2 cycles The Maximum Command Size is limited by the Size of the LTDC ctrl Pixel FIFO ie 1280 * 24bitsPixels This timing must be preferably kept nul in Video Mode This timing must be preferably kept nul in Video Mode This timing must preferably be kept nul in Video Mode This timing must preferably be kept nul in Video Mode This timing must preferably be kept nul in Video Mode This timing must preferably be kept nul in Video Mode This timing must preferably be kept nul in Video Mode This timing must preferably be kept nul in Video Mode This timing must preferably be kept nul in Video Mode This timing must preferably be kept nul in Video Mode This Timing depends on hardware implementation but can be redefined using a dedicated register The default value set in this register defines the same timing as the hardware timing This Timing depends on hardware implementation but can be redefined using a dedicated register The default value set in this register defines the same timing as the hardware timing This Timing depends on hardware implementation but can be redefined using a dedicated register The default value set in this register defines the same timing as the hardware timing This Timing depends on hardware implementation but can be redefined using a dedicated register The default value set in this register defines the same timing as the hardware timing This Timing depends on hardware implementation but can be redefined using a dedicated register The default value set in this register defines the same timing as the hardware timing This Timing depends on hardware implementation but can be redefined using a dedicated register The default value set in this register defines the same timing as the hardware timing This Timing depends on hardware implementation but can be redefined using a dedicated register The default value set in this register defines the same timing as the hardware timing This Timing depends on hardware implementation but can be redefined using a dedicated register The default value set in this register defines the same timing as the hardware timing This Timing depends on hardware implementation but can be redefined using a dedicated register The default value set in this register defines the same timing as the hardware timing DSI_Init DSI_ConfigCommandModeOnly DSI_ConfigCommandModeOnly DSI_ConfigVideoMode DSI_ConfigVideoMode DSI_ConfigAdaptedCommandMode DSI_ConfigAdaptedCommandMode DSI_ConfigAdaptedCommandModeTE DSI_ConfigAdaptedCommandModeTE DSIUsed_ForRCC Semaphore_MODEVIDEO$IpInstance DSIUsed_ForRCC Semaphore_MODEVIDEO$IpInstance Semaphore_onelane$IpInstance DSIUsed_ForRCC Semaphore_MODEADAPTED$IpInstance DSIUsed_ForRCC Semaphore_MODEADAPTED$IpInstance Semaphore_onelane$IpInstance DSIUsed_ForRCC Semaphore_MODEADAPTEDTE$IpInstance MW_DSIHOST_MW DSIUsed_ForRCC Semaphore_MODEADAPTEDTE$IpInstance Semaphore_onelane$IpInstance DSIUsed_ForRCC Semaphore_MODESTANDALONE$IpInstance DSIUsed_ForRCC Semaphore_MODESTANDALONE$IpInstance Semaphore_onelane$IpInstance $IpInstance