Digital Filter for delta-Sigma Modulators Output clock enable/disable Output clock enable Output clock disable Output clock enable Output clock is system clock or audio clock. Output clock is system clock or audio clock. Output clock divider. Output clock divider. Input is external serial inputs or internal register. Input is external serial inputs Input is internal register Standard, interleaved or dual mode for internal register. Standard, interleaved or dual mode for internal register. Input pins are taken from same or following channel. Input pins are taken from same channel. Input pins are taken from following channel. SPI modes. Manchester modes. SPI default but null expected SPI clock select SHOULD BE null. SPI clock select (external with different sampling point). SPI clock select (internal with different sampling point). Analog watchdog sinc filter order. Analog watchdog sinc filter order.SHOULD BE null Analog watchdog filter oversampling ratio. Analog watchdog filter oversampling ratio.SHOULD BE null DFSDM channel offset. DFSDM channel offset.SHOULD BE null DFSDM channel right bit shift. Input is external serial inputs or internal register. Input is external serial inputs Input is internal register Standard, interleaved or dual mode for internal register. Standard, interleaved or dual mode for internal register. Input pins are taken from same or following channel. Input pins are taken from same channel. Input pins are taken from following channel. SPI modes. Manchester modes. SPI default but null expected SPI clock select SHOULD BE null. SPI clock select (external with different sampling point). SPI clock select (internal with different sampling point). Analog watchdog sinc filter order. Analog watchdog sinc filter order.SHOULD BE null Analog watchdog filter oversampling ratio. Analog watchdog filter oversampling ratio.SHOULD BE null DFSDM channel offset. DFSDM channel offset.SHOULD BE null DFSDM channel right bit shift. Input is external serial inputs or internal register. Input is external serial inputs Input is internal register Standard, interleaved or dual mode for internal register. Standard, interleaved or dual mode for internal register. Input pins are taken from same or following channel. Input pins are taken from same channel. Input pins are taken from following channel. SPI modes. Manchester modes. SPI default but null expected SPI clock select SHOULD BE null. SPI clock select (external with different sampling point). SPI clock select (internal with different sampling point). Analog watchdog sinc filter order. Analog watchdog sinc filter order.SHOULD BE null Analog watchdog filter oversampling ratio. Analog watchdog filter oversampling ratio.SHOULD BE null DFSDM channel offset. DFSDM channel offset.SHOULD BE null DFSDM channel right bit shift. Input is external serial inputs or internal register. Input is external serial inputs Input is internal register Standard, interleaved or dual mode for internal register. Standard, interleaved or dual mode for internal register. Input pins are taken from same or following channel. Input pins are taken from same channel. Input pins are taken from following channel. SPI modes. Manchester modes. SPI default but null expected SPI clock select SHOULD BE null. SPI clock select (external with different sampling point). SPI clock select (internal with different sampling point). Analog watchdog sinc filter order. Analog watchdog sinc filter order.SHOULD BE null Analog watchdog filter oversampling ratio. Analog watchdog filter oversampling ratio.SHOULD BE null DFSDM channel offset. DFSDM channel offset.SHOULD BE null DFSDM channel right bit shift. Input is external serial inputs or internal register. Input is external serial inputs Input is internal register Standard, interleaved or dual mode for internal register. Standard, interleaved or dual mode for internal register. Input pins are taken from same or following channel. Input pins are taken from same channel. Input pins are taken from following channel. SPI modes. Manchester modes. SPI default but null expected SPI clock select SHOULD BE null. SPI clock select (external with different sampling point). SPI clock select (internal with different sampling point). Analog watchdog sinc filter order. Analog watchdog sinc filter order.SHOULD BE null Analog watchdog filter oversampling ratio. Analog watchdog filter oversampling ratio.SHOULD BE null DFSDM channel offset. DFSDM channel offset.SHOULD BE null DFSDM channel right bit shift. Input is external serial inputs or internal register. Input is external serial inputs Input is internal register Standard, interleaved or dual mode for internal register. Standard, interleaved or dual mode for internal register. Input pins are taken from same or following channel. Input pins are taken from same channel. Input pins are taken from following channel. SPI modes. Manchester modes. SPI default but null expected SPI clock select SHOULD BE null. SPI clock select (external with different sampling point). SPI clock select (internal with different sampling point). Analog watchdog sinc filter order. Analog watchdog sinc filter order.SHOULD BE null Analog watchdog filter oversampling ratio. Analog watchdog filter oversampling ratio.SHOULD BE null DFSDM channel offset. DFSDM channel offset.SHOULD BE null DFSDM channel right bit shift. Input is external serial inputs or internal register. Input is external serial inputs Input is internal register Standard, interleaved or dual mode for internal register. Standard, interleaved or dual mode for internal register. Input pins are taken from same or following channel. Input pins are taken from same channel. Input pins are taken from following channel. SPI modes. Manchester modes. SPI default but null expected SPI clock select SHOULD BE null. SPI clock select (external with different sampling point). SPI clock select (internal with different sampling point). Analog watchdog sinc filter order. Analog watchdog sinc filter order.SHOULD BE null Analog watchdog filter oversampling ratio. Analog watchdog filter oversampling ratio.SHOULD BE null DFSDM channel offset. DFSDM channel offset.SHOULD BE null DFSDM channel right bit shift. Input is external serial inputs or internal register. Input is external serial inputs Input is internal register Standard, interleaved or dual mode for internal register. Standard, interleaved or dual mode for internal register. Input pins are taken from same or following channel. Input pins are taken from same channel. Input pins are taken from following channel. SPI modes. Manchester modes. SPI default but null expected SPI clock select SHOULD BE null. SPI clock select (external with different sampling point). SPI clock select (internal with different sampling point). Analog watchdog sinc filter order. Analog watchdog sinc filter order.SHOULD BE null Analog watchdog filter oversampling ratio. Analog watchdog filter oversampling ratio.SHOULD BE null DFSDM channel offset. DFSDM channel offset.SHOULD BE null DFSDM channel right bit shift. Trigger used to start regular conversion: software or synchronous. Trigger used to start regular conversion: software or synchronous. Enable/disable fast mode for regular conversion Enable/disable fast mode for regular conversion Enable/disable DMA for regular conversion Enable/disable DMA for regular conversion Trigger used to start injected conversion: software, external or synchronous. Trigger used to start injected conversion: software, external or synchronous. Enable/disable scanning mode for injected conversion Enable/disable scanning mode for injected conversion Enable/disable DMA for injected conversion Enable/disable DMA for injected conversion External trigger. External trigger. External trigger. External trigger edge: rising, falling or both. External trigger edge: rising, falling or both. External trigger edge: rising, falling or both. Sinc filter order. Sinc filter order. Filter oversampling ratio ( 1 means bypass). Filter oversampling ratio ( 1 means bypass). Filter oversampling ratio ( 1 means bypass). Filter oversampling ratio ( 1 means bypass). Integrator oversampling ratio. Integrator oversampling ratio. Pointer on DMA handler for regular conversions Pointer on DMA handler for regular conversions Pointer on DMA handler for injected conversions Pointer on DMA handler for injected conversions regular channel selection. regular conversion continous/one shot mode. (Bit field RCONT in DFSDM_CR1 register) regular conversion continous/one shot mode. (Bit field RCONT in DFSDM_CR1 register) injected channel selection. injected channel selection. injected channel selection. injected channel selection. injected channel selection. injected channel selection. injected channel selection. injected channel selection. to indicate to NVIC or DMA that the filter is active to indicate to NVIC or DMA that the filter is active Trigger used to start regular conversion: software or synchronous. Trigger used to start regular conversion: software or synchronous. Enable/disable fast mode for regular conversion Enable/disable fast mode for regular conversion Enable/disable DMA for regular conversion Enable/disable DMA for regular conversion Trigger used to start injected conversion: software, external or synchronous. Trigger used to start injected conversion: software, external or synchronous. Enable/disable scanning mode for injected conversion Enable/disable scanning mode for injected conversion Enable/disable DMA for injected conversion Enable/disable DMA for injected conversion External trigger. External trigger. External trigger. External trigger edge: rising, falling or both. External trigger edge: rising, falling or both. External trigger edge: rising, falling or both. Sinc filter order. Sinc filter order. Filter oversampling ratio ( 1 means bypass). Filter oversampling ratio ( 1 means bypass). Filter oversampling ratio ( 1 means bypass). Filter oversampling ratio ( 1 means bypass). Integrator oversampling ratio. Integrator oversampling ratio. Pointer on DMA handler for regular conversions Pointer on DMA handler for regular conversions Pointer on DMA handler for injected conversions Pointer on DMA handler for injected conversions regular channel selection. regular conversion continous/one shot mode. (Bit field RCONT in DFSDM_CR1 register) regular conversion continous/one shot mode. (Bit field RCONT in DFSDM_CR1 register) injected channel selection. injected channel selection. injected channel selection. injected channel selection. injected channel selection. injected channel selection. injected channel selection. injected channel selection. to indicate to NVIC or DMA that the filter is active to indicate to NVIC or DMA that the filter is active Trigger used to start regular conversion: software or synchronous. Trigger used to start regular conversion: software or synchronous. Enable/disable fast mode for regular conversion Enable/disable fast mode for regular conversion Enable/disable DMA for regular conversion Enable/disable DMA for regular conversion Trigger used to start injected conversion: software, external or synchronous. Trigger used to start injected conversion: software, external or synchronous. Enable/disable scanning mode for injected conversion Enable/disable scanning mode for injected conversion Enable/disable DMA for injected conversion Enable/disable DMA for injected conversion External trigger. External trigger. External trigger. External trigger edge: rising, falling or both. External trigger edge: rising, falling or both. External trigger edge: rising, falling or both. Sinc filter order. Sinc filter order. Filter oversampling ratio ( 1 means bypass). Filter oversampling ratio ( 1 means bypass). Filter oversampling ratio ( 1 means bypass). Filter oversampling ratio ( 1 means bypass). Integrator oversampling ratio. Integrator oversampling ratio. Pointer on DMA handler for regular conversions Pointer on DMA handler for regular conversions Pointer on DMA handler for injected conversions Pointer on DMA handler for injected conversions regular channel selection. regular conversion continous/one shot mode. (Bit field RCONT in DFSDM_CR1 register) regular conversion continous/one shot mode. (Bit field RCONT in DFSDM_CR1 register) injected channel selection. injected channel selection. injected channel selection. injected channel selection. injected channel selection. injected channel selection. injected channel selection. injected channel selection. to indicate to NVIC or DMA that the filter is active to indicate to NVIC or DMA that the filter is active Trigger used to start regular conversion: software or synchronous. Trigger used to start regular conversion: software or synchronous. Enable/disable fast mode for regular conversion Enable/disable fast mode for regular conversion Enable/disable DMA for regular conversion Enable/disable DMA for regular conversion Trigger used to start injected conversion: software, external or synchronous. Trigger used to start injected conversion: software, external or synchronous. Enable/disable scanning mode for injected conversion Enable/disable scanning mode for injected conversion Enable/disable DMA for injected conversion Enable/disable DMA for injected conversion External trigger. External trigger. External trigger. External trigger edge: rising, falling or both. External trigger edge: rising, falling or both. External trigger edge: rising, falling or both. Sinc filter order. Sinc filter order. Filter oversampling ratio ( 1 means bypass). Filter oversampling ratio ( 1 means bypass). Filter oversampling ratio ( 1 means bypass). Filter oversampling ratio ( 1 means bypass). Integrator oversampling ratio. Integrator oversampling ratio. Pointer on DMA handler for regular conversions Pointer on DMA handler for regular conversions Pointer on DMA handler for injected conversions Pointer on DMA handler for injected conversions regular channel selection. regular conversion continous/one shot mode. (Bit field RCONT in DFSDM_CR1 register) regular conversion continous/one shot mode. (Bit field RCONT in DFSDM_CR1 register) injected channel selection. injected channel selection. injected channel selection. injected channel selection. injected channel selection. injected channel selection. injected channel selection. injected channel selection. to indicate to NVIC or DMA that the filter is active to indicate to NVIC or DMA that the filter is active Values from digital filter or from channel watchdog filter. Analog watchdog channel selection. High threshold for the analog watchdog. Low threshold for the analog watchdog. Break signal assigned to analog watchdog high threshold event. Break signal assigned to analog watchdog low threshold event. External trigger. Regular conversion continuous mode Trigger used for regular conversion Trigger used for injected conversion Rising, falling or both edges selected Injected scanning mode Number of channels in injected sequence Injected conversions remaining DFSDM filter error code Filter3_regConfig Filter3_injConfig Filter3_init Filter2_regConfig Filter2_injConfig Filter2_init Filter1_regConfig Filter1_injConfig Filter1_init Filter0_regConfig Filter0_injConfig Filter0_init Channel_init_CH0_parallel Channel_init_CH0_spisame_extClk Channel_init_CH0_spisame_intClk Channel_init_CH0_mansame Channel_init_CH0_spinext_extClk Channel_init_CH0_spinext_intClk Channel_init_CH0_mannext Channel_init_CH1_parallel Channel_init_CH1_spisame_extClk Channel_init_CH1_spisame_intClk Channel_init_CH1_mansame Channel_init_CH1_spinext_extClk Channel_init_CH1_spinext_intClk Channel_init_CH1_mannext Channel_init_CH2_parallel Channel_init_CH2_spisame_extClk Channel_init_CH2_spisame_intClk Channel_init_CH2_mansame Channel_init_CH2_spinext_extClk Channel_init_CH2_spinext_intClk Channel_init_CH2_mannext Channel_init_CH3_parallel Channel_init_CH3_spisame_extClk Channel_init_CH3_spisame_intClk Channel_init_CH3_mansame Channel_init_CH3_spinext_extClk Channel_init_CH3_spinext_intClk Channel_init_CH3_mannext Channel_init_CH4_parallel Channel_init_CH4_spisame_extClk Channel_init_CH4_spisame_intClk Channel_init_CH4_mansame Channel_init_CH4_spinext_extClk Channel_init_CH4_spinext_intClk Channel_init_CH4_mannext Channel_init_CH5_parallel Channel_init_CH5_spisame_extClk Channel_init_CH5_spisame_intClk Channel_init_CH5_mansame Channel_init_CH5_spinext_extClk Channel_init_CH5_spinext_intClk Channel_init_CH5_mannext Channel_init_CH6_parallel Channel_init_CH6_spisame_extClk Channel_init_CH6_spisame_intClk Channel_init_CH6_mansame Channel_init_CH6_spinext_extClk Channel_init_CH6_spinext_intClk Channel_init_CH6_mannext Channel_init_CH7_parallel Channel_init_CH7_spisame_extClk Channel_init_CH7_spisame_intClk Channel_init_CH7_mansame Channel_init_CH7_spinext_extClk Channel_init_CH7_spinext_intClk Channel_init_CH7_mannext Semaphore_Channel_Active_$IpInstance Semaphore_Channel_0_$IpInstance $IpInstanceUsed_ForRCC Semaphore_Parallel_Input_CH0_$IpInstance Semaphore_Internal_Clock_$IpInstance Semaphore_Internal_Clock_$IpInstance Semaphore_Channel_Active_$IpInstance Semaphore_Channel_1_$IpInstance $IpInstanceUsed_ForRCC Semaphore_Parallel_Input_CH1_$IpInstance Semaphore_Internal_Clock_$IpInstance Semaphore_Internal_Clock_$IpInstance Semaphore_Channel_Active_$IpInstance Semaphore_Channel_2_$IpInstance $IpInstanceUsed_ForRCC Semaphore_Parallel_Input_CH2_$IpInstance Semaphore_Internal_Clock_$IpInstance Semaphore_Internal_Clock_$IpInstance Semaphore_Channel_Active_$IpInstance Semaphore_Channel_3_$IpInstance $IpInstanceUsed_ForRCC Semaphore_Parallel_Input_CH3_$IpInstance Semaphore_Internal_Clock_$IpInstance Semaphore_Internal_Clock_$IpInstance Semaphore_Channel_Active_$IpInstance Semaphore_Channel_4_$IpInstance $IpInstanceUsed_ForRCC Semaphore_Parallel_Input_CH4_$IpInstance Semaphore_Internal_Clock_$IpInstance Semaphore_Internal_Clock_$IpInstance Semaphore_Channel_Active_$IpInstance Semaphore_Channel_5_$IpInstance $IpInstanceUsed_ForRCC Semaphore_Parallel_Input_CH5_$IpInstance Semaphore_Internal_Clock_$IpInstance Semaphore_Internal_Clock_$IpInstance Semaphore_Channel_Active_$IpInstance Semaphore_Channel_6_$IpInstance $IpInstanceUsed_ForRCC Semaphore_Parallel_Input_CH6_$IpInstance Semaphore_Internal_Clock_$IpInstance Semaphore_Internal_Clock_$IpInstance Semaphore_Channel_Active_$IpInstance Semaphore_Channel_7_$IpInstance $IpInstanceUsed_ForRCC Semaphore_Parallel_Input_CH7_$IpInstance Semaphore_Internal_Clock_$IpInstance Semaphore_Internal_Clock_$IpInstance Semaphore_CKOUT_Mode_$IpInstance