DDR: Dual Data Rate DDR subsystem frequency. This value is copied from the Clock Configuration panel DDR subsystem frequency. This value is copied from the Clock Configuration panel DDR Address mapping can be configured in RBC (Row-Bank-Column) or BRC (Bank-Row-Column) Add one supplementary clock cycle to some key DDR parameters. This ease the DDR bring-up by relaxing some key timings. The relaxed timing parameters are: tRC, tRCD and tRP. The +1 is made before register computation, thus not visible in the parameter edition interface DDR3 only, when TC > 85 TREFI = 3.9 and ASR = 1 Changing Output impedance (DDR) and ODT (PHY) for read Operations. Changing Output impedance (DDR) for read Operations. Changing Output impedance (PHY) and ODT (DDR) for write Operations. Changing Output impedance (PHY) for write Operations. JEDEC Standard for DDR3 SDRAM. Set value of each timings from JEDEC standard for this 'Speed Bin Grade' selection. Tick 'Show Advanced Parameters' to see the involved timings. Select Speed Bin / Grade combination according to the DDR you have provisioned. In case your Speed Bin / Grade is not listed, please use: "1066G / 8-8-8” as a relaxed configuration that should work with most of DDRs. "1066E / 6-6-6” if you have faster DDR Speed Bin / Grade” Allows to choose the best scheduling and Quality of Service configuration for the targeted project. The various configurations possible are: - CONFIG 0: 1 port + No VPR/VPW + antistarvation - CONFIG 1: 2 ports + No VPR/VPW + antistarvation - CONFIG 2: 2 ports + QoS VPR/VPW + antistarvation - CONFIG 3: 2 ports + QoS VPR/VPW + timeout + antistarvation - CONFIG 4: 2 ports + QoS VPR/VPW + timeout + antistarvation - CONFIG 5: 1 port + intelligent percharge + No VPR/VPW + antistarvation Burst Length (BL) is variable for LPDDR2. Fixed for other DDR types. Possible values are 4, 8 and 16. Burst Length (BL) is fixed for DDR3, it can not be changed Burst Length (BL) is fixed for LPDDR3, it can not be changed The number of cycles between sending a column address to the memory and the beginning of the data in response. This is the number of cycles it takes to read the first bit of memory from a DRAM with the correct row already open. Unlike the other numbers, this is not a maximum, but an exact number that must be agreed on between the memory controller and the memory "CAS Write Latency is the delay, in clock cycles, between the internal Write command and the availability of the first bit of input data. ACT to PRE command period the minimum number of clock cycles required between a row active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlaps with TRCD. In SDRAM modules, it is simply TRCD + CL. Otherwise, approximately equal to TRCD + 2×CL. ACT to PRE command period the minimum number of clock cycles required between a row active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlaps with TRCD. In SDRAM modules, it is simply TRCD + CL. Otherwise, approximately equal to TRCD + 2×CL. Mode Register Set command cycle time MODE REGISTER SET command delay (MRW command to non-MRW command interval) Mode Register Set command update delay. This parameter can be found expressed in ns in the DRAM datasheet. Tools requires a conversion to clk. Please make sure you use your target DDR clock value for conversion. Activate to Read/Write command period: the minimum number of clock cycles required between opening a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is TRCD + CL Activate to Read/Write command period: the minimum number of clock cycles required between opening a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is TRCD + CL Activate to Read/Write command period: the minimum number of clock cycles required between opening a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is TRCD + CL PRE command period: the minimum number of clock cycles required between issuing the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is TRP + TRCD + CL Row Precharge Time (all banks) The Write Latency is defined from the rising edge of the clock on which the Write Command is issued to the rising edge of the clock from which the tDQSS delay is measured. The Write Latency is defined from the rising edge of the clock on which the Write Command is issued to the rising edge of the clock from which the tDQSS delay is measured. Write to Precharge Delay / Write Recovery Time or tWR: This sets the number of clock cycles between the completion of a valid write operation and before an active bank can be precharged. Write to precharge formula is tCL -1 +(Burst Legnth / 2)+tWTR CAS# to CAS#, min between 2 READ or 2 WRITE (burst can’tbe interrupted with DDR3) CAS# to CAS#, min between 2 READ or 2 WRITE . READ may be interrupted by read and write by write MR write command period MR write command period MR read command period MR read command period Activate to Activate delay or tRRD: Number of clock cycles between the activation of two rows in different banks of the same rank. (not much of a performance boost). This parameter can be found expressed in ns in the DRAM datasheet. Tools requires a conversion to clk. Please make sure you use your target DDR clock value for conversion. Activate to Activate delay or tRRD: Number of clock cycles between the activation of two rows in different banks of the same rank. (not much of a performance boost). This parameter can be found expressed in ns in the DRAM datasheet. Tools requires a conversion to clk. Please make sure you use your target DDR clock value for conversion. Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX) or Reset Exit. This parameter can be found expressed in ns in the DRAM datasheet. Tools requires a conversion to clk. Please make sure you use your target DDR clock value for conversion. Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE). This parameter can be found expressed in ns in the DRAM datasheet. Tools requires a conversion to clk. Please make sure you use your target DDR clock value for conversion. CKE minimum pulse width. This parameter can be found expressed in ns in the DRAM datasheet. Tools requires a conversion to clk. Please make sure you use your target DDR clock value for conversion. CKE min. pulse width (high and low pulse width). This parameter can be found expressed in ns in the DRAM datasheet. Tools requires a conversion to clk. Please make sure you use your target DDR clock value for conversion. CKE minimum pulse width during SELF REFRESH (low pulse width during SELF REFRESH) CKE minimum pulse width during SELF REFRESH (low pulse width during SELF REFRESH) Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL. This parameter can be found expressed in ns in the DRAM datasheet. Tools requires a conversion to clk. Please make sure you use your target DDR clock value for conversion. Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL. This parameter can be found expressed in ns in the DRAM datasheet. Tools requires a conversion to clk. Please make sure you use your target DDR clock value for conversion. Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL. This parameter can be found expressed in ns in the DRAM datasheet. Tools requires a conversion to clk. Please make sure you use your target DDR clock value for conversion. DQS, DQS# rising edge output access time from rising CK, CK# - max value DQS, DQS# rising edge output access time from rising CK, CK# - min value Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL. This parameter can be found expressed in ns in the DRAM datasheet. Tools requires a conversion to clk. Please make sure you use your target DDR clock value for conversion. Refresh to Activate Delay / Refresh Cycle Time or tRFC: Sets the number of clock cycles from the refresh command until the first activate command to the same rank. Minimum time from refresh to refresh or activate, if using all-bank refreshes Minimum time from refresh to refresh or activate, if using all-bank refreshes Exit SR to CMD not requiring locked DLL: = max(5 clk , tRFC +10ns) Exit Self Refresh to commands requiring a locked DLL The Read Latency is defined from the rising edge of the clock on which the Read Command is issued to the rising edge of the clock from which the tDQSCK delay is measured. The Read Latency is defined from the rising edge of the clock on which the Read Command is issued to the rising edge of the clock from which the tDQSCK delay is measured. Four Activate Window or tFAW: The number of cycles in which four activates are allowed within the same rank. Four Activate Window or tFAW: The number of cycles in which four activates are allowed within the same rank. Max between ACT and PRE to same bank in 1024 clk: 9 *tREFI Read to Precharge delay or tRTP: The number of clock cycles between a read command to a row pre-charge command of the same rank. This parameter can be found expressed in ns in the DRAM datasheet. Tools requires a conversion to clk. Please make sure you use your target DDR clock value for conversion. Read to Precharge delay or tRTP: The number of clock cycles between a read command to a row pre-charge command of the same rank. This parameter can be found expressed in ns in the DRAM datasheet. Tools requires a conversion to clk. Please make sure you use your target DDR clock value for conversion. Row Cycle Time or tRC:This sets the number of cpu cycles a memory row (Remeber that memory is devided into "cells" much like an excel spredsheet) takes to complete a full cycle. A full cycle is from row activation to precharging of the active row. This setting has major affect on memory speed w/ a lower timing being faster. tRC= tras + tRP Row Cycle Time or tRC:This sets the number of cpu cycles a memory row (Remeber that memory is devided into "cells" much like an excel spredsheet) takes to complete a full cycle. A full cycle is from row activation to precharging of the active row. This setting has major affect on memory speed w/ a lower timing being faster. tRC= tras + tRP Refresh Mode Select / Refresh Period or tREFi: Sets the number of clock cycles refreshes. 3,9us (DDR TcMax above 85°C) or 7,8us (DDR TcMax 85°C). Refresh Mode Select / Refresh Period or tREFi: Sets the number of clock cycles refreshes will be executed. Possible values are 3,9us and 7,8us. Delay from start of internal write transaction to internal read command. This parameter can be found expressed in ns in the DRAM datasheet. Tools requires a conversion to clk. Please make sure you use your target DDR clock value for conversion. Delay from start of internal write transaction to internal read command. This parameter can be found expressed in ns in the DRAM datasheet. Tools requires a conversion to clk. Please make sure you use your target DDR clock value for conversion. This option enable/disable the built-in calibration for DDR tuning. -Enable: skip built-in calibration and use the tuning parameters done by DDR Test Suite tool (DDR Tuning service), those parameters are present in the generated device tree. -Disable: use built-in calibration. This parameter contains the DQS Phase after tuning. Default value is 0. Coarse position: Phase delay (7 steps: 0 to 6). Possible values are: Reported Index: 0 (36 degrees) Reported Index: 1 (54 degrees) Reported Index: 2 (72 degrees) Reported Index: 3 (90 degrees) (default value) Reported Index: 4 (108 degrees) Reported Index: 5 (126 degrees) Reported Index: 6 (144 degrees) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS# fine tuning. Default value is 3. Valid values are: 0 (nominal delay - 3 steps) 1 (nominal delay - 2 steps) 2 (nominal delay - 1 steps) 3 (nominal delay) 4 (nominal delay + 1 step) 5 (nominal delay + 2 steps) 6 (nominal delay + 3 steps) 7 (nominal delay + 4 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS fine tuning. Default value is 3. Valid values are: 0 (nominal delay - 3 steps) 1 (nominal delay - 2 steps) 2 (nominal delay - 1 steps) 3 (nominal delay) 4 (nominal delay + 1 step) 5 (nominal delay + 2 steps) 6 (nominal delay + 3 steps) 7 (nominal delay + 4 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS gating phase select fine tuning. Default value is 2. Valid values are: 0 (clk180) 1 (clk270) 2 (clk0) (default value) 3 (next clk90) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS gating system latency fine tuning. Default value is 3. Valid values are: 0 (No extra clock cycles) (default value) 1 (1 extra clock cycle) 2 (2 extra clock cycles) 3 (3 extra clock cycles) 4 (4 extra clock cycles) 5 (5 extra clock cycles) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS Phase after tuning. Default value is 0. Coarse position: Phase delay (7 steps: 0 to 6). Possible values are: Reported Index: 0 (36 degrees) Reported Index: 1 (54 degrees) Reported Index: 2 (72 degrees) Reported Index: 3 (90 degrees) (default value) Reported Index: 4 (108 degrees) Reported Index: 5 (126 degrees) Reported Index: 6 (144 degrees) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS# fine tuning. Default value is 3. Valid values are: 0 (nominal delay - 3 steps) 1 (nominal delay - 2 steps) 2 (nominal delay - 1 steps) 3 (nominal delay) 4 (nominal delay + 1 step) 5 (nominal delay + 2 steps) 6 (nominal delay + 3 steps) 7 (nominal delay + 4 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS fine tuning. Default value is 3. Valid values are: 0 (nominal delay - 3 steps) 1 (nominal delay - 2 steps) 2 (nominal delay - 1 steps) 3 (nominal delay) 4 (nominal delay + 1 step) 5 (nominal delay + 2 steps) 6 (nominal delay + 3 steps) 7 (nominal delay + 4 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS gating phase select fine tuning. Default value is 2. Valid values are: 0 (clk180) 1 (clk270) 2 (clk0) (default value) 3 (next clk90) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS gating system latency fine tuning. Default value is 3. Valid values are: 0 (No extra clock cycles) (default value) 1 (1 extra clock cycle) 2 (2 extra clock cycles) 3 (3 extra clock cycles) 4 (4 extra clock cycles) 5 (5 extra clock cycles) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS Phase after tuning. Default value is 0. Coarse position: Phase delay (7 steps: 0 to 6). Possible values are: Reported Index: 0 (36 degrees) Reported Index: 1 (54 degrees) Reported Index: 2 (72 degrees) Reported Index: 3 (90 degrees) (default value) Reported Index: 4 (108 degrees) Reported Index: 5 (126 degrees) Reported Index: 6 (144 degrees) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS# fine tuning. Default value is 3. Valid values are: 0 (nominal delay - 3 steps) 1 (nominal delay - 2 steps) 2 (nominal delay - 1 steps) 3 (nominal delay) 4 (nominal delay + 1 step) 5 (nominal delay + 2 steps) 6 (nominal delay + 3 steps) 7 (nominal delay + 4 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS fine tuning. Default value is 3. Valid values are: 0 (nominal delay - 3 steps) 1 (nominal delay - 2 steps) 2 (nominal delay - 1 steps) 3 (nominal delay) 4 (nominal delay + 1 step) 5 (nominal delay + 2 steps) 6 (nominal delay + 3 steps) 7 (nominal delay + 4 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS gating phase select fine tuning. Default value is 2. Valid values are: 0 (clk180) 1 (clk270) 2 (clk0) (default value) 3 (next clk90) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS gating system latency fine tuning. Default value is 3. Valid values are: 0 (No extra clock cycles) (default value) 1 (1 extra clock cycle) 2 (2 extra clock cycles) 3 (3 extra clock cycles) 4 (4 extra clock cycles) 5 (5 extra clock cycles) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS Phase after tuning. Default value is 0. Coarse position: Phase delay (7 steps: 0 to 6). Possible values are: Reported Index: 0 (36 degrees) Reported Index: 1 (54 degrees) Reported Index: 2 (72 degrees) Reported Index: 3 (90 degrees) (default value) Reported Index: 4 (108 degrees) Reported Index: 5 (126 degrees) Reported Index: 6 (144 degrees) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQ bit lane fine delay after tuning. Default value is 0x0F. Valid settings for each 2-bit control field are: 0 stands for 0 (DQ=00 DQ#=00 0000(0)) (nominal delay) 5 stands for 1 (DQ=01 DQ#=01 0101(5)) (nominal delay + 1 step) A stands for 2 (DQ=10 DQ#=10 1010(A)) (nominal delay + 2 steps) F stands for 3 (DQ=11 DQ#=11 1111(F)) (nominal delay + 3 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS# fine tuning. Default value is 3. Valid values are: 0 (nominal delay - 3 steps) 1 (nominal delay - 2 steps) 2 (nominal delay - 1 steps) 3 (nominal delay) 4 (nominal delay + 1 step) 5 (nominal delay + 2 steps) 6 (nominal delay + 3 steps) 7 (nominal delay + 4 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS fine tuning. Default value is 3. Valid values are: 0 (nominal delay - 3 steps) 1 (nominal delay - 2 steps) 2 (nominal delay - 1 steps) 3 (nominal delay) 4 (nominal delay + 1 step) 5 (nominal delay + 2 steps) 6 (nominal delay + 3 steps) 7 (nominal delay + 4 steps) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS gating phase select fine tuning. Default value is 2. Valid values are: 0 (clk180) 1 (clk270) 2 (clk0) (default value) 3 (next clk90) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. This parameter contains the DQS gating system latency fine tuning. Default value is 3. Valid values are: 0 (No extra clock cycles) (default value) 1 (1 extra clock cycle) 2 (2 extra clock cycles) 3 (3 extra clock cycles) 4 (4 extra clock cycles) 5 (5 extra clock cycles) Please use the DDR Tuning feature of STM32CubeMx DDR Test Suite to get tuned values for your hardware design. tbc tbc tbc tbc DDR3 LPDDR2 LPDDR3 DDR_TYPE_SET DDR_16_bits DDR_32_bits WIDTH_SET DDR3_16_1Gb DDR3_16_2Gb DDR3_16_4Gb DDR3_16_8Gb DENSITY_SET DDR3_32_2Gb DDR3_32_4Gb DDR3_32_8Gb DENSITY_SET LPDDR23_1Gb LPDDR23_2Gb LPDDR23_4Gb LPDDR23_8Gb DENSITY_SET